1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_string_fns.h>
6 #include <rte_ethdev_pci.h>
13 #include "base/ice_sched.h"
14 #include "base/ice_flow.h"
15 #include "base/ice_dcb.h"
16 #include "base/ice_common.h"
17 #include "ice_ethdev.h"
19 #include "ice_generic_flow.h"
22 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
23 #define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support"
24 #define ICE_PROTO_XTR_ARG "proto_xtr"
26 static const char * const ice_valid_args[] = {
27 ICE_SAFE_MODE_SUPPORT_ARG,
28 ICE_PIPELINE_MODE_SUPPORT_ARG,
33 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
35 /* DDP package search path */
36 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
37 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
38 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
39 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
41 #define ICE_OS_DEFAULT_PKG_NAME "ICE OS Default Package"
42 #define ICE_COMMS_PKG_NAME "ICE COMMS Package"
43 #define ICE_MAX_PKG_FILENAME_SIZE 256
44 #define ICE_MAX_RES_DESC_NUM 1024
47 int ice_logtype_driver;
48 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
51 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
54 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
55 int ice_logtype_tx_free;
58 static int ice_dev_configure(struct rte_eth_dev *dev);
59 static int ice_dev_start(struct rte_eth_dev *dev);
60 static void ice_dev_stop(struct rte_eth_dev *dev);
61 static void ice_dev_close(struct rte_eth_dev *dev);
62 static int ice_dev_reset(struct rte_eth_dev *dev);
63 static int ice_dev_info_get(struct rte_eth_dev *dev,
64 struct rte_eth_dev_info *dev_info);
65 static int ice_link_update(struct rte_eth_dev *dev,
66 int wait_to_complete);
67 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
68 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
70 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
71 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
72 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
73 enum rte_vlan_type vlan_type,
75 static int ice_rss_reta_update(struct rte_eth_dev *dev,
76 struct rte_eth_rss_reta_entry64 *reta_conf,
78 static int ice_rss_reta_query(struct rte_eth_dev *dev,
79 struct rte_eth_rss_reta_entry64 *reta_conf,
81 static int ice_rss_hash_update(struct rte_eth_dev *dev,
82 struct rte_eth_rss_conf *rss_conf);
83 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
84 struct rte_eth_rss_conf *rss_conf);
85 static int ice_promisc_enable(struct rte_eth_dev *dev);
86 static int ice_promisc_disable(struct rte_eth_dev *dev);
87 static int ice_allmulti_enable(struct rte_eth_dev *dev);
88 static int ice_allmulti_disable(struct rte_eth_dev *dev);
89 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
92 static int ice_macaddr_set(struct rte_eth_dev *dev,
93 struct rte_ether_addr *mac_addr);
94 static int ice_macaddr_add(struct rte_eth_dev *dev,
95 struct rte_ether_addr *mac_addr,
96 __rte_unused uint32_t index,
98 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
99 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
101 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
103 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
105 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
106 uint16_t pvid, int on);
107 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
108 static int ice_get_eeprom(struct rte_eth_dev *dev,
109 struct rte_dev_eeprom_info *eeprom);
110 static int ice_stats_get(struct rte_eth_dev *dev,
111 struct rte_eth_stats *stats);
112 static int ice_stats_reset(struct rte_eth_dev *dev);
113 static int ice_xstats_get(struct rte_eth_dev *dev,
114 struct rte_eth_xstat *xstats, unsigned int n);
115 static int ice_xstats_get_names(struct rte_eth_dev *dev,
116 struct rte_eth_xstat_name *xstats_names,
118 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
119 enum rte_filter_type filter_type,
120 enum rte_filter_op filter_op,
122 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
123 struct rte_eth_udp_tunnel *udp_tunnel);
124 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
125 struct rte_eth_udp_tunnel *udp_tunnel);
127 static const struct rte_pci_id pci_id_ice_map[] = {
128 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
129 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
130 { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
131 { .vendor_id = 0, /* sentinel */ },
134 static const struct eth_dev_ops ice_eth_dev_ops = {
135 .dev_configure = ice_dev_configure,
136 .dev_start = ice_dev_start,
137 .dev_stop = ice_dev_stop,
138 .dev_close = ice_dev_close,
139 .dev_reset = ice_dev_reset,
140 .dev_set_link_up = ice_dev_set_link_up,
141 .dev_set_link_down = ice_dev_set_link_down,
142 .rx_queue_start = ice_rx_queue_start,
143 .rx_queue_stop = ice_rx_queue_stop,
144 .tx_queue_start = ice_tx_queue_start,
145 .tx_queue_stop = ice_tx_queue_stop,
146 .rx_queue_setup = ice_rx_queue_setup,
147 .rx_queue_release = ice_rx_queue_release,
148 .tx_queue_setup = ice_tx_queue_setup,
149 .tx_queue_release = ice_tx_queue_release,
150 .dev_infos_get = ice_dev_info_get,
151 .dev_supported_ptypes_get = ice_dev_supported_ptypes_get,
152 .link_update = ice_link_update,
153 .mtu_set = ice_mtu_set,
154 .mac_addr_set = ice_macaddr_set,
155 .mac_addr_add = ice_macaddr_add,
156 .mac_addr_remove = ice_macaddr_remove,
157 .vlan_filter_set = ice_vlan_filter_set,
158 .vlan_offload_set = ice_vlan_offload_set,
159 .vlan_tpid_set = ice_vlan_tpid_set,
160 .reta_update = ice_rss_reta_update,
161 .reta_query = ice_rss_reta_query,
162 .rss_hash_update = ice_rss_hash_update,
163 .rss_hash_conf_get = ice_rss_hash_conf_get,
164 .promiscuous_enable = ice_promisc_enable,
165 .promiscuous_disable = ice_promisc_disable,
166 .allmulticast_enable = ice_allmulti_enable,
167 .allmulticast_disable = ice_allmulti_disable,
168 .rx_queue_intr_enable = ice_rx_queue_intr_enable,
169 .rx_queue_intr_disable = ice_rx_queue_intr_disable,
170 .fw_version_get = ice_fw_version_get,
171 .vlan_pvid_set = ice_vlan_pvid_set,
172 .rxq_info_get = ice_rxq_info_get,
173 .txq_info_get = ice_txq_info_get,
174 .rx_burst_mode_get = ice_rx_burst_mode_get,
175 .tx_burst_mode_get = ice_tx_burst_mode_get,
176 .get_eeprom_length = ice_get_eeprom_length,
177 .get_eeprom = ice_get_eeprom,
178 .rx_queue_count = ice_rx_queue_count,
179 .rx_descriptor_status = ice_rx_descriptor_status,
180 .tx_descriptor_status = ice_tx_descriptor_status,
181 .stats_get = ice_stats_get,
182 .stats_reset = ice_stats_reset,
183 .xstats_get = ice_xstats_get,
184 .xstats_get_names = ice_xstats_get_names,
185 .xstats_reset = ice_stats_reset,
186 .filter_ctrl = ice_dev_filter_ctrl,
187 .udp_tunnel_port_add = ice_dev_udp_tunnel_port_add,
188 .udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,
191 /* store statistics names and its offset in stats structure */
192 struct ice_xstats_name_off {
193 char name[RTE_ETH_XSTATS_NAME_SIZE];
197 static const struct ice_xstats_name_off ice_stats_strings[] = {
198 {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
199 {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
200 {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
201 {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
202 {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
203 rx_unknown_protocol)},
204 {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
205 {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
206 {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
207 {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
210 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
211 sizeof(ice_stats_strings[0]))
213 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
214 {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
215 tx_dropped_link_down)},
216 {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
217 {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
219 {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
220 {"mac_local_errors", offsetof(struct ice_hw_port_stats,
222 {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
224 {"rx_len_errors", offsetof(struct ice_hw_port_stats,
226 {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
227 {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
228 {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
229 {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
230 {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
231 {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
233 {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
235 {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
237 {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
239 {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
241 {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
243 {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
245 {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
247 {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
248 mac_short_pkt_dropped)},
249 {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
251 {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
252 {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
253 {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
255 {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
257 {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
259 {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
261 {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
263 {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
267 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
268 sizeof(ice_hw_port_strings[0]))
271 ice_init_controlq_parameter(struct ice_hw *hw)
273 /* fields for adminq */
274 hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
275 hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
276 hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
277 hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
279 /* fields for mailboxq, DPDK used as PF host */
280 hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
281 hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
282 hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
283 hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
287 lookup_proto_xtr_type(const char *xtr_name)
291 enum proto_xtr_type type;
293 { "vlan", PROTO_XTR_VLAN },
294 { "ipv4", PROTO_XTR_IPV4 },
295 { "ipv6", PROTO_XTR_IPV6 },
296 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
297 { "tcp", PROTO_XTR_TCP },
301 for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
302 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
303 return xtr_type_map[i].type;
310 * Parse elem, the elem could be single number/range or '(' ')' group
311 * 1) A single number elem, it's just a simple digit. e.g. 9
312 * 2) A single range elem, two digits with a '-' between. e.g. 2-6
313 * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
314 * Within group elem, '-' used for a range separator;
315 * ',' used for a single number.
318 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
320 const char *str = input;
325 while (isblank(*str))
328 if (!isdigit(*str) && *str != '(')
331 /* process single number or single range of number */
334 idx = strtoul(str, &end, 10);
335 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
338 while (isblank(*end))
344 /* process single <number>-<number> */
347 while (isblank(*end))
353 idx = strtoul(end, &end, 10);
354 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
358 while (isblank(*end))
365 for (idx = RTE_MIN(min, max);
366 idx <= RTE_MAX(min, max); idx++)
367 devargs->proto_xtr[idx] = xtr_type;
372 /* process set within bracket */
374 while (isblank(*str))
379 min = ICE_MAX_QUEUE_NUM;
381 /* go ahead to the first digit */
382 while (isblank(*str))
387 /* get the digit value */
389 idx = strtoul(str, &end, 10);
390 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
393 /* go ahead to separator '-',',' and ')' */
394 while (isblank(*end))
397 if (min == ICE_MAX_QUEUE_NUM)
399 else /* avoid continuous '-' */
401 } else if (*end == ',' || *end == ')') {
403 if (min == ICE_MAX_QUEUE_NUM)
406 for (idx = RTE_MIN(min, max);
407 idx <= RTE_MAX(min, max); idx++)
408 devargs->proto_xtr[idx] = xtr_type;
410 min = ICE_MAX_QUEUE_NUM;
416 } while (*end != ')' && *end != '\0');
422 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
424 const char *queue_start;
429 while (isblank(*queues))
432 if (*queues != '[') {
433 xtr_type = lookup_proto_xtr_type(queues);
437 devargs->proto_xtr_dflt = xtr_type;
444 while (isblank(*queues))
449 queue_start = queues;
451 /* go across a complete bracket */
452 if (*queue_start == '(') {
453 queues += strcspn(queues, ")");
458 /* scan the separator ':' */
459 queues += strcspn(queues, ":");
460 if (*queues++ != ':')
462 while (isblank(*queues))
465 for (idx = 0; ; idx++) {
466 if (isblank(queues[idx]) ||
467 queues[idx] == ',' ||
468 queues[idx] == ']' ||
472 if (idx > sizeof(xtr_name) - 2)
475 xtr_name[idx] = queues[idx];
477 xtr_name[idx] = '\0';
478 xtr_type = lookup_proto_xtr_type(xtr_name);
484 while (isblank(*queues) || *queues == ',' || *queues == ']')
487 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
489 } while (*queues != '\0');
495 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
498 struct ice_devargs *devargs = extra_args;
500 if (value == NULL || extra_args == NULL)
503 if (parse_queue_proto_xtr(value, devargs) < 0) {
505 "The protocol extraction parameter is wrong : '%s'",
514 ice_proto_xtr_support(struct ice_hw *hw)
516 #define FLX_REG(val, fld, idx) \
517 (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
518 GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
524 { ICE_RXDID_COMMS_AUX_VLAN, ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O },
525 { ICE_RXDID_COMMS_AUX_IPV4, ICE_PROT_IPV4_OF_OR_S,
526 ICE_PROT_IPV4_OF_OR_S },
527 { ICE_RXDID_COMMS_AUX_IPV6, ICE_PROT_IPV6_OF_OR_S,
528 ICE_PROT_IPV6_OF_OR_S },
529 { ICE_RXDID_COMMS_AUX_IPV6_FLOW, ICE_PROT_IPV6_OF_OR_S,
530 ICE_PROT_IPV6_OF_OR_S },
531 { ICE_RXDID_COMMS_AUX_TCP, ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
535 for (i = 0; i < RTE_DIM(xtr_sets); i++) {
536 uint32_t rxdid = xtr_sets[i].rxdid;
539 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
540 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
542 if (FLX_REG(v, PROT_MDID, 4) != xtr_sets[i].protid_0 ||
543 FLX_REG(v, RXDID_OPCODE, 4) != ICE_RX_OPC_EXTRACT)
547 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
548 v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
550 if (FLX_REG(v, PROT_MDID, 5) != xtr_sets[i].protid_1 ||
551 FLX_REG(v, RXDID_OPCODE, 5) != ICE_RX_OPC_EXTRACT)
560 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
563 struct pool_entry *entry;
568 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
571 "Failed to allocate memory for resource pool");
575 /* queue heap initialize */
576 pool->num_free = num;
579 LIST_INIT(&pool->alloc_list);
580 LIST_INIT(&pool->free_list);
582 /* Initialize element */
586 LIST_INSERT_HEAD(&pool->free_list, entry, next);
591 ice_res_pool_alloc(struct ice_res_pool_info *pool,
594 struct pool_entry *entry, *valid_entry;
597 PMD_INIT_LOG(ERR, "Invalid parameter");
601 if (pool->num_free < num) {
602 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
603 num, pool->num_free);
608 /* Lookup in free list and find most fit one */
609 LIST_FOREACH(entry, &pool->free_list, next) {
610 if (entry->len >= num) {
612 if (entry->len == num) {
617 valid_entry->len > entry->len)
622 /* Not find one to satisfy the request, return */
624 PMD_INIT_LOG(ERR, "No valid entry found");
628 * The entry have equal queue number as requested,
629 * remove it from alloc_list.
631 if (valid_entry->len == num) {
632 LIST_REMOVE(valid_entry, next);
635 * The entry have more numbers than requested,
636 * create a new entry for alloc_list and minus its
637 * queue base and number in free_list.
639 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
642 "Failed to allocate memory for "
646 entry->base = valid_entry->base;
648 valid_entry->base += num;
649 valid_entry->len -= num;
653 /* Insert it into alloc list, not sorted */
654 LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
656 pool->num_free -= valid_entry->len;
657 pool->num_alloc += valid_entry->len;
659 return valid_entry->base + pool->base;
663 ice_res_pool_destroy(struct ice_res_pool_info *pool)
665 struct pool_entry *entry, *next_entry;
670 for (entry = LIST_FIRST(&pool->alloc_list);
671 entry && (next_entry = LIST_NEXT(entry, next), 1);
672 entry = next_entry) {
673 LIST_REMOVE(entry, next);
677 for (entry = LIST_FIRST(&pool->free_list);
678 entry && (next_entry = LIST_NEXT(entry, next), 1);
679 entry = next_entry) {
680 LIST_REMOVE(entry, next);
687 LIST_INIT(&pool->alloc_list);
688 LIST_INIT(&pool->free_list);
692 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
694 /* Set VSI LUT selection */
695 info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
696 ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
697 /* Set Hash scheme */
698 info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
699 ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
701 info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
704 static enum ice_status
705 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
706 struct ice_aqc_vsi_props *info,
707 uint8_t enabled_tcmap)
709 uint16_t bsf, qp_idx;
711 /* default tc 0 now. Multi-TC supporting need to be done later.
712 * Configure TC and queue mapping parameters, for enabled TC,
713 * allocate qpnum_per_tc queues to this traffic.
715 if (enabled_tcmap != 0x01) {
716 PMD_INIT_LOG(ERR, "only TC0 is supported");
720 vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
721 bsf = rte_bsf32(vsi->nb_qps);
722 /* Adjust the queue number to actual queues that can be applied */
723 vsi->nb_qps = 0x1 << bsf;
726 /* Set tc and queue mapping with VSI */
727 info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
728 ICE_AQ_VSI_TC_Q_OFFSET_S) |
729 (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
731 /* Associate queue number with VSI */
732 info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
733 info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
734 info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
735 info->valid_sections |=
736 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
737 /* Set the info.ingress_table and info.egress_table
738 * for UP translate table. Now just set it to 1:1 map by default
739 * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
741 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
742 info->ingress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
743 info->egress_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
744 info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
749 ice_init_mac_address(struct rte_eth_dev *dev)
751 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
753 if (!rte_is_unicast_ether_addr
754 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
755 PMD_INIT_LOG(ERR, "Invalid MAC address");
760 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
761 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
763 dev->data->mac_addrs =
764 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
765 if (!dev->data->mac_addrs) {
767 "Failed to allocate memory to store mac address");
770 /* store it to dev data */
772 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
773 &dev->data->mac_addrs[0]);
777 /* Find out specific MAC filter */
778 static struct ice_mac_filter *
779 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
781 struct ice_mac_filter *f;
783 TAILQ_FOREACH(f, &vsi->mac_list, next) {
784 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
792 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
794 struct ice_fltr_list_entry *m_list_itr = NULL;
795 struct ice_mac_filter *f;
796 struct LIST_HEAD_TYPE list_head;
797 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
800 /* If it's added and configured, return */
801 f = ice_find_mac_filter(vsi, mac_addr);
803 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
807 INIT_LIST_HEAD(&list_head);
809 m_list_itr = (struct ice_fltr_list_entry *)
810 ice_malloc(hw, sizeof(*m_list_itr));
815 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
816 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
817 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
818 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
819 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
820 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
821 m_list_itr->fltr_info.vsi_handle = vsi->idx;
823 LIST_ADD(&m_list_itr->list_entry, &list_head);
826 ret = ice_add_mac(hw, &list_head);
827 if (ret != ICE_SUCCESS) {
828 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
832 /* Add the mac addr into mac list */
833 f = rte_zmalloc(NULL, sizeof(*f), 0);
835 PMD_DRV_LOG(ERR, "failed to allocate memory");
839 rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
840 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
846 rte_free(m_list_itr);
851 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
853 struct ice_fltr_list_entry *m_list_itr = NULL;
854 struct ice_mac_filter *f;
855 struct LIST_HEAD_TYPE list_head;
856 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
859 /* Can't find it, return an error */
860 f = ice_find_mac_filter(vsi, mac_addr);
864 INIT_LIST_HEAD(&list_head);
866 m_list_itr = (struct ice_fltr_list_entry *)
867 ice_malloc(hw, sizeof(*m_list_itr));
872 ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
873 mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
874 m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
875 m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
876 m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
877 m_list_itr->fltr_info.flag = ICE_FLTR_TX;
878 m_list_itr->fltr_info.vsi_handle = vsi->idx;
880 LIST_ADD(&m_list_itr->list_entry, &list_head);
882 /* remove the mac filter */
883 ret = ice_remove_mac(hw, &list_head);
884 if (ret != ICE_SUCCESS) {
885 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
890 /* Remove the mac addr from mac list */
891 TAILQ_REMOVE(&vsi->mac_list, f, next);
897 rte_free(m_list_itr);
901 /* Find out specific VLAN filter */
902 static struct ice_vlan_filter *
903 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
905 struct ice_vlan_filter *f;
907 TAILQ_FOREACH(f, &vsi->vlan_list, next) {
908 if (vlan_id == f->vlan_info.vlan_id)
916 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
918 struct ice_fltr_list_entry *v_list_itr = NULL;
919 struct ice_vlan_filter *f;
920 struct LIST_HEAD_TYPE list_head;
924 if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
927 hw = ICE_VSI_TO_HW(vsi);
929 /* If it's added and configured, return. */
930 f = ice_find_vlan_filter(vsi, vlan_id);
932 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
936 if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
939 INIT_LIST_HEAD(&list_head);
941 v_list_itr = (struct ice_fltr_list_entry *)
942 ice_malloc(hw, sizeof(*v_list_itr));
947 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
948 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
949 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
950 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
951 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
952 v_list_itr->fltr_info.vsi_handle = vsi->idx;
954 LIST_ADD(&v_list_itr->list_entry, &list_head);
957 ret = ice_add_vlan(hw, &list_head);
958 if (ret != ICE_SUCCESS) {
959 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
964 /* Add vlan into vlan list */
965 f = rte_zmalloc(NULL, sizeof(*f), 0);
967 PMD_DRV_LOG(ERR, "failed to allocate memory");
971 f->vlan_info.vlan_id = vlan_id;
972 TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
978 rte_free(v_list_itr);
983 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
985 struct ice_fltr_list_entry *v_list_itr = NULL;
986 struct ice_vlan_filter *f;
987 struct LIST_HEAD_TYPE list_head;
992 * Vlan 0 is the generic filter for untagged packets
993 * and can't be removed.
995 if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
998 hw = ICE_VSI_TO_HW(vsi);
1000 /* Can't find it, return an error */
1001 f = ice_find_vlan_filter(vsi, vlan_id);
1005 INIT_LIST_HEAD(&list_head);
1007 v_list_itr = (struct ice_fltr_list_entry *)
1008 ice_malloc(hw, sizeof(*v_list_itr));
1014 v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1015 v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1016 v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1017 v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1018 v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1019 v_list_itr->fltr_info.vsi_handle = vsi->idx;
1021 LIST_ADD(&v_list_itr->list_entry, &list_head);
1023 /* remove the vlan filter */
1024 ret = ice_remove_vlan(hw, &list_head);
1025 if (ret != ICE_SUCCESS) {
1026 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1031 /* Remove the vlan id from vlan list */
1032 TAILQ_REMOVE(&vsi->vlan_list, f, next);
1038 rte_free(v_list_itr);
1043 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1045 struct ice_mac_filter *m_f;
1046 struct ice_vlan_filter *v_f;
1049 if (!vsi || !vsi->mac_num)
1052 TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1053 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1054 if (ret != ICE_SUCCESS) {
1060 if (vsi->vlan_num == 0)
1063 TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1064 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1065 if (ret != ICE_SUCCESS) {
1076 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
1078 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1079 struct ice_vsi_ctx ctxt;
1083 /* Check if it has been already on or off */
1084 if (vsi->info.valid_sections &
1085 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1087 if ((vsi->info.outer_tag_flags &
1088 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
1089 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
1090 return 0; /* already on */
1092 if (!(vsi->info.outer_tag_flags &
1093 ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
1094 return 0; /* already off */
1099 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
1102 /* clear global insertion and use per packet insertion */
1103 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
1104 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
1105 vsi->info.outer_tag_flags |= qinq_flags;
1106 /* use default vlan type 0x8100 */
1107 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1108 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1109 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1110 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1111 ctxt.info.valid_sections =
1112 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1113 ctxt.vsi_num = vsi->vsi_id;
1114 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1117 "Update VSI failed to %s qinq stripping",
1118 on ? "enable" : "disable");
1122 vsi->info.valid_sections |=
1123 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1129 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
1131 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1132 struct ice_vsi_ctx ctxt;
1136 /* Check if it has been already on or off */
1137 if (vsi->info.valid_sections &
1138 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
1140 if ((vsi->info.outer_tag_flags &
1141 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1142 ICE_AQ_VSI_OUTER_TAG_COPY)
1143 return 0; /* already on */
1145 if ((vsi->info.outer_tag_flags &
1146 ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
1147 ICE_AQ_VSI_OUTER_TAG_NOTHING)
1148 return 0; /* already off */
1153 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
1155 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
1156 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
1157 vsi->info.outer_tag_flags |= qinq_flags;
1158 /* use default vlan type 0x8100 */
1159 vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
1160 vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
1161 ICE_AQ_VSI_OUTER_TAG_TYPE_S;
1162 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
1163 ctxt.info.valid_sections =
1164 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1165 ctxt.vsi_num = vsi->vsi_id;
1166 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
1169 "Update VSI failed to %s qinq stripping",
1170 on ? "enable" : "disable");
1174 vsi->info.valid_sections |=
1175 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
1181 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
1185 ret = ice_vsi_config_qinq_stripping(vsi, on);
1187 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
1189 ret = ice_vsi_config_qinq_insertion(vsi, on);
1191 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
1198 ice_pf_enable_irq0(struct ice_hw *hw)
1200 /* reset the registers */
1201 ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1202 ICE_READ_REG(hw, PFINT_OICR);
1205 ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1206 (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1207 (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1209 ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1210 (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1211 ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1212 PFINT_OICR_CTL_ITR_INDX_M) |
1213 PFINT_OICR_CTL_CAUSE_ENA_M);
1215 ICE_WRITE_REG(hw, PFINT_FW_CTL,
1216 (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1217 ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1218 PFINT_FW_CTL_ITR_INDX_M) |
1219 PFINT_FW_CTL_CAUSE_ENA_M);
1221 ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1224 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1225 GLINT_DYN_CTL_INTENA_M |
1226 GLINT_DYN_CTL_CLEARPBA_M |
1227 GLINT_DYN_CTL_ITR_INDX_M);
1234 ice_pf_disable_irq0(struct ice_hw *hw)
1236 /* Disable all interrupt types */
1237 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1243 ice_handle_aq_msg(struct rte_eth_dev *dev)
1245 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1246 struct ice_ctl_q_info *cq = &hw->adminq;
1247 struct ice_rq_event_info event;
1248 uint16_t pending, opcode;
1251 event.buf_len = ICE_AQ_MAX_BUF_LEN;
1252 event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1253 if (!event.msg_buf) {
1254 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1260 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1262 if (ret != ICE_SUCCESS) {
1264 "Failed to read msg from AdminQ, "
1266 hw->adminq.sq_last_status);
1269 opcode = rte_le_to_cpu_16(event.desc.opcode);
1272 case ice_aqc_opc_get_link_status:
1273 ret = ice_link_update(dev, 0);
1275 _rte_eth_dev_callback_process
1276 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1279 PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1284 rte_free(event.msg_buf);
1289 * Interrupt handler triggered by NIC for handling
1290 * specific interrupt.
1293 * Pointer to interrupt handle.
1295 * The address of parameter (struct rte_eth_dev *) regsitered before.
1301 ice_interrupt_handler(void *param)
1303 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1304 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1312 uint32_t int_fw_ctl;
1315 /* Disable interrupt */
1316 ice_pf_disable_irq0(hw);
1318 /* read out interrupt causes */
1319 oicr = ICE_READ_REG(hw, PFINT_OICR);
1321 int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1324 /* No interrupt event indicated */
1325 if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1326 PMD_DRV_LOG(INFO, "No interrupt event");
1331 if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1332 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1333 ice_handle_aq_msg(dev);
1336 if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1337 PMD_DRV_LOG(INFO, "OICR: link state change event");
1338 ret = ice_link_update(dev, 0);
1340 _rte_eth_dev_callback_process
1341 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1345 if (oicr & PFINT_OICR_MAL_DETECT_M) {
1346 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1347 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1348 if (reg & GL_MDET_TX_PQM_VALID_M) {
1349 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1350 GL_MDET_TX_PQM_PF_NUM_S;
1351 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1352 GL_MDET_TX_PQM_MAL_TYPE_S;
1353 queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1354 GL_MDET_TX_PQM_QNUM_S;
1356 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1357 "%d by PQM on TX queue %d PF# %d",
1358 event, queue, pf_num);
1361 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1362 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1363 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1364 GL_MDET_TX_TCLAN_PF_NUM_S;
1365 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1366 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1367 queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1368 GL_MDET_TX_TCLAN_QNUM_S;
1370 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1371 "%d by TCLAN on TX queue %d PF# %d",
1372 event, queue, pf_num);
1376 /* Enable interrupt */
1377 ice_pf_enable_irq0(hw);
1378 rte_intr_ack(dev->intr_handle);
1382 ice_init_proto_xtr(struct rte_eth_dev *dev)
1384 struct ice_adapter *ad =
1385 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1386 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1387 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1390 if (!ice_proto_xtr_support(hw)) {
1391 PMD_DRV_LOG(NOTICE, "Protocol extraction is not supported");
1395 pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1396 if (unlikely(pf->proto_xtr == NULL)) {
1397 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1401 for (i = 0; i < pf->lan_nb_qps; i++)
1402 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1403 ad->devargs.proto_xtr[i] :
1404 ad->devargs.proto_xtr_dflt;
1407 /* Initialize SW parameters of PF */
1409 ice_pf_sw_init(struct rte_eth_dev *dev)
1411 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1412 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1415 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1416 hw->func_caps.common_cap.num_rxq);
1418 pf->lan_nb_qps = pf->lan_nb_qp_max;
1420 ice_init_proto_xtr(dev);
1422 if (hw->func_caps.fd_fltr_guar > 0 ||
1423 hw->func_caps.fd_fltr_best_effort > 0) {
1424 pf->flags |= ICE_FLAG_FDIR;
1425 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1426 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1428 pf->fdir_nb_qps = 0;
1430 pf->fdir_qp_offset = 0;
1436 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1438 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1439 struct ice_vsi *vsi = NULL;
1440 struct ice_vsi_ctx vsi_ctx;
1442 struct rte_ether_addr broadcast = {
1443 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1444 struct rte_ether_addr mac_addr;
1445 uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1446 uint8_t tc_bitmap = 0x1;
1449 /* hw->num_lports = 1 in NIC mode */
1450 vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1454 vsi->idx = pf->next_vsi_idx;
1457 vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1458 vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1459 vsi->vlan_anti_spoof_on = 0;
1460 vsi->vlan_filter_on = 1;
1461 TAILQ_INIT(&vsi->mac_list);
1462 TAILQ_INIT(&vsi->vlan_list);
1464 /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1465 pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1466 ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1467 hw->func_caps.common_cap.rss_table_size;
1468 pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1470 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1473 vsi->nb_qps = pf->lan_nb_qps;
1474 vsi->base_queue = 1;
1475 ice_vsi_config_default_rss(&vsi_ctx.info);
1476 vsi_ctx.alloc_from_pool = true;
1477 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1478 /* switch_id is queried by get_switch_config aq, which is done
1481 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1482 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1483 /* Allow all untagged or tagged packets */
1484 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1485 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1486 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1487 ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1490 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1491 ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1492 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1493 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1494 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1495 vsi_ctx.info.max_fd_fltr_dedicated =
1496 rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1497 vsi_ctx.info.max_fd_fltr_shared =
1498 rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1500 /* Enable VLAN/UP trip */
1501 ret = ice_vsi_config_tc_queue_mapping(vsi,
1506 "tc queue mapping with vsi failed, "
1514 vsi->nb_qps = pf->fdir_nb_qps;
1515 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1516 vsi_ctx.alloc_from_pool = true;
1517 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1519 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1520 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1521 cfg = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
1522 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1523 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1524 ret = ice_vsi_config_tc_queue_mapping(vsi,
1529 "tc queue mapping with vsi failed, "
1536 /* for other types of VSI */
1537 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1541 /* VF has MSIX interrupt in VF range, don't allocate here */
1542 if (type == ICE_VSI_PF) {
1543 ret = ice_res_pool_alloc(&pf->msix_pool,
1544 RTE_MIN(vsi->nb_qps,
1545 RTE_MAX_RXTX_INTR_VEC_ID));
1547 PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1550 vsi->msix_intr = ret;
1551 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1552 } else if (type == ICE_VSI_CTRL) {
1553 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1555 PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1558 vsi->msix_intr = ret;
1564 ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1565 if (ret != ICE_SUCCESS) {
1566 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1569 /* store vsi information is SW structure */
1570 vsi->vsi_id = vsi_ctx.vsi_num;
1571 vsi->info = vsi_ctx.info;
1572 pf->vsis_allocated = vsi_ctx.vsis_allocd;
1573 pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1575 if (type == ICE_VSI_PF) {
1576 /* MAC configuration */
1577 rte_memcpy(pf->dev_addr.addr_bytes,
1578 hw->port_info->mac.perm_addr,
1581 rte_memcpy(&mac_addr, &pf->dev_addr, RTE_ETHER_ADDR_LEN);
1582 ret = ice_add_mac_filter(vsi, &mac_addr);
1583 if (ret != ICE_SUCCESS)
1584 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1586 rte_memcpy(&mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
1587 ret = ice_add_mac_filter(vsi, &mac_addr);
1588 if (ret != ICE_SUCCESS)
1589 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1592 /* At the beginning, only TC0. */
1593 /* What we need here is the maximam number of the TX queues.
1594 * Currently vsi->nb_qps means it.
1595 * Correct it if any change.
1597 max_txqs[0] = vsi->nb_qps;
1598 ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1599 tc_bitmap, max_txqs);
1600 if (ret != ICE_SUCCESS)
1601 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1611 ice_send_driver_ver(struct ice_hw *hw)
1613 struct ice_driver_ver dv;
1615 /* we don't have driver version use 0 for dummy */
1619 dv.subbuild_ver = 0;
1620 strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1622 return ice_aq_send_driver_ver(hw, &dv, NULL);
1626 ice_pf_setup(struct ice_pf *pf)
1628 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1629 struct ice_vsi *vsi;
1632 /* Clear all stats counters */
1633 pf->offset_loaded = FALSE;
1634 memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1635 memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1636 memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1637 memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1639 /* force guaranteed filter pool for PF */
1640 ice_alloc_fd_guar_item(hw, &unused,
1641 hw->func_caps.fd_fltr_guar);
1642 /* force shared filter pool for PF */
1643 ice_alloc_fd_shrd_item(hw, &unused,
1644 hw->func_caps.fd_fltr_best_effort);
1646 vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1648 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1657 /* PCIe configuration space setting */
1658 #define PCI_CFG_SPACE_SIZE 256
1659 #define PCI_CFG_SPACE_EXP_SIZE 4096
1660 #define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff)
1661 #define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc)
1662 #define PCI_EXT_CAP_ID_DSN 0x03
1665 ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap)
1669 int pos = PCI_CFG_SPACE_SIZE;
1671 /* minimum 8 bytes per capability */
1672 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1674 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1675 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1680 * If we have no capabilities, this is indicated by cap ID,
1681 * cap version and next pointer all being 0.
1687 if (PCI_EXT_CAP_ID(header) == cap)
1690 pos = PCI_EXT_CAP_NEXT(header);
1692 if (pos < PCI_CFG_SPACE_SIZE)
1695 if (rte_pci_read_config(dev, &header, 4, pos) < 0) {
1696 PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n");
1705 * Extract device serial number from PCIe Configuration Space and
1706 * determine the pkg file path according to the DSN.
1709 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1712 char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1713 uint32_t dsn_low, dsn_high;
1714 memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1716 pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN);
1719 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1720 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1721 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1722 "ice-%08x%08x.pkg", dsn_high, dsn_low);
1724 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1728 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1729 ICE_MAX_PKG_FILENAME_SIZE);
1730 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1733 strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1734 ICE_MAX_PKG_FILENAME_SIZE);
1735 if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1739 strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1740 if (!access(pkg_file, 0))
1742 strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1746 static enum ice_pkg_type
1747 ice_load_pkg_type(struct ice_hw *hw)
1749 enum ice_pkg_type package_type;
1751 /* store the activated package type (OS default or Comms) */
1752 if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1754 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1755 else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1757 package_type = ICE_PKG_TYPE_COMMS;
1759 package_type = ICE_PKG_TYPE_UNKNOWN;
1761 PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1762 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1763 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1764 hw->active_pkg_name);
1766 return package_type;
1769 static int ice_load_pkg(struct rte_eth_dev *dev)
1771 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772 char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1778 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1779 struct ice_adapter *ad =
1780 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1782 ice_pkg_file_search_path(pci_dev, pkg_file);
1784 file = fopen(pkg_file, "rb");
1786 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1790 err = stat(pkg_file, &fstat);
1792 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1797 buf_len = fstat.st_size;
1798 buf = rte_malloc(NULL, buf_len, 0);
1801 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1807 err = fread(buf, buf_len, 1, file);
1809 PMD_INIT_LOG(ERR, "failed to read package data\n");
1817 err = ice_copy_and_init_pkg(hw, buf, buf_len);
1819 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1823 /* store the loaded pkg type info */
1824 ad->active_pkg_type = ice_load_pkg_type(hw);
1826 err = ice_init_hw_tbls(hw);
1828 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1829 goto fail_init_tbls;
1835 rte_free(hw->pkg_copy);
1842 ice_base_queue_get(struct ice_pf *pf)
1845 struct ice_hw *hw = ICE_PF_TO_HW(pf);
1847 reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1848 if (reg & PFLAN_RX_QALLOC_VALID_M) {
1849 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1851 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1857 parse_bool(const char *key, const char *value, void *args)
1859 int *i = (int *)args;
1863 num = strtoul(value, &end, 10);
1865 if (num != 0 && num != 1) {
1866 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1867 "value must be 0 or 1",
1876 static int ice_parse_devargs(struct rte_eth_dev *dev)
1878 struct ice_adapter *ad =
1879 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1880 struct rte_devargs *devargs = dev->device->devargs;
1881 struct rte_kvargs *kvlist;
1884 if (devargs == NULL)
1887 kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1888 if (kvlist == NULL) {
1889 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1893 ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1894 memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1895 sizeof(ad->devargs.proto_xtr));
1897 ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1898 &handle_proto_xtr_arg, &ad->devargs);
1902 ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1903 &parse_bool, &ad->devargs.safe_mode_support);
1907 ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1908 &parse_bool, &ad->devargs.pipe_mode_support);
1911 rte_kvargs_free(kvlist);
1915 /* Forward LLDP packets to default VSI by set switch rules */
1917 ice_vsi_config_sw_lldp(struct ice_vsi *vsi, bool on)
1919 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1920 struct ice_fltr_list_entry *s_list_itr = NULL;
1921 struct LIST_HEAD_TYPE list_head;
1924 INIT_LIST_HEAD(&list_head);
1926 s_list_itr = (struct ice_fltr_list_entry *)
1927 ice_malloc(hw, sizeof(*s_list_itr));
1930 s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1931 s_list_itr->fltr_info.vsi_handle = vsi->idx;
1932 s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1933 RTE_ETHER_TYPE_LLDP;
1934 s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1935 s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1936 s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1937 LIST_ADD(&s_list_itr->list_entry, &list_head);
1939 ret = ice_add_eth_mac(hw, &list_head);
1941 ret = ice_remove_eth_mac(hw, &list_head);
1943 rte_free(s_list_itr);
1947 static enum ice_status
1948 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1949 uint16_t num, uint16_t desc_id,
1950 uint16_t *prof_buf, uint16_t *num_prof)
1952 struct ice_aqc_get_allocd_res_desc_resp *resp_buf;
1955 bool res_shared = 1;
1956 struct ice_aq_desc aq_desc;
1957 struct ice_sq_cd *cd = NULL;
1958 struct ice_aqc_get_allocd_res_desc *cmd =
1959 &aq_desc.params.get_res_desc;
1961 buf_len = sizeof(resp_buf->elem) * num;
1962 resp_buf = ice_malloc(hw, buf_len);
1966 ice_fill_dflt_direct_cmd_desc(&aq_desc,
1967 ice_aqc_opc_get_allocd_res_desc);
1969 cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1970 ICE_AQC_RES_TYPE_M) | (res_shared ?
1971 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1972 cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1974 ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1976 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1980 ice_memcpy(prof_buf, resp_buf->elem, sizeof(resp_buf->elem) *
1981 (*num_prof), ICE_NONDMA_TO_NONDMA);
1988 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1992 uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1993 uint16_t first_desc = 1;
1994 uint16_t num_prof = 0;
1996 ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1997 first_desc, prof_buf, &num_prof);
1999 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
2003 for (prof_id = 0; prof_id < num_prof; prof_id++) {
2004 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
2006 PMD_INIT_LOG(ERR, "Failed to free fxp resource");
2014 ice_reset_fxp_resource(struct ice_hw *hw)
2018 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
2020 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
2024 ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
2026 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
2034 ice_dev_init(struct rte_eth_dev *dev)
2036 struct rte_pci_device *pci_dev;
2037 struct rte_intr_handle *intr_handle;
2038 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2039 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2040 struct ice_adapter *ad =
2041 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2042 struct ice_vsi *vsi;
2045 dev->dev_ops = &ice_eth_dev_ops;
2046 dev->rx_pkt_burst = ice_recv_pkts;
2047 dev->tx_pkt_burst = ice_xmit_pkts;
2048 dev->tx_pkt_prepare = ice_prep_pkts;
2050 /* for secondary processes, we don't initialise any further as primary
2051 * has already done this work.
2053 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2054 ice_set_rx_function(dev);
2055 ice_set_tx_function(dev);
2059 ice_set_default_ptype_table(dev);
2060 pci_dev = RTE_DEV_TO_PCI(dev->device);
2061 intr_handle = &pci_dev->intr_handle;
2063 pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2064 pf->adapter->eth_dev = dev;
2065 pf->dev_data = dev->data;
2066 hw->back = pf->adapter;
2067 hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2068 hw->vendor_id = pci_dev->id.vendor_id;
2069 hw->device_id = pci_dev->id.device_id;
2070 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2071 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2072 hw->bus.device = pci_dev->addr.devid;
2073 hw->bus.func = pci_dev->addr.function;
2075 ret = ice_parse_devargs(dev);
2077 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2081 ice_init_controlq_parameter(hw);
2083 ret = ice_init_hw(hw);
2085 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2089 ret = ice_load_pkg(dev);
2091 if (ad->devargs.safe_mode_support == 0) {
2092 PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2093 "Use safe-mode-support=1 to enter Safe Mode");
2097 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2098 "Entering Safe Mode");
2099 ad->is_safe_mode = 1;
2102 PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2103 hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2104 hw->api_maj_ver, hw->api_min_ver);
2106 ice_pf_sw_init(dev);
2107 ret = ice_init_mac_address(dev);
2109 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2113 /* Pass the information to the rte_eth_dev_close() that it should also
2114 * release the private port resources.
2116 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
2118 ret = ice_res_pool_init(&pf->msix_pool, 1,
2119 hw->func_caps.common_cap.num_msix_vectors - 1);
2121 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2122 goto err_msix_pool_init;
2125 ret = ice_pf_setup(pf);
2127 PMD_INIT_LOG(ERR, "Failed to setup PF");
2131 ret = ice_send_driver_ver(hw);
2133 PMD_INIT_LOG(ERR, "Failed to send driver version");
2139 /* Disable double vlan by default */
2140 ice_vsi_config_double_vlan(vsi, FALSE);
2142 ret = ice_aq_stop_lldp(hw, TRUE, FALSE, NULL);
2143 if (ret != ICE_SUCCESS)
2144 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2145 ret = ice_init_dcb(hw, TRUE);
2146 if (ret != ICE_SUCCESS)
2147 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2148 /* Forward LLDP packets to default VSI */
2149 ret = ice_vsi_config_sw_lldp(vsi, TRUE);
2150 if (ret != ICE_SUCCESS)
2151 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2152 /* register callback func to eal lib */
2153 rte_intr_callback_register(intr_handle,
2154 ice_interrupt_handler, dev);
2156 ice_pf_enable_irq0(hw);
2158 /* enable uio intr after callback register */
2159 rte_intr_enable(intr_handle);
2161 /* get base queue pairs index in the device */
2162 ice_base_queue_get(pf);
2164 ret = ice_flow_init(ad);
2166 PMD_INIT_LOG(ERR, "Failed to initialize flow");
2170 ret = ice_reset_fxp_resource(hw);
2172 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2179 ice_res_pool_destroy(&pf->msix_pool);
2181 rte_free(dev->data->mac_addrs);
2182 dev->data->mac_addrs = NULL;
2184 ice_sched_cleanup_all(hw);
2185 rte_free(hw->port_info);
2186 ice_shutdown_all_ctrlq(hw);
2187 rte_free(pf->proto_xtr);
2193 ice_release_vsi(struct ice_vsi *vsi)
2196 struct ice_vsi_ctx vsi_ctx;
2197 enum ice_status ret;
2202 hw = ICE_VSI_TO_HW(vsi);
2204 ice_remove_all_mac_vlan_filters(vsi);
2206 memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2208 vsi_ctx.vsi_num = vsi->vsi_id;
2209 vsi_ctx.info = vsi->info;
2210 ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2211 if (ret != ICE_SUCCESS) {
2212 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2222 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2224 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2225 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2226 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2227 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2228 uint16_t msix_intr, i;
2230 /* disable interrupt and also clear all the exist config */
2231 for (i = 0; i < vsi->nb_qps; i++) {
2232 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2233 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2237 if (rte_intr_allow_others(intr_handle))
2239 for (i = 0; i < vsi->nb_msix; i++) {
2240 msix_intr = vsi->msix_intr + i;
2241 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2242 GLINT_DYN_CTL_WB_ON_ITR_M);
2246 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2250 ice_dev_stop(struct rte_eth_dev *dev)
2252 struct rte_eth_dev_data *data = dev->data;
2253 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2254 struct ice_vsi *main_vsi = pf->main_vsi;
2255 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2256 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2259 /* avoid stopping again */
2260 if (pf->adapter_stopped)
2263 /* stop and clear all Rx queues */
2264 for (i = 0; i < data->nb_rx_queues; i++)
2265 ice_rx_queue_stop(dev, i);
2267 /* stop and clear all Tx queues */
2268 for (i = 0; i < data->nb_tx_queues; i++)
2269 ice_tx_queue_stop(dev, i);
2271 /* disable all queue interrupts */
2272 ice_vsi_disable_queues_intr(main_vsi);
2274 if (pf->fdir.fdir_vsi)
2275 ice_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2277 /* Clear all queues and release mbufs */
2278 ice_clear_queues(dev);
2280 ice_dev_set_link_down(dev);
2282 /* Clean datapath event and queue/vec mapping */
2283 rte_intr_efd_disable(intr_handle);
2284 if (intr_handle->intr_vec) {
2285 rte_free(intr_handle->intr_vec);
2286 intr_handle->intr_vec = NULL;
2289 pf->adapter_stopped = true;
2293 ice_dev_close(struct rte_eth_dev *dev)
2295 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2296 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2297 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2298 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2299 struct ice_adapter *ad =
2300 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2302 /* Since stop will make link down, then the link event will be
2303 * triggered, disable the irq firstly to avoid the port_infoe etc
2304 * resources deallocation causing the interrupt service thread
2307 ice_pf_disable_irq0(hw);
2311 ice_flow_uninit(ad);
2313 /* release all queue resource */
2314 ice_free_queues(dev);
2316 ice_res_pool_destroy(&pf->msix_pool);
2317 ice_release_vsi(pf->main_vsi);
2318 ice_sched_cleanup_all(hw);
2319 rte_free(hw->port_info);
2320 hw->port_info = NULL;
2321 ice_shutdown_all_ctrlq(hw);
2322 rte_free(pf->proto_xtr);
2323 pf->proto_xtr = NULL;
2325 dev->dev_ops = NULL;
2326 dev->rx_pkt_burst = NULL;
2327 dev->tx_pkt_burst = NULL;
2329 rte_free(dev->data->mac_addrs);
2330 dev->data->mac_addrs = NULL;
2332 /* disable uio intr before callback unregister */
2333 rte_intr_disable(intr_handle);
2335 /* unregister callback func from eal lib */
2336 rte_intr_callback_unregister(intr_handle,
2337 ice_interrupt_handler, dev);
2341 ice_dev_uninit(struct rte_eth_dev *dev)
2349 ice_dev_configure(struct rte_eth_dev *dev)
2351 struct ice_adapter *ad =
2352 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2354 /* Initialize to TRUE. If any of Rx queues doesn't meet the
2355 * bulk allocation or vector Rx preconditions we will reset it.
2357 ad->rx_bulk_alloc_allowed = true;
2358 ad->tx_simple_allowed = true;
2363 static int ice_init_rss(struct ice_pf *pf)
2365 struct ice_hw *hw = ICE_PF_TO_HW(pf);
2366 struct ice_vsi *vsi = pf->main_vsi;
2367 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2368 struct rte_eth_rss_conf *rss_conf;
2369 struct ice_aqc_get_set_rss_keys key;
2372 bool is_safe_mode = pf->adapter->is_safe_mode;
2374 rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
2375 nb_q = dev->data->nb_rx_queues;
2376 vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
2377 vsi->rss_lut_size = pf->hash_lut_size;
2380 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
2385 vsi->rss_key = rte_zmalloc(NULL,
2386 vsi->rss_key_size, 0);
2388 vsi->rss_lut = rte_zmalloc(NULL,
2389 vsi->rss_lut_size, 0);
2391 /* configure RSS key */
2392 if (!rss_conf->rss_key) {
2393 /* Calculate the default hash key */
2394 for (i = 0; i <= vsi->rss_key_size; i++)
2395 vsi->rss_key[i] = (uint8_t)rte_rand();
2397 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
2398 RTE_MIN(rss_conf->rss_key_len,
2399 vsi->rss_key_size));
2401 rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
2402 ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
2406 /* init RSS LUT table */
2407 for (i = 0; i < vsi->rss_lut_size; i++)
2408 vsi->rss_lut[i] = i % nb_q;
2410 ret = ice_aq_set_rss_lut(hw, vsi->idx,
2411 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
2412 vsi->rss_lut, vsi->rss_lut_size);
2416 /* configure RSS for IPv4 with input set IPv4 src/dst */
2417 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2418 ICE_FLOW_SEG_HDR_IPV4, 0);
2420 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
2422 /* configure RSS for IPv6 with input set IPv6 src/dst */
2423 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2424 ICE_FLOW_SEG_HDR_IPV6, 0);
2426 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
2428 /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
2429 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
2430 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6, 0);
2432 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
2434 /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
2435 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
2436 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6, 0);
2438 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
2440 /* configure RSS for sctp6 with input set IPv6 src/dst */
2441 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
2442 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6, 0);
2444 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2447 /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
2448 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
2449 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4, 0);
2451 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
2453 /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
2454 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
2455 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4, 0);
2457 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
2459 /* configure RSS for sctp4 with input set IP src/dst */
2460 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
2461 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4, 0);
2463 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2466 /* configure RSS for gtpu with input set TEID */
2467 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_GTP_U_IPV4_TEID,
2468 ICE_FLOW_SEG_HDR_GTPU_IP, 0);
2470 PMD_DRV_LOG(ERR, "%s GTPU_TEID rss flow fail %d",
2474 * configure RSS for pppoe/pppod with input set
2475 * Source MAC and Session ID
2477 ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_PPPOE_SESS_ID_ETH,
2478 ICE_FLOW_SEG_HDR_PPPOE, 0);
2480 PMD_DRV_LOG(ERR, "%s PPPoE/PPPoD_SessionID rss flow fail %d",
2487 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
2488 int base_queue, int nb_queue)
2490 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2491 uint32_t val, val_tx;
2494 for (i = 0; i < nb_queue; i++) {
2496 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
2497 (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
2498 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
2499 (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
2501 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
2502 base_queue + i, msix_vect);
2503 /* set ITR0 value */
2504 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
2505 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
2506 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
2511 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
2513 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2514 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2515 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2516 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2517 uint16_t msix_vect = vsi->msix_intr;
2518 uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2519 uint16_t queue_idx = 0;
2523 /* clear Rx/Tx queue interrupt */
2524 for (i = 0; i < vsi->nb_used_qps; i++) {
2525 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2526 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2529 /* PF bind interrupt */
2530 if (rte_intr_dp_is_en(intr_handle)) {
2535 for (i = 0; i < vsi->nb_used_qps; i++) {
2537 if (!rte_intr_allow_others(intr_handle))
2538 msix_vect = ICE_MISC_VEC_ID;
2540 /* uio mapping all queue to one msix_vect */
2541 __vsi_queues_bind_intr(vsi, msix_vect,
2542 vsi->base_queue + i,
2543 vsi->nb_used_qps - i);
2545 for (; !!record && i < vsi->nb_used_qps; i++)
2546 intr_handle->intr_vec[queue_idx + i] =
2551 /* vfio 1:1 queue/msix_vect mapping */
2552 __vsi_queues_bind_intr(vsi, msix_vect,
2553 vsi->base_queue + i, 1);
2556 intr_handle->intr_vec[queue_idx + i] = msix_vect;
2564 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
2566 struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2567 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2568 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2569 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2570 uint16_t msix_intr, i;
2572 if (rte_intr_allow_others(intr_handle))
2573 for (i = 0; i < vsi->nb_used_qps; i++) {
2574 msix_intr = vsi->msix_intr + i;
2575 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2576 GLINT_DYN_CTL_INTENA_M |
2577 GLINT_DYN_CTL_CLEARPBA_M |
2578 GLINT_DYN_CTL_ITR_INDX_M |
2579 GLINT_DYN_CTL_WB_ON_ITR_M);
2582 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
2583 GLINT_DYN_CTL_INTENA_M |
2584 GLINT_DYN_CTL_CLEARPBA_M |
2585 GLINT_DYN_CTL_ITR_INDX_M |
2586 GLINT_DYN_CTL_WB_ON_ITR_M);
2590 ice_rxq_intr_setup(struct rte_eth_dev *dev)
2592 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2593 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2594 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2595 struct ice_vsi *vsi = pf->main_vsi;
2596 uint32_t intr_vector = 0;
2598 rte_intr_disable(intr_handle);
2600 /* check and configure queue intr-vector mapping */
2601 if ((rte_intr_cap_multiple(intr_handle) ||
2602 !RTE_ETH_DEV_SRIOV(dev).active) &&
2603 dev->data->dev_conf.intr_conf.rxq != 0) {
2604 intr_vector = dev->data->nb_rx_queues;
2605 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
2606 PMD_DRV_LOG(ERR, "At most %d intr queues supported",
2607 ICE_MAX_INTR_QUEUE_NUM);
2610 if (rte_intr_efd_enable(intr_handle, intr_vector))
2614 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2615 intr_handle->intr_vec =
2616 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
2618 if (!intr_handle->intr_vec) {
2620 "Failed to allocate %d rx_queues intr_vec",
2621 dev->data->nb_rx_queues);
2626 /* Map queues with MSIX interrupt */
2627 vsi->nb_used_qps = dev->data->nb_rx_queues;
2628 ice_vsi_queues_bind_intr(vsi);
2630 /* Enable interrupts for all the queues */
2631 ice_vsi_enable_queues_intr(vsi);
2633 /* Enable FDIR MSIX interrupt */
2634 if (pf->fdir.fdir_vsi) {
2635 ice_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
2636 ice_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2639 rte_intr_enable(intr_handle);
2645 ice_dev_start(struct rte_eth_dev *dev)
2647 struct rte_eth_dev_data *data = dev->data;
2648 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2649 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2650 struct ice_vsi *vsi = pf->main_vsi;
2651 uint16_t nb_rxq = 0;
2655 /* program Tx queues' context in hardware */
2656 for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
2657 ret = ice_tx_queue_start(dev, nb_txq);
2659 PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
2664 /* program Rx queues' context in hardware*/
2665 for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
2666 ret = ice_rx_queue_start(dev, nb_rxq);
2668 PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
2673 ret = ice_init_rss(pf);
2675 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
2679 ice_set_rx_function(dev);
2680 ice_set_tx_function(dev);
2682 mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
2683 ETH_VLAN_EXTEND_MASK;
2684 ret = ice_vlan_offload_set(dev, mask);
2686 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
2690 /* enable Rx interrput and mapping Rx queue to interrupt vector */
2691 if (ice_rxq_intr_setup(dev))
2694 /* Enable receiving broadcast packets and transmitting packets */
2695 ret = ice_set_vsi_promisc(hw, vsi->idx,
2696 ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
2697 ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
2699 if (ret != ICE_SUCCESS)
2700 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2702 ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
2703 ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
2704 ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
2705 ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
2706 ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
2707 ICE_AQ_LINK_EVENT_AN_COMPLETED |
2708 ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
2710 if (ret != ICE_SUCCESS)
2711 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2713 ice_dev_set_link_up(dev);
2715 /* Call get_link_info aq commond to enable/disable LSE */
2716 ice_link_update(dev, 0);
2718 pf->adapter_stopped = false;
2722 /* stop the started queues if failed to start all queues */
2724 for (i = 0; i < nb_rxq; i++)
2725 ice_rx_queue_stop(dev, i);
2727 for (i = 0; i < nb_txq; i++)
2728 ice_tx_queue_stop(dev, i);
2734 ice_dev_reset(struct rte_eth_dev *dev)
2738 if (dev->data->sriov.active)
2741 ret = ice_dev_uninit(dev);
2743 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
2747 ret = ice_dev_init(dev);
2749 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2757 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2759 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2760 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2761 struct ice_vsi *vsi = pf->main_vsi;
2762 struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2763 bool is_safe_mode = pf->adapter->is_safe_mode;
2767 dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2768 dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2769 dev_info->max_rx_queues = vsi->nb_qps;
2770 dev_info->max_tx_queues = vsi->nb_qps;
2771 dev_info->max_mac_addrs = vsi->max_macaddrs;
2772 dev_info->max_vfs = pci_dev->max_vfs;
2773 dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2774 dev_info->min_mtu = RTE_ETHER_MIN_MTU;
2776 dev_info->rx_offload_capa =
2777 DEV_RX_OFFLOAD_VLAN_STRIP |
2778 DEV_RX_OFFLOAD_JUMBO_FRAME |
2779 DEV_RX_OFFLOAD_KEEP_CRC |
2780 DEV_RX_OFFLOAD_SCATTER |
2781 DEV_RX_OFFLOAD_VLAN_FILTER;
2782 dev_info->tx_offload_capa =
2783 DEV_TX_OFFLOAD_VLAN_INSERT |
2784 DEV_TX_OFFLOAD_TCP_TSO |
2785 DEV_TX_OFFLOAD_MULTI_SEGS |
2786 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2787 dev_info->flow_type_rss_offloads = 0;
2789 if (!is_safe_mode) {
2790 dev_info->rx_offload_capa |=
2791 DEV_RX_OFFLOAD_IPV4_CKSUM |
2792 DEV_RX_OFFLOAD_UDP_CKSUM |
2793 DEV_RX_OFFLOAD_TCP_CKSUM |
2794 DEV_RX_OFFLOAD_QINQ_STRIP |
2795 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2796 DEV_RX_OFFLOAD_VLAN_EXTEND;
2797 dev_info->tx_offload_capa |=
2798 DEV_TX_OFFLOAD_QINQ_INSERT |
2799 DEV_TX_OFFLOAD_IPV4_CKSUM |
2800 DEV_TX_OFFLOAD_UDP_CKSUM |
2801 DEV_TX_OFFLOAD_TCP_CKSUM |
2802 DEV_TX_OFFLOAD_SCTP_CKSUM |
2803 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
2804 DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
2805 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2808 dev_info->rx_queue_offload_capa = 0;
2809 dev_info->tx_queue_offload_capa = 0;
2811 dev_info->reta_size = pf->hash_lut_size;
2812 dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2814 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2816 .pthresh = ICE_DEFAULT_RX_PTHRESH,
2817 .hthresh = ICE_DEFAULT_RX_HTHRESH,
2818 .wthresh = ICE_DEFAULT_RX_WTHRESH,
2820 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2825 dev_info->default_txconf = (struct rte_eth_txconf) {
2827 .pthresh = ICE_DEFAULT_TX_PTHRESH,
2828 .hthresh = ICE_DEFAULT_TX_HTHRESH,
2829 .wthresh = ICE_DEFAULT_TX_WTHRESH,
2831 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2832 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2836 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2837 .nb_max = ICE_MAX_RING_DESC,
2838 .nb_min = ICE_MIN_RING_DESC,
2839 .nb_align = ICE_ALIGN_RING_DESC,
2842 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2843 .nb_max = ICE_MAX_RING_DESC,
2844 .nb_min = ICE_MIN_RING_DESC,
2845 .nb_align = ICE_ALIGN_RING_DESC,
2848 dev_info->speed_capa = ETH_LINK_SPEED_10M |
2849 ETH_LINK_SPEED_100M |
2851 ETH_LINK_SPEED_2_5G |
2853 ETH_LINK_SPEED_10G |
2854 ETH_LINK_SPEED_20G |
2857 phy_type_low = hw->port_info->phy.phy_type_low;
2858 phy_type_high = hw->port_info->phy.phy_type_high;
2860 if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2861 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2863 if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2864 ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2865 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2867 dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2868 dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2870 dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2871 dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2872 dev_info->default_rxportconf.nb_queues = 1;
2873 dev_info->default_txportconf.nb_queues = 1;
2874 dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2875 dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2881 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2882 struct rte_eth_link *link)
2884 struct rte_eth_link *dst = link;
2885 struct rte_eth_link *src = &dev->data->dev_link;
2887 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2888 *(uint64_t *)src) == 0)
2895 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2896 struct rte_eth_link *link)
2898 struct rte_eth_link *dst = &dev->data->dev_link;
2899 struct rte_eth_link *src = link;
2901 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2902 *(uint64_t *)src) == 0)
2909 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2911 #define CHECK_INTERVAL 100 /* 100ms */
2912 #define MAX_REPEAT_TIME 10 /* 1s (10 * 100ms) in total */
2913 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2914 struct ice_link_status link_status;
2915 struct rte_eth_link link, old;
2917 unsigned int rep_cnt = MAX_REPEAT_TIME;
2918 bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2920 memset(&link, 0, sizeof(link));
2921 memset(&old, 0, sizeof(old));
2922 memset(&link_status, 0, sizeof(link_status));
2923 ice_atomic_read_link_status(dev, &old);
2926 /* Get link status information from hardware */
2927 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2928 &link_status, NULL);
2929 if (status != ICE_SUCCESS) {
2930 link.link_speed = ETH_SPEED_NUM_100M;
2931 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2932 PMD_DRV_LOG(ERR, "Failed to get link info");
2936 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2937 if (!wait_to_complete || link.link_status)
2940 rte_delay_ms(CHECK_INTERVAL);
2941 } while (--rep_cnt);
2943 if (!link.link_status)
2946 /* Full-duplex operation at all supported speeds */
2947 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2949 /* Parse the link status */
2950 switch (link_status.link_speed) {
2951 case ICE_AQ_LINK_SPEED_10MB:
2952 link.link_speed = ETH_SPEED_NUM_10M;
2954 case ICE_AQ_LINK_SPEED_100MB:
2955 link.link_speed = ETH_SPEED_NUM_100M;
2957 case ICE_AQ_LINK_SPEED_1000MB:
2958 link.link_speed = ETH_SPEED_NUM_1G;
2960 case ICE_AQ_LINK_SPEED_2500MB:
2961 link.link_speed = ETH_SPEED_NUM_2_5G;
2963 case ICE_AQ_LINK_SPEED_5GB:
2964 link.link_speed = ETH_SPEED_NUM_5G;
2966 case ICE_AQ_LINK_SPEED_10GB:
2967 link.link_speed = ETH_SPEED_NUM_10G;
2969 case ICE_AQ_LINK_SPEED_20GB:
2970 link.link_speed = ETH_SPEED_NUM_20G;
2972 case ICE_AQ_LINK_SPEED_25GB:
2973 link.link_speed = ETH_SPEED_NUM_25G;
2975 case ICE_AQ_LINK_SPEED_40GB:
2976 link.link_speed = ETH_SPEED_NUM_40G;
2978 case ICE_AQ_LINK_SPEED_50GB:
2979 link.link_speed = ETH_SPEED_NUM_50G;
2981 case ICE_AQ_LINK_SPEED_100GB:
2982 link.link_speed = ETH_SPEED_NUM_100G;
2984 case ICE_AQ_LINK_SPEED_UNKNOWN:
2986 PMD_DRV_LOG(ERR, "Unknown link speed");
2987 link.link_speed = ETH_SPEED_NUM_NONE;
2991 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2992 ETH_LINK_SPEED_FIXED);
2995 ice_atomic_write_link_status(dev, &link);
2996 if (link.link_status == old.link_status)
3002 /* Force the physical link state by getting the current PHY capabilities from
3003 * hardware and setting the PHY config based on the determined capabilities. If
3004 * link changes, link event will be triggered because both the Enable Automatic
3005 * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3007 static enum ice_status
3008 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3010 struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3011 struct ice_aqc_get_phy_caps_data *pcaps;
3012 struct ice_port_info *pi;
3013 enum ice_status status;
3015 if (!hw || !hw->port_info)
3016 return ICE_ERR_PARAM;
3020 pcaps = (struct ice_aqc_get_phy_caps_data *)
3021 ice_malloc(hw, sizeof(*pcaps));
3023 return ICE_ERR_NO_MEMORY;
3025 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
3030 /* No change in link */
3031 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3032 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3035 cfg.phy_type_low = pcaps->phy_type_low;
3036 cfg.phy_type_high = pcaps->phy_type_high;
3037 cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3038 cfg.low_power_ctrl = pcaps->low_power_ctrl;
3039 cfg.eee_cap = pcaps->eee_cap;
3040 cfg.eeer_value = pcaps->eeer_value;
3041 cfg.link_fec_opt = pcaps->link_fec_options;
3043 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3045 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3047 status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3050 ice_free(hw, pcaps);
3055 ice_dev_set_link_up(struct rte_eth_dev *dev)
3057 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3059 return ice_force_phys_link_state(hw, true);
3063 ice_dev_set_link_down(struct rte_eth_dev *dev)
3065 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3067 return ice_force_phys_link_state(hw, false);
3071 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3073 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3074 struct rte_eth_dev_data *dev_data = pf->dev_data;
3075 uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3077 /* check if mtu is within the allowed range */
3078 if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3081 /* mtu setting is forbidden if port is start */
3082 if (dev_data->dev_started) {
3084 "port %d must be stopped before configuration",
3089 if (frame_size > RTE_ETHER_MAX_LEN)
3090 dev_data->dev_conf.rxmode.offloads |=
3091 DEV_RX_OFFLOAD_JUMBO_FRAME;
3093 dev_data->dev_conf.rxmode.offloads &=
3094 ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3096 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3101 static int ice_macaddr_set(struct rte_eth_dev *dev,
3102 struct rte_ether_addr *mac_addr)
3104 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3105 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3106 struct ice_vsi *vsi = pf->main_vsi;
3107 struct ice_mac_filter *f;
3111 if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3112 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3116 TAILQ_FOREACH(f, &vsi->mac_list, next) {
3117 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3122 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3126 ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3127 if (ret != ICE_SUCCESS) {
3128 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3131 ret = ice_add_mac_filter(vsi, mac_addr);
3132 if (ret != ICE_SUCCESS) {
3133 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3136 memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
3138 flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3139 ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3140 if (ret != ICE_SUCCESS)
3141 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3146 /* Add a MAC address, and update filters */
3148 ice_macaddr_add(struct rte_eth_dev *dev,
3149 struct rte_ether_addr *mac_addr,
3150 __rte_unused uint32_t index,
3151 __rte_unused uint32_t pool)
3153 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3154 struct ice_vsi *vsi = pf->main_vsi;
3157 ret = ice_add_mac_filter(vsi, mac_addr);
3158 if (ret != ICE_SUCCESS) {
3159 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3166 /* Remove a MAC address, and update filters */
3168 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3170 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3171 struct ice_vsi *vsi = pf->main_vsi;
3172 struct rte_eth_dev_data *data = dev->data;
3173 struct rte_ether_addr *macaddr;
3176 macaddr = &data->mac_addrs[index];
3177 ret = ice_remove_mac_filter(vsi, macaddr);
3179 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3185 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3187 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3188 struct ice_vsi *vsi = pf->main_vsi;
3191 PMD_INIT_FUNC_TRACE();
3194 ret = ice_add_vlan_filter(vsi, vlan_id);
3196 PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3200 ret = ice_remove_vlan_filter(vsi, vlan_id);
3202 PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3210 /* Configure vlan filter on or off */
3212 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3214 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3215 struct ice_vsi_ctx ctxt;
3216 uint8_t sec_flags, sw_flags2;
3219 sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3220 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3221 sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3224 vsi->info.sec_flags |= sec_flags;
3225 vsi->info.sw_flags2 |= sw_flags2;
3227 vsi->info.sec_flags &= ~sec_flags;
3228 vsi->info.sw_flags2 &= ~sw_flags2;
3230 vsi->info.sw_id = hw->port_info->sw_id;
3231 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3232 ctxt.info.valid_sections =
3233 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3234 ICE_AQ_VSI_PROP_SECURITY_VALID);
3235 ctxt.vsi_num = vsi->vsi_id;
3237 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3239 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3240 on ? "enable" : "disable");
3243 vsi->info.valid_sections |=
3244 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3245 ICE_AQ_VSI_PROP_SECURITY_VALID);
3248 /* consist with other drivers, allow untagged packet when vlan filter on */
3250 ret = ice_add_vlan_filter(vsi, 0);
3252 ret = ice_remove_vlan_filter(vsi, 0);
3258 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
3260 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3261 struct ice_vsi_ctx ctxt;
3265 /* Check if it has been already on or off */
3266 if (vsi->info.valid_sections &
3267 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
3269 if ((vsi->info.vlan_flags &
3270 ICE_AQ_VSI_VLAN_EMOD_M) ==
3271 ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
3272 return 0; /* already on */
3274 if ((vsi->info.vlan_flags &
3275 ICE_AQ_VSI_VLAN_EMOD_M) ==
3276 ICE_AQ_VSI_VLAN_EMOD_NOTHING)
3277 return 0; /* already off */
3282 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
3284 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3285 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
3286 vsi->info.vlan_flags |= vlan_flags;
3287 (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3288 ctxt.info.valid_sections =
3289 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3290 ctxt.vsi_num = vsi->vsi_id;
3291 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3293 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3294 on ? "enable" : "disable");
3298 vsi->info.valid_sections |=
3299 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3305 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3307 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3308 struct ice_vsi *vsi = pf->main_vsi;
3309 struct rte_eth_rxmode *rxmode;
3311 rxmode = &dev->data->dev_conf.rxmode;
3312 if (mask & ETH_VLAN_FILTER_MASK) {
3313 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3314 ice_vsi_config_vlan_filter(vsi, TRUE);
3316 ice_vsi_config_vlan_filter(vsi, FALSE);
3319 if (mask & ETH_VLAN_STRIP_MASK) {
3320 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3321 ice_vsi_config_vlan_stripping(vsi, TRUE);
3323 ice_vsi_config_vlan_stripping(vsi, FALSE);
3326 if (mask & ETH_VLAN_EXTEND_MASK) {
3327 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
3328 ice_vsi_config_double_vlan(vsi, TRUE);
3330 ice_vsi_config_double_vlan(vsi, FALSE);
3337 ice_vlan_tpid_set(struct rte_eth_dev *dev,
3338 enum rte_vlan_type vlan_type,
3341 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3342 uint64_t reg_r = 0, reg_w = 0;
3343 uint16_t reg_id = 0;
3345 int qinq = dev->data->dev_conf.rxmode.offloads &
3346 DEV_RX_OFFLOAD_VLAN_EXTEND;
3348 switch (vlan_type) {
3349 case ETH_VLAN_TYPE_OUTER:
3355 case ETH_VLAN_TYPE_INNER:
3360 "Unsupported vlan type in single vlan.");
3365 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
3368 reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
3369 PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
3370 "0x%08"PRIx64"", reg_id, reg_r);
3372 reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
3373 reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
3374 if (reg_r == reg_w) {
3375 PMD_DRV_LOG(DEBUG, "No need to write");
3379 ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
3380 PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
3381 "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
3387 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3389 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
3390 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3396 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3397 ret = ice_aq_get_rss_lut(hw, vsi->idx,
3398 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3400 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3404 uint64_t *lut_dw = (uint64_t *)lut;
3405 uint16_t i, lut_size_dw = lut_size / 4;
3407 for (i = 0; i < lut_size_dw; i++)
3408 lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
3415 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3424 pf = ICE_VSI_TO_PF(vsi);
3425 hw = ICE_VSI_TO_HW(vsi);
3427 if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
3428 ret = ice_aq_set_rss_lut(hw, vsi->idx,
3429 ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF, lut, lut_size);
3431 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3435 uint64_t *lut_dw = (uint64_t *)lut;
3436 uint16_t i, lut_size_dw = lut_size / 4;
3438 for (i = 0; i < lut_size_dw; i++)
3439 ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
3448 ice_rss_reta_update(struct rte_eth_dev *dev,
3449 struct rte_eth_rss_reta_entry64 *reta_conf,
3452 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3453 uint16_t i, lut_size = pf->hash_lut_size;
3454 uint16_t idx, shift;
3458 if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
3459 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
3460 reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
3462 "The size of hash lookup table configured (%d)"
3463 "doesn't match the number hardware can "
3464 "supported (128, 512, 2048)",
3469 /* It MUST use the current LUT size to get the RSS lookup table,
3470 * otherwise if will fail with -100 error code.
3472 lut = rte_zmalloc(NULL, RTE_MAX(reta_size, lut_size), 0);
3474 PMD_DRV_LOG(ERR, "No memory can be allocated");
3477 ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
3481 for (i = 0; i < reta_size; i++) {
3482 idx = i / RTE_RETA_GROUP_SIZE;
3483 shift = i % RTE_RETA_GROUP_SIZE;
3484 if (reta_conf[idx].mask & (1ULL << shift))
3485 lut[i] = reta_conf[idx].reta[shift];
3487 ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
3488 if (ret == 0 && lut_size != reta_size) {
3490 "The size of hash lookup table is changed from (%d) to (%d)",
3491 lut_size, reta_size);
3492 pf->hash_lut_size = reta_size;
3502 ice_rss_reta_query(struct rte_eth_dev *dev,
3503 struct rte_eth_rss_reta_entry64 *reta_conf,
3506 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3507 uint16_t i, lut_size = pf->hash_lut_size;
3508 uint16_t idx, shift;
3512 if (reta_size != lut_size) {
3514 "The size of hash lookup table configured (%d)"
3515 "doesn't match the number hardware can "
3517 reta_size, lut_size);
3521 lut = rte_zmalloc(NULL, reta_size, 0);
3523 PMD_DRV_LOG(ERR, "No memory can be allocated");
3527 ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
3531 for (i = 0; i < reta_size; i++) {
3532 idx = i / RTE_RETA_GROUP_SIZE;
3533 shift = i % RTE_RETA_GROUP_SIZE;
3534 if (reta_conf[idx].mask & (1ULL << shift))
3535 reta_conf[idx].reta[shift] = lut[i];
3545 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
3547 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3550 if (!key || key_len == 0) {
3551 PMD_DRV_LOG(DEBUG, "No key to be configured");
3553 } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
3555 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
3559 struct ice_aqc_get_set_rss_keys *key_dw =
3560 (struct ice_aqc_get_set_rss_keys *)key;
3562 ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
3564 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
3572 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
3574 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3577 if (!key || !key_len)
3580 ret = ice_aq_get_rss_key
3582 (struct ice_aqc_get_set_rss_keys *)key);
3584 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
3587 *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3593 ice_rss_hash_update(struct rte_eth_dev *dev,
3594 struct rte_eth_rss_conf *rss_conf)
3596 enum ice_status status = ICE_SUCCESS;
3597 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3598 struct ice_vsi *vsi = pf->main_vsi;
3601 status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
3605 /* TODO: hash enable config, ice_add_rss_cfg */
3610 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
3611 struct rte_eth_rss_conf *rss_conf)
3613 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3614 struct ice_vsi *vsi = pf->main_vsi;
3616 ice_get_rss_key(vsi, rss_conf->rss_key,
3617 &rss_conf->rss_key_len);
3619 /* TODO: default set to 0 as hf config is not supported now */
3620 rss_conf->rss_hf = 0;
3625 ice_promisc_enable(struct rte_eth_dev *dev)
3627 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3628 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3629 struct ice_vsi *vsi = pf->main_vsi;
3630 enum ice_status status;
3634 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3635 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3637 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3639 case ICE_ERR_ALREADY_EXISTS:
3640 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
3644 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
3652 ice_promisc_disable(struct rte_eth_dev *dev)
3654 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3655 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3656 struct ice_vsi *vsi = pf->main_vsi;
3657 enum ice_status status;
3661 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
3662 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3664 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3665 if (status != ICE_SUCCESS) {
3666 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
3674 ice_allmulti_enable(struct rte_eth_dev *dev)
3676 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3677 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3678 struct ice_vsi *vsi = pf->main_vsi;
3679 enum ice_status status;
3683 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3685 status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
3688 case ICE_ERR_ALREADY_EXISTS:
3689 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
3693 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
3701 ice_allmulti_disable(struct rte_eth_dev *dev)
3703 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3704 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3705 struct ice_vsi *vsi = pf->main_vsi;
3706 enum ice_status status;
3710 if (dev->data->promiscuous == 1)
3711 return 0; /* must remain in all_multicast mode */
3713 pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
3715 status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
3716 if (status != ICE_SUCCESS) {
3717 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
3724 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
3727 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3728 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3729 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3733 msix_intr = intr_handle->intr_vec[queue_id];
3735 val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
3736 GLINT_DYN_CTL_ITR_INDX_M;
3737 val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
3739 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
3740 rte_intr_ack(&pci_dev->intr_handle);
3745 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
3748 struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3749 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3750 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3753 msix_intr = intr_handle->intr_vec[queue_id];
3755 ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
3761 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3763 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3769 full_ver = hw->nvm.oem_ver;
3770 ver = (u8)(full_ver >> 24);
3771 build = (u16)((full_ver >> 8) & 0xffff);
3772 patch = (u8)(full_ver & 0xff);
3774 ret = snprintf(fw_version, fw_size,
3775 "%d.%d%d 0x%08x %d.%d.%d",
3776 ((hw->nvm.ver >> 12) & 0xf),
3777 ((hw->nvm.ver >> 4) & 0xff),
3778 (hw->nvm.ver & 0xf), hw->nvm.eetrack,
3781 /* add the size of '\0' */
3783 if (fw_size < (u32)ret)
3790 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3793 struct ice_vsi_ctx ctxt;
3794 uint8_t vlan_flags = 0;
3797 if (!vsi || !info) {
3798 PMD_DRV_LOG(ERR, "invalid parameters");
3803 vsi->info.pvid = info->config.pvid;
3805 * If insert pvid is enabled, only tagged pkts are
3806 * allowed to be sent out.
3808 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3809 ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3812 if (info->config.reject.tagged == 0)
3813 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3815 if (info->config.reject.untagged == 0)
3816 vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3818 vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3819 ICE_AQ_VSI_VLAN_MODE_M);
3820 vsi->info.vlan_flags |= vlan_flags;
3821 memset(&ctxt, 0, sizeof(ctxt));
3822 rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3823 ctxt.info.valid_sections =
3824 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3825 ctxt.vsi_num = vsi->vsi_id;
3827 hw = ICE_VSI_TO_HW(vsi);
3828 ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3829 if (ret != ICE_SUCCESS) {
3831 "update VSI for VLAN insert failed, err %d",
3836 vsi->info.valid_sections |=
3837 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3843 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3845 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3846 struct ice_vsi *vsi = pf->main_vsi;
3847 struct rte_eth_dev_data *data = pf->dev_data;
3848 struct ice_vsi_vlan_pvid_info info;
3851 memset(&info, 0, sizeof(info));
3854 info.config.pvid = pvid;
3856 info.config.reject.tagged =
3857 data->dev_conf.txmode.hw_vlan_reject_tagged;
3858 info.config.reject.untagged =
3859 data->dev_conf.txmode.hw_vlan_reject_untagged;
3862 ret = ice_vsi_vlan_pvid_set(vsi, &info);
3864 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3872 ice_get_eeprom_length(struct rte_eth_dev *dev)
3874 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3876 /* Convert word count to byte count */
3877 return hw->nvm.sr_words << 1;
3881 ice_get_eeprom(struct rte_eth_dev *dev,
3882 struct rte_dev_eeprom_info *eeprom)
3884 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3885 uint16_t *data = eeprom->data;
3886 uint16_t first_word, last_word, nwords;
3887 enum ice_status status = ICE_SUCCESS;
3889 first_word = eeprom->offset >> 1;
3890 last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3891 nwords = last_word - first_word + 1;
3893 if (first_word >= hw->nvm.sr_words ||
3894 last_word >= hw->nvm.sr_words) {
3895 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3899 eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3901 status = ice_read_sr_buf(hw, first_word, &nwords, data);
3903 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3904 eeprom->length = sizeof(uint16_t) * nwords;
3912 ice_stat_update_32(struct ice_hw *hw,
3920 new_data = (uint64_t)ICE_READ_REG(hw, reg);
3924 if (new_data >= *offset)
3925 *stat = (uint64_t)(new_data - *offset);
3927 *stat = (uint64_t)((new_data +
3928 ((uint64_t)1 << ICE_32_BIT_WIDTH))
3933 ice_stat_update_40(struct ice_hw *hw,
3942 new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3943 new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3949 if (new_data >= *offset)
3950 *stat = new_data - *offset;
3952 *stat = (uint64_t)((new_data +
3953 ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3956 *stat &= ICE_40_BIT_MASK;
3959 /* Get all the statistics of a VSI */
3961 ice_update_vsi_stats(struct ice_vsi *vsi)
3963 struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3964 struct ice_eth_stats *nes = &vsi->eth_stats;
3965 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3966 int idx = rte_le_to_cpu_16(vsi->vsi_id);
3968 ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3969 vsi->offset_loaded, &oes->rx_bytes,
3971 ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3972 vsi->offset_loaded, &oes->rx_unicast,
3974 ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3975 vsi->offset_loaded, &oes->rx_multicast,
3976 &nes->rx_multicast);
3977 ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3978 vsi->offset_loaded, &oes->rx_broadcast,
3979 &nes->rx_broadcast);
3980 /* exclude CRC bytes */
3981 nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3982 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
3984 ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3985 &oes->rx_discards, &nes->rx_discards);
3986 /* GLV_REPC not supported */
3987 /* GLV_RMPC not supported */
3988 ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3989 &oes->rx_unknown_protocol,
3990 &nes->rx_unknown_protocol);
3991 ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3992 vsi->offset_loaded, &oes->tx_bytes,
3994 ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3995 vsi->offset_loaded, &oes->tx_unicast,
3997 ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3998 vsi->offset_loaded, &oes->tx_multicast,
3999 &nes->tx_multicast);
4000 ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4001 vsi->offset_loaded, &oes->tx_broadcast,
4002 &nes->tx_broadcast);
4003 /* GLV_TDPC not supported */
4004 ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4005 &oes->tx_errors, &nes->tx_errors);
4006 vsi->offset_loaded = true;
4008 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4010 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", nes->rx_bytes);
4011 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", nes->rx_unicast);
4012 PMD_DRV_LOG(DEBUG, "rx_multicast: %"PRIu64"", nes->rx_multicast);
4013 PMD_DRV_LOG(DEBUG, "rx_broadcast: %"PRIu64"", nes->rx_broadcast);
4014 PMD_DRV_LOG(DEBUG, "rx_discards: %"PRIu64"", nes->rx_discards);
4015 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4016 nes->rx_unknown_protocol);
4017 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", nes->tx_bytes);
4018 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", nes->tx_unicast);
4019 PMD_DRV_LOG(DEBUG, "tx_multicast: %"PRIu64"", nes->tx_multicast);
4020 PMD_DRV_LOG(DEBUG, "tx_broadcast: %"PRIu64"", nes->tx_broadcast);
4021 PMD_DRV_LOG(DEBUG, "tx_discards: %"PRIu64"", nes->tx_discards);
4022 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", nes->tx_errors);
4023 PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4028 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4030 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4031 struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4033 /* Get statistics of struct ice_eth_stats */
4034 ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4035 GLPRT_GORCL(hw->port_info->lport),
4036 pf->offset_loaded, &os->eth.rx_bytes,
4038 ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4039 GLPRT_UPRCL(hw->port_info->lport),
4040 pf->offset_loaded, &os->eth.rx_unicast,
4041 &ns->eth.rx_unicast);
4042 ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4043 GLPRT_MPRCL(hw->port_info->lport),
4044 pf->offset_loaded, &os->eth.rx_multicast,
4045 &ns->eth.rx_multicast);
4046 ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4047 GLPRT_BPRCL(hw->port_info->lport),
4048 pf->offset_loaded, &os->eth.rx_broadcast,
4049 &ns->eth.rx_broadcast);
4050 ice_stat_update_32(hw, PRTRPB_RDPC,
4051 pf->offset_loaded, &os->eth.rx_discards,
4052 &ns->eth.rx_discards);
4054 /* Workaround: CRC size should not be included in byte statistics,
4055 * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4058 ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4059 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4061 /* GLPRT_REPC not supported */
4062 /* GLPRT_RMPC not supported */
4063 ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4065 &os->eth.rx_unknown_protocol,
4066 &ns->eth.rx_unknown_protocol);
4067 ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4068 GLPRT_GOTCL(hw->port_info->lport),
4069 pf->offset_loaded, &os->eth.tx_bytes,
4071 ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4072 GLPRT_UPTCL(hw->port_info->lport),
4073 pf->offset_loaded, &os->eth.tx_unicast,
4074 &ns->eth.tx_unicast);
4075 ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4076 GLPRT_MPTCL(hw->port_info->lport),
4077 pf->offset_loaded, &os->eth.tx_multicast,
4078 &ns->eth.tx_multicast);
4079 ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4080 GLPRT_BPTCL(hw->port_info->lport),
4081 pf->offset_loaded, &os->eth.tx_broadcast,
4082 &ns->eth.tx_broadcast);
4083 ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4084 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4086 /* GLPRT_TEPC not supported */
4088 /* additional port specific stats */
4089 ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4090 pf->offset_loaded, &os->tx_dropped_link_down,
4091 &ns->tx_dropped_link_down);
4092 ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4093 pf->offset_loaded, &os->crc_errors,
4095 ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4096 pf->offset_loaded, &os->illegal_bytes,
4097 &ns->illegal_bytes);
4098 /* GLPRT_ERRBC not supported */
4099 ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4100 pf->offset_loaded, &os->mac_local_faults,
4101 &ns->mac_local_faults);
4102 ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4103 pf->offset_loaded, &os->mac_remote_faults,
4104 &ns->mac_remote_faults);
4106 ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4107 pf->offset_loaded, &os->rx_len_errors,
4108 &ns->rx_len_errors);
4110 ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4111 pf->offset_loaded, &os->link_xon_rx,
4113 ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4114 pf->offset_loaded, &os->link_xoff_rx,
4116 ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4117 pf->offset_loaded, &os->link_xon_tx,
4119 ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4120 pf->offset_loaded, &os->link_xoff_tx,
4122 ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4123 GLPRT_PRC64L(hw->port_info->lport),
4124 pf->offset_loaded, &os->rx_size_64,
4126 ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4127 GLPRT_PRC127L(hw->port_info->lport),
4128 pf->offset_loaded, &os->rx_size_127,
4130 ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4131 GLPRT_PRC255L(hw->port_info->lport),
4132 pf->offset_loaded, &os->rx_size_255,
4134 ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4135 GLPRT_PRC511L(hw->port_info->lport),
4136 pf->offset_loaded, &os->rx_size_511,
4138 ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4139 GLPRT_PRC1023L(hw->port_info->lport),
4140 pf->offset_loaded, &os->rx_size_1023,
4142 ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4143 GLPRT_PRC1522L(hw->port_info->lport),
4144 pf->offset_loaded, &os->rx_size_1522,
4146 ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4147 GLPRT_PRC9522L(hw->port_info->lport),
4148 pf->offset_loaded, &os->rx_size_big,
4150 ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4151 pf->offset_loaded, &os->rx_undersize,
4153 ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4154 pf->offset_loaded, &os->rx_fragments,
4156 ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4157 pf->offset_loaded, &os->rx_oversize,
4159 ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4160 pf->offset_loaded, &os->rx_jabber,
4162 ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4163 GLPRT_PTC64L(hw->port_info->lport),
4164 pf->offset_loaded, &os->tx_size_64,
4166 ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4167 GLPRT_PTC127L(hw->port_info->lport),
4168 pf->offset_loaded, &os->tx_size_127,
4170 ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4171 GLPRT_PTC255L(hw->port_info->lport),
4172 pf->offset_loaded, &os->tx_size_255,
4174 ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4175 GLPRT_PTC511L(hw->port_info->lport),
4176 pf->offset_loaded, &os->tx_size_511,
4178 ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4179 GLPRT_PTC1023L(hw->port_info->lport),
4180 pf->offset_loaded, &os->tx_size_1023,
4182 ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4183 GLPRT_PTC1522L(hw->port_info->lport),
4184 pf->offset_loaded, &os->tx_size_1522,
4186 ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4187 GLPRT_PTC9522L(hw->port_info->lport),
4188 pf->offset_loaded, &os->tx_size_big,
4191 /* GLPRT_MSPDC not supported */
4192 /* GLPRT_XEC not supported */
4194 pf->offset_loaded = true;
4197 ice_update_vsi_stats(pf->main_vsi);
4200 /* Get all statistics of a port */
4202 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4204 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4205 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4206 struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4208 /* call read registers - updates values, now write them to struct */
4209 ice_read_stats_registers(pf, hw);
4211 stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4212 pf->main_vsi->eth_stats.rx_multicast +
4213 pf->main_vsi->eth_stats.rx_broadcast -
4214 pf->main_vsi->eth_stats.rx_discards;
4215 stats->opackets = ns->eth.tx_unicast +
4216 ns->eth.tx_multicast +
4217 ns->eth.tx_broadcast;
4218 stats->ibytes = pf->main_vsi->eth_stats.rx_bytes;
4219 stats->obytes = ns->eth.tx_bytes;
4220 stats->oerrors = ns->eth.tx_errors +
4221 pf->main_vsi->eth_stats.tx_errors;
4224 stats->imissed = ns->eth.rx_discards +
4225 pf->main_vsi->eth_stats.rx_discards;
4226 stats->ierrors = ns->crc_errors +
4228 ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
4230 PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
4231 PMD_DRV_LOG(DEBUG, "rx_bytes: %"PRIu64"", ns->eth.rx_bytes);
4232 PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
4233 PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
4234 PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
4235 PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
4236 PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
4237 pf->main_vsi->eth_stats.rx_discards);
4238 PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4239 ns->eth.rx_unknown_protocol);
4240 PMD_DRV_LOG(DEBUG, "tx_bytes: %"PRIu64"", ns->eth.tx_bytes);
4241 PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
4242 PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
4243 PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
4244 PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
4245 PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
4246 pf->main_vsi->eth_stats.tx_discards);
4247 PMD_DRV_LOG(DEBUG, "tx_errors: %"PRIu64"", ns->eth.tx_errors);
4249 PMD_DRV_LOG(DEBUG, "tx_dropped_link_down: %"PRIu64"",
4250 ns->tx_dropped_link_down);
4251 PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
4252 PMD_DRV_LOG(DEBUG, "illegal_bytes: %"PRIu64"",
4254 PMD_DRV_LOG(DEBUG, "error_bytes: %"PRIu64"", ns->error_bytes);
4255 PMD_DRV_LOG(DEBUG, "mac_local_faults: %"PRIu64"",
4256 ns->mac_local_faults);
4257 PMD_DRV_LOG(DEBUG, "mac_remote_faults: %"PRIu64"",
4258 ns->mac_remote_faults);
4259 PMD_DRV_LOG(DEBUG, "link_xon_rx: %"PRIu64"", ns->link_xon_rx);
4260 PMD_DRV_LOG(DEBUG, "link_xoff_rx: %"PRIu64"", ns->link_xoff_rx);
4261 PMD_DRV_LOG(DEBUG, "link_xon_tx: %"PRIu64"", ns->link_xon_tx);
4262 PMD_DRV_LOG(DEBUG, "link_xoff_tx: %"PRIu64"", ns->link_xoff_tx);
4263 PMD_DRV_LOG(DEBUG, "rx_size_64: %"PRIu64"", ns->rx_size_64);
4264 PMD_DRV_LOG(DEBUG, "rx_size_127: %"PRIu64"", ns->rx_size_127);
4265 PMD_DRV_LOG(DEBUG, "rx_size_255: %"PRIu64"", ns->rx_size_255);
4266 PMD_DRV_LOG(DEBUG, "rx_size_511: %"PRIu64"", ns->rx_size_511);
4267 PMD_DRV_LOG(DEBUG, "rx_size_1023: %"PRIu64"", ns->rx_size_1023);
4268 PMD_DRV_LOG(DEBUG, "rx_size_1522: %"PRIu64"", ns->rx_size_1522);
4269 PMD_DRV_LOG(DEBUG, "rx_size_big: %"PRIu64"", ns->rx_size_big);
4270 PMD_DRV_LOG(DEBUG, "rx_undersize: %"PRIu64"", ns->rx_undersize);
4271 PMD_DRV_LOG(DEBUG, "rx_fragments: %"PRIu64"", ns->rx_fragments);
4272 PMD_DRV_LOG(DEBUG, "rx_oversize: %"PRIu64"", ns->rx_oversize);
4273 PMD_DRV_LOG(DEBUG, "rx_jabber: %"PRIu64"", ns->rx_jabber);
4274 PMD_DRV_LOG(DEBUG, "tx_size_64: %"PRIu64"", ns->tx_size_64);
4275 PMD_DRV_LOG(DEBUG, "tx_size_127: %"PRIu64"", ns->tx_size_127);
4276 PMD_DRV_LOG(DEBUG, "tx_size_255: %"PRIu64"", ns->tx_size_255);
4277 PMD_DRV_LOG(DEBUG, "tx_size_511: %"PRIu64"", ns->tx_size_511);
4278 PMD_DRV_LOG(DEBUG, "tx_size_1023: %"PRIu64"", ns->tx_size_1023);
4279 PMD_DRV_LOG(DEBUG, "tx_size_1522: %"PRIu64"", ns->tx_size_1522);
4280 PMD_DRV_LOG(DEBUG, "tx_size_big: %"PRIu64"", ns->tx_size_big);
4281 PMD_DRV_LOG(DEBUG, "rx_len_errors: %"PRIu64"", ns->rx_len_errors);
4282 PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
4286 /* Reset the statistics */
4288 ice_stats_reset(struct rte_eth_dev *dev)
4290 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4291 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4293 /* Mark PF and VSI stats to update the offset, aka "reset" */
4294 pf->offset_loaded = false;
4296 pf->main_vsi->offset_loaded = false;
4298 /* read the stats, reading current register values into offset */
4299 ice_read_stats_registers(pf, hw);
4305 ice_xstats_calc_num(void)
4309 num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
4315 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
4318 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4319 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4322 struct ice_hw_port_stats *hw_stats = &pf->stats;
4324 count = ice_xstats_calc_num();
4328 ice_read_stats_registers(pf, hw);
4335 /* Get stats from ice_eth_stats struct */
4336 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4337 xstats[count].value =
4338 *(uint64_t *)((char *)&hw_stats->eth +
4339 ice_stats_strings[i].offset);
4340 xstats[count].id = count;
4344 /* Get individiual stats from ice_hw_port struct */
4345 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4346 xstats[count].value =
4347 *(uint64_t *)((char *)hw_stats +
4348 ice_hw_port_strings[i].offset);
4349 xstats[count].id = count;
4356 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
4357 struct rte_eth_xstat_name *xstats_names,
4358 __rte_unused unsigned int limit)
4360 unsigned int count = 0;
4364 return ice_xstats_calc_num();
4366 /* Note: limit checked in rte_eth_xstats_names() */
4368 /* Get stats from ice_eth_stats struct */
4369 for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
4370 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
4371 sizeof(xstats_names[count].name));
4375 /* Get individiual stats from ice_hw_port struct */
4376 for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
4377 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
4378 sizeof(xstats_names[count].name));
4386 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
4387 enum rte_filter_type filter_type,
4388 enum rte_filter_op filter_op,
4396 switch (filter_type) {
4397 case RTE_ETH_FILTER_GENERIC:
4398 if (filter_op != RTE_ETH_FILTER_GET)
4400 *(const void **)arg = &ice_flow_ops;
4403 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4412 /* Add UDP tunneling port */
4414 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4415 struct rte_eth_udp_tunnel *udp_tunnel)
4418 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4420 if (udp_tunnel == NULL)
4423 switch (udp_tunnel->prot_type) {
4424 case RTE_TUNNEL_TYPE_VXLAN:
4425 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
4428 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4436 /* Delete UDP tunneling port */
4438 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
4439 struct rte_eth_udp_tunnel *udp_tunnel)
4442 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4444 if (udp_tunnel == NULL)
4447 switch (udp_tunnel->prot_type) {
4448 case RTE_TUNNEL_TYPE_VXLAN:
4449 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
4452 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4461 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
4462 struct rte_pci_device *pci_dev)
4464 return rte_eth_dev_pci_generic_probe(pci_dev,
4465 sizeof(struct ice_adapter),
4470 ice_pci_remove(struct rte_pci_device *pci_dev)
4472 return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
4475 static struct rte_pci_driver rte_ice_pmd = {
4476 .id_table = pci_id_ice_map,
4477 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
4478 .probe = ice_pci_probe,
4479 .remove = ice_pci_remove,
4483 * Driver initialization routine.
4484 * Invoked once at EAL init time.
4485 * Register itself as the [Poll Mode] Driver of PCI devices.
4487 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
4488 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
4489 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
4490 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
4491 ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp>"
4492 ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
4493 ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
4495 RTE_INIT(ice_init_log)
4497 ice_logtype_init = rte_log_register("pmd.net.ice.init");
4498 if (ice_logtype_init >= 0)
4499 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
4500 ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
4501 if (ice_logtype_driver >= 0)
4502 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
4504 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
4505 ice_logtype_rx = rte_log_register("pmd.net.ice.rx");
4506 if (ice_logtype_rx >= 0)
4507 rte_log_set_level(ice_logtype_rx, RTE_LOG_DEBUG);
4510 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
4511 ice_logtype_tx = rte_log_register("pmd.net.ice.tx");
4512 if (ice_logtype_tx >= 0)
4513 rte_log_set_level(ice_logtype_tx, RTE_LOG_DEBUG);
4516 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
4517 ice_logtype_tx_free = rte_log_register("pmd.net.ice.tx_free");
4518 if (ice_logtype_tx_free >= 0)
4519 rte_log_set_level(ice_logtype_tx_free, RTE_LOG_DEBUG);