drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  27
  28 static const char * const ice_valid_args[] = {
  29         ICE_SAFE_MODE_SUPPORT_ARG,
  30         ICE_PIPELINE_MODE_SUPPORT_ARG,
  31         ICE_PROTO_XTR_ARG,
  32         NULL
  33 };
  34
  35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  36         .name = "intel_pmd_dynfield_proto_xtr_metadata",
  37         .size = sizeof(uint32_t),
  38         .align = __alignof__(uint32_t),
  39         .flags = 0,
  40 };
  41
  42 struct proto_xtr_ol_flag {
  43         const struct rte_mbuf_dynflag param;
  44         uint64_t *ol_flag;
  45         bool required;
  46 };
  47
  48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66         [PROTO_XTR_IP_OFFSET] = {
  67                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
  68                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  69 };
  70
  71 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  72 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  73 #define ICE_MAX_RES_DESC_NUM        1024
  74
  75 static int ice_dev_configure(struct rte_eth_dev *dev);
  76 static int ice_dev_start(struct rte_eth_dev *dev);
  77 static int ice_dev_stop(struct rte_eth_dev *dev);
  78 static int ice_dev_close(struct rte_eth_dev *dev);
  79 static int ice_dev_reset(struct rte_eth_dev *dev);
  80 static int ice_dev_info_get(struct rte_eth_dev *dev,
  81                             struct rte_eth_dev_info *dev_info);
  82 static int ice_link_update(struct rte_eth_dev *dev,
  83                            int wait_to_complete);
  84 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  85 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  86
  87 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  88 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  89 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  90                                struct rte_eth_rss_reta_entry64 *reta_conf,
  91                                uint16_t reta_size);
  92 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  93                               struct rte_eth_rss_reta_entry64 *reta_conf,
  94                               uint16_t reta_size);
  95 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  96                                struct rte_eth_rss_conf *rss_conf);
  97 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  98                                  struct rte_eth_rss_conf *rss_conf);
  99 static int ice_promisc_enable(struct rte_eth_dev *dev);
 100 static int ice_promisc_disable(struct rte_eth_dev *dev);
 101 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 102 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 103 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 104                                uint16_t vlan_id,
 105                                int on);
 106 static int ice_macaddr_set(struct rte_eth_dev *dev,
 107                            struct rte_ether_addr *mac_addr);
 108 static int ice_macaddr_add(struct rte_eth_dev *dev,
 109                            struct rte_ether_addr *mac_addr,
 110                            __rte_unused uint32_t index,
 111                            uint32_t pool);
 112 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 113 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 114                                     uint16_t queue_id);
 115 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 116                                      uint16_t queue_id);
 117 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 118                               size_t fw_size);
 119 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 120                              uint16_t pvid, int on);
 121 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 122 static int ice_get_eeprom(struct rte_eth_dev *dev,
 123                           struct rte_dev_eeprom_info *eeprom);
 124 static int ice_stats_get(struct rte_eth_dev *dev,
 125                          struct rte_eth_stats *stats);
 126 static int ice_stats_reset(struct rte_eth_dev *dev);
 127 static int ice_xstats_get(struct rte_eth_dev *dev,
 128                           struct rte_eth_xstat *xstats, unsigned int n);
 129 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 130                                 struct rte_eth_xstat_name *xstats_names,
 131                                 unsigned int limit);
 132 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 133                         enum rte_filter_type filter_type,
 134                         enum rte_filter_op filter_op,
 135                         void *arg);
 136 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 137                         struct rte_eth_udp_tunnel *udp_tunnel);
 138 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 139                         struct rte_eth_udp_tunnel *udp_tunnel);
 140
 141 static const struct rte_pci_id pci_id_ice_map[] = {
 142         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 143         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 144         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 145         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 146         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 147         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 148         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 149         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 150         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
 165         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
 166         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
 167         { .vendor_id = 0, /* sentinel */ },
 168 };
 169
 170 static const struct eth_dev_ops ice_eth_dev_ops = {
 171         .dev_configure                = ice_dev_configure,
 172         .dev_start                    = ice_dev_start,
 173         .dev_stop                     = ice_dev_stop,
 174         .dev_close                    = ice_dev_close,
 175         .dev_reset                    = ice_dev_reset,
 176         .dev_set_link_up              = ice_dev_set_link_up,
 177         .dev_set_link_down            = ice_dev_set_link_down,
 178         .rx_queue_start               = ice_rx_queue_start,
 179         .rx_queue_stop                = ice_rx_queue_stop,
 180         .tx_queue_start               = ice_tx_queue_start,
 181         .tx_queue_stop                = ice_tx_queue_stop,
 182         .rx_queue_setup               = ice_rx_queue_setup,
 183         .rx_queue_release             = ice_rx_queue_release,
 184         .tx_queue_setup               = ice_tx_queue_setup,
 185         .tx_queue_release             = ice_tx_queue_release,
 186         .dev_infos_get                = ice_dev_info_get,
 187         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 188         .link_update                  = ice_link_update,
 189         .mtu_set                      = ice_mtu_set,
 190         .mac_addr_set                 = ice_macaddr_set,
 191         .mac_addr_add                 = ice_macaddr_add,
 192         .mac_addr_remove              = ice_macaddr_remove,
 193         .vlan_filter_set              = ice_vlan_filter_set,
 194         .vlan_offload_set             = ice_vlan_offload_set,
 195         .reta_update                  = ice_rss_reta_update,
 196         .reta_query                   = ice_rss_reta_query,
 197         .rss_hash_update              = ice_rss_hash_update,
 198         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 199         .promiscuous_enable           = ice_promisc_enable,
 200         .promiscuous_disable          = ice_promisc_disable,
 201         .allmulticast_enable          = ice_allmulti_enable,
 202         .allmulticast_disable         = ice_allmulti_disable,
 203         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 204         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 205         .fw_version_get               = ice_fw_version_get,
 206         .vlan_pvid_set                = ice_vlan_pvid_set,
 207         .rxq_info_get                 = ice_rxq_info_get,
 208         .txq_info_get                 = ice_txq_info_get,
 209         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 210         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 211         .get_eeprom_length            = ice_get_eeprom_length,
 212         .get_eeprom                   = ice_get_eeprom,
 213         .stats_get                    = ice_stats_get,
 214         .stats_reset                  = ice_stats_reset,
 215         .xstats_get                   = ice_xstats_get,
 216         .xstats_get_names             = ice_xstats_get_names,
 217         .xstats_reset                 = ice_stats_reset,
 218         .filter_ctrl                  = ice_dev_filter_ctrl,
 219         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 220         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 221         .tx_done_cleanup              = ice_tx_done_cleanup,
 222         .get_monitor_addr             = ice_get_monitor_addr,
 223 };
 224
 225 /* store statistics names and its offset in stats structure */
 226 struct ice_xstats_name_off {
 227         char name[RTE_ETH_XSTATS_NAME_SIZE];
 228         unsigned int offset;
 229 };
 230
 231 static const struct ice_xstats_name_off ice_stats_strings[] = {
 232         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 233         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 234         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 235         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 236         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 237                 rx_unknown_protocol)},
 238         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 239         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 240         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 241         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 242 };
 243
 244 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 245                 sizeof(ice_stats_strings[0]))
 246
 247 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 248         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 249                 tx_dropped_link_down)},
 250         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 251         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 252                 illegal_bytes)},
 253         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 254         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 255                 mac_local_faults)},
 256         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 257                 mac_remote_faults)},
 258         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 259                 rx_len_errors)},
 260         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 261         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 262         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 263         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 264         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 265         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 266                 rx_size_127)},
 267         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 268                 rx_size_255)},
 269         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_511)},
 271         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_1023)},
 273         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 274                 rx_size_1522)},
 275         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 276                 rx_size_big)},
 277         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 278                 rx_undersize)},
 279         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 280                 rx_oversize)},
 281         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 282                 mac_short_pkt_dropped)},
 283         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 284                 rx_fragments)},
 285         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 286         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 287         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 288                 tx_size_127)},
 289         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 290                 tx_size_255)},
 291         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_511)},
 293         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_1023)},
 295         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 296                 tx_size_1522)},
 297         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 298                 tx_size_big)},
 299 };
 300
 301 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 302                 sizeof(ice_hw_port_strings[0]))
 303
 304 static void
 305 ice_init_controlq_parameter(struct ice_hw *hw)
 306 {
 307         /* fields for adminq */
 308         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 309         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 310         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 311         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 312
 313         /* fields for mailboxq, DPDK used as PF host */
 314         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 315         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 316         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 317         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 318 }
 319
 320 static int
 321 lookup_proto_xtr_type(const char *xtr_name)
 322 {
 323         static struct {
 324                 const char *name;
 325                 enum proto_xtr_type type;
 326         } xtr_type_map[] = {
 327                 { "vlan",      PROTO_XTR_VLAN      },
 328                 { "ipv4",      PROTO_XTR_IPV4      },
 329                 { "ipv6",      PROTO_XTR_IPV6      },
 330                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 331                 { "tcp",       PROTO_XTR_TCP       },
 332                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 333         };
 334         uint32_t i;
 335
 336         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 337                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 338                         return xtr_type_map[i].type;
 339         }
 340
 341         return -1;
 342 }
 343
 344 /*
 345  * Parse elem, the elem could be single number/range or '(' ')' group
 346  * 1) A single number elem, it's just a simple digit. e.g. 9
 347  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 348  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 349  *    Within group elem, '-' used for a range separator;
 350  *                       ',' used for a single number.
 351  */
 352 static int
 353 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 354 {
 355         const char *str = input;
 356         char *end = NULL;
 357         uint32_t min, max;
 358         uint32_t idx;
 359
 360         while (isblank(*str))
 361                 str++;
 362
 363         if (!isdigit(*str) && *str != '(')
 364                 return -1;
 365
 366         /* process single number or single range of number */
 367         if (*str != '(') {
 368                 errno = 0;
 369                 idx = strtoul(str, &end, 10);
 370                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 371                         return -1;
 372
 373                 while (isblank(*end))
 374                         end++;
 375
 376                 min = idx;
 377                 max = idx;
 378
 379                 /* process single <number>-<number> */
 380                 if (*end == '-') {
 381                         end++;
 382                         while (isblank(*end))
 383                                 end++;
 384                         if (!isdigit(*end))
 385                                 return -1;
 386
 387                         errno = 0;
 388                         idx = strtoul(end, &end, 10);
 389                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 390                                 return -1;
 391
 392                         max = idx;
 393                         while (isblank(*end))
 394                                 end++;
 395                 }
 396
 397                 if (*end != ':')
 398                         return -1;
 399
 400                 for (idx = RTE_MIN(min, max);
 401                      idx <= RTE_MAX(min, max); idx++)
 402                         devargs->proto_xtr[idx] = xtr_type;
 403
 404                 return 0;
 405         }
 406
 407         /* process set within bracket */
 408         str++;
 409         while (isblank(*str))
 410                 str++;
 411         if (*str == '\0')
 412                 return -1;
 413
 414         min = ICE_MAX_QUEUE_NUM;
 415         do {
 416                 /* go ahead to the first digit */
 417                 while (isblank(*str))
 418                         str++;
 419                 if (!isdigit(*str))
 420                         return -1;
 421
 422                 /* get the digit value */
 423                 errno = 0;
 424                 idx = strtoul(str, &end, 10);
 425                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 426                         return -1;
 427
 428                 /* go ahead to separator '-',',' and ')' */
 429                 while (isblank(*end))
 430                         end++;
 431                 if (*end == '-') {
 432                         if (min == ICE_MAX_QUEUE_NUM)
 433                                 min = idx;
 434                         else /* avoid continuous '-' */
 435                                 return -1;
 436                 } else if (*end == ',' || *end == ')') {
 437                         max = idx;
 438                         if (min == ICE_MAX_QUEUE_NUM)
 439                                 min = idx;
 440
 441                         for (idx = RTE_MIN(min, max);
 442                              idx <= RTE_MAX(min, max); idx++)
 443                                 devargs->proto_xtr[idx] = xtr_type;
 444
 445                         min = ICE_MAX_QUEUE_NUM;
 446                 } else {
 447                         return -1;
 448                 }
 449
 450                 str = end + 1;
 451         } while (*end != ')' && *end != '\0');
 452
 453         return 0;
 454 }
 455
 456 static int
 457 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 458 {
 459         const char *queue_start;
 460         uint32_t idx;
 461         int xtr_type;
 462         char xtr_name[32];
 463
 464         while (isblank(*queues))
 465                 queues++;
 466
 467         if (*queues != '[') {
 468                 xtr_type = lookup_proto_xtr_type(queues);
 469                 if (xtr_type < 0)
 470                         return -1;
 471
 472                 devargs->proto_xtr_dflt = xtr_type;
 473
 474                 return 0;
 475         }
 476
 477         queues++;
 478         do {
 479                 while (isblank(*queues))
 480                         queues++;
 481                 if (*queues == '\0')
 482                         return -1;
 483
 484                 queue_start = queues;
 485
 486                 /* go across a complete bracket */
 487                 if (*queue_start == '(') {
 488                         queues += strcspn(queues, ")");
 489                         if (*queues != ')')
 490                                 return -1;
 491                 }
 492
 493                 /* scan the separator ':' */
 494                 queues += strcspn(queues, ":");
 495                 if (*queues++ != ':')
 496                         return -1;
 497                 while (isblank(*queues))
 498                         queues++;
 499
 500                 for (idx = 0; ; idx++) {
 501                         if (isblank(queues[idx]) ||
 502                             queues[idx] == ',' ||
 503                             queues[idx] == ']' ||
 504                             queues[idx] == '\0')
 505                                 break;
 506
 507                         if (idx > sizeof(xtr_name) - 2)
 508                                 return -1;
 509
 510                         xtr_name[idx] = queues[idx];
 511                 }
 512                 xtr_name[idx] = '\0';
 513                 xtr_type = lookup_proto_xtr_type(xtr_name);
 514                 if (xtr_type < 0)
 515                         return -1;
 516
 517                 queues += idx;
 518
 519                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 520                         queues++;
 521
 522                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 523                         return -1;
 524         } while (*queues != '\0');
 525
 526         return 0;
 527 }
 528
 529 static int
 530 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 531                      void *extra_args)
 532 {
 533         struct ice_devargs *devargs = extra_args;
 534
 535         if (value == NULL || extra_args == NULL)
 536                 return -EINVAL;
 537
 538         if (parse_queue_proto_xtr(value, devargs) < 0) {
 539                 PMD_DRV_LOG(ERR,
 540                             "The protocol extraction parameter is wrong : '%s'",
 541                             value);
 542                 return -1;
 543         }
 544
 545         return 0;
 546 }
 547
 548 static void
 549 ice_check_proto_xtr_support(struct ice_hw *hw)
 550 {
 551 #define FLX_REG(val, fld, idx) \
 552         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 553          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 554         static struct {
 555                 uint32_t rxdid;
 556                 uint8_t opcode;
 557                 uint8_t protid_0;
 558                 uint8_t protid_1;
 559         } xtr_sets[] = {
 560                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 561                                      ICE_RX_OPC_EXTRACT,
 562                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 563                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 564                                      ICE_RX_OPC_EXTRACT,
 565                                      ICE_PROT_IPV4_OF_OR_S,
 566                                      ICE_PROT_IPV4_OF_OR_S },
 567                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 568                                      ICE_RX_OPC_EXTRACT,
 569                                      ICE_PROT_IPV6_OF_OR_S,
 570                                      ICE_PROT_IPV6_OF_OR_S },
 571                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 572                                           ICE_RX_OPC_EXTRACT,
 573                                           ICE_PROT_IPV6_OF_OR_S,
 574                                           ICE_PROT_IPV6_OF_OR_S },
 575                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 576                                     ICE_RX_OPC_EXTRACT,
 577                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 578                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 579                                           ICE_RX_OPC_PROTID,
 580                                           ICE_PROT_IPV4_OF_OR_S,
 581                                           ICE_PROT_IPV6_OF_OR_S },
 582         };
 583         uint32_t i;
 584
 585         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 586                 uint32_t rxdid = xtr_sets[i].rxdid;
 587                 uint32_t v;
 588
 589                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 590                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 591
 592                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 593                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 594                                 ice_proto_xtr_hw_support[i] = true;
 595                 }
 596
 597                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 598                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 599
 600                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 601                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 602                                 ice_proto_xtr_hw_support[i] = true;
 603                 }
 604         }
 605 }
 606
 607 static int
 608 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 609                   uint32_t num)
 610 {
 611         struct pool_entry *entry;
 612
 613         if (!pool || !num)
 614                 return -EINVAL;
 615
 616         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 617         if (!entry) {
 618                 PMD_INIT_LOG(ERR,
 619                              "Failed to allocate memory for resource pool");
 620                 return -ENOMEM;
 621         }
 622
 623         /* queue heap initialize */
 624         pool->num_free = num;
 625         pool->num_alloc = 0;
 626         pool->base = base;
 627         LIST_INIT(&pool->alloc_list);
 628         LIST_INIT(&pool->free_list);
 629
 630         /* Initialize element  */
 631         entry->base = 0;
 632         entry->len = num;
 633
 634         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 635         return 0;
 636 }
 637
 638 static int
 639 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 640                    uint16_t num)
 641 {
 642         struct pool_entry *entry, *valid_entry;
 643
 644         if (!pool || !num) {
 645                 PMD_INIT_LOG(ERR, "Invalid parameter");
 646                 return -EINVAL;
 647         }
 648
 649         if (pool->num_free < num) {
 650                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 651                              num, pool->num_free);
 652                 return -ENOMEM;
 653         }
 654
 655         valid_entry = NULL;
 656         /* Lookup  in free list and find most fit one */
 657         LIST_FOREACH(entry, &pool->free_list, next) {
 658                 if (entry->len >= num) {
 659                         /* Find best one */
 660                         if (entry->len == num) {
 661                                 valid_entry = entry;
 662                                 break;
 663                         }
 664                         if (!valid_entry ||
 665                             valid_entry->len > entry->len)
 666                                 valid_entry = entry;
 667                 }
 668         }
 669
 670         /* Not find one to satisfy the request, return */
 671         if (!valid_entry) {
 672                 PMD_INIT_LOG(ERR, "No valid entry found");
 673                 return -ENOMEM;
 674         }
 675         /**
 676          * The entry have equal queue number as requested,
 677          * remove it from alloc_list.
 678          */
 679         if (valid_entry->len == num) {
 680                 LIST_REMOVE(valid_entry, next);
 681         } else {
 682                 /**
 683                  * The entry have more numbers than requested,
 684                  * create a new entry for alloc_list and minus its
 685                  * queue base and number in free_list.
 686                  */
 687                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 688                 if (!entry) {
 689                         PMD_INIT_LOG(ERR,
 690                                      "Failed to allocate memory for "
 691                                      "resource pool");
 692                         return -ENOMEM;
 693                 }
 694                 entry->base = valid_entry->base;
 695                 entry->len = num;
 696                 valid_entry->base += num;
 697                 valid_entry->len -= num;
 698                 valid_entry = entry;
 699         }
 700
 701         /* Insert it into alloc list, not sorted */
 702         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 703
 704         pool->num_free -= valid_entry->len;
 705         pool->num_alloc += valid_entry->len;
 706
 707         return valid_entry->base + pool->base;
 708 }
 709
 710 static void
 711 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 712 {
 713         struct pool_entry *entry, *next_entry;
 714
 715         if (!pool)
 716                 return;
 717
 718         for (entry = LIST_FIRST(&pool->alloc_list);
 719              entry && (next_entry = LIST_NEXT(entry, next), 1);
 720              entry = next_entry) {
 721                 LIST_REMOVE(entry, next);
 722                 rte_free(entry);
 723         }
 724
 725         for (entry = LIST_FIRST(&pool->free_list);
 726              entry && (next_entry = LIST_NEXT(entry, next), 1);
 727              entry = next_entry) {
 728                 LIST_REMOVE(entry, next);
 729                 rte_free(entry);
 730         }
 731
 732         pool->num_free = 0;
 733         pool->num_alloc = 0;
 734         pool->base = 0;
 735         LIST_INIT(&pool->alloc_list);
 736         LIST_INIT(&pool->free_list);
 737 }
 738
 739 static void
 740 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 741 {
 742         /* Set VSI LUT selection */
 743         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 744                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 745         /* Set Hash scheme */
 746         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 747                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 748         /* enable TC */
 749         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 750 }
 751
 752 static enum ice_status
 753 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 754                                 struct ice_aqc_vsi_props *info,
 755                                 uint8_t enabled_tcmap)
 756 {
 757         uint16_t bsf, qp_idx;
 758
 759         /* default tc 0 now. Multi-TC supporting need to be done later.
 760          * Configure TC and queue mapping parameters, for enabled TC,
 761          * allocate qpnum_per_tc queues to this traffic.
 762          */
 763         if (enabled_tcmap != 0x01) {
 764                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 765                 return -ENOTSUP;
 766         }
 767
 768         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 769         bsf = rte_bsf32(vsi->nb_qps);
 770         /* Adjust the queue number to actual queues that can be applied */
 771         vsi->nb_qps = 0x1 << bsf;
 772
 773         qp_idx = 0;
 774         /* Set tc and queue mapping with VSI */
 775         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 776                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 777                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 778
 779         /* Associate queue number with VSI */
 780         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 781         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 782         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 783         info->valid_sections |=
 784                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 785         /* Set the info.ingress_table and info.egress_table
 786          * for UP translate table. Now just set it to 1:1 map by default
 787          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 788          */
 789 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 790         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 791         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 792         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 793         return 0;
 794 }
 795
 796 static int
 797 ice_init_mac_address(struct rte_eth_dev *dev)
 798 {
 799         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 800
 801         if (!rte_is_unicast_ether_addr
 802                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 803                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 804                 return -EINVAL;
 805         }
 806
 807         rte_ether_addr_copy(
 808                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 809                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 810
 811         dev->data->mac_addrs =
 812                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 813         if (!dev->data->mac_addrs) {
 814                 PMD_INIT_LOG(ERR,
 815                              "Failed to allocate memory to store mac address");
 816                 return -ENOMEM;
 817         }
 818         /* store it to dev data */
 819         rte_ether_addr_copy(
 820                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 821                 &dev->data->mac_addrs[0]);
 822         return 0;
 823 }
 824
 825 /* Find out specific MAC filter */
 826 static struct ice_mac_filter *
 827 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 828 {
 829         struct ice_mac_filter *f;
 830
 831         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 832                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 833                         return f;
 834         }
 835
 836         return NULL;
 837 }
 838
 839 static int
 840 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 841 {
 842         struct ice_fltr_list_entry *m_list_itr = NULL;
 843         struct ice_mac_filter *f;
 844         struct LIST_HEAD_TYPE list_head;
 845         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 846         int ret = 0;
 847
 848         /* If it's added and configured, return */
 849         f = ice_find_mac_filter(vsi, mac_addr);
 850         if (f) {
 851                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 852                 return 0;
 853         }
 854
 855         INIT_LIST_HEAD(&list_head);
 856
 857         m_list_itr = (struct ice_fltr_list_entry *)
 858                 ice_malloc(hw, sizeof(*m_list_itr));
 859         if (!m_list_itr) {
 860                 ret = -ENOMEM;
 861                 goto DONE;
 862         }
 863         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 864                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 865         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 866         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 867         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 868         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 869         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 870
 871         LIST_ADD(&m_list_itr->list_entry, &list_head);
 872
 873         /* Add the mac */
 874         ret = ice_add_mac(hw, &list_head);
 875         if (ret != ICE_SUCCESS) {
 876                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 877                 ret = -EINVAL;
 878                 goto DONE;
 879         }
 880         /* Add the mac addr into mac list */
 881         f = rte_zmalloc(NULL, sizeof(*f), 0);
 882         if (!f) {
 883                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 884                 ret = -ENOMEM;
 885                 goto DONE;
 886         }
 887         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 888         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 889         vsi->mac_num++;
 890
 891         ret = 0;
 892
 893 DONE:
 894         rte_free(m_list_itr);
 895         return ret;
 896 }
 897
 898 static int
 899 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 900 {
 901         struct ice_fltr_list_entry *m_list_itr = NULL;
 902         struct ice_mac_filter *f;
 903         struct LIST_HEAD_TYPE list_head;
 904         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 905         int ret = 0;
 906
 907         /* Can't find it, return an error */
 908         f = ice_find_mac_filter(vsi, mac_addr);
 909         if (!f)
 910                 return -EINVAL;
 911
 912         INIT_LIST_HEAD(&list_head);
 913
 914         m_list_itr = (struct ice_fltr_list_entry *)
 915                 ice_malloc(hw, sizeof(*m_list_itr));
 916         if (!m_list_itr) {
 917                 ret = -ENOMEM;
 918                 goto DONE;
 919         }
 920         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 921                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 922         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 923         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 924         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 925         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 926         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 927
 928         LIST_ADD(&m_list_itr->list_entry, &list_head);
 929
 930         /* remove the mac filter */
 931         ret = ice_remove_mac(hw, &list_head);
 932         if (ret != ICE_SUCCESS) {
 933                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 934                 ret = -EINVAL;
 935                 goto DONE;
 936         }
 937
 938         /* Remove the mac addr from mac list */
 939         TAILQ_REMOVE(&vsi->mac_list, f, next);
 940         rte_free(f);
 941         vsi->mac_num--;
 942
 943         ret = 0;
 944 DONE:
 945         rte_free(m_list_itr);
 946         return ret;
 947 }
 948
 949 /* Find out specific VLAN filter */
 950 static struct ice_vlan_filter *
 951 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 952 {
 953         struct ice_vlan_filter *f;
 954
 955         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 956                 if (vlan_id == f->vlan_info.vlan_id)
 957                         return f;
 958         }
 959
 960         return NULL;
 961 }
 962
 963 static int
 964 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 965 {
 966         struct ice_fltr_list_entry *v_list_itr = NULL;
 967         struct ice_vlan_filter *f;
 968         struct LIST_HEAD_TYPE list_head;
 969         struct ice_hw *hw;
 970         int ret = 0;
 971
 972         if (!vsi || vlan_id > RTE_ETHER_MAX_VLAN_ID)
 973                 return -EINVAL;
 974
 975         hw = ICE_VSI_TO_HW(vsi);
 976
 977         /* If it's added and configured, return. */
 978         f = ice_find_vlan_filter(vsi, vlan_id);
 979         if (f) {
 980                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 981                 return 0;
 982         }
 983
 984         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 985                 return 0;
 986
 987         INIT_LIST_HEAD(&list_head);
 988
 989         v_list_itr = (struct ice_fltr_list_entry *)
 990                       ice_malloc(hw, sizeof(*v_list_itr));
 991         if (!v_list_itr) {
 992                 ret = -ENOMEM;
 993                 goto DONE;
 994         }
 995         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 996         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 997         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 998         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 999         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1000         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1001
1002         LIST_ADD(&v_list_itr->list_entry, &list_head);
1003
1004         /* Add the vlan */
1005         ret = ice_add_vlan(hw, &list_head);
1006         if (ret != ICE_SUCCESS) {
1007                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1008                 ret = -EINVAL;
1009                 goto DONE;
1010         }
1011
1012         /* Add vlan into vlan list */
1013         f = rte_zmalloc(NULL, sizeof(*f), 0);
1014         if (!f) {
1015                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1016                 ret = -ENOMEM;
1017                 goto DONE;
1018         }
1019         f->vlan_info.vlan_id = vlan_id;
1020         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1021         vsi->vlan_num++;
1022
1023         ret = 0;
1024
1025 DONE:
1026         rte_free(v_list_itr);
1027         return ret;
1028 }
1029
1030 static int
1031 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
1032 {
1033         struct ice_fltr_list_entry *v_list_itr = NULL;
1034         struct ice_vlan_filter *f;
1035         struct LIST_HEAD_TYPE list_head;
1036         struct ice_hw *hw;
1037         int ret = 0;
1038
1039         /**
1040          * Vlan 0 is the generic filter for untagged packets
1041          * and can't be removed.
1042          */
1043         if (!vsi || vlan_id == 0 || vlan_id > RTE_ETHER_MAX_VLAN_ID)
1044                 return -EINVAL;
1045
1046         hw = ICE_VSI_TO_HW(vsi);
1047
1048         /* Can't find it, return an error */
1049         f = ice_find_vlan_filter(vsi, vlan_id);
1050         if (!f)
1051                 return -EINVAL;
1052
1053         INIT_LIST_HEAD(&list_head);
1054
1055         v_list_itr = (struct ice_fltr_list_entry *)
1056                       ice_malloc(hw, sizeof(*v_list_itr));
1057         if (!v_list_itr) {
1058                 ret = -ENOMEM;
1059                 goto DONE;
1060         }
1061
1062         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
1063         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1064         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1065         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1066         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1067         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1068
1069         LIST_ADD(&v_list_itr->list_entry, &list_head);
1070
1071         /* remove the vlan filter */
1072         ret = ice_remove_vlan(hw, &list_head);
1073         if (ret != ICE_SUCCESS) {
1074                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1075                 ret = -EINVAL;
1076                 goto DONE;
1077         }
1078
1079         /* Remove the vlan id from vlan list */
1080         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1081         rte_free(f);
1082         vsi->vlan_num--;
1083
1084         ret = 0;
1085 DONE:
1086         rte_free(v_list_itr);
1087         return ret;
1088 }
1089
1090 static int
1091 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1092 {
1093         struct ice_mac_filter *m_f;
1094         struct ice_vlan_filter *v_f;
1095         int ret = 0;
1096
1097         if (!vsi || !vsi->mac_num)
1098                 return -EINVAL;
1099
1100         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1101                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1102                 if (ret != ICE_SUCCESS) {
1103                         ret = -EINVAL;
1104                         goto DONE;
1105                 }
1106         }
1107
1108         if (vsi->vlan_num == 0)
1109                 return 0;
1110
1111         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1112                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
1113                 if (ret != ICE_SUCCESS) {
1114                         ret = -EINVAL;
1115                         goto DONE;
1116                 }
1117         }
1118
1119 DONE:
1120         return ret;
1121 }
1122
1123 /* Enable IRQ0 */
1124 static void
1125 ice_pf_enable_irq0(struct ice_hw *hw)
1126 {
1127         /* reset the registers */
1128         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1129         ICE_READ_REG(hw, PFINT_OICR);
1130
1131 #ifdef ICE_LSE_SPT
1132         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1133                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1134                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1135
1136         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1137                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1138                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1139                        PFINT_OICR_CTL_ITR_INDX_M) |
1140                       PFINT_OICR_CTL_CAUSE_ENA_M);
1141
1142         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1143                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1144                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1145                        PFINT_FW_CTL_ITR_INDX_M) |
1146                       PFINT_FW_CTL_CAUSE_ENA_M);
1147 #else
1148         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1149 #endif
1150
1151         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1152                       GLINT_DYN_CTL_INTENA_M |
1153                       GLINT_DYN_CTL_CLEARPBA_M |
1154                       GLINT_DYN_CTL_ITR_INDX_M);
1155
1156         ice_flush(hw);
1157 }
1158
1159 /* Disable IRQ0 */
1160 static void
1161 ice_pf_disable_irq0(struct ice_hw *hw)
1162 {
1163         /* Disable all interrupt types */
1164         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1165         ice_flush(hw);
1166 }
1167
1168 #ifdef ICE_LSE_SPT
1169 static void
1170 ice_handle_aq_msg(struct rte_eth_dev *dev)
1171 {
1172         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1173         struct ice_ctl_q_info *cq = &hw->adminq;
1174         struct ice_rq_event_info event;
1175         uint16_t pending, opcode;
1176         int ret;
1177
1178         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1179         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1180         if (!event.msg_buf) {
1181                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1182                 return;
1183         }
1184
1185         pending = 1;
1186         while (pending) {
1187                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1188
1189                 if (ret != ICE_SUCCESS) {
1190                         PMD_DRV_LOG(INFO,
1191                                     "Failed to read msg from AdminQ, "
1192                                     "adminq_err: %u",
1193                                     hw->adminq.sq_last_status);
1194                         break;
1195                 }
1196                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1197
1198                 switch (opcode) {
1199                 case ice_aqc_opc_get_link_status:
1200                         ret = ice_link_update(dev, 0);
1201                         if (!ret)
1202                                 rte_eth_dev_callback_process
1203                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1204                         break;
1205                 default:
1206                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1207                                     opcode);
1208                         break;
1209                 }
1210         }
1211         rte_free(event.msg_buf);
1212 }
1213 #endif
1214
1215 /**
1216  * Interrupt handler triggered by NIC for handling
1217  * specific interrupt.
1218  *
1219  * @param handle
1220  *  Pointer to interrupt handle.
1221  * @param param
1222  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1223  *
1224  * @return
1225  *  void
1226  */
1227 static void
1228 ice_interrupt_handler(void *param)
1229 {
1230         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1231         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232         uint32_t oicr;
1233         uint32_t reg;
1234         uint8_t pf_num;
1235         uint8_t event;
1236         uint16_t queue;
1237         int ret;
1238 #ifdef ICE_LSE_SPT
1239         uint32_t int_fw_ctl;
1240 #endif
1241
1242         /* Disable interrupt */
1243         ice_pf_disable_irq0(hw);
1244
1245         /* read out interrupt causes */
1246         oicr = ICE_READ_REG(hw, PFINT_OICR);
1247 #ifdef ICE_LSE_SPT
1248         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1249 #endif
1250
1251         /* No interrupt event indicated */
1252         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1253                 PMD_DRV_LOG(INFO, "No interrupt event");
1254                 goto done;
1255         }
1256
1257 #ifdef ICE_LSE_SPT
1258         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1259                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1260                 ice_handle_aq_msg(dev);
1261         }
1262 #else
1263         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1264                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1265                 ret = ice_link_update(dev, 0);
1266                 if (!ret)
1267                         rte_eth_dev_callback_process
1268                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1269         }
1270 #endif
1271
1272         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1273                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1274                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1275                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1276                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1277                                  GL_MDET_TX_PQM_PF_NUM_S;
1278                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1279                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1280                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1281                                 GL_MDET_TX_PQM_QNUM_S;
1282
1283                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1284                                     "%d by PQM on TX queue %d PF# %d",
1285                                     event, queue, pf_num);
1286                 }
1287
1288                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1289                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1290                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1291                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1292                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1293                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1294                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1295                                 GL_MDET_TX_TCLAN_QNUM_S;
1296
1297                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1298                                     "%d by TCLAN on TX queue %d PF# %d",
1299                                     event, queue, pf_num);
1300                 }
1301         }
1302 done:
1303         /* Enable interrupt */
1304         ice_pf_enable_irq0(hw);
1305         rte_intr_ack(dev->intr_handle);
1306 }
1307
1308 static void
1309 ice_init_proto_xtr(struct rte_eth_dev *dev)
1310 {
1311         struct ice_adapter *ad =
1312                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1313         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1314         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1315         const struct proto_xtr_ol_flag *ol_flag;
1316         bool proto_xtr_enable = false;
1317         int offset;
1318         uint16_t i;
1319
1320         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1321         if (unlikely(pf->proto_xtr == NULL)) {
1322                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1323                 return;
1324         }
1325
1326         for (i = 0; i < pf->lan_nb_qps; i++) {
1327                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1328                                    ad->devargs.proto_xtr[i] :
1329                                    ad->devargs.proto_xtr_dflt;
1330
1331                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1332                         uint8_t type = pf->proto_xtr[i];
1333
1334                         ice_proto_xtr_ol_flag_params[type].required = true;
1335                         proto_xtr_enable = true;
1336                 }
1337         }
1338
1339         if (likely(!proto_xtr_enable))
1340                 return;
1341
1342         ice_check_proto_xtr_support(hw);
1343
1344         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1345         if (unlikely(offset == -1)) {
1346                 PMD_DRV_LOG(ERR,
1347                             "Protocol extraction metadata is disabled in mbuf with error %d",
1348                             -rte_errno);
1349                 return;
1350         }
1351
1352         PMD_DRV_LOG(DEBUG,
1353                     "Protocol extraction metadata offset in mbuf is : %d",
1354                     offset);
1355         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1356
1357         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1358                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1359
1360                 if (!ol_flag->required)
1361                         continue;
1362
1363                 if (!ice_proto_xtr_hw_support[i]) {
1364                         PMD_DRV_LOG(ERR,
1365                                     "Protocol extraction type %u is not supported in hardware",
1366                                     i);
1367                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1368                         break;
1369                 }
1370
1371                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1372                 if (unlikely(offset == -1)) {
1373                         PMD_DRV_LOG(ERR,
1374                                     "Protocol extraction offload '%s' failed to register with error %d",
1375                                     ol_flag->param.name, -rte_errno);
1376
1377                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1378                         break;
1379                 }
1380
1381                 PMD_DRV_LOG(DEBUG,
1382                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1383                             ol_flag->param.name, offset);
1384                 *ol_flag->ol_flag = 1ULL << offset;
1385         }
1386 }
1387
1388 /*  Initialize SW parameters of PF */
1389 static int
1390 ice_pf_sw_init(struct rte_eth_dev *dev)
1391 {
1392         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1393         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1394
1395         pf->lan_nb_qp_max =
1396                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1397                                   hw->func_caps.common_cap.num_rxq);
1398
1399         pf->lan_nb_qps = pf->lan_nb_qp_max;
1400
1401         ice_init_proto_xtr(dev);
1402
1403         if (hw->func_caps.fd_fltr_guar > 0 ||
1404             hw->func_caps.fd_fltr_best_effort > 0) {
1405                 pf->flags |= ICE_FLAG_FDIR;
1406                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1407                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1408         } else {
1409                 pf->fdir_nb_qps = 0;
1410         }
1411         pf->fdir_qp_offset = 0;
1412
1413         return 0;
1414 }
1415
1416 struct ice_vsi *
1417 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1418 {
1419         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1420         struct ice_vsi *vsi = NULL;
1421         struct ice_vsi_ctx vsi_ctx;
1422         int ret;
1423         struct rte_ether_addr broadcast = {
1424                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1425         struct rte_ether_addr mac_addr;
1426         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1427         uint8_t tc_bitmap = 0x1;
1428         uint16_t cfg;
1429
1430         /* hw->num_lports = 1 in NIC mode */
1431         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1432         if (!vsi)
1433                 return NULL;
1434
1435         vsi->idx = pf->next_vsi_idx;
1436         pf->next_vsi_idx++;
1437         vsi->type = type;
1438         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1439         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1440         vsi->vlan_anti_spoof_on = 0;
1441         vsi->vlan_filter_on = 1;
1442         TAILQ_INIT(&vsi->mac_list);
1443         TAILQ_INIT(&vsi->vlan_list);
1444
1445         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1446         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1447                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1448                         hw->func_caps.common_cap.rss_table_size;
1449         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1450
1451         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1452         switch (type) {
1453         case ICE_VSI_PF:
1454                 vsi->nb_qps = pf->lan_nb_qps;
1455                 vsi->base_queue = 1;
1456                 ice_vsi_config_default_rss(&vsi_ctx.info);
1457                 vsi_ctx.alloc_from_pool = true;
1458                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1459                 /* switch_id is queried by get_switch_config aq, which is done
1460                  * by ice_init_hw
1461                  */
1462                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1463                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1464                 /* Allow all untagged or tagged packets */
1465                 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1466                 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1467                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1468                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1469
1470                 /* FDIR */
1471                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1472                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1473                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1474                 cfg = ICE_AQ_VSI_FD_ENABLE;
1475                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1476                 vsi_ctx.info.max_fd_fltr_dedicated =
1477                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1478                 vsi_ctx.info.max_fd_fltr_shared =
1479                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1480
1481                 /* Enable VLAN/UP trip */
1482                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1483                                                       &vsi_ctx.info,
1484                                                       ICE_DEFAULT_TCMAP);
1485                 if (ret) {
1486                         PMD_INIT_LOG(ERR,
1487                                      "tc queue mapping with vsi failed, "
1488                                      "err = %d",
1489                                      ret);
1490                         goto fail_mem;
1491                 }
1492
1493                 break;
1494         case ICE_VSI_CTRL:
1495                 vsi->nb_qps = pf->fdir_nb_qps;
1496                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1497                 vsi_ctx.alloc_from_pool = true;
1498                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1499
1500                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1501                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1502                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1503                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1504                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1505                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1506                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1507                                                       &vsi_ctx.info,
1508                                                       ICE_DEFAULT_TCMAP);
1509                 if (ret) {
1510                         PMD_INIT_LOG(ERR,
1511                                      "tc queue mapping with vsi failed, "
1512                                      "err = %d",
1513                                      ret);
1514                         goto fail_mem;
1515                 }
1516                 break;
1517         default:
1518                 /* for other types of VSI */
1519                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1520                 goto fail_mem;
1521         }
1522
1523         /* VF has MSIX interrupt in VF range, don't allocate here */
1524         if (type == ICE_VSI_PF) {
1525                 ret = ice_res_pool_alloc(&pf->msix_pool,
1526                                          RTE_MIN(vsi->nb_qps,
1527                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1528                 if (ret < 0) {
1529                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1530                                      vsi->vsi_id, ret);
1531                 }
1532                 vsi->msix_intr = ret;
1533                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1534         } else if (type == ICE_VSI_CTRL) {
1535                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1536                 if (ret < 0) {
1537                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1538                                     vsi->vsi_id, ret);
1539                 }
1540                 vsi->msix_intr = ret;
1541                 vsi->nb_msix = 1;
1542         } else {
1543                 vsi->msix_intr = 0;
1544                 vsi->nb_msix = 0;
1545         }
1546         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1547         if (ret != ICE_SUCCESS) {
1548                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1549                 goto fail_mem;
1550         }
1551         /* store vsi information is SW structure */
1552         vsi->vsi_id = vsi_ctx.vsi_num;
1553         vsi->info = vsi_ctx.info;
1554         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1555         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1556
1557         if (type == ICE_VSI_PF) {
1558                 /* MAC configuration */
1559                 rte_ether_addr_copy((struct rte_ether_addr *)
1560                                         hw->port_info->mac.perm_addr,
1561                                     &pf->dev_addr);
1562
1563                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1564                 ret = ice_add_mac_filter(vsi, &mac_addr);
1565                 if (ret != ICE_SUCCESS)
1566                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1567
1568                 rte_ether_addr_copy(&broadcast, &mac_addr);
1569                 ret = ice_add_mac_filter(vsi, &mac_addr);
1570                 if (ret != ICE_SUCCESS)
1571                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1572         }
1573
1574         /* At the beginning, only TC0. */
1575         /* What we need here is the maximam number of the TX queues.
1576          * Currently vsi->nb_qps means it.
1577          * Correct it if any change.
1578          */
1579         max_txqs[0] = vsi->nb_qps;
1580         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1581                               tc_bitmap, max_txqs);
1582         if (ret != ICE_SUCCESS)
1583                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1584
1585         return vsi;
1586 fail_mem:
1587         rte_free(vsi);
1588         pf->next_vsi_idx--;
1589         return NULL;
1590 }
1591
1592 static int
1593 ice_send_driver_ver(struct ice_hw *hw)
1594 {
1595         struct ice_driver_ver dv;
1596
1597         /* we don't have driver version use 0 for dummy */
1598         dv.major_ver = 0;
1599         dv.minor_ver = 0;
1600         dv.build_ver = 0;
1601         dv.subbuild_ver = 0;
1602         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1603
1604         return ice_aq_send_driver_ver(hw, &dv, NULL);
1605 }
1606
1607 static int
1608 ice_pf_setup(struct ice_pf *pf)
1609 {
1610         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1611         struct ice_vsi *vsi;
1612         uint16_t unused;
1613
1614         /* Clear all stats counters */
1615         pf->offset_loaded = false;
1616         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1617         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1618         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1619         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1620
1621         /* force guaranteed filter pool for PF */
1622         ice_alloc_fd_guar_item(hw, &unused,
1623                                hw->func_caps.fd_fltr_guar);
1624         /* force shared filter pool for PF */
1625         ice_alloc_fd_shrd_item(hw, &unused,
1626                                hw->func_caps.fd_fltr_best_effort);
1627
1628         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1629         if (!vsi) {
1630                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1631                 return -EINVAL;
1632         }
1633
1634         pf->main_vsi = vsi;
1635
1636         return 0;
1637 }
1638
1639 /*
1640  * Extract device serial number from PCIe Configuration Space and
1641  * determine the pkg file path according to the DSN.
1642  */
1643 static int
1644 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1645 {
1646         off_t pos;
1647         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1648         uint32_t dsn_low, dsn_high;
1649         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1650
1651         pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1652
1653         if (pos) {
1654                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1655                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1656                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1657                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1658         } else {
1659                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1660                 goto fail_dsn;
1661         }
1662
1663         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1664                 ICE_MAX_PKG_FILENAME_SIZE);
1665         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1666                 return 0;
1667
1668         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1669                 ICE_MAX_PKG_FILENAME_SIZE);
1670         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1671                 return 0;
1672
1673 fail_dsn:
1674         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1675         if (!access(pkg_file, 0))
1676                 return 0;
1677         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1678         return 0;
1679 }
1680
1681 enum ice_pkg_type
1682 ice_load_pkg_type(struct ice_hw *hw)
1683 {
1684         enum ice_pkg_type package_type;
1685
1686         /* store the activated package type (OS default or Comms) */
1687         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1688                 ICE_PKG_NAME_SIZE))
1689                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1690         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1691                 ICE_PKG_NAME_SIZE))
1692                 package_type = ICE_PKG_TYPE_COMMS;
1693         else
1694                 package_type = ICE_PKG_TYPE_UNKNOWN;
1695
1696         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s",
1697                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1698                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1699                 hw->active_pkg_name);
1700
1701         return package_type;
1702 }
1703
1704 static int ice_load_pkg(struct rte_eth_dev *dev)
1705 {
1706         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1707         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1708         int err;
1709         uint8_t *buf;
1710         int buf_len;
1711         FILE *file;
1712         struct stat fstat;
1713         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1714         struct ice_adapter *ad =
1715                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1716
1717         ice_pkg_file_search_path(pci_dev, pkg_file);
1718
1719         file = fopen(pkg_file, "rb");
1720         if (!file)  {
1721                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1722                 return -1;
1723         }
1724
1725         err = stat(pkg_file, &fstat);
1726         if (err) {
1727                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1728                 fclose(file);
1729                 return err;
1730         }
1731
1732         buf_len = fstat.st_size;
1733         buf = rte_malloc(NULL, buf_len, 0);
1734
1735         if (!buf) {
1736                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1737                                 buf_len);
1738                 fclose(file);
1739                 return -1;
1740         }
1741
1742         err = fread(buf, buf_len, 1, file);
1743         if (err != 1) {
1744                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1745                 fclose(file);
1746                 err = -1;
1747                 goto fail_exit;
1748         }
1749
1750         fclose(file);
1751
1752         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1753         if (err) {
1754                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1755                 goto fail_exit;
1756         }
1757
1758         /* store the loaded pkg type info */
1759         ad->active_pkg_type = ice_load_pkg_type(hw);
1760
1761         err = ice_init_hw_tbls(hw);
1762         if (err) {
1763                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1764                 goto fail_init_tbls;
1765         }
1766
1767         return 0;
1768
1769 fail_init_tbls:
1770         rte_free(hw->pkg_copy);
1771 fail_exit:
1772         rte_free(buf);
1773         return err;
1774 }
1775
1776 static void
1777 ice_base_queue_get(struct ice_pf *pf)
1778 {
1779         uint32_t reg;
1780         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1781
1782         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1783         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1784                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1785         } else {
1786                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1787                                         " index");
1788         }
1789 }
1790
1791 static int
1792 parse_bool(const char *key, const char *value, void *args)
1793 {
1794         int *i = (int *)args;
1795         char *end;
1796         int num;
1797
1798         num = strtoul(value, &end, 10);
1799
1800         if (num != 0 && num != 1) {
1801                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1802                         "value must be 0 or 1",
1803                         value, key);
1804                 return -1;
1805         }
1806
1807         *i = num;
1808         return 0;
1809 }
1810
1811 static int ice_parse_devargs(struct rte_eth_dev *dev)
1812 {
1813         struct ice_adapter *ad =
1814                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1815         struct rte_devargs *devargs = dev->device->devargs;
1816         struct rte_kvargs *kvlist;
1817         int ret;
1818
1819         if (devargs == NULL)
1820                 return 0;
1821
1822         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1823         if (kvlist == NULL) {
1824                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1825                 return -EINVAL;
1826         }
1827
1828         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1829         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1830                sizeof(ad->devargs.proto_xtr));
1831
1832         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1833                                  &handle_proto_xtr_arg, &ad->devargs);
1834         if (ret)
1835                 goto bail;
1836
1837         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1838                                  &parse_bool, &ad->devargs.safe_mode_support);
1839         if (ret)
1840                 goto bail;
1841
1842         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1843                                  &parse_bool, &ad->devargs.pipe_mode_support);
1844         if (ret)
1845                 goto bail;
1846
1847 bail:
1848         rte_kvargs_free(kvlist);
1849         return ret;
1850 }
1851
1852 /* Forward LLDP packets to default VSI by set switch rules */
1853 static int
1854 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1855 {
1856         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1857         struct ice_fltr_list_entry *s_list_itr = NULL;
1858         struct LIST_HEAD_TYPE list_head;
1859         int ret = 0;
1860
1861         INIT_LIST_HEAD(&list_head);
1862
1863         s_list_itr = (struct ice_fltr_list_entry *)
1864                         ice_malloc(hw, sizeof(*s_list_itr));
1865         if (!s_list_itr)
1866                 return -ENOMEM;
1867         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1868         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1869         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1870                         RTE_ETHER_TYPE_LLDP;
1871         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1872         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1873         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1874         LIST_ADD(&s_list_itr->list_entry, &list_head);
1875         if (on)
1876                 ret = ice_add_eth_mac(hw, &list_head);
1877         else
1878                 ret = ice_remove_eth_mac(hw, &list_head);
1879
1880         rte_free(s_list_itr);
1881         return ret;
1882 }
1883
1884 static enum ice_status
1885 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1886                 uint16_t num, uint16_t desc_id,
1887                 uint16_t *prof_buf, uint16_t *num_prof)
1888 {
1889         struct ice_aqc_res_elem *resp_buf;
1890         int ret;
1891         uint16_t buf_len;
1892         bool res_shared = 1;
1893         struct ice_aq_desc aq_desc;
1894         struct ice_sq_cd *cd = NULL;
1895         struct ice_aqc_get_allocd_res_desc *cmd =
1896                         &aq_desc.params.get_res_desc;
1897
1898         buf_len = sizeof(*resp_buf) * num;
1899         resp_buf = ice_malloc(hw, buf_len);
1900         if (!resp_buf)
1901                 return -ENOMEM;
1902
1903         ice_fill_dflt_direct_cmd_desc(&aq_desc,
1904                         ice_aqc_opc_get_allocd_res_desc);
1905
1906         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1907                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
1908                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1909         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1910
1911         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1912         if (!ret)
1913                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1914         else
1915                 goto exit;
1916
1917         ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
1918                         (*num_prof), ICE_NONDMA_TO_NONDMA);
1919
1920 exit:
1921         rte_free(resp_buf);
1922         return ret;
1923 }
1924 static int
1925 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1926 {
1927         int ret;
1928         uint16_t prof_id;
1929         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1930         uint16_t first_desc = 1;
1931         uint16_t num_prof = 0;
1932
1933         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1934                         first_desc, prof_buf, &num_prof);
1935         if (ret) {
1936                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
1937                 return ret;
1938         }
1939
1940         for (prof_id = 0; prof_id < num_prof; prof_id++) {
1941                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
1942                 if (ret) {
1943                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
1944                         return ret;
1945                 }
1946         }
1947         return 0;
1948 }
1949
1950 static int
1951 ice_reset_fxp_resource(struct ice_hw *hw)
1952 {
1953         int ret;
1954
1955         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
1956         if (ret) {
1957                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
1958                 return ret;
1959         }
1960
1961         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
1962         if (ret) {
1963                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
1964                 return ret;
1965         }
1966
1967         return 0;
1968 }
1969
1970 static void
1971 ice_rss_ctx_init(struct ice_pf *pf)
1972 {
1973         memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
1974 }
1975
1976 static uint64_t
1977 ice_get_supported_rxdid(struct ice_hw *hw)
1978 {
1979         uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
1980         uint32_t regval;
1981         int i;
1982
1983         supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
1984
1985         for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
1986                 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
1987                 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
1988                         & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
1989                         supported_rxdid |= BIT(i);
1990         }
1991         return supported_rxdid;
1992 }
1993
1994 static int
1995 ice_dev_init(struct rte_eth_dev *dev)
1996 {
1997         struct rte_pci_device *pci_dev;
1998         struct rte_intr_handle *intr_handle;
1999         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2000         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2001         struct ice_adapter *ad =
2002                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2003         struct ice_vsi *vsi;
2004         int ret;
2005
2006         dev->dev_ops = &ice_eth_dev_ops;
2007         dev->rx_queue_count = ice_rx_queue_count;
2008         dev->rx_descriptor_status = ice_rx_descriptor_status;
2009         dev->tx_descriptor_status = ice_tx_descriptor_status;
2010         dev->rx_pkt_burst = ice_recv_pkts;
2011         dev->tx_pkt_burst = ice_xmit_pkts;
2012         dev->tx_pkt_prepare = ice_prep_pkts;
2013
2014         /* for secondary processes, we don't initialise any further as primary
2015          * has already done this work.
2016          */
2017         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2018                 ice_set_rx_function(dev);
2019                 ice_set_tx_function(dev);
2020                 return 0;
2021         }
2022
2023         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2024
2025         ice_set_default_ptype_table(dev);
2026         pci_dev = RTE_DEV_TO_PCI(dev->device);
2027         intr_handle = &pci_dev->intr_handle;
2028
2029         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2030         pf->adapter->eth_dev = dev;
2031         pf->dev_data = dev->data;
2032         hw->back = pf->adapter;
2033         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2034         hw->vendor_id = pci_dev->id.vendor_id;
2035         hw->device_id = pci_dev->id.device_id;
2036         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2037         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2038         hw->bus.device = pci_dev->addr.devid;
2039         hw->bus.func = pci_dev->addr.function;
2040
2041         ret = ice_parse_devargs(dev);
2042         if (ret) {
2043                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2044                 return -EINVAL;
2045         }
2046
2047         ice_init_controlq_parameter(hw);
2048
2049         ret = ice_init_hw(hw);
2050         if (ret) {
2051                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2052                 return -EINVAL;
2053         }
2054
2055         ret = ice_load_pkg(dev);
2056         if (ret) {
2057                 if (ad->devargs.safe_mode_support == 0) {
2058                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2059                                         "Use safe-mode-support=1 to enter Safe Mode");
2060                         return ret;
2061                 }
2062
2063                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2064                                         "Entering Safe Mode");
2065                 ad->is_safe_mode = 1;
2066         }
2067
2068         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2069                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2070                      hw->api_maj_ver, hw->api_min_ver);
2071
2072         ice_pf_sw_init(dev);
2073         ret = ice_init_mac_address(dev);
2074         if (ret) {
2075                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2076                 goto err_init_mac;
2077         }
2078
2079         ret = ice_res_pool_init(&pf->msix_pool, 1,
2080                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2081         if (ret) {
2082                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2083                 goto err_msix_pool_init;
2084         }
2085
2086         ret = ice_pf_setup(pf);
2087         if (ret) {
2088                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2089                 goto err_pf_setup;
2090         }
2091
2092         ret = ice_send_driver_ver(hw);
2093         if (ret) {
2094                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2095                 goto err_pf_setup;
2096         }
2097
2098         vsi = pf->main_vsi;
2099
2100         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2101         if (ret != ICE_SUCCESS)
2102                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2103         ret = ice_init_dcb(hw, true);
2104         if (ret != ICE_SUCCESS)
2105                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2106         /* Forward LLDP packets to default VSI */
2107         ret = ice_vsi_config_sw_lldp(vsi, true);
2108         if (ret != ICE_SUCCESS)
2109                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2110         /* register callback func to eal lib */
2111         rte_intr_callback_register(intr_handle,
2112                                    ice_interrupt_handler, dev);
2113
2114         ice_pf_enable_irq0(hw);
2115
2116         /* enable uio intr after callback register */
2117         rte_intr_enable(intr_handle);
2118
2119         /* get base queue pairs index  in the device */
2120         ice_base_queue_get(pf);
2121
2122         /* Initialize RSS context for gtpu_eh */
2123         ice_rss_ctx_init(pf);
2124
2125         if (!ad->is_safe_mode) {
2126                 ret = ice_flow_init(ad);
2127                 if (ret) {
2128                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2129                         return ret;
2130                 }
2131         }
2132
2133         ret = ice_reset_fxp_resource(hw);
2134         if (ret) {
2135                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2136                 return ret;
2137         }
2138
2139         pf->supported_rxdid = ice_get_supported_rxdid(hw);
2140
2141         return 0;
2142
2143 err_pf_setup:
2144         ice_res_pool_destroy(&pf->msix_pool);
2145 err_msix_pool_init:
2146         rte_free(dev->data->mac_addrs);
2147         dev->data->mac_addrs = NULL;
2148 err_init_mac:
2149         ice_sched_cleanup_all(hw);
2150         rte_free(hw->port_info);
2151         ice_shutdown_all_ctrlq(hw);
2152         rte_free(pf->proto_xtr);
2153
2154         return ret;
2155 }
2156
2157 int
2158 ice_release_vsi(struct ice_vsi *vsi)
2159 {
2160         struct ice_hw *hw;
2161         struct ice_vsi_ctx vsi_ctx;
2162         enum ice_status ret;
2163         int error = 0;
2164
2165         if (!vsi)
2166                 return error;
2167
2168         hw = ICE_VSI_TO_HW(vsi);
2169
2170         ice_remove_all_mac_vlan_filters(vsi);
2171
2172         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2173
2174         vsi_ctx.vsi_num = vsi->vsi_id;
2175         vsi_ctx.info = vsi->info;
2176         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2177         if (ret != ICE_SUCCESS) {
2178                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2179                 error = -1;
2180         }
2181
2182         rte_free(vsi->rss_lut);
2183         rte_free(vsi->rss_key);
2184         rte_free(vsi);
2185         return error;
2186 }
2187
2188 void
2189 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2190 {
2191         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2192         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2193         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2194         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2195         uint16_t msix_intr, i;
2196
2197         /* disable interrupt and also clear all the exist config */
2198         for (i = 0; i < vsi->nb_qps; i++) {
2199                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2200                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2201                 rte_wmb();
2202         }
2203
2204         if (rte_intr_allow_others(intr_handle))
2205                 /* vfio-pci */
2206                 for (i = 0; i < vsi->nb_msix; i++) {
2207                         msix_intr = vsi->msix_intr + i;
2208                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2209                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2210                 }
2211         else
2212                 /* igb_uio */
2213                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2214 }
2215
2216 static int
2217 ice_dev_stop(struct rte_eth_dev *dev)
2218 {
2219         struct rte_eth_dev_data *data = dev->data;
2220         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2221         struct ice_vsi *main_vsi = pf->main_vsi;
2222         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2223         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2224         uint16_t i;
2225
2226         /* avoid stopping again */
2227         if (pf->adapter_stopped)
2228                 return 0;
2229
2230         /* stop and clear all Rx queues */
2231         for (i = 0; i < data->nb_rx_queues; i++)
2232                 ice_rx_queue_stop(dev, i);
2233
2234         /* stop and clear all Tx queues */
2235         for (i = 0; i < data->nb_tx_queues; i++)
2236                 ice_tx_queue_stop(dev, i);
2237
2238         /* disable all queue interrupts */
2239         ice_vsi_disable_queues_intr(main_vsi);
2240
2241         if (pf->init_link_up)
2242                 ice_dev_set_link_up(dev);
2243         else
2244                 ice_dev_set_link_down(dev);
2245
2246         /* Clean datapath event and queue/vec mapping */
2247         rte_intr_efd_disable(intr_handle);
2248         if (intr_handle->intr_vec) {
2249                 rte_free(intr_handle->intr_vec);
2250                 intr_handle->intr_vec = NULL;
2251         }
2252
2253         pf->adapter_stopped = true;
2254         dev->data->dev_started = 0;
2255
2256         return 0;
2257 }
2258
2259 static int
2260 ice_dev_close(struct rte_eth_dev *dev)
2261 {
2262         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2263         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2264         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2265         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2266         struct ice_adapter *ad =
2267                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2268         int ret;
2269
2270         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2271                 return 0;
2272
2273         /* Since stop will make link down, then the link event will be
2274          * triggered, disable the irq firstly to avoid the port_infoe etc
2275          * resources deallocation causing the interrupt service thread
2276          * crash.
2277          */
2278         ice_pf_disable_irq0(hw);
2279
2280         ret = ice_dev_stop(dev);
2281
2282         if (!ad->is_safe_mode)
2283                 ice_flow_uninit(ad);
2284
2285         /* release all queue resource */
2286         ice_free_queues(dev);
2287
2288         ice_res_pool_destroy(&pf->msix_pool);
2289         ice_release_vsi(pf->main_vsi);
2290         ice_sched_cleanup_all(hw);
2291         ice_free_hw_tbls(hw);
2292         rte_free(hw->port_info);
2293         hw->port_info = NULL;
2294         ice_shutdown_all_ctrlq(hw);
2295         rte_free(pf->proto_xtr);
2296         pf->proto_xtr = NULL;
2297
2298         /* disable uio intr before callback unregister */
2299         rte_intr_disable(intr_handle);
2300
2301         /* unregister callback func from eal lib */
2302         rte_intr_callback_unregister(intr_handle,
2303                                      ice_interrupt_handler, dev);
2304
2305         return ret;
2306 }
2307
2308 static int
2309 ice_dev_uninit(struct rte_eth_dev *dev)
2310 {
2311         ice_dev_close(dev);
2312
2313         return 0;
2314 }
2315
2316 static bool
2317 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2318 {
2319         return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2320 }
2321
2322 static void
2323 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2324 {
2325         cfg->hash_flds = 0;
2326         cfg->addl_hdrs = 0;
2327         cfg->symm = 0;
2328         cfg->hdr_type = ICE_RSS_ANY_HEADERS;
2329 }
2330
2331 static int
2332 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2333 {
2334         enum ice_status status = ICE_SUCCESS;
2335         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2336         struct ice_vsi *vsi = pf->main_vsi;
2337
2338         if (!is_hash_cfg_valid(cfg))
2339                 return -ENOENT;
2340
2341         status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2342         if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2343                 PMD_DRV_LOG(ERR,
2344                             "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2345                             vsi->idx, status);
2346                 return -EBUSY;
2347         }
2348
2349         return 0;
2350 }
2351
2352 static int
2353 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2354 {
2355         enum ice_status status = ICE_SUCCESS;
2356         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2357         struct ice_vsi *vsi = pf->main_vsi;
2358
2359         if (!is_hash_cfg_valid(cfg))
2360                 return -ENOENT;
2361
2362         status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2363         if (status) {
2364                 PMD_DRV_LOG(ERR,
2365                             "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2366                             vsi->idx, status);
2367                 return -EBUSY;
2368         }
2369
2370         return 0;
2371 }
2372
2373 static int
2374 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2375 {
2376         int ret;
2377
2378         ret = ice_hash_moveout(pf, cfg);
2379         if (ret && (ret != -ENOENT))
2380                 return ret;
2381
2382         hash_cfg_reset(cfg);
2383
2384         return 0;
2385 }
2386
2387 static int
2388 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2389                          u8 ctx_idx)
2390 {
2391         int ret;
2392
2393         switch (ctx_idx) {
2394         case ICE_HASH_GTPU_CTX_EH_IP:
2395                 ret = ice_hash_remove(pf,
2396                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2397                 if (ret && (ret != -ENOENT))
2398                         return ret;
2399
2400                 ret = ice_hash_remove(pf,
2401                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2402                 if (ret && (ret != -ENOENT))
2403                         return ret;
2404
2405                 ret = ice_hash_remove(pf,
2406                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2407                 if (ret && (ret != -ENOENT))
2408                         return ret;
2409
2410                 ret = ice_hash_remove(pf,
2411                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2412                 if (ret && (ret != -ENOENT))
2413                         return ret;
2414
2415                 ret = ice_hash_remove(pf,
2416                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2417                 if (ret && (ret != -ENOENT))
2418                         return ret;
2419
2420                 ret = ice_hash_remove(pf,
2421                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2422                 if (ret && (ret != -ENOENT))
2423                         return ret;
2424
2425                 ret = ice_hash_remove(pf,
2426                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2427                 if (ret && (ret != -ENOENT))
2428                         return ret;
2429
2430                 ret = ice_hash_remove(pf,
2431                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2432                 if (ret && (ret != -ENOENT))
2433                         return ret;
2434
2435                 break;
2436         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2437                 ret = ice_hash_remove(pf,
2438                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2439                 if (ret && (ret != -ENOENT))
2440                         return ret;
2441
2442                 ret = ice_hash_remove(pf,
2443                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2444                 if (ret && (ret != -ENOENT))
2445                         return ret;
2446
2447                 ret = ice_hash_moveout(pf,
2448                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2449                 if (ret && (ret != -ENOENT))
2450                         return ret;
2451
2452                 ret = ice_hash_moveout(pf,
2453                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2454                 if (ret && (ret != -ENOENT))
2455                         return ret;
2456
2457                 ret = ice_hash_moveout(pf,
2458                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2459                 if (ret && (ret != -ENOENT))
2460                         return ret;
2461
2462                 ret = ice_hash_moveout(pf,
2463                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2464                 if (ret && (ret != -ENOENT))
2465                         return ret;
2466
2467                 break;
2468         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2469                 ret = ice_hash_remove(pf,
2470                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2471                 if (ret && (ret != -ENOENT))
2472                         return ret;
2473
2474                 ret = ice_hash_remove(pf,
2475                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2476                 if (ret && (ret != -ENOENT))
2477                         return ret;
2478
2479                 ret = ice_hash_moveout(pf,
2480                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2481                 if (ret && (ret != -ENOENT))
2482                         return ret;
2483
2484                 ret = ice_hash_moveout(pf,
2485                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2486                 if (ret && (ret != -ENOENT))
2487                         return ret;
2488
2489                 ret = ice_hash_moveout(pf,
2490                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2491                 if (ret && (ret != -ENOENT))
2492                         return ret;
2493
2494                 ret = ice_hash_moveout(pf,
2495                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2496                 if (ret && (ret != -ENOENT))
2497                         return ret;
2498
2499                 break;
2500         case ICE_HASH_GTPU_CTX_UP_IP:
2501                 ret = ice_hash_remove(pf,
2502                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2503                 if (ret && (ret != -ENOENT))
2504                         return ret;
2505
2506                 ret = ice_hash_remove(pf,
2507                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2508                 if (ret && (ret != -ENOENT))
2509                         return ret;
2510
2511                 ret = ice_hash_moveout(pf,
2512                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2513                 if (ret && (ret != -ENOENT))
2514                         return ret;
2515
2516                 ret = ice_hash_moveout(pf,
2517                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2518                 if (ret && (ret != -ENOENT))
2519                         return ret;
2520
2521                 ret = ice_hash_moveout(pf,
2522                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2523                 if (ret && (ret != -ENOENT))
2524                         return ret;
2525
2526                 break;
2527         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2528         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2529                 ret = ice_hash_moveout(pf,
2530                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2531                 if (ret && (ret != -ENOENT))
2532                         return ret;
2533
2534                 ret = ice_hash_moveout(pf,
2535                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2536                 if (ret && (ret != -ENOENT))
2537                         return ret;
2538
2539                 ret = ice_hash_moveout(pf,
2540                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2541                 if (ret && (ret != -ENOENT))
2542                         return ret;
2543
2544                 break;
2545         case ICE_HASH_GTPU_CTX_DW_IP:
2546                 ret = ice_hash_remove(pf,
2547                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2548                 if (ret && (ret != -ENOENT))
2549                         return ret;
2550
2551                 ret = ice_hash_remove(pf,
2552                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2553                 if (ret && (ret != -ENOENT))
2554                         return ret;
2555
2556                 ret = ice_hash_moveout(pf,
2557                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2558                 if (ret && (ret != -ENOENT))
2559                         return ret;
2560
2561                 ret = ice_hash_moveout(pf,
2562                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2563                 if (ret && (ret != -ENOENT))
2564                         return ret;
2565
2566                 ret = ice_hash_moveout(pf,
2567                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2568                 if (ret && (ret != -ENOENT))
2569                         return ret;
2570
2571                 break;
2572         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2573         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2574                 ret = ice_hash_moveout(pf,
2575                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2576                 if (ret && (ret != -ENOENT))
2577                         return ret;
2578
2579                 ret = ice_hash_moveout(pf,
2580                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2581                 if (ret && (ret != -ENOENT))
2582                         return ret;
2583
2584                 ret = ice_hash_moveout(pf,
2585                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2586                 if (ret && (ret != -ENOENT))
2587                         return ret;
2588
2589                 break;
2590         default:
2591                 break;
2592         }
2593
2594         return 0;
2595 }
2596
2597 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2598 {
2599         u8 eh_idx, ip_idx;
2600
2601         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2602                 eh_idx = 0;
2603         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2604                 eh_idx = 1;
2605         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2606                 eh_idx = 2;
2607         else
2608                 return ICE_HASH_GTPU_CTX_MAX;
2609
2610         ip_idx = 0;
2611         if (hdr & ICE_FLOW_SEG_HDR_UDP)
2612                 ip_idx = 1;
2613         else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2614                 ip_idx = 2;
2615
2616         if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2617                 return eh_idx * 3 + ip_idx;
2618         else
2619                 return ICE_HASH_GTPU_CTX_MAX;
2620 }
2621
2622 static int
2623 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2624 {
2625         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2626
2627         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2628                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2629                                                 gtpu_ctx_idx);
2630         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2631                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2632                                                 gtpu_ctx_idx);
2633
2634         return 0;
2635 }
2636
2637 static int
2638 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2639                           u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2640 {
2641         int ret;
2642
2643         if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2644                 ctx->ctx[ctx_idx] = *cfg;
2645
2646         switch (ctx_idx) {
2647         case ICE_HASH_GTPU_CTX_EH_IP:
2648                 break;
2649         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2650                 ret = ice_hash_moveback(pf,
2651                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2652                 if (ret && (ret != -ENOENT))
2653                         return ret;
2654
2655                 ret = ice_hash_moveback(pf,
2656                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2657                 if (ret && (ret != -ENOENT))
2658                         return ret;
2659
2660                 ret = ice_hash_moveback(pf,
2661                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2662                 if (ret && (ret != -ENOENT))
2663                         return ret;
2664
2665                 ret = ice_hash_moveback(pf,
2666                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2667                 if (ret && (ret != -ENOENT))
2668                         return ret;
2669
2670                 break;
2671         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2672                 ret = ice_hash_moveback(pf,
2673                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2674                 if (ret && (ret != -ENOENT))
2675                         return ret;
2676
2677                 ret = ice_hash_moveback(pf,
2678                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2679                 if (ret && (ret != -ENOENT))
2680                         return ret;
2681
2682                 ret = ice_hash_moveback(pf,
2683                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2684                 if (ret && (ret != -ENOENT))
2685                         return ret;
2686
2687                 ret = ice_hash_moveback(pf,
2688                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2689                 if (ret && (ret != -ENOENT))
2690                         return ret;
2691
2692                 break;
2693         case ICE_HASH_GTPU_CTX_UP_IP:
2694         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2695         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2696         case ICE_HASH_GTPU_CTX_DW_IP:
2697         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2698         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2699                 ret = ice_hash_moveback(pf,
2700                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2701                 if (ret && (ret != -ENOENT))
2702                         return ret;
2703
2704                 ret = ice_hash_moveback(pf,
2705                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2706                 if (ret && (ret != -ENOENT))
2707                         return ret;
2708
2709                 ret = ice_hash_moveback(pf,
2710                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2711                 if (ret && (ret != -ENOENT))
2712                         return ret;
2713
2714                 break;
2715         default:
2716                 break;
2717         }
2718
2719         return 0;
2720 }
2721
2722 static int
2723 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2724 {
2725         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2726
2727         if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2728                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2729                                                  gtpu_ctx_idx, cfg);
2730         else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2731                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2732                                                  gtpu_ctx_idx, cfg);
2733
2734         return 0;
2735 }
2736
2737 static void
2738 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2739 {
2740         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2741
2742         if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2743                 return;
2744
2745         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2746                 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2747         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2748                 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2749 }
2750
2751 int
2752 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2753                      struct ice_rss_hash_cfg *cfg)
2754 {
2755         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2756         int ret;
2757
2758         ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2759         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2760                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2761
2762         ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2763
2764         return 0;
2765 }
2766
2767 int
2768 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2769                      struct ice_rss_hash_cfg *cfg)
2770 {
2771         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2772         int ret;
2773
2774         ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2775         if (ret)
2776                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2777
2778         ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2779         if (ret)
2780                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2781
2782         ret = ice_add_rss_cfg_post(pf, cfg);
2783         if (ret)
2784                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2785
2786         return 0;
2787 }
2788
2789 static void
2790 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2791 {
2792         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2793         struct ice_vsi *vsi = pf->main_vsi;
2794         struct ice_rss_hash_cfg cfg;
2795         int ret;
2796
2797 #define ICE_RSS_HF_ALL ( \
2798         ETH_RSS_IPV4 | \
2799         ETH_RSS_IPV6 | \
2800         ETH_RSS_NONFRAG_IPV4_UDP | \
2801         ETH_RSS_NONFRAG_IPV6_UDP | \
2802         ETH_RSS_NONFRAG_IPV4_TCP | \
2803         ETH_RSS_NONFRAG_IPV6_TCP | \
2804         ETH_RSS_NONFRAG_IPV4_SCTP | \
2805         ETH_RSS_NONFRAG_IPV6_SCTP)
2806
2807         ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2808         if (ret)
2809                 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2810                             __func__, ret);
2811
2812         cfg.symm = 0;
2813         cfg.hdr_type = ICE_RSS_ANY_HEADERS;
2814         /* Configure RSS for IPv4 with src/dst addr as input set */
2815         if (rss_hf & ETH_RSS_IPV4) {
2816                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2817                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2818                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2819                 if (ret)
2820                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2821                                     __func__, ret);
2822         }
2823
2824         /* Configure RSS for IPv6 with src/dst addr as input set */
2825         if (rss_hf & ETH_RSS_IPV6) {
2826                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2827                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2828                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2829                 if (ret)
2830                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2831                                     __func__, ret);
2832         }
2833
2834         /* Configure RSS for udp4 with src/dst addr and port as input set */
2835         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2836                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2837                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2838                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2839                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2840                 if (ret)
2841                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2842                                     __func__, ret);
2843         }
2844
2845         /* Configure RSS for udp6 with src/dst addr and port as input set */
2846         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2847                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2848                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2849                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2850                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2851                 if (ret)
2852                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2853                                     __func__, ret);
2854         }
2855
2856         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2857         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2858                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2859                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2860                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2861                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2862                 if (ret)
2863                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2864                                     __func__, ret);
2865         }
2866
2867         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2868         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2869                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2870                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2871                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2872                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2873                 if (ret)
2874                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2875                                     __func__, ret);
2876         }
2877
2878         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2879         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2880                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
2881                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2882                 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
2883                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2884                 if (ret)
2885                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2886                                     __func__, ret);
2887         }
2888
2889         /* Configure RSS for sctp6 with src/dst addr and port as input set */
2890         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2891                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
2892                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2893                 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
2894                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2895                 if (ret)
2896                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2897                                     __func__, ret);
2898         }
2899
2900         if (rss_hf & ETH_RSS_IPV4) {
2901                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV4 |
2902                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2903                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2904                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2905                 if (ret)
2906                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2907                                     __func__, ret);
2908
2909                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV4 |
2910                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2911                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2912                 if (ret)
2913                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2914                                     __func__, ret);
2915
2916                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
2917                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2918                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2919                 if (ret)
2920                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2921                                     __func__, ret);
2922         }
2923
2924         if (rss_hf & ETH_RSS_IPV6) {
2925                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV6 |
2926                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2927                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2928                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2929                 if (ret)
2930                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2931                                     __func__, ret);
2932
2933                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV6 |
2934                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2935                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2936                 if (ret)
2937                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2938                                     __func__, ret);
2939
2940                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
2941                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2942                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2943                 if (ret)
2944                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2945                                     __func__, ret);
2946         }
2947
2948         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2949                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2950                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2951                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2952                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2953                 if (ret)
2954                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2955                                     __func__, ret);
2956
2957                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
2958                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2959                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2960                 if (ret)
2961                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2962                                     __func__, ret);
2963
2964                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2965                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2966                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2967                 if (ret)
2968                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2969                                     __func__, ret);
2970         }
2971
2972         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2973                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2974                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2975                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2976                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2977                 if (ret)
2978                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
2979                                     __func__, ret);
2980
2981                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
2982                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2983                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2984                 if (ret)
2985                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
2986                                     __func__, ret);
2987
2988                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2989                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2990                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2991                 if (ret)
2992                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
2993                                     __func__, ret);
2994         }
2995
2996         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2997                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
2998                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2999                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3000                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3001                 if (ret)
3002                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
3003                                     __func__, ret);
3004
3005                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3006                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3007                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3008                 if (ret)
3009                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
3010                                     __func__, ret);
3011
3012                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3013                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3014                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3015                 if (ret)
3016                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3017                                     __func__, ret);
3018         }
3019
3020         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3021                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3022                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3023                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3024                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3025                 if (ret)
3026                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
3027                                     __func__, ret);
3028
3029                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3030                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3031                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3032                 if (ret)
3033                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
3034                                     __func__, ret);
3035
3036                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3037                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3038                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3039                 if (ret)
3040                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3041                                     __func__, ret);
3042         }
3043
3044         pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3045 }
3046
3047 static int ice_init_rss(struct ice_pf *pf)
3048 {
3049         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3050         struct ice_vsi *vsi = pf->main_vsi;
3051         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3052         struct ice_aq_get_set_rss_lut_params lut_params;
3053         struct rte_eth_rss_conf *rss_conf;
3054         struct ice_aqc_get_set_rss_keys key;
3055         uint16_t i, nb_q;
3056         int ret = 0;
3057         bool is_safe_mode = pf->adapter->is_safe_mode;
3058         uint32_t reg;
3059
3060         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3061         nb_q = dev->data->nb_rx_queues;
3062         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3063         vsi->rss_lut_size = pf->hash_lut_size;
3064
3065         if (nb_q == 0) {
3066                 PMD_DRV_LOG(WARNING,
3067                         "RSS is not supported as rx queues number is zero\n");
3068                 return 0;
3069         }
3070
3071         if (is_safe_mode) {
3072                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3073                 return 0;
3074         }
3075
3076         if (!vsi->rss_key) {
3077                 vsi->rss_key = rte_zmalloc(NULL,
3078                                            vsi->rss_key_size, 0);
3079                 if (vsi->rss_key == NULL) {
3080                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3081                         return -ENOMEM;
3082                 }
3083         }
3084         if (!vsi->rss_lut) {
3085                 vsi->rss_lut = rte_zmalloc(NULL,
3086                                            vsi->rss_lut_size, 0);
3087                 if (vsi->rss_lut == NULL) {
3088                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3089                         rte_free(vsi->rss_key);
3090                         vsi->rss_key = NULL;
3091                         return -ENOMEM;
3092                 }
3093         }
3094         /* configure RSS key */
3095         if (!rss_conf->rss_key) {
3096                 /* Calculate the default hash key */
3097                 for (i = 0; i <= vsi->rss_key_size; i++)
3098                         vsi->rss_key[i] = (uint8_t)rte_rand();
3099         } else {
3100                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3101                            RTE_MIN(rss_conf->rss_key_len,
3102                                    vsi->rss_key_size));
3103         }
3104         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3105         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3106         if (ret)
3107                 goto out;
3108
3109         /* init RSS LUT table */
3110         for (i = 0; i < vsi->rss_lut_size; i++)
3111                 vsi->rss_lut[i] = i % nb_q;
3112
3113         lut_params.vsi_handle = vsi->idx;
3114         lut_params.lut_size = vsi->rss_lut_size;
3115         lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3116         lut_params.lut = vsi->rss_lut;
3117         lut_params.global_lut_id = 0;
3118         ret = ice_aq_set_rss_lut(hw, &lut_params);
3119         if (ret)
3120                 goto out;
3121
3122         /* Enable registers for symmetric_toeplitz function. */
3123         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3124         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3125                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3126         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3127
3128         /* RSS hash configuration */
3129         ice_rss_hash_set(pf, rss_conf->rss_hf);
3130
3131         return 0;
3132 out:
3133         rte_free(vsi->rss_key);
3134         vsi->rss_key = NULL;
3135         rte_free(vsi->rss_lut);
3136         vsi->rss_lut = NULL;
3137         return -EINVAL;
3138 }
3139
3140 static int
3141 ice_dev_configure(struct rte_eth_dev *dev)
3142 {
3143         struct ice_adapter *ad =
3144                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3145         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3146         int ret;
3147
3148         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3149          * bulk allocation or vector Rx preconditions we will reset it.
3150          */
3151         ad->rx_bulk_alloc_allowed = true;
3152         ad->tx_simple_allowed = true;
3153
3154         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3155                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3156
3157         if (dev->data->nb_rx_queues) {
3158                 ret = ice_init_rss(pf);
3159                 if (ret) {
3160                         PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3161                         return ret;
3162                 }
3163         }
3164
3165         return 0;
3166 }
3167
3168 static void
3169 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3170                        int base_queue, int nb_queue)
3171 {
3172         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3173         uint32_t val, val_tx;
3174         int i;
3175
3176         for (i = 0; i < nb_queue; i++) {
3177                 /*do actual bind*/
3178                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3179                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3180                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3181                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3182
3183                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3184                             base_queue + i, msix_vect);
3185                 /* set ITR0 value */
3186                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3187                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3188                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3189         }
3190 }
3191
3192 void
3193 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3194 {
3195         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3196         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3197         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3198         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3199         uint16_t msix_vect = vsi->msix_intr;
3200         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3201         uint16_t queue_idx = 0;
3202         int record = 0;
3203         int i;
3204
3205         /* clear Rx/Tx queue interrupt */
3206         for (i = 0; i < vsi->nb_used_qps; i++) {
3207                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3208                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3209         }
3210
3211         /* PF bind interrupt */
3212         if (rte_intr_dp_is_en(intr_handle)) {
3213                 queue_idx = 0;
3214                 record = 1;
3215         }
3216
3217         for (i = 0; i < vsi->nb_used_qps; i++) {
3218                 if (nb_msix <= 1) {
3219                         if (!rte_intr_allow_others(intr_handle))
3220                                 msix_vect = ICE_MISC_VEC_ID;
3221
3222                         /* uio mapping all queue to one msix_vect */
3223                         __vsi_queues_bind_intr(vsi, msix_vect,
3224                                                vsi->base_queue + i,
3225                                                vsi->nb_used_qps - i);
3226
3227                         for (; !!record && i < vsi->nb_used_qps; i++)
3228                                 intr_handle->intr_vec[queue_idx + i] =
3229                                         msix_vect;
3230                         break;
3231                 }
3232
3233                 /* vfio 1:1 queue/msix_vect mapping */
3234                 __vsi_queues_bind_intr(vsi, msix_vect,
3235                                        vsi->base_queue + i, 1);
3236
3237                 if (!!record)
3238                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3239
3240                 msix_vect++;
3241                 nb_msix--;
3242         }
3243 }
3244
3245 void
3246 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3247 {
3248         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3249         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3250         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3251         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3252         uint16_t msix_intr, i;
3253
3254         if (rte_intr_allow_others(intr_handle))
3255                 for (i = 0; i < vsi->nb_used_qps; i++) {
3256                         msix_intr = vsi->msix_intr + i;
3257                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3258                                       GLINT_DYN_CTL_INTENA_M |
3259                                       GLINT_DYN_CTL_CLEARPBA_M |
3260                                       GLINT_DYN_CTL_ITR_INDX_M |
3261                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3262                 }
3263         else
3264                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3265                               GLINT_DYN_CTL_INTENA_M |
3266                               GLINT_DYN_CTL_CLEARPBA_M |
3267                               GLINT_DYN_CTL_ITR_INDX_M |
3268                               GLINT_DYN_CTL_WB_ON_ITR_M);
3269 }
3270
3271 static int
3272 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3273 {
3274         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3275         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3276         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3277         struct ice_vsi *vsi = pf->main_vsi;
3278         uint32_t intr_vector = 0;
3279
3280         rte_intr_disable(intr_handle);
3281
3282         /* check and configure queue intr-vector mapping */
3283         if ((rte_intr_cap_multiple(intr_handle) ||
3284              !RTE_ETH_DEV_SRIOV(dev).active) &&
3285             dev->data->dev_conf.intr_conf.rxq != 0) {
3286                 intr_vector = dev->data->nb_rx_queues;
3287                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3288                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3289                                     ICE_MAX_INTR_QUEUE_NUM);
3290                         return -ENOTSUP;
3291                 }
3292                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3293                         return -1;
3294         }
3295
3296         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3297                 intr_handle->intr_vec =
3298                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3299                             0);
3300                 if (!intr_handle->intr_vec) {
3301                         PMD_DRV_LOG(ERR,
3302                                     "Failed to allocate %d rx_queues intr_vec",
3303                                     dev->data->nb_rx_queues);
3304                         return -ENOMEM;
3305                 }
3306         }
3307
3308         /* Map queues with MSIX interrupt */
3309         vsi->nb_used_qps = dev->data->nb_rx_queues;
3310         ice_vsi_queues_bind_intr(vsi);
3311
3312         /* Enable interrupts for all the queues */
3313         ice_vsi_enable_queues_intr(vsi);
3314
3315         rte_intr_enable(intr_handle);
3316
3317         return 0;
3318 }
3319
3320 static void
3321 ice_get_init_link_status(struct rte_eth_dev *dev)
3322 {
3323         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3324         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3325         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3326         struct ice_link_status link_status;
3327         int ret;
3328
3329         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3330                                    &link_status, NULL);
3331         if (ret != ICE_SUCCESS) {
3332                 PMD_DRV_LOG(ERR, "Failed to get link info");
3333                 pf->init_link_up = false;
3334                 return;
3335         }
3336
3337         if (link_status.link_info & ICE_AQ_LINK_UP)
3338                 pf->init_link_up = true;
3339 }
3340
3341 static int
3342 ice_dev_start(struct rte_eth_dev *dev)
3343 {
3344         struct rte_eth_dev_data *data = dev->data;
3345         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3346         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3347         struct ice_vsi *vsi = pf->main_vsi;
3348         uint16_t nb_rxq = 0;
3349         uint16_t nb_txq, i;
3350         uint16_t max_frame_size;
3351         int mask, ret;
3352
3353         /* program Tx queues' context in hardware */
3354         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3355                 ret = ice_tx_queue_start(dev, nb_txq);
3356                 if (ret) {
3357                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3358                         goto tx_err;
3359                 }
3360         }
3361
3362         /* program Rx queues' context in hardware*/
3363         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3364                 ret = ice_rx_queue_start(dev, nb_rxq);
3365                 if (ret) {
3366                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3367                         goto rx_err;
3368                 }
3369         }
3370
3371         ice_set_rx_function(dev);
3372         ice_set_tx_function(dev);
3373
3374         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3375                         ETH_VLAN_EXTEND_MASK;
3376         ret = ice_vlan_offload_set(dev, mask);
3377         if (ret) {
3378                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3379                 goto rx_err;
3380         }
3381
3382         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3383         if (ice_rxq_intr_setup(dev))
3384                 return -EIO;
3385
3386         /* Enable receiving broadcast packets and transmitting packets */
3387         ret = ice_set_vsi_promisc(hw, vsi->idx,
3388                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3389                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3390                                   0);
3391         if (ret != ICE_SUCCESS)
3392                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3393
3394         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3395                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3396                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3397                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3398                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3399                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3400                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3401                                      NULL);
3402         if (ret != ICE_SUCCESS)
3403                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3404
3405         ice_get_init_link_status(dev);
3406
3407         ice_dev_set_link_up(dev);
3408
3409         /* Call get_link_info aq commond to enable/disable LSE */
3410         ice_link_update(dev, 0);
3411
3412         pf->adapter_stopped = false;
3413
3414         /* Set the max frame size to default value*/
3415         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3416                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3417                 ICE_FRAME_SIZE_MAX;
3418
3419         /* Set the max frame size to HW*/
3420         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3421
3422         return 0;
3423
3424         /* stop the started queues if failed to start all queues */
3425 rx_err:
3426         for (i = 0; i < nb_rxq; i++)
3427                 ice_rx_queue_stop(dev, i);
3428 tx_err:
3429         for (i = 0; i < nb_txq; i++)
3430                 ice_tx_queue_stop(dev, i);
3431
3432         return -EIO;
3433 }
3434
3435 static int
3436 ice_dev_reset(struct rte_eth_dev *dev)
3437 {
3438         int ret;
3439
3440         if (dev->data->sriov.active)
3441                 return -ENOTSUP;
3442
3443         ret = ice_dev_uninit(dev);
3444         if (ret) {
3445                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3446                 return -ENXIO;
3447         }
3448
3449         ret = ice_dev_init(dev);
3450         if (ret) {
3451                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3452                 return -ENXIO;
3453         }
3454
3455         return 0;
3456 }
3457
3458 static int
3459 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3460 {
3461         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3462         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3463         struct ice_vsi *vsi = pf->main_vsi;
3464         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3465         bool is_safe_mode = pf->adapter->is_safe_mode;
3466         u64 phy_type_low;
3467         u64 phy_type_high;
3468
3469         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3470         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3471         dev_info->max_rx_queues = vsi->nb_qps;
3472         dev_info->max_tx_queues = vsi->nb_qps;
3473         dev_info->max_mac_addrs = vsi->max_macaddrs;
3474         dev_info->max_vfs = pci_dev->max_vfs;
3475         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3476         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3477
3478         dev_info->rx_offload_capa =
3479                 DEV_RX_OFFLOAD_VLAN_STRIP |
3480                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3481                 DEV_RX_OFFLOAD_KEEP_CRC |
3482                 DEV_RX_OFFLOAD_SCATTER |
3483                 DEV_RX_OFFLOAD_VLAN_FILTER;
3484         dev_info->tx_offload_capa =
3485                 DEV_TX_OFFLOAD_VLAN_INSERT |
3486                 DEV_TX_OFFLOAD_TCP_TSO |
3487                 DEV_TX_OFFLOAD_MULTI_SEGS |
3488                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3489         dev_info->flow_type_rss_offloads = 0;
3490
3491         if (!is_safe_mode) {
3492                 dev_info->rx_offload_capa |=
3493                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3494                         DEV_RX_OFFLOAD_UDP_CKSUM |
3495                         DEV_RX_OFFLOAD_TCP_CKSUM |
3496                         DEV_RX_OFFLOAD_QINQ_STRIP |
3497                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3498                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3499                         DEV_RX_OFFLOAD_RSS_HASH;
3500                 dev_info->tx_offload_capa |=
3501                         DEV_TX_OFFLOAD_QINQ_INSERT |
3502                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3503                         DEV_TX_OFFLOAD_UDP_CKSUM |
3504                         DEV_TX_OFFLOAD_TCP_CKSUM |
3505                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3506                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3507                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3508                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3509         }
3510
3511         dev_info->rx_queue_offload_capa = 0;
3512         dev_info->tx_queue_offload_capa = 0;
3513
3514         dev_info->reta_size = pf->hash_lut_size;
3515         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3516
3517         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3518                 .rx_thresh = {
3519                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3520                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3521                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3522                 },
3523                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3524                 .rx_drop_en = 0,
3525                 .offloads = 0,
3526         };
3527
3528         dev_info->default_txconf = (struct rte_eth_txconf) {
3529                 .tx_thresh = {
3530                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3531                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3532                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3533                 },
3534                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3535                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3536                 .offloads = 0,
3537         };
3538
3539         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3540                 .nb_max = ICE_MAX_RING_DESC,
3541                 .nb_min = ICE_MIN_RING_DESC,
3542                 .nb_align = ICE_ALIGN_RING_DESC,
3543         };
3544
3545         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3546                 .nb_max = ICE_MAX_RING_DESC,
3547                 .nb_min = ICE_MIN_RING_DESC,
3548                 .nb_align = ICE_ALIGN_RING_DESC,
3549         };
3550
3551         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3552                                ETH_LINK_SPEED_100M |
3553                                ETH_LINK_SPEED_1G |
3554                                ETH_LINK_SPEED_2_5G |
3555                                ETH_LINK_SPEED_5G |
3556                                ETH_LINK_SPEED_10G |
3557                                ETH_LINK_SPEED_20G |
3558                                ETH_LINK_SPEED_25G;
3559
3560         phy_type_low = hw->port_info->phy.phy_type_low;
3561         phy_type_high = hw->port_info->phy.phy_type_high;
3562
3563         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3564                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3565
3566         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3567                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3568                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3569
3570         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3571         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3572
3573         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3574         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3575         dev_info->default_rxportconf.nb_queues = 1;
3576         dev_info->default_txportconf.nb_queues = 1;
3577         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3578         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3579
3580         return 0;
3581 }
3582
3583 static inline int
3584 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3585                             struct rte_eth_link *link)
3586 {
3587         struct rte_eth_link *dst = link;
3588         struct rte_eth_link *src = &dev->data->dev_link;
3589
3590         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3591                                 *(uint64_t *)src) == 0)
3592                 return -1;
3593
3594         return 0;
3595 }
3596
3597 static inline int
3598 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3599                              struct rte_eth_link *link)
3600 {
3601         struct rte_eth_link *dst = &dev->data->dev_link;
3602         struct rte_eth_link *src = link;
3603
3604         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3605                                 *(uint64_t *)src) == 0)
3606                 return -1;
3607
3608         return 0;
3609 }
3610
3611 static int
3612 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3613 {
3614 #define CHECK_INTERVAL 100  /* 100ms */
3615 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3616         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3617         struct ice_link_status link_status;
3618         struct rte_eth_link link, old;
3619         int status;
3620         unsigned int rep_cnt = MAX_REPEAT_TIME;
3621         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3622
3623         memset(&link, 0, sizeof(link));
3624         memset(&old, 0, sizeof(old));
3625         memset(&link_status, 0, sizeof(link_status));
3626         ice_atomic_read_link_status(dev, &old);
3627
3628         do {
3629                 /* Get link status information from hardware */
3630                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3631                                               &link_status, NULL);
3632                 if (status != ICE_SUCCESS) {
3633                         link.link_speed = ETH_SPEED_NUM_100M;
3634                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3635                         PMD_DRV_LOG(ERR, "Failed to get link info");
3636                         goto out;
3637                 }
3638
3639                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3640                 if (!wait_to_complete || link.link_status)
3641                         break;
3642
3643                 rte_delay_ms(CHECK_INTERVAL);
3644         } while (--rep_cnt);
3645
3646         if (!link.link_status)
3647                 goto out;
3648
3649         /* Full-duplex operation at all supported speeds */
3650         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3651
3652         /* Parse the link status */
3653         switch (link_status.link_speed) {
3654         case ICE_AQ_LINK_SPEED_10MB:
3655                 link.link_speed = ETH_SPEED_NUM_10M;
3656                 break;
3657         case ICE_AQ_LINK_SPEED_100MB:
3658                 link.link_speed = ETH_SPEED_NUM_100M;
3659                 break;
3660         case ICE_AQ_LINK_SPEED_1000MB:
3661                 link.link_speed = ETH_SPEED_NUM_1G;
3662                 break;
3663         case ICE_AQ_LINK_SPEED_2500MB:
3664                 link.link_speed = ETH_SPEED_NUM_2_5G;
3665                 break;
3666         case ICE_AQ_LINK_SPEED_5GB:
3667                 link.link_speed = ETH_SPEED_NUM_5G;
3668                 break;
3669         case ICE_AQ_LINK_SPEED_10GB:
3670                 link.link_speed = ETH_SPEED_NUM_10G;
3671                 break;
3672         case ICE_AQ_LINK_SPEED_20GB:
3673                 link.link_speed = ETH_SPEED_NUM_20G;
3674                 break;
3675         case ICE_AQ_LINK_SPEED_25GB:
3676                 link.link_speed = ETH_SPEED_NUM_25G;
3677                 break;
3678         case ICE_AQ_LINK_SPEED_40GB:
3679                 link.link_speed = ETH_SPEED_NUM_40G;
3680                 break;
3681         case ICE_AQ_LINK_SPEED_50GB:
3682                 link.link_speed = ETH_SPEED_NUM_50G;
3683                 break;
3684         case ICE_AQ_LINK_SPEED_100GB:
3685                 link.link_speed = ETH_SPEED_NUM_100G;
3686                 break;
3687         case ICE_AQ_LINK_SPEED_UNKNOWN:
3688                 PMD_DRV_LOG(ERR, "Unknown link speed");
3689                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3690                 break;
3691         default:
3692                 PMD_DRV_LOG(ERR, "None link speed");
3693                 link.link_speed = ETH_SPEED_NUM_NONE;
3694                 break;
3695         }
3696
3697         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3698                               ETH_LINK_SPEED_FIXED);
3699
3700 out:
3701         ice_atomic_write_link_status(dev, &link);
3702         if (link.link_status == old.link_status)
3703                 return -1;
3704
3705         return 0;
3706 }
3707
3708 /* Force the physical link state by getting the current PHY capabilities from
3709  * hardware and setting the PHY config based on the determined capabilities. If
3710  * link changes, link event will be triggered because both the Enable Automatic
3711  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3712  */
3713 static enum ice_status
3714 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3715 {
3716         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3717         struct ice_aqc_get_phy_caps_data *pcaps;
3718         struct ice_port_info *pi;
3719         enum ice_status status;
3720
3721         if (!hw || !hw->port_info)
3722                 return ICE_ERR_PARAM;
3723
3724         pi = hw->port_info;
3725
3726         pcaps = (struct ice_aqc_get_phy_caps_data *)
3727                 ice_malloc(hw, sizeof(*pcaps));
3728         if (!pcaps)
3729                 return ICE_ERR_NO_MEMORY;
3730
3731         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3732                                      pcaps, NULL);
3733         if (status)
3734                 goto out;
3735
3736         /* No change in link */
3737         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3738             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3739                 goto out;
3740
3741         cfg.phy_type_low = pcaps->phy_type_low;
3742         cfg.phy_type_high = pcaps->phy_type_high;
3743         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3744         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3745         cfg.eee_cap = pcaps->eee_cap;
3746         cfg.eeer_value = pcaps->eeer_value;
3747         cfg.link_fec_opt = pcaps->link_fec_options;
3748         if (link_up)
3749                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3750         else
3751                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3752
3753         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3754
3755 out:
3756         ice_free(hw, pcaps);
3757         return status;
3758 }
3759
3760 static int
3761 ice_dev_set_link_up(struct rte_eth_dev *dev)
3762 {
3763         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3764
3765         return ice_force_phys_link_state(hw, true);
3766 }
3767
3768 static int
3769 ice_dev_set_link_down(struct rte_eth_dev *dev)
3770 {
3771         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3772
3773         return ice_force_phys_link_state(hw, false);
3774 }
3775
3776 static int
3777 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3778 {
3779         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3780         struct rte_eth_dev_data *dev_data = pf->dev_data;
3781         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3782
3783         /* check if mtu is within the allowed range */
3784         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3785                 return -EINVAL;
3786
3787         /* mtu setting is forbidden if port is start */
3788         if (dev_data->dev_started) {
3789                 PMD_DRV_LOG(ERR,
3790                             "port %d must be stopped before configuration",
3791                             dev_data->port_id);
3792                 return -EBUSY;
3793         }
3794
3795         if (frame_size > ICE_ETH_MAX_LEN)
3796                 dev_data->dev_conf.rxmode.offloads |=
3797                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3798         else
3799                 dev_data->dev_conf.rxmode.offloads &=
3800                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3801
3802         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3803
3804         return 0;
3805 }
3806
3807 static int ice_macaddr_set(struct rte_eth_dev *dev,
3808                            struct rte_ether_addr *mac_addr)
3809 {
3810         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3811         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3812         struct ice_vsi *vsi = pf->main_vsi;
3813         struct ice_mac_filter *f;
3814         uint8_t flags = 0;
3815         int ret;
3816
3817         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3818                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3819                 return -EINVAL;
3820         }
3821
3822         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3823                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3824                         break;
3825         }
3826
3827         if (!f) {
3828                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3829                 return -EIO;
3830         }
3831
3832         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3833         if (ret != ICE_SUCCESS) {
3834                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3835                 return -EIO;
3836         }
3837         ret = ice_add_mac_filter(vsi, mac_addr);
3838         if (ret != ICE_SUCCESS) {
3839                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3840                 return -EIO;
3841         }
3842         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3843
3844         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3845         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3846         if (ret != ICE_SUCCESS)
3847                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3848
3849         return 0;
3850 }
3851
3852 /* Add a MAC address, and update filters */
3853 static int
3854 ice_macaddr_add(struct rte_eth_dev *dev,
3855                 struct rte_ether_addr *mac_addr,
3856                 __rte_unused uint32_t index,
3857                 __rte_unused uint32_t pool)
3858 {
3859         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3860         struct ice_vsi *vsi = pf->main_vsi;
3861         int ret;
3862
3863         ret = ice_add_mac_filter(vsi, mac_addr);
3864         if (ret != ICE_SUCCESS) {
3865                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3866                 return -EINVAL;
3867         }
3868
3869         return ICE_SUCCESS;
3870 }
3871
3872 /* Remove a MAC address, and update filters */
3873 static void
3874 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3875 {
3876         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3877         struct ice_vsi *vsi = pf->main_vsi;
3878         struct rte_eth_dev_data *data = dev->data;
3879         struct rte_ether_addr *macaddr;
3880         int ret;
3881
3882         macaddr = &data->mac_addrs[index];
3883         ret = ice_remove_mac_filter(vsi, macaddr);
3884         if (ret) {
3885                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3886                 return;
3887         }
3888 }
3889
3890 static int
3891 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3892 {
3893         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3894         struct ice_vsi *vsi = pf->main_vsi;
3895         int ret;
3896
3897         PMD_INIT_FUNC_TRACE();
3898
3899         if (on) {
3900                 ret = ice_add_vlan_filter(vsi, vlan_id);
3901                 if (ret < 0) {
3902                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3903                         return -EINVAL;
3904                 }
3905         } else {
3906                 ret = ice_remove_vlan_filter(vsi, vlan_id);
3907                 if (ret < 0) {
3908                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3909                         return -EINVAL;
3910                 }
3911         }
3912
3913         return 0;
3914 }
3915
3916 /* Configure vlan filter on or off */
3917 static int
3918 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3919 {
3920         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3921         struct ice_vsi_ctx ctxt;
3922         uint8_t sec_flags, sw_flags2;
3923         int ret = 0;
3924
3925         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3926                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
3927         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3928
3929         if (on) {
3930                 vsi->info.sec_flags |= sec_flags;
3931                 vsi->info.sw_flags2 |= sw_flags2;
3932         } else {
3933                 vsi->info.sec_flags &= ~sec_flags;
3934                 vsi->info.sw_flags2 &= ~sw_flags2;
3935         }
3936         vsi->info.sw_id = hw->port_info->sw_id;
3937         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3938         ctxt.info.valid_sections =
3939                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3940                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3941         ctxt.vsi_num = vsi->vsi_id;
3942
3943         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3944         if (ret) {
3945                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
3946                             on ? "enable" : "disable");
3947                 return -EINVAL;
3948         } else {
3949                 vsi->info.valid_sections |=
3950                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3951                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
3952         }
3953
3954         /* consist with other drivers, allow untagged packet when vlan filter on */
3955         if (on)
3956                 ret = ice_add_vlan_filter(vsi, 0);
3957         else
3958                 ret = ice_remove_vlan_filter(vsi, 0);
3959
3960         return 0;
3961 }
3962
3963 /* Manage VLAN stripping for the VSI for Rx */
3964 static int
3965 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
3966 {
3967         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3968         struct ice_vsi_ctx ctxt;
3969         enum ice_status status;
3970         int err = 0;
3971
3972         /* do not allow modifying VLAN stripping when a port VLAN is configured
3973          * on this VSI
3974          */
3975         if (vsi->info.port_based_inner_vlan)
3976                 return 0;
3977
3978         memset(&ctxt, 0, sizeof(ctxt));
3979
3980         if (ena)
3981                 /* Strip VLAN tag from Rx packet and put it in the desc */
3982                 ctxt.info.inner_vlan_flags =
3983                                         ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
3984         else
3985                 /* Disable stripping. Leave tag in packet */
3986                 ctxt.info.inner_vlan_flags =
3987                                         ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
3988
3989         /* Allow all packets untagged/tagged */
3990         ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
3991
3992         ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3993
3994         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3995         if (status) {
3996                 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
3997                             ena ? "enable" : "disable");
3998                 err = -EIO;
3999         } else {
4000                 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4001         }
4002
4003         return err;
4004 }
4005
4006 static int
4007 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4008 {
4009         return ice_vsi_manage_vlan_stripping(vsi, true);
4010 }
4011
4012 static int
4013 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4014 {
4015         return ice_vsi_manage_vlan_stripping(vsi, false);
4016 }
4017
4018 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4019 {
4020         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4021         struct ice_vsi_ctx ctxt;
4022         enum ice_status status;
4023         int err = 0;
4024
4025         /* do not allow modifying VLAN stripping when a port VLAN is configured
4026          * on this VSI
4027          */
4028         if (vsi->info.port_based_outer_vlan)
4029                 return 0;
4030
4031         memset(&ctxt, 0, sizeof(ctxt));
4032
4033         ctxt.info.valid_sections =
4034                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4035         /* clear current outer VLAN strip settings */
4036         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4037                 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4038         ctxt.info.outer_vlan_flags |=
4039                 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4040                  ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4041                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4042                  ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4043
4044         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4045         if (status) {
4046                 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4047                 err = -EIO;
4048         } else {
4049                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4050         }
4051
4052         return err;
4053 }
4054
4055 static int
4056 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4057 {
4058         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4059         struct ice_vsi_ctx ctxt;
4060         enum ice_status status;
4061         int err = 0;
4062
4063         if (vsi->info.port_based_outer_vlan)
4064                 return 0;
4065
4066         memset(&ctxt, 0, sizeof(ctxt));
4067
4068         ctxt.info.valid_sections =
4069                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4070         /* clear current outer VLAN strip settings */
4071         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4072                 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4073         ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4074                 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4075
4076         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4077         if (status) {
4078                 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4079                 err = -EIO;
4080         } else {
4081                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4082         }
4083
4084         return err;
4085 }
4086
4087 static int
4088 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4089 {
4090         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4091         int ret;
4092
4093         if (ice_is_dvm_ena(hw)) {
4094                 if (ena)
4095                         ret = ice_vsi_ena_outer_stripping(vsi);
4096                 else
4097                         ret = ice_vsi_dis_outer_stripping(vsi);
4098         } else {
4099                 if (ena)
4100                         ret = ice_vsi_ena_inner_stripping(vsi);
4101                 else
4102                         ret = ice_vsi_dis_inner_stripping(vsi);
4103         }
4104
4105         return ret;
4106 }
4107
4108 static int
4109 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4110 {
4111         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4112         struct ice_vsi *vsi = pf->main_vsi;
4113         struct rte_eth_rxmode *rxmode;
4114
4115         rxmode = &dev->data->dev_conf.rxmode;
4116         if (mask & ETH_VLAN_FILTER_MASK) {
4117                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4118                         ice_vsi_config_vlan_filter(vsi, true);
4119                 else
4120                         ice_vsi_config_vlan_filter(vsi, false);
4121         }
4122
4123         if (mask & ETH_VLAN_STRIP_MASK) {
4124                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4125                         ice_vsi_config_vlan_stripping(vsi, true);
4126                 else
4127                         ice_vsi_config_vlan_stripping(vsi, false);
4128         }
4129
4130         return 0;
4131 }
4132
4133 static int
4134 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4135 {
4136         struct ice_aq_get_set_rss_lut_params lut_params;
4137         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4138         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4139         int ret;
4140
4141         if (!lut)
4142                 return -EINVAL;
4143
4144         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4145                 lut_params.vsi_handle = vsi->idx;
4146                 lut_params.lut_size = lut_size;
4147                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4148                 lut_params.lut = lut;
4149                 lut_params.global_lut_id = 0;
4150                 ret = ice_aq_get_rss_lut(hw, &lut_params);
4151                 if (ret) {
4152                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4153                         return -EINVAL;
4154                 }
4155         } else {
4156                 uint64_t *lut_dw = (uint64_t *)lut;
4157                 uint16_t i, lut_size_dw = lut_size / 4;
4158
4159                 for (i = 0; i < lut_size_dw; i++)
4160                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4161         }
4162
4163         return 0;
4164 }
4165
4166 static int
4167 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4168 {
4169         struct ice_aq_get_set_rss_lut_params lut_params;
4170         struct ice_pf *pf;
4171         struct ice_hw *hw;
4172         int ret;
4173
4174         if (!vsi || !lut)
4175                 return -EINVAL;
4176
4177         pf = ICE_VSI_TO_PF(vsi);
4178         hw = ICE_VSI_TO_HW(vsi);
4179
4180         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4181                 lut_params.vsi_handle = vsi->idx;
4182                 lut_params.lut_size = lut_size;
4183                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4184                 lut_params.lut = lut;
4185                 lut_params.global_lut_id = 0;
4186                 ret = ice_aq_set_rss_lut(hw, &lut_params);
4187                 if (ret) {
4188                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4189                         return -EINVAL;
4190                 }
4191         } else {
4192                 uint64_t *lut_dw = (uint64_t *)lut;
4193                 uint16_t i, lut_size_dw = lut_size / 4;
4194
4195                 for (i = 0; i < lut_size_dw; i++)
4196                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4197
4198                 ice_flush(hw);
4199         }
4200
4201         return 0;
4202 }
4203
4204 static int
4205 ice_rss_reta_update(struct rte_eth_dev *dev,
4206                     struct rte_eth_rss_reta_entry64 *reta_conf,
4207                     uint16_t reta_size)
4208 {
4209         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4210         uint16_t i, lut_size = pf->hash_lut_size;
4211         uint16_t idx, shift;
4212         uint8_t *lut;
4213         int ret;
4214
4215         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4216             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4217             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4218                 PMD_DRV_LOG(ERR,
4219                             "The size of hash lookup table configured (%d)"
4220                             "doesn't match the number hardware can "
4221                             "supported (128, 512, 2048)",
4222                             reta_size);
4223                 return -EINVAL;
4224         }
4225
4226         /* It MUST use the current LUT size to get the RSS lookup table,
4227          * otherwise if will fail with -100 error code.
4228          */
4229         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4230         if (!lut) {
4231                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4232                 return -ENOMEM;
4233         }
4234         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4235         if (ret)
4236                 goto out;
4237
4238         for (i = 0; i < reta_size; i++) {
4239                 idx = i / RTE_RETA_GROUP_SIZE;
4240                 shift = i % RTE_RETA_GROUP_SIZE;
4241                 if (reta_conf[idx].mask & (1ULL << shift))
4242                         lut[i] = reta_conf[idx].reta[shift];
4243         }
4244         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4245         if (ret == 0 && lut_size != reta_size) {
4246                 PMD_DRV_LOG(INFO,
4247                             "The size of hash lookup table is changed from (%d) to (%d)",
4248                             lut_size, reta_size);
4249                 pf->hash_lut_size = reta_size;
4250         }
4251
4252 out:
4253         rte_free(lut);
4254
4255         return ret;
4256 }
4257
4258 static int
4259 ice_rss_reta_query(struct rte_eth_dev *dev,
4260                    struct rte_eth_rss_reta_entry64 *reta_conf,
4261                    uint16_t reta_size)
4262 {
4263         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4264         uint16_t i, lut_size = pf->hash_lut_size;
4265         uint16_t idx, shift;
4266         uint8_t *lut;
4267         int ret;
4268
4269         if (reta_size != lut_size) {
4270                 PMD_DRV_LOG(ERR,
4271                             "The size of hash lookup table configured (%d)"
4272                             "doesn't match the number hardware can "
4273                             "supported (%d)",
4274                             reta_size, lut_size);
4275                 return -EINVAL;
4276         }
4277
4278         lut = rte_zmalloc(NULL, reta_size, 0);
4279         if (!lut) {
4280                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4281                 return -ENOMEM;
4282         }
4283
4284         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4285         if (ret)
4286                 goto out;
4287
4288         for (i = 0; i < reta_size; i++) {
4289                 idx = i / RTE_RETA_GROUP_SIZE;
4290                 shift = i % RTE_RETA_GROUP_SIZE;
4291                 if (reta_conf[idx].mask & (1ULL << shift))
4292                         reta_conf[idx].reta[shift] = lut[i];
4293         }
4294
4295 out:
4296         rte_free(lut);
4297
4298         return ret;
4299 }
4300
4301 static int
4302 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4303 {
4304         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4305         int ret = 0;
4306
4307         if (!key || key_len == 0) {
4308                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4309                 return 0;
4310         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4311                    sizeof(uint32_t)) {
4312                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4313                 return -EINVAL;
4314         }
4315
4316         struct ice_aqc_get_set_rss_keys *key_dw =
4317                 (struct ice_aqc_get_set_rss_keys *)key;
4318
4319         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4320         if (ret) {
4321                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4322                 ret = -EINVAL;
4323         }
4324
4325         return ret;
4326 }
4327
4328 static int
4329 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4330 {
4331         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4332         int ret;
4333
4334         if (!key || !key_len)
4335                 return -EINVAL;
4336
4337         ret = ice_aq_get_rss_key
4338                 (hw, vsi->idx,
4339                  (struct ice_aqc_get_set_rss_keys *)key);
4340         if (ret) {
4341                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4342                 return -EINVAL;
4343         }
4344         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4345
4346         return 0;
4347 }
4348
4349 static int
4350 ice_rss_hash_update(struct rte_eth_dev *dev,
4351                     struct rte_eth_rss_conf *rss_conf)
4352 {
4353         enum ice_status status = ICE_SUCCESS;
4354         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4355         struct ice_vsi *vsi = pf->main_vsi;
4356
4357         /* set hash key */
4358         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4359         if (status)
4360                 return status;
4361
4362         if (rss_conf->rss_hf == 0)
4363                 return 0;
4364
4365         /* RSS hash configuration */
4366         ice_rss_hash_set(pf, rss_conf->rss_hf);
4367
4368         return 0;
4369 }
4370
4371 static int
4372 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4373                       struct rte_eth_rss_conf *rss_conf)
4374 {
4375         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4376         struct ice_vsi *vsi = pf->main_vsi;
4377
4378         ice_get_rss_key(vsi, rss_conf->rss_key,
4379                         &rss_conf->rss_key_len);
4380
4381         rss_conf->rss_hf = pf->rss_hf;
4382         return 0;
4383 }
4384
4385 static int
4386 ice_promisc_enable(struct rte_eth_dev *dev)
4387 {
4388         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4389         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4390         struct ice_vsi *vsi = pf->main_vsi;
4391         enum ice_status status;
4392         uint8_t pmask;
4393         int ret = 0;
4394
4395         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4396                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4397
4398         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4399         switch (status) {
4400         case ICE_ERR_ALREADY_EXISTS:
4401                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4402         case ICE_SUCCESS:
4403                 break;
4404         default:
4405                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4406                 ret = -EAGAIN;
4407         }
4408
4409         return ret;
4410 }
4411
4412 static int
4413 ice_promisc_disable(struct rte_eth_dev *dev)
4414 {
4415         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4416         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4417         struct ice_vsi *vsi = pf->main_vsi;
4418         enum ice_status status;
4419         uint8_t pmask;
4420         int ret = 0;
4421
4422         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4423                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4424
4425         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4426         if (status != ICE_SUCCESS) {
4427                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4428                 ret = -EAGAIN;
4429         }
4430
4431         return ret;
4432 }
4433
4434 static int
4435 ice_allmulti_enable(struct rte_eth_dev *dev)
4436 {
4437         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4438         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4439         struct ice_vsi *vsi = pf->main_vsi;
4440         enum ice_status status;
4441         uint8_t pmask;
4442         int ret = 0;
4443
4444         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4445
4446         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4447
4448         switch (status) {
4449         case ICE_ERR_ALREADY_EXISTS:
4450                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4451         case ICE_SUCCESS:
4452                 break;
4453         default:
4454                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4455                 ret = -EAGAIN;
4456         }
4457
4458         return ret;
4459 }
4460
4461 static int
4462 ice_allmulti_disable(struct rte_eth_dev *dev)
4463 {
4464         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4465         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4466         struct ice_vsi *vsi = pf->main_vsi;
4467         enum ice_status status;
4468         uint8_t pmask;
4469         int ret = 0;
4470
4471         if (dev->data->promiscuous == 1)
4472                 return 0; /* must remain in all_multicast mode */
4473
4474         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4475
4476         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4477         if (status != ICE_SUCCESS) {
4478                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4479                 ret = -EAGAIN;
4480         }
4481
4482         return ret;
4483 }
4484
4485 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4486                                     uint16_t queue_id)
4487 {
4488         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4489         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4490         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4491         uint32_t val;
4492         uint16_t msix_intr;
4493
4494         msix_intr = intr_handle->intr_vec[queue_id];
4495
4496         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4497               GLINT_DYN_CTL_ITR_INDX_M;
4498         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4499
4500         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4501         rte_intr_ack(&pci_dev->intr_handle);
4502
4503         return 0;
4504 }
4505
4506 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4507                                      uint16_t queue_id)
4508 {
4509         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4510         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4511         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4512         uint16_t msix_intr;
4513
4514         msix_intr = intr_handle->intr_vec[queue_id];
4515
4516         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4517
4518         return 0;
4519 }
4520
4521 static int
4522 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4523 {
4524         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4525         u8 ver, patch;
4526         u16 build;
4527         int ret;
4528
4529         ver = hw->flash.orom.major;
4530         patch = hw->flash.orom.patch;
4531         build = hw->flash.orom.build;
4532
4533         ret = snprintf(fw_version, fw_size,
4534                         "%x.%02x 0x%08x %d.%d.%d",
4535                         hw->flash.nvm.major,
4536                         hw->flash.nvm.minor,
4537                         hw->flash.nvm.eetrack,
4538                         ver, build, patch);
4539
4540         /* add the size of '\0' */
4541         ret += 1;
4542         if (fw_size < (u32)ret)
4543                 return ret;
4544         else
4545                 return 0;
4546 }
4547
4548 static int
4549 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4550 {
4551         struct ice_hw *hw;
4552         struct ice_vsi_ctx ctxt;
4553         uint8_t vlan_flags = 0;
4554         int ret;
4555
4556         if (!vsi || !info) {
4557                 PMD_DRV_LOG(ERR, "invalid parameters");
4558                 return -EINVAL;
4559         }
4560
4561         if (info->on) {
4562                 vsi->info.port_based_inner_vlan = info->config.pvid;
4563                 /**
4564                  * If insert pvid is enabled, only tagged pkts are
4565                  * allowed to be sent out.
4566                  */
4567                 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4568                              ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4569         } else {
4570                 vsi->info.port_based_inner_vlan = 0;
4571                 if (info->config.reject.tagged == 0)
4572                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4573
4574                 if (info->config.reject.untagged == 0)
4575                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4576         }
4577         vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4578                                   ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4579         vsi->info.inner_vlan_flags |= vlan_flags;
4580         memset(&ctxt, 0, sizeof(ctxt));
4581         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4582         ctxt.info.valid_sections =
4583                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4584         ctxt.vsi_num = vsi->vsi_id;
4585
4586         hw = ICE_VSI_TO_HW(vsi);
4587         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4588         if (ret != ICE_SUCCESS) {
4589                 PMD_DRV_LOG(ERR,
4590                             "update VSI for VLAN insert failed, err %d",
4591                             ret);
4592                 return -EINVAL;
4593         }
4594
4595         vsi->info.valid_sections |=
4596                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4597
4598         return ret;
4599 }
4600
4601 static int
4602 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4603 {
4604         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4605         struct ice_vsi *vsi = pf->main_vsi;
4606         struct rte_eth_dev_data *data = pf->dev_data;
4607         struct ice_vsi_vlan_pvid_info info;
4608         int ret;
4609
4610         memset(&info, 0, sizeof(info));
4611         info.on = on;
4612         if (info.on) {
4613                 info.config.pvid = pvid;
4614         } else {
4615                 info.config.reject.tagged =
4616                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4617                 info.config.reject.untagged =
4618                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4619         }
4620
4621         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4622         if (ret < 0) {
4623                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4624                 return -EINVAL;
4625         }
4626
4627         return 0;
4628 }
4629
4630 static int
4631 ice_get_eeprom_length(struct rte_eth_dev *dev)
4632 {
4633         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4634
4635         return hw->flash.flash_size;
4636 }
4637
4638 static int
4639 ice_get_eeprom(struct rte_eth_dev *dev,
4640                struct rte_dev_eeprom_info *eeprom)
4641 {
4642         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4643         enum ice_status status = ICE_SUCCESS;
4644         uint8_t *data = eeprom->data;
4645
4646         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4647
4648         status = ice_acquire_nvm(hw, ICE_RES_READ);
4649         if (status) {
4650                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4651                 return -EIO;
4652         }
4653
4654         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4655                                    data, false);
4656
4657         ice_release_nvm(hw);
4658
4659         if (status) {
4660                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4661                 return -EIO;
4662         }
4663
4664         return 0;
4665 }
4666
4667 static void
4668 ice_stat_update_32(struct ice_hw *hw,
4669                    uint32_t reg,
4670                    bool offset_loaded,
4671                    uint64_t *offset,
4672                    uint64_t *stat)
4673 {
4674         uint64_t new_data;
4675
4676         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4677         if (!offset_loaded)
4678                 *offset = new_data;
4679
4680         if (new_data >= *offset)
4681                 *stat = (uint64_t)(new_data - *offset);
4682         else
4683                 *stat = (uint64_t)((new_data +
4684                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4685                                    - *offset);
4686 }
4687
4688 static void
4689 ice_stat_update_40(struct ice_hw *hw,
4690                    uint32_t hireg,
4691                    uint32_t loreg,
4692                    bool offset_loaded,
4693                    uint64_t *offset,
4694                    uint64_t *stat)
4695 {
4696         uint64_t new_data;
4697
4698         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4699         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4700                     ICE_32_BIT_WIDTH;
4701
4702         if (!offset_loaded)
4703                 *offset = new_data;
4704
4705         if (new_data >= *offset)
4706                 *stat = new_data - *offset;
4707         else
4708                 *stat = (uint64_t)((new_data +
4709                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4710                                    *offset);
4711
4712         *stat &= ICE_40_BIT_MASK;
4713 }
4714
4715 /* Get all the statistics of a VSI */
4716 static void
4717 ice_update_vsi_stats(struct ice_vsi *vsi)
4718 {
4719         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4720         struct ice_eth_stats *nes = &vsi->eth_stats;
4721         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4722         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4723
4724         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4725                            vsi->offset_loaded, &oes->rx_bytes,
4726                            &nes->rx_bytes);
4727         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4728                            vsi->offset_loaded, &oes->rx_unicast,
4729                            &nes->rx_unicast);
4730         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4731                            vsi->offset_loaded, &oes->rx_multicast,
4732                            &nes->rx_multicast);
4733         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4734                            vsi->offset_loaded, &oes->rx_broadcast,
4735                            &nes->rx_broadcast);
4736         /* enlarge the limitation when rx_bytes overflowed */
4737         if (vsi->offset_loaded) {
4738                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4739                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4740                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4741         }
4742         vsi->old_rx_bytes = nes->rx_bytes;
4743         /* exclude CRC bytes */
4744         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4745                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4746
4747         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4748                            &oes->rx_discards, &nes->rx_discards);
4749         /* GLV_REPC not supported */
4750         /* GLV_RMPC not supported */
4751         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4752                            &oes->rx_unknown_protocol,
4753                            &nes->rx_unknown_protocol);
4754         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4755                            vsi->offset_loaded, &oes->tx_bytes,
4756                            &nes->tx_bytes);
4757         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4758                            vsi->offset_loaded, &oes->tx_unicast,
4759                            &nes->tx_unicast);
4760         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4761                            vsi->offset_loaded, &oes->tx_multicast,
4762                            &nes->tx_multicast);
4763         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4764                            vsi->offset_loaded,  &oes->tx_broadcast,
4765                            &nes->tx_broadcast);
4766         /* GLV_TDPC not supported */
4767         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4768                            &oes->tx_errors, &nes->tx_errors);
4769         /* enlarge the limitation when tx_bytes overflowed */
4770         if (vsi->offset_loaded) {
4771                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4772                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4773                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4774         }
4775         vsi->old_tx_bytes = nes->tx_bytes;
4776         vsi->offset_loaded = true;
4777
4778         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4779                     vsi->vsi_id);
4780         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4781         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4782         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4783         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4784         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4785         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4786                     nes->rx_unknown_protocol);
4787         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4788         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4789         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4790         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4791         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4792         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4793         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4794                     vsi->vsi_id);
4795 }
4796
4797 static void
4798 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4799 {
4800         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4801         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4802
4803         /* Get statistics of struct ice_eth_stats */
4804         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4805                            GLPRT_GORCL(hw->port_info->lport),
4806                            pf->offset_loaded, &os->eth.rx_bytes,
4807                            &ns->eth.rx_bytes);
4808         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4809                            GLPRT_UPRCL(hw->port_info->lport),
4810                            pf->offset_loaded, &os->eth.rx_unicast,
4811                            &ns->eth.rx_unicast);
4812         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4813                            GLPRT_MPRCL(hw->port_info->lport),
4814                            pf->offset_loaded, &os->eth.rx_multicast,
4815                            &ns->eth.rx_multicast);
4816         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4817                            GLPRT_BPRCL(hw->port_info->lport),
4818                            pf->offset_loaded, &os->eth.rx_broadcast,
4819                            &ns->eth.rx_broadcast);
4820         ice_stat_update_32(hw, PRTRPB_RDPC,
4821                            pf->offset_loaded, &os->eth.rx_discards,
4822                            &ns->eth.rx_discards);
4823         /* enlarge the limitation when rx_bytes overflowed */
4824         if (pf->offset_loaded) {
4825                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4826                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4827                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4828         }
4829         pf->old_rx_bytes = ns->eth.rx_bytes;
4830
4831         /* Workaround: CRC size should not be included in byte statistics,
4832          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4833          * packet.
4834          */
4835         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4836                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4837
4838         /* GLPRT_REPC not supported */
4839         /* GLPRT_RMPC not supported */
4840         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4841                            pf->offset_loaded,
4842                            &os->eth.rx_unknown_protocol,
4843                            &ns->eth.rx_unknown_protocol);
4844         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4845                            GLPRT_GOTCL(hw->port_info->lport),
4846                            pf->offset_loaded, &os->eth.tx_bytes,
4847                            &ns->eth.tx_bytes);
4848         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4849                            GLPRT_UPTCL(hw->port_info->lport),
4850                            pf->offset_loaded, &os->eth.tx_unicast,
4851                            &ns->eth.tx_unicast);
4852         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4853                            GLPRT_MPTCL(hw->port_info->lport),
4854                            pf->offset_loaded, &os->eth.tx_multicast,
4855                            &ns->eth.tx_multicast);
4856         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4857                            GLPRT_BPTCL(hw->port_info->lport),
4858                            pf->offset_loaded, &os->eth.tx_broadcast,
4859                            &ns->eth.tx_broadcast);
4860         /* enlarge the limitation when tx_bytes overflowed */
4861         if (pf->offset_loaded) {
4862                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4863                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4864                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4865         }
4866         pf->old_tx_bytes = ns->eth.tx_bytes;
4867         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4868                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4869
4870         /* GLPRT_TEPC not supported */
4871
4872         /* additional port specific stats */
4873         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4874                            pf->offset_loaded, &os->tx_dropped_link_down,
4875                            &ns->tx_dropped_link_down);
4876         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4877                            pf->offset_loaded, &os->crc_errors,
4878                            &ns->crc_errors);
4879         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4880                            pf->offset_loaded, &os->illegal_bytes,
4881                            &ns->illegal_bytes);
4882         /* GLPRT_ERRBC not supported */
4883         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4884                            pf->offset_loaded, &os->mac_local_faults,
4885                            &ns->mac_local_faults);
4886         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4887                            pf->offset_loaded, &os->mac_remote_faults,
4888                            &ns->mac_remote_faults);
4889
4890         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4891                            pf->offset_loaded, &os->rx_len_errors,
4892                            &ns->rx_len_errors);
4893
4894         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4895                            pf->offset_loaded, &os->link_xon_rx,
4896                            &ns->link_xon_rx);
4897         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4898                            pf->offset_loaded, &os->link_xoff_rx,
4899                            &ns->link_xoff_rx);
4900         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4901                            pf->offset_loaded, &os->link_xon_tx,
4902                            &ns->link_xon_tx);
4903         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4904                            pf->offset_loaded, &os->link_xoff_tx,
4905                            &ns->link_xoff_tx);
4906         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4907                            GLPRT_PRC64L(hw->port_info->lport),
4908                            pf->offset_loaded, &os->rx_size_64,
4909                            &ns->rx_size_64);
4910         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4911                            GLPRT_PRC127L(hw->port_info->lport),
4912                            pf->offset_loaded, &os->rx_size_127,
4913                            &ns->rx_size_127);
4914         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4915                            GLPRT_PRC255L(hw->port_info->lport),
4916                            pf->offset_loaded, &os->rx_size_255,
4917                            &ns->rx_size_255);
4918         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4919                            GLPRT_PRC511L(hw->port_info->lport),
4920                            pf->offset_loaded, &os->rx_size_511,
4921                            &ns->rx_size_511);
4922         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4923                            GLPRT_PRC1023L(hw->port_info->lport),
4924                            pf->offset_loaded, &os->rx_size_1023,
4925                            &ns->rx_size_1023);
4926         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4927                            GLPRT_PRC1522L(hw->port_info->lport),
4928                            pf->offset_loaded, &os->rx_size_1522,
4929                            &ns->rx_size_1522);
4930         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4931                            GLPRT_PRC9522L(hw->port_info->lport),
4932                            pf->offset_loaded, &os->rx_size_big,
4933                            &ns->rx_size_big);
4934         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4935                            pf->offset_loaded, &os->rx_undersize,
4936                            &ns->rx_undersize);
4937         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4938                            pf->offset_loaded, &os->rx_fragments,
4939                            &ns->rx_fragments);
4940         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
4941                            pf->offset_loaded, &os->rx_oversize,
4942                            &ns->rx_oversize);
4943         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
4944                            pf->offset_loaded, &os->rx_jabber,
4945                            &ns->rx_jabber);
4946         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
4947                            GLPRT_PTC64L(hw->port_info->lport),
4948                            pf->offset_loaded, &os->tx_size_64,
4949                            &ns->tx_size_64);
4950         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
4951                            GLPRT_PTC127L(hw->port_info->lport),
4952                            pf->offset_loaded, &os->tx_size_127,
4953                            &ns->tx_size_127);
4954         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
4955                            GLPRT_PTC255L(hw->port_info->lport),
4956                            pf->offset_loaded, &os->tx_size_255,
4957                            &ns->tx_size_255);
4958         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
4959                            GLPRT_PTC511L(hw->port_info->lport),
4960                            pf->offset_loaded, &os->tx_size_511,
4961                            &ns->tx_size_511);
4962         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
4963                            GLPRT_PTC1023L(hw->port_info->lport),
4964                            pf->offset_loaded, &os->tx_size_1023,
4965                            &ns->tx_size_1023);
4966         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
4967                            GLPRT_PTC1522L(hw->port_info->lport),
4968                            pf->offset_loaded, &os->tx_size_1522,
4969                            &ns->tx_size_1522);
4970         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
4971                            GLPRT_PTC9522L(hw->port_info->lport),
4972                            pf->offset_loaded, &os->tx_size_big,
4973                            &ns->tx_size_big);
4974
4975         /* GLPRT_MSPDC not supported */
4976         /* GLPRT_XEC not supported */
4977
4978         pf->offset_loaded = true;
4979
4980         if (pf->main_vsi)
4981                 ice_update_vsi_stats(pf->main_vsi);
4982 }
4983
4984 /* Get all statistics of a port */
4985 static int
4986 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
4987 {
4988         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4989         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4990         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4991
4992         /* call read registers - updates values, now write them to struct */
4993         ice_read_stats_registers(pf, hw);
4994
4995         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
4996                           pf->main_vsi->eth_stats.rx_multicast +
4997                           pf->main_vsi->eth_stats.rx_broadcast -
4998                           pf->main_vsi->eth_stats.rx_discards;
4999         stats->opackets = ns->eth.tx_unicast +
5000                           ns->eth.tx_multicast +
5001                           ns->eth.tx_broadcast;
5002         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
5003         stats->obytes   = ns->eth.tx_bytes;
5004         stats->oerrors  = ns->eth.tx_errors +
5005                           pf->main_vsi->eth_stats.tx_errors;
5006
5007         /* Rx Errors */
5008         stats->imissed  = ns->eth.rx_discards +
5009                           pf->main_vsi->eth_stats.rx_discards;
5010         stats->ierrors  = ns->crc_errors +
5011                           ns->rx_undersize +
5012                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5013
5014         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5015         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
5016         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5017         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5018         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5019         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5020         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5021                     pf->main_vsi->eth_stats.rx_discards);
5022         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
5023                     ns->eth.rx_unknown_protocol);
5024         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
5025         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5026         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5027         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5028         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5029         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5030                     pf->main_vsi->eth_stats.tx_discards);
5031         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
5032
5033         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
5034                     ns->tx_dropped_link_down);
5035         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5036         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
5037                     ns->illegal_bytes);
5038         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
5039         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
5040                     ns->mac_local_faults);
5041         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
5042                     ns->mac_remote_faults);
5043         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
5044         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
5045         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
5046         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
5047         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
5048         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
5049         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
5050         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
5051         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
5052         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
5053         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
5054         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
5055         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
5056         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
5057         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
5058         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
5059         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
5060         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
5061         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
5062         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
5063         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
5064         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
5065         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
5066         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5067         return 0;
5068 }
5069
5070 /* Reset the statistics */
5071 static int
5072 ice_stats_reset(struct rte_eth_dev *dev)
5073 {
5074         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5075         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5076
5077         /* Mark PF and VSI stats to update the offset, aka "reset" */
5078         pf->offset_loaded = false;
5079         if (pf->main_vsi)
5080                 pf->main_vsi->offset_loaded = false;
5081
5082         /* read the stats, reading current register values into offset */
5083         ice_read_stats_registers(pf, hw);
5084
5085         return 0;
5086 }
5087
5088 static uint32_t
5089 ice_xstats_calc_num(void)
5090 {
5091         uint32_t num;
5092
5093         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5094
5095         return num;
5096 }
5097
5098 static int
5099 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5100                unsigned int n)
5101 {
5102         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5103         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5104         unsigned int i;
5105         unsigned int count;
5106         struct ice_hw_port_stats *hw_stats = &pf->stats;
5107
5108         count = ice_xstats_calc_num();
5109         if (n < count)
5110                 return count;
5111
5112         ice_read_stats_registers(pf, hw);
5113
5114         if (!xstats)
5115                 return 0;
5116
5117         count = 0;
5118
5119         /* Get stats from ice_eth_stats struct */
5120         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5121                 xstats[count].value =
5122                         *(uint64_t *)((char *)&hw_stats->eth +
5123                                       ice_stats_strings[i].offset);
5124                 xstats[count].id = count;
5125                 count++;
5126         }
5127
5128         /* Get individiual stats from ice_hw_port struct */
5129         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5130                 xstats[count].value =
5131                         *(uint64_t *)((char *)hw_stats +
5132                                       ice_hw_port_strings[i].offset);
5133                 xstats[count].id = count;
5134                 count++;
5135         }
5136
5137         return count;
5138 }
5139
5140 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5141                                 struct rte_eth_xstat_name *xstats_names,
5142                                 __rte_unused unsigned int limit)
5143 {
5144         unsigned int count = 0;
5145         unsigned int i;
5146
5147         if (!xstats_names)
5148                 return ice_xstats_calc_num();
5149
5150         /* Note: limit checked in rte_eth_xstats_names() */
5151
5152         /* Get stats from ice_eth_stats struct */
5153         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5154                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5155                         sizeof(xstats_names[count].name));
5156                 count++;
5157         }
5158
5159         /* Get individiual stats from ice_hw_port struct */
5160         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5161                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5162                         sizeof(xstats_names[count].name));
5163                 count++;
5164         }
5165
5166         return count;
5167 }
5168
5169 static int
5170 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5171                      enum rte_filter_type filter_type,
5172                      enum rte_filter_op filter_op,
5173                      void *arg)
5174 {
5175         int ret = 0;
5176
5177         if (!dev)
5178                 return -EINVAL;
5179
5180         switch (filter_type) {
5181         case RTE_ETH_FILTER_GENERIC:
5182                 if (filter_op != RTE_ETH_FILTER_GET)
5183                         return -EINVAL;
5184                 *(const void **)arg = &ice_flow_ops;
5185                 break;
5186         default:
5187                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5188                                         filter_type);
5189                 ret = -EINVAL;
5190                 break;
5191         }
5192
5193         return ret;
5194 }
5195
5196 /* Add UDP tunneling port */
5197 static int
5198 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5199                              struct rte_eth_udp_tunnel *udp_tunnel)
5200 {
5201         int ret = 0;
5202         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5203
5204         if (udp_tunnel == NULL)
5205                 return -EINVAL;
5206
5207         switch (udp_tunnel->prot_type) {
5208         case RTE_TUNNEL_TYPE_VXLAN:
5209                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5210                 break;
5211         default:
5212                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5213                 ret = -EINVAL;
5214                 break;
5215         }
5216
5217         return ret;
5218 }
5219
5220 /* Delete UDP tunneling port */
5221 static int
5222 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5223                              struct rte_eth_udp_tunnel *udp_tunnel)
5224 {
5225         int ret = 0;
5226         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5227
5228         if (udp_tunnel == NULL)
5229                 return -EINVAL;
5230
5231         switch (udp_tunnel->prot_type) {
5232         case RTE_TUNNEL_TYPE_VXLAN:
5233                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5234                 break;
5235         default:
5236                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5237                 ret = -EINVAL;
5238                 break;
5239         }
5240
5241         return ret;
5242 }
5243
5244 static int
5245 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5246               struct rte_pci_device *pci_dev)
5247 {
5248         return rte_eth_dev_pci_generic_probe(pci_dev,
5249                                              sizeof(struct ice_adapter),
5250                                              ice_dev_init);
5251 }
5252
5253 static int
5254 ice_pci_remove(struct rte_pci_device *pci_dev)
5255 {
5256         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5257 }
5258
5259 static struct rte_pci_driver rte_ice_pmd = {
5260         .id_table = pci_id_ice_map,
5261         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5262         .probe = ice_pci_probe,
5263         .remove = ice_pci_remove,
5264 };
5265
5266 /**
5267  * Driver initialization routine.
5268  * Invoked once at EAL init time.
5269  * Register itself as the [Poll Mode] Driver of PCI devices.
5270  */
5271 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5272 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5273 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5274 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5275                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5276                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5277                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5278
5279 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5280 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5281 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5282 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5283 #endif
5284 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5285 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5286 #endif
5287 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5288 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);
5289 #endif