drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "base/ice_common.h"
  17
  18 #include "rte_pmd_ice.h"
  19 #include "ice_ethdev.h"
  20 #include "ice_rxtx.h"
  21 #include "ice_generic_flow.h"
  22
  23 /* devargs */
  24 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  25 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  26 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  27
  28 static const char * const ice_valid_args[] = {
  29         ICE_SAFE_MODE_SUPPORT_ARG,
  30         ICE_PIPELINE_MODE_SUPPORT_ARG,
  31         ICE_PROTO_XTR_ARG,
  32         NULL
  33 };
  34
  35 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  36         .name = "intel_pmd_dynfield_proto_xtr_metadata",
  37         .size = sizeof(uint32_t),
  38         .align = __alignof__(uint32_t),
  39         .flags = 0,
  40 };
  41
  42 struct proto_xtr_ol_flag {
  43         const struct rte_mbuf_dynflag param;
  44         uint64_t *ol_flag;
  45         bool required;
  46 };
  47
  48 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  49
  50 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  51         [PROTO_XTR_VLAN] = {
  52                 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
  53                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  54         [PROTO_XTR_IPV4] = {
  55                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
  56                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  57         [PROTO_XTR_IPV6] = {
  58                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  60         [PROTO_XTR_IPV6_FLOW] = {
  61                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  63         [PROTO_XTR_TCP] = {
  64                 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  66         [PROTO_XTR_IP_OFFSET] = {
  67                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
  68                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  69 };
  70
  71 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  72 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  73 #define ICE_MAX_RES_DESC_NUM        1024
  74
  75 static int ice_dev_configure(struct rte_eth_dev *dev);
  76 static int ice_dev_start(struct rte_eth_dev *dev);
  77 static int ice_dev_stop(struct rte_eth_dev *dev);
  78 static int ice_dev_close(struct rte_eth_dev *dev);
  79 static int ice_dev_reset(struct rte_eth_dev *dev);
  80 static int ice_dev_info_get(struct rte_eth_dev *dev,
  81                             struct rte_eth_dev_info *dev_info);
  82 static int ice_link_update(struct rte_eth_dev *dev,
  83                            int wait_to_complete);
  84 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  85 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  86
  87 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  88 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  89 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  90                                struct rte_eth_rss_reta_entry64 *reta_conf,
  91                                uint16_t reta_size);
  92 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  93                               struct rte_eth_rss_reta_entry64 *reta_conf,
  94                               uint16_t reta_size);
  95 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  96                                struct rte_eth_rss_conf *rss_conf);
  97 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  98                                  struct rte_eth_rss_conf *rss_conf);
  99 static int ice_promisc_enable(struct rte_eth_dev *dev);
 100 static int ice_promisc_disable(struct rte_eth_dev *dev);
 101 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 102 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 103 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 104                                uint16_t vlan_id,
 105                                int on);
 106 static int ice_macaddr_set(struct rte_eth_dev *dev,
 107                            struct rte_ether_addr *mac_addr);
 108 static int ice_macaddr_add(struct rte_eth_dev *dev,
 109                            struct rte_ether_addr *mac_addr,
 110                            __rte_unused uint32_t index,
 111                            uint32_t pool);
 112 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 113 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 114                                     uint16_t queue_id);
 115 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 116                                      uint16_t queue_id);
 117 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 118                               size_t fw_size);
 119 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 120                              uint16_t pvid, int on);
 121 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 122 static int ice_get_eeprom(struct rte_eth_dev *dev,
 123                           struct rte_dev_eeprom_info *eeprom);
 124 static int ice_stats_get(struct rte_eth_dev *dev,
 125                          struct rte_eth_stats *stats);
 126 static int ice_stats_reset(struct rte_eth_dev *dev);
 127 static int ice_xstats_get(struct rte_eth_dev *dev,
 128                           struct rte_eth_xstat *xstats, unsigned int n);
 129 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 130                                 struct rte_eth_xstat_name *xstats_names,
 131                                 unsigned int limit);
 132 static int ice_dev_filter_ctrl(struct rte_eth_dev *dev,
 133                         enum rte_filter_type filter_type,
 134                         enum rte_filter_op filter_op,
 135                         void *arg);
 136 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 137                         struct rte_eth_udp_tunnel *udp_tunnel);
 138 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 139                         struct rte_eth_udp_tunnel *udp_tunnel);
 140
 141 static const struct rte_pci_id pci_id_ice_map[] = {
 142         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 143         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 144         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 145         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 146         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 147         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 148         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 149         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 150         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
 165         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
 166         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
 167         { .vendor_id = 0, /* sentinel */ },
 168 };
 169
 170 static const struct eth_dev_ops ice_eth_dev_ops = {
 171         .dev_configure                = ice_dev_configure,
 172         .dev_start                    = ice_dev_start,
 173         .dev_stop                     = ice_dev_stop,
 174         .dev_close                    = ice_dev_close,
 175         .dev_reset                    = ice_dev_reset,
 176         .dev_set_link_up              = ice_dev_set_link_up,
 177         .dev_set_link_down            = ice_dev_set_link_down,
 178         .rx_queue_start               = ice_rx_queue_start,
 179         .rx_queue_stop                = ice_rx_queue_stop,
 180         .tx_queue_start               = ice_tx_queue_start,
 181         .tx_queue_stop                = ice_tx_queue_stop,
 182         .rx_queue_setup               = ice_rx_queue_setup,
 183         .rx_queue_release             = ice_rx_queue_release,
 184         .tx_queue_setup               = ice_tx_queue_setup,
 185         .tx_queue_release             = ice_tx_queue_release,
 186         .dev_infos_get                = ice_dev_info_get,
 187         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 188         .link_update                  = ice_link_update,
 189         .mtu_set                      = ice_mtu_set,
 190         .mac_addr_set                 = ice_macaddr_set,
 191         .mac_addr_add                 = ice_macaddr_add,
 192         .mac_addr_remove              = ice_macaddr_remove,
 193         .vlan_filter_set              = ice_vlan_filter_set,
 194         .vlan_offload_set             = ice_vlan_offload_set,
 195         .reta_update                  = ice_rss_reta_update,
 196         .reta_query                   = ice_rss_reta_query,
 197         .rss_hash_update              = ice_rss_hash_update,
 198         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 199         .promiscuous_enable           = ice_promisc_enable,
 200         .promiscuous_disable          = ice_promisc_disable,
 201         .allmulticast_enable          = ice_allmulti_enable,
 202         .allmulticast_disable         = ice_allmulti_disable,
 203         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 204         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 205         .fw_version_get               = ice_fw_version_get,
 206         .vlan_pvid_set                = ice_vlan_pvid_set,
 207         .rxq_info_get                 = ice_rxq_info_get,
 208         .txq_info_get                 = ice_txq_info_get,
 209         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 210         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 211         .get_eeprom_length            = ice_get_eeprom_length,
 212         .get_eeprom                   = ice_get_eeprom,
 213         .stats_get                    = ice_stats_get,
 214         .stats_reset                  = ice_stats_reset,
 215         .xstats_get                   = ice_xstats_get,
 216         .xstats_get_names             = ice_xstats_get_names,
 217         .xstats_reset                 = ice_stats_reset,
 218         .filter_ctrl                  = ice_dev_filter_ctrl,
 219         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 220         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 221         .tx_done_cleanup              = ice_tx_done_cleanup,
 222         .get_monitor_addr             = ice_get_monitor_addr,
 223 };
 224
 225 /* store statistics names and its offset in stats structure */
 226 struct ice_xstats_name_off {
 227         char name[RTE_ETH_XSTATS_NAME_SIZE];
 228         unsigned int offset;
 229 };
 230
 231 static const struct ice_xstats_name_off ice_stats_strings[] = {
 232         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 233         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 234         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 235         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 236         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 237                 rx_unknown_protocol)},
 238         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 239         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 240         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 241         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 242 };
 243
 244 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 245                 sizeof(ice_stats_strings[0]))
 246
 247 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 248         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 249                 tx_dropped_link_down)},
 250         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 251         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 252                 illegal_bytes)},
 253         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 254         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 255                 mac_local_faults)},
 256         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 257                 mac_remote_faults)},
 258         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 259                 rx_len_errors)},
 260         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 261         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 262         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 263         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 264         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 265         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 266                 rx_size_127)},
 267         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 268                 rx_size_255)},
 269         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_511)},
 271         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_1023)},
 273         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 274                 rx_size_1522)},
 275         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 276                 rx_size_big)},
 277         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 278                 rx_undersize)},
 279         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 280                 rx_oversize)},
 281         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 282                 mac_short_pkt_dropped)},
 283         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 284                 rx_fragments)},
 285         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 286         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 287         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 288                 tx_size_127)},
 289         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 290                 tx_size_255)},
 291         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_511)},
 293         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_1023)},
 295         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 296                 tx_size_1522)},
 297         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 298                 tx_size_big)},
 299 };
 300
 301 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 302                 sizeof(ice_hw_port_strings[0]))
 303
 304 static void
 305 ice_init_controlq_parameter(struct ice_hw *hw)
 306 {
 307         /* fields for adminq */
 308         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 309         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 310         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 311         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 312
 313         /* fields for mailboxq, DPDK used as PF host */
 314         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 315         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 316         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 317         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 318 }
 319
 320 static int
 321 lookup_proto_xtr_type(const char *xtr_name)
 322 {
 323         static struct {
 324                 const char *name;
 325                 enum proto_xtr_type type;
 326         } xtr_type_map[] = {
 327                 { "vlan",      PROTO_XTR_VLAN      },
 328                 { "ipv4",      PROTO_XTR_IPV4      },
 329                 { "ipv6",      PROTO_XTR_IPV6      },
 330                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 331                 { "tcp",       PROTO_XTR_TCP       },
 332                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 333         };
 334         uint32_t i;
 335
 336         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 337                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 338                         return xtr_type_map[i].type;
 339         }
 340
 341         return -1;
 342 }
 343
 344 /*
 345  * Parse elem, the elem could be single number/range or '(' ')' group
 346  * 1) A single number elem, it's just a simple digit. e.g. 9
 347  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 348  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 349  *    Within group elem, '-' used for a range separator;
 350  *                       ',' used for a single number.
 351  */
 352 static int
 353 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 354 {
 355         const char *str = input;
 356         char *end = NULL;
 357         uint32_t min, max;
 358         uint32_t idx;
 359
 360         while (isblank(*str))
 361                 str++;
 362
 363         if (!isdigit(*str) && *str != '(')
 364                 return -1;
 365
 366         /* process single number or single range of number */
 367         if (*str != '(') {
 368                 errno = 0;
 369                 idx = strtoul(str, &end, 10);
 370                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 371                         return -1;
 372
 373                 while (isblank(*end))
 374                         end++;
 375
 376                 min = idx;
 377                 max = idx;
 378
 379                 /* process single <number>-<number> */
 380                 if (*end == '-') {
 381                         end++;
 382                         while (isblank(*end))
 383                                 end++;
 384                         if (!isdigit(*end))
 385                                 return -1;
 386
 387                         errno = 0;
 388                         idx = strtoul(end, &end, 10);
 389                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 390                                 return -1;
 391
 392                         max = idx;
 393                         while (isblank(*end))
 394                                 end++;
 395                 }
 396
 397                 if (*end != ':')
 398                         return -1;
 399
 400                 for (idx = RTE_MIN(min, max);
 401                      idx <= RTE_MAX(min, max); idx++)
 402                         devargs->proto_xtr[idx] = xtr_type;
 403
 404                 return 0;
 405         }
 406
 407         /* process set within bracket */
 408         str++;
 409         while (isblank(*str))
 410                 str++;
 411         if (*str == '\0')
 412                 return -1;
 413
 414         min = ICE_MAX_QUEUE_NUM;
 415         do {
 416                 /* go ahead to the first digit */
 417                 while (isblank(*str))
 418                         str++;
 419                 if (!isdigit(*str))
 420                         return -1;
 421
 422                 /* get the digit value */
 423                 errno = 0;
 424                 idx = strtoul(str, &end, 10);
 425                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 426                         return -1;
 427
 428                 /* go ahead to separator '-',',' and ')' */
 429                 while (isblank(*end))
 430                         end++;
 431                 if (*end == '-') {
 432                         if (min == ICE_MAX_QUEUE_NUM)
 433                                 min = idx;
 434                         else /* avoid continuous '-' */
 435                                 return -1;
 436                 } else if (*end == ',' || *end == ')') {
 437                         max = idx;
 438                         if (min == ICE_MAX_QUEUE_NUM)
 439                                 min = idx;
 440
 441                         for (idx = RTE_MIN(min, max);
 442                              idx <= RTE_MAX(min, max); idx++)
 443                                 devargs->proto_xtr[idx] = xtr_type;
 444
 445                         min = ICE_MAX_QUEUE_NUM;
 446                 } else {
 447                         return -1;
 448                 }
 449
 450                 str = end + 1;
 451         } while (*end != ')' && *end != '\0');
 452
 453         return 0;
 454 }
 455
 456 static int
 457 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 458 {
 459         const char *queue_start;
 460         uint32_t idx;
 461         int xtr_type;
 462         char xtr_name[32];
 463
 464         while (isblank(*queues))
 465                 queues++;
 466
 467         if (*queues != '[') {
 468                 xtr_type = lookup_proto_xtr_type(queues);
 469                 if (xtr_type < 0)
 470                         return -1;
 471
 472                 devargs->proto_xtr_dflt = xtr_type;
 473
 474                 return 0;
 475         }
 476
 477         queues++;
 478         do {
 479                 while (isblank(*queues))
 480                         queues++;
 481                 if (*queues == '\0')
 482                         return -1;
 483
 484                 queue_start = queues;
 485
 486                 /* go across a complete bracket */
 487                 if (*queue_start == '(') {
 488                         queues += strcspn(queues, ")");
 489                         if (*queues != ')')
 490                                 return -1;
 491                 }
 492
 493                 /* scan the separator ':' */
 494                 queues += strcspn(queues, ":");
 495                 if (*queues++ != ':')
 496                         return -1;
 497                 while (isblank(*queues))
 498                         queues++;
 499
 500                 for (idx = 0; ; idx++) {
 501                         if (isblank(queues[idx]) ||
 502                             queues[idx] == ',' ||
 503                             queues[idx] == ']' ||
 504                             queues[idx] == '\0')
 505                                 break;
 506
 507                         if (idx > sizeof(xtr_name) - 2)
 508                                 return -1;
 509
 510                         xtr_name[idx] = queues[idx];
 511                 }
 512                 xtr_name[idx] = '\0';
 513                 xtr_type = lookup_proto_xtr_type(xtr_name);
 514                 if (xtr_type < 0)
 515                         return -1;
 516
 517                 queues += idx;
 518
 519                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 520                         queues++;
 521
 522                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 523                         return -1;
 524         } while (*queues != '\0');
 525
 526         return 0;
 527 }
 528
 529 static int
 530 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 531                      void *extra_args)
 532 {
 533         struct ice_devargs *devargs = extra_args;
 534
 535         if (value == NULL || extra_args == NULL)
 536                 return -EINVAL;
 537
 538         if (parse_queue_proto_xtr(value, devargs) < 0) {
 539                 PMD_DRV_LOG(ERR,
 540                             "The protocol extraction parameter is wrong : '%s'",
 541                             value);
 542                 return -1;
 543         }
 544
 545         return 0;
 546 }
 547
 548 static void
 549 ice_check_proto_xtr_support(struct ice_hw *hw)
 550 {
 551 #define FLX_REG(val, fld, idx) \
 552         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 553          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 554         static struct {
 555                 uint32_t rxdid;
 556                 uint8_t opcode;
 557                 uint8_t protid_0;
 558                 uint8_t protid_1;
 559         } xtr_sets[] = {
 560                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 561                                      ICE_RX_OPC_EXTRACT,
 562                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 563                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 564                                      ICE_RX_OPC_EXTRACT,
 565                                      ICE_PROT_IPV4_OF_OR_S,
 566                                      ICE_PROT_IPV4_OF_OR_S },
 567                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 568                                      ICE_RX_OPC_EXTRACT,
 569                                      ICE_PROT_IPV6_OF_OR_S,
 570                                      ICE_PROT_IPV6_OF_OR_S },
 571                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 572                                           ICE_RX_OPC_EXTRACT,
 573                                           ICE_PROT_IPV6_OF_OR_S,
 574                                           ICE_PROT_IPV6_OF_OR_S },
 575                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 576                                     ICE_RX_OPC_EXTRACT,
 577                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 578                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 579                                           ICE_RX_OPC_PROTID,
 580                                           ICE_PROT_IPV4_OF_OR_S,
 581                                           ICE_PROT_IPV6_OF_OR_S },
 582         };
 583         uint32_t i;
 584
 585         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 586                 uint32_t rxdid = xtr_sets[i].rxdid;
 587                 uint32_t v;
 588
 589                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 590                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 591
 592                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 593                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 594                                 ice_proto_xtr_hw_support[i] = true;
 595                 }
 596
 597                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 598                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 599
 600                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 601                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 602                                 ice_proto_xtr_hw_support[i] = true;
 603                 }
 604         }
 605 }
 606
 607 static int
 608 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 609                   uint32_t num)
 610 {
 611         struct pool_entry *entry;
 612
 613         if (!pool || !num)
 614                 return -EINVAL;
 615
 616         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 617         if (!entry) {
 618                 PMD_INIT_LOG(ERR,
 619                              "Failed to allocate memory for resource pool");
 620                 return -ENOMEM;
 621         }
 622
 623         /* queue heap initialize */
 624         pool->num_free = num;
 625         pool->num_alloc = 0;
 626         pool->base = base;
 627         LIST_INIT(&pool->alloc_list);
 628         LIST_INIT(&pool->free_list);
 629
 630         /* Initialize element  */
 631         entry->base = 0;
 632         entry->len = num;
 633
 634         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 635         return 0;
 636 }
 637
 638 static int
 639 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 640                    uint16_t num)
 641 {
 642         struct pool_entry *entry, *valid_entry;
 643
 644         if (!pool || !num) {
 645                 PMD_INIT_LOG(ERR, "Invalid parameter");
 646                 return -EINVAL;
 647         }
 648
 649         if (pool->num_free < num) {
 650                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 651                              num, pool->num_free);
 652                 return -ENOMEM;
 653         }
 654
 655         valid_entry = NULL;
 656         /* Lookup  in free list and find most fit one */
 657         LIST_FOREACH(entry, &pool->free_list, next) {
 658                 if (entry->len >= num) {
 659                         /* Find best one */
 660                         if (entry->len == num) {
 661                                 valid_entry = entry;
 662                                 break;
 663                         }
 664                         if (!valid_entry ||
 665                             valid_entry->len > entry->len)
 666                                 valid_entry = entry;
 667                 }
 668         }
 669
 670         /* Not find one to satisfy the request, return */
 671         if (!valid_entry) {
 672                 PMD_INIT_LOG(ERR, "No valid entry found");
 673                 return -ENOMEM;
 674         }
 675         /**
 676          * The entry have equal queue number as requested,
 677          * remove it from alloc_list.
 678          */
 679         if (valid_entry->len == num) {
 680                 LIST_REMOVE(valid_entry, next);
 681         } else {
 682                 /**
 683                  * The entry have more numbers than requested,
 684                  * create a new entry for alloc_list and minus its
 685                  * queue base and number in free_list.
 686                  */
 687                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 688                 if (!entry) {
 689                         PMD_INIT_LOG(ERR,
 690                                      "Failed to allocate memory for "
 691                                      "resource pool");
 692                         return -ENOMEM;
 693                 }
 694                 entry->base = valid_entry->base;
 695                 entry->len = num;
 696                 valid_entry->base += num;
 697                 valid_entry->len -= num;
 698                 valid_entry = entry;
 699         }
 700
 701         /* Insert it into alloc list, not sorted */
 702         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 703
 704         pool->num_free -= valid_entry->len;
 705         pool->num_alloc += valid_entry->len;
 706
 707         return valid_entry->base + pool->base;
 708 }
 709
 710 static void
 711 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 712 {
 713         struct pool_entry *entry, *next_entry;
 714
 715         if (!pool)
 716                 return;
 717
 718         for (entry = LIST_FIRST(&pool->alloc_list);
 719              entry && (next_entry = LIST_NEXT(entry, next), 1);
 720              entry = next_entry) {
 721                 LIST_REMOVE(entry, next);
 722                 rte_free(entry);
 723         }
 724
 725         for (entry = LIST_FIRST(&pool->free_list);
 726              entry && (next_entry = LIST_NEXT(entry, next), 1);
 727              entry = next_entry) {
 728                 LIST_REMOVE(entry, next);
 729                 rte_free(entry);
 730         }
 731
 732         pool->num_free = 0;
 733         pool->num_alloc = 0;
 734         pool->base = 0;
 735         LIST_INIT(&pool->alloc_list);
 736         LIST_INIT(&pool->free_list);
 737 }
 738
 739 static void
 740 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 741 {
 742         /* Set VSI LUT selection */
 743         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 744                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 745         /* Set Hash scheme */
 746         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 747                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 748         /* enable TC */
 749         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 750 }
 751
 752 static enum ice_status
 753 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 754                                 struct ice_aqc_vsi_props *info,
 755                                 uint8_t enabled_tcmap)
 756 {
 757         uint16_t bsf, qp_idx;
 758
 759         /* default tc 0 now. Multi-TC supporting need to be done later.
 760          * Configure TC and queue mapping parameters, for enabled TC,
 761          * allocate qpnum_per_tc queues to this traffic.
 762          */
 763         if (enabled_tcmap != 0x01) {
 764                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 765                 return -ENOTSUP;
 766         }
 767
 768         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 769         bsf = rte_bsf32(vsi->nb_qps);
 770         /* Adjust the queue number to actual queues that can be applied */
 771         vsi->nb_qps = 0x1 << bsf;
 772
 773         qp_idx = 0;
 774         /* Set tc and queue mapping with VSI */
 775         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 776                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 777                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 778
 779         /* Associate queue number with VSI */
 780         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 781         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 782         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 783         info->valid_sections |=
 784                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 785         /* Set the info.ingress_table and info.egress_table
 786          * for UP translate table. Now just set it to 1:1 map by default
 787          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 788          */
 789 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 790         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 791         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 792         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 793         return 0;
 794 }
 795
 796 static int
 797 ice_init_mac_address(struct rte_eth_dev *dev)
 798 {
 799         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 800
 801         if (!rte_is_unicast_ether_addr
 802                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 803                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 804                 return -EINVAL;
 805         }
 806
 807         rte_ether_addr_copy(
 808                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 809                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 810
 811         dev->data->mac_addrs =
 812                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr), 0);
 813         if (!dev->data->mac_addrs) {
 814                 PMD_INIT_LOG(ERR,
 815                              "Failed to allocate memory to store mac address");
 816                 return -ENOMEM;
 817         }
 818         /* store it to dev data */
 819         rte_ether_addr_copy(
 820                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 821                 &dev->data->mac_addrs[0]);
 822         return 0;
 823 }
 824
 825 /* Find out specific MAC filter */
 826 static struct ice_mac_filter *
 827 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 828 {
 829         struct ice_mac_filter *f;
 830
 831         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 832                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 833                         return f;
 834         }
 835
 836         return NULL;
 837 }
 838
 839 static int
 840 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 841 {
 842         struct ice_fltr_list_entry *m_list_itr = NULL;
 843         struct ice_mac_filter *f;
 844         struct LIST_HEAD_TYPE list_head;
 845         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 846         int ret = 0;
 847
 848         /* If it's added and configured, return */
 849         f = ice_find_mac_filter(vsi, mac_addr);
 850         if (f) {
 851                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 852                 return 0;
 853         }
 854
 855         INIT_LIST_HEAD(&list_head);
 856
 857         m_list_itr = (struct ice_fltr_list_entry *)
 858                 ice_malloc(hw, sizeof(*m_list_itr));
 859         if (!m_list_itr) {
 860                 ret = -ENOMEM;
 861                 goto DONE;
 862         }
 863         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 864                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 865         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 866         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 867         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 868         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 869         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 870
 871         LIST_ADD(&m_list_itr->list_entry, &list_head);
 872
 873         /* Add the mac */
 874         ret = ice_add_mac(hw, &list_head);
 875         if (ret != ICE_SUCCESS) {
 876                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 877                 ret = -EINVAL;
 878                 goto DONE;
 879         }
 880         /* Add the mac addr into mac list */
 881         f = rte_zmalloc(NULL, sizeof(*f), 0);
 882         if (!f) {
 883                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 884                 ret = -ENOMEM;
 885                 goto DONE;
 886         }
 887         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 888         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 889         vsi->mac_num++;
 890
 891         ret = 0;
 892
 893 DONE:
 894         rte_free(m_list_itr);
 895         return ret;
 896 }
 897
 898 static int
 899 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 900 {
 901         struct ice_fltr_list_entry *m_list_itr = NULL;
 902         struct ice_mac_filter *f;
 903         struct LIST_HEAD_TYPE list_head;
 904         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 905         int ret = 0;
 906
 907         /* Can't find it, return an error */
 908         f = ice_find_mac_filter(vsi, mac_addr);
 909         if (!f)
 910                 return -EINVAL;
 911
 912         INIT_LIST_HEAD(&list_head);
 913
 914         m_list_itr = (struct ice_fltr_list_entry *)
 915                 ice_malloc(hw, sizeof(*m_list_itr));
 916         if (!m_list_itr) {
 917                 ret = -ENOMEM;
 918                 goto DONE;
 919         }
 920         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 921                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 922         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 923         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 924         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 925         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 926         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 927
 928         LIST_ADD(&m_list_itr->list_entry, &list_head);
 929
 930         /* remove the mac filter */
 931         ret = ice_remove_mac(hw, &list_head);
 932         if (ret != ICE_SUCCESS) {
 933                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 934                 ret = -EINVAL;
 935                 goto DONE;
 936         }
 937
 938         /* Remove the mac addr from mac list */
 939         TAILQ_REMOVE(&vsi->mac_list, f, next);
 940         rte_free(f);
 941         vsi->mac_num--;
 942
 943         ret = 0;
 944 DONE:
 945         rte_free(m_list_itr);
 946         return ret;
 947 }
 948
 949 /* Find out specific VLAN filter */
 950 static struct ice_vlan_filter *
 951 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 952 {
 953         struct ice_vlan_filter *f;
 954
 955         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 956                 if (vlan->tpid == f->vlan_info.vlan.tpid &&
 957                     vlan->vid == f->vlan_info.vlan.vid)
 958                         return f;
 959         }
 960
 961         return NULL;
 962 }
 963
 964 static int
 965 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 966 {
 967         struct ice_fltr_list_entry *v_list_itr = NULL;
 968         struct ice_vlan_filter *f;
 969         struct LIST_HEAD_TYPE list_head;
 970         struct ice_hw *hw;
 971         int ret = 0;
 972
 973         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
 974                 return -EINVAL;
 975
 976         hw = ICE_VSI_TO_HW(vsi);
 977
 978         /* If it's added and configured, return. */
 979         f = ice_find_vlan_filter(vsi, vlan);
 980         if (f) {
 981                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 982                 return 0;
 983         }
 984
 985         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 986                 return 0;
 987
 988         INIT_LIST_HEAD(&list_head);
 989
 990         v_list_itr = (struct ice_fltr_list_entry *)
 991                       ice_malloc(hw, sizeof(*v_list_itr));
 992         if (!v_list_itr) {
 993                 ret = -ENOMEM;
 994                 goto DONE;
 995         }
 996         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
 997         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
 998         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
 999         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1000         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1001         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1002         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1003         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1004
1005         LIST_ADD(&v_list_itr->list_entry, &list_head);
1006
1007         /* Add the vlan */
1008         ret = ice_add_vlan(hw, &list_head);
1009         if (ret != ICE_SUCCESS) {
1010                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1011                 ret = -EINVAL;
1012                 goto DONE;
1013         }
1014
1015         /* Add vlan into vlan list */
1016         f = rte_zmalloc(NULL, sizeof(*f), 0);
1017         if (!f) {
1018                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1019                 ret = -ENOMEM;
1020                 goto DONE;
1021         }
1022         f->vlan_info.vlan.tpid = vlan->tpid;
1023         f->vlan_info.vlan.vid = vlan->vid;
1024         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1025         vsi->vlan_num++;
1026
1027         ret = 0;
1028
1029 DONE:
1030         rte_free(v_list_itr);
1031         return ret;
1032 }
1033
1034 static int
1035 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1036 {
1037         struct ice_fltr_list_entry *v_list_itr = NULL;
1038         struct ice_vlan_filter *f;
1039         struct LIST_HEAD_TYPE list_head;
1040         struct ice_hw *hw;
1041         int ret = 0;
1042
1043         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1044                 return -EINVAL;
1045
1046         hw = ICE_VSI_TO_HW(vsi);
1047
1048         /* Can't find it, return an error */
1049         f = ice_find_vlan_filter(vsi, vlan);
1050         if (!f)
1051                 return -EINVAL;
1052
1053         INIT_LIST_HEAD(&list_head);
1054
1055         v_list_itr = (struct ice_fltr_list_entry *)
1056                       ice_malloc(hw, sizeof(*v_list_itr));
1057         if (!v_list_itr) {
1058                 ret = -ENOMEM;
1059                 goto DONE;
1060         }
1061
1062         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1063         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1064         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1065         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1066         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1067         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1068         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1069         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1070
1071         LIST_ADD(&v_list_itr->list_entry, &list_head);
1072
1073         /* remove the vlan filter */
1074         ret = ice_remove_vlan(hw, &list_head);
1075         if (ret != ICE_SUCCESS) {
1076                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1077                 ret = -EINVAL;
1078                 goto DONE;
1079         }
1080
1081         /* Remove the vlan id from vlan list */
1082         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1083         rte_free(f);
1084         vsi->vlan_num--;
1085
1086         ret = 0;
1087 DONE:
1088         rte_free(v_list_itr);
1089         return ret;
1090 }
1091
1092 static int
1093 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1094 {
1095         struct ice_mac_filter *m_f;
1096         struct ice_vlan_filter *v_f;
1097         int ret = 0;
1098
1099         if (!vsi || !vsi->mac_num)
1100                 return -EINVAL;
1101
1102         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
1103                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1104                 if (ret != ICE_SUCCESS) {
1105                         ret = -EINVAL;
1106                         goto DONE;
1107                 }
1108         }
1109
1110         if (vsi->vlan_num == 0)
1111                 return 0;
1112
1113         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
1114                 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1115                 if (ret != ICE_SUCCESS) {
1116                         ret = -EINVAL;
1117                         goto DONE;
1118                 }
1119         }
1120
1121 DONE:
1122         return ret;
1123 }
1124
1125 /* Enable IRQ0 */
1126 static void
1127 ice_pf_enable_irq0(struct ice_hw *hw)
1128 {
1129         /* reset the registers */
1130         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1131         ICE_READ_REG(hw, PFINT_OICR);
1132
1133 #ifdef ICE_LSE_SPT
1134         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1135                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1136                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1137
1138         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1139                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1140                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1141                        PFINT_OICR_CTL_ITR_INDX_M) |
1142                       PFINT_OICR_CTL_CAUSE_ENA_M);
1143
1144         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1145                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1146                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1147                        PFINT_FW_CTL_ITR_INDX_M) |
1148                       PFINT_FW_CTL_CAUSE_ENA_M);
1149 #else
1150         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1151 #endif
1152
1153         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1154                       GLINT_DYN_CTL_INTENA_M |
1155                       GLINT_DYN_CTL_CLEARPBA_M |
1156                       GLINT_DYN_CTL_ITR_INDX_M);
1157
1158         ice_flush(hw);
1159 }
1160
1161 /* Disable IRQ0 */
1162 static void
1163 ice_pf_disable_irq0(struct ice_hw *hw)
1164 {
1165         /* Disable all interrupt types */
1166         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1167         ice_flush(hw);
1168 }
1169
1170 #ifdef ICE_LSE_SPT
1171 static void
1172 ice_handle_aq_msg(struct rte_eth_dev *dev)
1173 {
1174         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1175         struct ice_ctl_q_info *cq = &hw->adminq;
1176         struct ice_rq_event_info event;
1177         uint16_t pending, opcode;
1178         int ret;
1179
1180         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1181         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1182         if (!event.msg_buf) {
1183                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1184                 return;
1185         }
1186
1187         pending = 1;
1188         while (pending) {
1189                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1190
1191                 if (ret != ICE_SUCCESS) {
1192                         PMD_DRV_LOG(INFO,
1193                                     "Failed to read msg from AdminQ, "
1194                                     "adminq_err: %u",
1195                                     hw->adminq.sq_last_status);
1196                         break;
1197                 }
1198                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1199
1200                 switch (opcode) {
1201                 case ice_aqc_opc_get_link_status:
1202                         ret = ice_link_update(dev, 0);
1203                         if (!ret)
1204                                 rte_eth_dev_callback_process
1205                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1206                         break;
1207                 default:
1208                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1209                                     opcode);
1210                         break;
1211                 }
1212         }
1213         rte_free(event.msg_buf);
1214 }
1215 #endif
1216
1217 /**
1218  * Interrupt handler triggered by NIC for handling
1219  * specific interrupt.
1220  *
1221  * @param handle
1222  *  Pointer to interrupt handle.
1223  * @param param
1224  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1225  *
1226  * @return
1227  *  void
1228  */
1229 static void
1230 ice_interrupt_handler(void *param)
1231 {
1232         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1233         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1234         uint32_t oicr;
1235         uint32_t reg;
1236         uint8_t pf_num;
1237         uint8_t event;
1238         uint16_t queue;
1239         int ret;
1240 #ifdef ICE_LSE_SPT
1241         uint32_t int_fw_ctl;
1242 #endif
1243
1244         /* Disable interrupt */
1245         ice_pf_disable_irq0(hw);
1246
1247         /* read out interrupt causes */
1248         oicr = ICE_READ_REG(hw, PFINT_OICR);
1249 #ifdef ICE_LSE_SPT
1250         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1251 #endif
1252
1253         /* No interrupt event indicated */
1254         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1255                 PMD_DRV_LOG(INFO, "No interrupt event");
1256                 goto done;
1257         }
1258
1259 #ifdef ICE_LSE_SPT
1260         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1261                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1262                 ice_handle_aq_msg(dev);
1263         }
1264 #else
1265         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1266                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1267                 ret = ice_link_update(dev, 0);
1268                 if (!ret)
1269                         rte_eth_dev_callback_process
1270                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1271         }
1272 #endif
1273
1274         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1275                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1276                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1277                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1278                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1279                                  GL_MDET_TX_PQM_PF_NUM_S;
1280                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1281                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1282                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1283                                 GL_MDET_TX_PQM_QNUM_S;
1284
1285                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1286                                     "%d by PQM on TX queue %d PF# %d",
1287                                     event, queue, pf_num);
1288                 }
1289
1290                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1291                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1292                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1293                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1294                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1295                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1296                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1297                                 GL_MDET_TX_TCLAN_QNUM_S;
1298
1299                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1300                                     "%d by TCLAN on TX queue %d PF# %d",
1301                                     event, queue, pf_num);
1302                 }
1303         }
1304 done:
1305         /* Enable interrupt */
1306         ice_pf_enable_irq0(hw);
1307         rte_intr_ack(dev->intr_handle);
1308 }
1309
1310 static void
1311 ice_init_proto_xtr(struct rte_eth_dev *dev)
1312 {
1313         struct ice_adapter *ad =
1314                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1315         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1316         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1317         const struct proto_xtr_ol_flag *ol_flag;
1318         bool proto_xtr_enable = false;
1319         int offset;
1320         uint16_t i;
1321
1322         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1323         if (unlikely(pf->proto_xtr == NULL)) {
1324                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1325                 return;
1326         }
1327
1328         for (i = 0; i < pf->lan_nb_qps; i++) {
1329                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1330                                    ad->devargs.proto_xtr[i] :
1331                                    ad->devargs.proto_xtr_dflt;
1332
1333                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1334                         uint8_t type = pf->proto_xtr[i];
1335
1336                         ice_proto_xtr_ol_flag_params[type].required = true;
1337                         proto_xtr_enable = true;
1338                 }
1339         }
1340
1341         if (likely(!proto_xtr_enable))
1342                 return;
1343
1344         ice_check_proto_xtr_support(hw);
1345
1346         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1347         if (unlikely(offset == -1)) {
1348                 PMD_DRV_LOG(ERR,
1349                             "Protocol extraction metadata is disabled in mbuf with error %d",
1350                             -rte_errno);
1351                 return;
1352         }
1353
1354         PMD_DRV_LOG(DEBUG,
1355                     "Protocol extraction metadata offset in mbuf is : %d",
1356                     offset);
1357         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1358
1359         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1360                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1361
1362                 if (!ol_flag->required)
1363                         continue;
1364
1365                 if (!ice_proto_xtr_hw_support[i]) {
1366                         PMD_DRV_LOG(ERR,
1367                                     "Protocol extraction type %u is not supported in hardware",
1368                                     i);
1369                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1370                         break;
1371                 }
1372
1373                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1374                 if (unlikely(offset == -1)) {
1375                         PMD_DRV_LOG(ERR,
1376                                     "Protocol extraction offload '%s' failed to register with error %d",
1377                                     ol_flag->param.name, -rte_errno);
1378
1379                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1380                         break;
1381                 }
1382
1383                 PMD_DRV_LOG(DEBUG,
1384                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1385                             ol_flag->param.name, offset);
1386                 *ol_flag->ol_flag = 1ULL << offset;
1387         }
1388 }
1389
1390 /*  Initialize SW parameters of PF */
1391 static int
1392 ice_pf_sw_init(struct rte_eth_dev *dev)
1393 {
1394         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1395         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1396
1397         pf->lan_nb_qp_max =
1398                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1399                                   hw->func_caps.common_cap.num_rxq);
1400
1401         pf->lan_nb_qps = pf->lan_nb_qp_max;
1402
1403         ice_init_proto_xtr(dev);
1404
1405         if (hw->func_caps.fd_fltr_guar > 0 ||
1406             hw->func_caps.fd_fltr_best_effort > 0) {
1407                 pf->flags |= ICE_FLAG_FDIR;
1408                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1409                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1410         } else {
1411                 pf->fdir_nb_qps = 0;
1412         }
1413         pf->fdir_qp_offset = 0;
1414
1415         return 0;
1416 }
1417
1418 struct ice_vsi *
1419 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1420 {
1421         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1422         struct ice_vsi *vsi = NULL;
1423         struct ice_vsi_ctx vsi_ctx;
1424         int ret;
1425         struct rte_ether_addr broadcast = {
1426                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1427         struct rte_ether_addr mac_addr;
1428         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1429         uint8_t tc_bitmap = 0x1;
1430         uint16_t cfg;
1431
1432         /* hw->num_lports = 1 in NIC mode */
1433         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1434         if (!vsi)
1435                 return NULL;
1436
1437         vsi->idx = pf->next_vsi_idx;
1438         pf->next_vsi_idx++;
1439         vsi->type = type;
1440         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1441         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1442         vsi->vlan_anti_spoof_on = 0;
1443         vsi->vlan_filter_on = 1;
1444         TAILQ_INIT(&vsi->mac_list);
1445         TAILQ_INIT(&vsi->vlan_list);
1446
1447         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1448         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1449                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1450                         hw->func_caps.common_cap.rss_table_size;
1451         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1452
1453         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1454         switch (type) {
1455         case ICE_VSI_PF:
1456                 vsi->nb_qps = pf->lan_nb_qps;
1457                 vsi->base_queue = 1;
1458                 ice_vsi_config_default_rss(&vsi_ctx.info);
1459                 vsi_ctx.alloc_from_pool = true;
1460                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1461                 /* switch_id is queried by get_switch_config aq, which is done
1462                  * by ice_init_hw
1463                  */
1464                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1465                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1466                 /* Allow all untagged or tagged packets */
1467                 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1468                 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1469                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1470                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1471                 if (ice_is_dvm_ena(hw)) {
1472                         vsi_ctx.info.outer_vlan_flags =
1473                                 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1474                                  ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1475                                 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1476                         vsi_ctx.info.outer_vlan_flags |=
1477                                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1478                                  ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1479                                 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1480                 }
1481
1482                 /* FDIR */
1483                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1484                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1485                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1486                 cfg = ICE_AQ_VSI_FD_ENABLE;
1487                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1488                 vsi_ctx.info.max_fd_fltr_dedicated =
1489                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1490                 vsi_ctx.info.max_fd_fltr_shared =
1491                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1492
1493                 /* Enable VLAN/UP trip */
1494                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1495                                                       &vsi_ctx.info,
1496                                                       ICE_DEFAULT_TCMAP);
1497                 if (ret) {
1498                         PMD_INIT_LOG(ERR,
1499                                      "tc queue mapping with vsi failed, "
1500                                      "err = %d",
1501                                      ret);
1502                         goto fail_mem;
1503                 }
1504
1505                 break;
1506         case ICE_VSI_CTRL:
1507                 vsi->nb_qps = pf->fdir_nb_qps;
1508                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1509                 vsi_ctx.alloc_from_pool = true;
1510                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1511
1512                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1513                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1514                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1515                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1516                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1517                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1518                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1519                                                       &vsi_ctx.info,
1520                                                       ICE_DEFAULT_TCMAP);
1521                 if (ret) {
1522                         PMD_INIT_LOG(ERR,
1523                                      "tc queue mapping with vsi failed, "
1524                                      "err = %d",
1525                                      ret);
1526                         goto fail_mem;
1527                 }
1528                 break;
1529         default:
1530                 /* for other types of VSI */
1531                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1532                 goto fail_mem;
1533         }
1534
1535         /* VF has MSIX interrupt in VF range, don't allocate here */
1536         if (type == ICE_VSI_PF) {
1537                 ret = ice_res_pool_alloc(&pf->msix_pool,
1538                                          RTE_MIN(vsi->nb_qps,
1539                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1540                 if (ret < 0) {
1541                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1542                                      vsi->vsi_id, ret);
1543                 }
1544                 vsi->msix_intr = ret;
1545                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1546         } else if (type == ICE_VSI_CTRL) {
1547                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1548                 if (ret < 0) {
1549                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1550                                     vsi->vsi_id, ret);
1551                 }
1552                 vsi->msix_intr = ret;
1553                 vsi->nb_msix = 1;
1554         } else {
1555                 vsi->msix_intr = 0;
1556                 vsi->nb_msix = 0;
1557         }
1558         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1559         if (ret != ICE_SUCCESS) {
1560                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1561                 goto fail_mem;
1562         }
1563         /* store vsi information is SW structure */
1564         vsi->vsi_id = vsi_ctx.vsi_num;
1565         vsi->info = vsi_ctx.info;
1566         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1567         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1568
1569         if (type == ICE_VSI_PF) {
1570                 /* MAC configuration */
1571                 rte_ether_addr_copy((struct rte_ether_addr *)
1572                                         hw->port_info->mac.perm_addr,
1573                                     &pf->dev_addr);
1574
1575                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1576                 ret = ice_add_mac_filter(vsi, &mac_addr);
1577                 if (ret != ICE_SUCCESS)
1578                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1579
1580                 rte_ether_addr_copy(&broadcast, &mac_addr);
1581                 ret = ice_add_mac_filter(vsi, &mac_addr);
1582                 if (ret != ICE_SUCCESS)
1583                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1584         }
1585
1586         /* At the beginning, only TC0. */
1587         /* What we need here is the maximam number of the TX queues.
1588          * Currently vsi->nb_qps means it.
1589          * Correct it if any change.
1590          */
1591         max_txqs[0] = vsi->nb_qps;
1592         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1593                               tc_bitmap, max_txqs);
1594         if (ret != ICE_SUCCESS)
1595                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1596
1597         return vsi;
1598 fail_mem:
1599         rte_free(vsi);
1600         pf->next_vsi_idx--;
1601         return NULL;
1602 }
1603
1604 static int
1605 ice_send_driver_ver(struct ice_hw *hw)
1606 {
1607         struct ice_driver_ver dv;
1608
1609         /* we don't have driver version use 0 for dummy */
1610         dv.major_ver = 0;
1611         dv.minor_ver = 0;
1612         dv.build_ver = 0;
1613         dv.subbuild_ver = 0;
1614         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1615
1616         return ice_aq_send_driver_ver(hw, &dv, NULL);
1617 }
1618
1619 static int
1620 ice_pf_setup(struct ice_pf *pf)
1621 {
1622         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1623         struct ice_vsi *vsi;
1624         uint16_t unused;
1625
1626         /* Clear all stats counters */
1627         pf->offset_loaded = false;
1628         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1629         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1630         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1631         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1632
1633         /* force guaranteed filter pool for PF */
1634         ice_alloc_fd_guar_item(hw, &unused,
1635                                hw->func_caps.fd_fltr_guar);
1636         /* force shared filter pool for PF */
1637         ice_alloc_fd_shrd_item(hw, &unused,
1638                                hw->func_caps.fd_fltr_best_effort);
1639
1640         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1641         if (!vsi) {
1642                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1643                 return -EINVAL;
1644         }
1645
1646         pf->main_vsi = vsi;
1647
1648         return 0;
1649 }
1650
1651 /*
1652  * Extract device serial number from PCIe Configuration Space and
1653  * determine the pkg file path according to the DSN.
1654  */
1655 static int
1656 ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file)
1657 {
1658         off_t pos;
1659         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1660         uint32_t dsn_low, dsn_high;
1661         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1662
1663         pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
1664
1665         if (pos) {
1666                 rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4);
1667                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8);
1668                 snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1669                          "ice-%08x%08x.pkg", dsn_high, dsn_low);
1670         } else {
1671                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
1672                 goto fail_dsn;
1673         }
1674
1675         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1676                 ICE_MAX_PKG_FILENAME_SIZE);
1677         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1678                 return 0;
1679
1680         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1681                 ICE_MAX_PKG_FILENAME_SIZE);
1682         if (!access(strcat(pkg_file, opt_ddp_filename), 0))
1683                 return 0;
1684
1685 fail_dsn:
1686         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1687         if (!access(pkg_file, 0))
1688                 return 0;
1689         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1690         return 0;
1691 }
1692
1693 enum ice_pkg_type
1694 ice_load_pkg_type(struct ice_hw *hw)
1695 {
1696         enum ice_pkg_type package_type;
1697
1698         /* store the activated package type (OS default or Comms) */
1699         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1700                 ICE_PKG_NAME_SIZE))
1701                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1702         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1703                 ICE_PKG_NAME_SIZE))
1704                 package_type = ICE_PKG_TYPE_COMMS;
1705         else
1706                 package_type = ICE_PKG_TYPE_UNKNOWN;
1707
1708         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1709                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1710                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1711                 hw->active_pkg_name,
1712                 ice_is_dvm_ena(hw) ? "double" : "single");
1713
1714         return package_type;
1715 }
1716
1717 static int ice_load_pkg(struct rte_eth_dev *dev)
1718 {
1719         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1720         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1721         int err;
1722         uint8_t *buf;
1723         int buf_len;
1724         FILE *file;
1725         struct stat fstat;
1726         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
1727         struct ice_adapter *ad =
1728                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1729
1730         ice_pkg_file_search_path(pci_dev, pkg_file);
1731
1732         file = fopen(pkg_file, "rb");
1733         if (!file)  {
1734                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1735                 return -1;
1736         }
1737
1738         err = stat(pkg_file, &fstat);
1739         if (err) {
1740                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1741                 fclose(file);
1742                 return err;
1743         }
1744
1745         buf_len = fstat.st_size;
1746         buf = rte_malloc(NULL, buf_len, 0);
1747
1748         if (!buf) {
1749                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1750                                 buf_len);
1751                 fclose(file);
1752                 return -1;
1753         }
1754
1755         err = fread(buf, buf_len, 1, file);
1756         if (err != 1) {
1757                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1758                 fclose(file);
1759                 err = -1;
1760                 goto fail_exit;
1761         }
1762
1763         fclose(file);
1764
1765         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1766         if (err) {
1767                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1768                 goto fail_exit;
1769         }
1770
1771         /* store the loaded pkg type info */
1772         ad->active_pkg_type = ice_load_pkg_type(hw);
1773
1774         err = ice_init_hw_tbls(hw);
1775         if (err) {
1776                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1777                 goto fail_init_tbls;
1778         }
1779
1780         return 0;
1781
1782 fail_init_tbls:
1783         rte_free(hw->pkg_copy);
1784 fail_exit:
1785         rte_free(buf);
1786         return err;
1787 }
1788
1789 static void
1790 ice_base_queue_get(struct ice_pf *pf)
1791 {
1792         uint32_t reg;
1793         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1794
1795         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1796         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1797                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1798         } else {
1799                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1800                                         " index");
1801         }
1802 }
1803
1804 static int
1805 parse_bool(const char *key, const char *value, void *args)
1806 {
1807         int *i = (int *)args;
1808         char *end;
1809         int num;
1810
1811         num = strtoul(value, &end, 10);
1812
1813         if (num != 0 && num != 1) {
1814                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1815                         "value must be 0 or 1",
1816                         value, key);
1817                 return -1;
1818         }
1819
1820         *i = num;
1821         return 0;
1822 }
1823
1824 static int ice_parse_devargs(struct rte_eth_dev *dev)
1825 {
1826         struct ice_adapter *ad =
1827                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1828         struct rte_devargs *devargs = dev->device->devargs;
1829         struct rte_kvargs *kvlist;
1830         int ret;
1831
1832         if (devargs == NULL)
1833                 return 0;
1834
1835         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1836         if (kvlist == NULL) {
1837                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1838                 return -EINVAL;
1839         }
1840
1841         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1842         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1843                sizeof(ad->devargs.proto_xtr));
1844
1845         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1846                                  &handle_proto_xtr_arg, &ad->devargs);
1847         if (ret)
1848                 goto bail;
1849
1850         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1851                                  &parse_bool, &ad->devargs.safe_mode_support);
1852         if (ret)
1853                 goto bail;
1854
1855         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1856                                  &parse_bool, &ad->devargs.pipe_mode_support);
1857         if (ret)
1858                 goto bail;
1859
1860 bail:
1861         rte_kvargs_free(kvlist);
1862         return ret;
1863 }
1864
1865 /* Forward LLDP packets to default VSI by set switch rules */
1866 static int
1867 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1868 {
1869         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1870         struct ice_fltr_list_entry *s_list_itr = NULL;
1871         struct LIST_HEAD_TYPE list_head;
1872         int ret = 0;
1873
1874         INIT_LIST_HEAD(&list_head);
1875
1876         s_list_itr = (struct ice_fltr_list_entry *)
1877                         ice_malloc(hw, sizeof(*s_list_itr));
1878         if (!s_list_itr)
1879                 return -ENOMEM;
1880         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1881         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1882         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1883                         RTE_ETHER_TYPE_LLDP;
1884         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1885         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1886         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1887         LIST_ADD(&s_list_itr->list_entry, &list_head);
1888         if (on)
1889                 ret = ice_add_eth_mac(hw, &list_head);
1890         else
1891                 ret = ice_remove_eth_mac(hw, &list_head);
1892
1893         rte_free(s_list_itr);
1894         return ret;
1895 }
1896
1897 static enum ice_status
1898 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1899                 uint16_t num, uint16_t desc_id,
1900                 uint16_t *prof_buf, uint16_t *num_prof)
1901 {
1902         struct ice_aqc_res_elem *resp_buf;
1903         int ret;
1904         uint16_t buf_len;
1905         bool res_shared = 1;
1906         struct ice_aq_desc aq_desc;
1907         struct ice_sq_cd *cd = NULL;
1908         struct ice_aqc_get_allocd_res_desc *cmd =
1909                         &aq_desc.params.get_res_desc;
1910
1911         buf_len = sizeof(*resp_buf) * num;
1912         resp_buf = ice_malloc(hw, buf_len);
1913         if (!resp_buf)
1914                 return -ENOMEM;
1915
1916         ice_fill_dflt_direct_cmd_desc(&aq_desc,
1917                         ice_aqc_opc_get_allocd_res_desc);
1918
1919         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1920                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
1921                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1922         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1923
1924         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1925         if (!ret)
1926                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1927         else
1928                 goto exit;
1929
1930         ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
1931                         (*num_prof), ICE_NONDMA_TO_NONDMA);
1932
1933 exit:
1934         rte_free(resp_buf);
1935         return ret;
1936 }
1937 static int
1938 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1939 {
1940         int ret;
1941         uint16_t prof_id;
1942         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1943         uint16_t first_desc = 1;
1944         uint16_t num_prof = 0;
1945
1946         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1947                         first_desc, prof_buf, &num_prof);
1948         if (ret) {
1949                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
1950                 return ret;
1951         }
1952
1953         for (prof_id = 0; prof_id < num_prof; prof_id++) {
1954                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
1955                 if (ret) {
1956                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
1957                         return ret;
1958                 }
1959         }
1960         return 0;
1961 }
1962
1963 static int
1964 ice_reset_fxp_resource(struct ice_hw *hw)
1965 {
1966         int ret;
1967
1968         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
1969         if (ret) {
1970                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
1971                 return ret;
1972         }
1973
1974         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
1975         if (ret) {
1976                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
1977                 return ret;
1978         }
1979
1980         return 0;
1981 }
1982
1983 static void
1984 ice_rss_ctx_init(struct ice_pf *pf)
1985 {
1986         memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
1987 }
1988
1989 static uint64_t
1990 ice_get_supported_rxdid(struct ice_hw *hw)
1991 {
1992         uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
1993         uint32_t regval;
1994         int i;
1995
1996         supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
1997
1998         for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
1999                 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
2000                 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
2001                         & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
2002                         supported_rxdid |= BIT(i);
2003         }
2004         return supported_rxdid;
2005 }
2006
2007 static int
2008 ice_dev_init(struct rte_eth_dev *dev)
2009 {
2010         struct rte_pci_device *pci_dev;
2011         struct rte_intr_handle *intr_handle;
2012         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2013         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2014         struct ice_adapter *ad =
2015                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2016         struct ice_vsi *vsi;
2017         int ret;
2018
2019         dev->dev_ops = &ice_eth_dev_ops;
2020         dev->rx_queue_count = ice_rx_queue_count;
2021         dev->rx_descriptor_status = ice_rx_descriptor_status;
2022         dev->tx_descriptor_status = ice_tx_descriptor_status;
2023         dev->rx_pkt_burst = ice_recv_pkts;
2024         dev->tx_pkt_burst = ice_xmit_pkts;
2025         dev->tx_pkt_prepare = ice_prep_pkts;
2026
2027         /* for secondary processes, we don't initialise any further as primary
2028          * has already done this work.
2029          */
2030         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2031                 ice_set_rx_function(dev);
2032                 ice_set_tx_function(dev);
2033                 return 0;
2034         }
2035
2036         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2037
2038         ice_set_default_ptype_table(dev);
2039         pci_dev = RTE_DEV_TO_PCI(dev->device);
2040         intr_handle = &pci_dev->intr_handle;
2041
2042         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2043         pf->adapter->eth_dev = dev;
2044         pf->dev_data = dev->data;
2045         hw->back = pf->adapter;
2046         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2047         hw->vendor_id = pci_dev->id.vendor_id;
2048         hw->device_id = pci_dev->id.device_id;
2049         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2050         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2051         hw->bus.device = pci_dev->addr.devid;
2052         hw->bus.func = pci_dev->addr.function;
2053
2054         ret = ice_parse_devargs(dev);
2055         if (ret) {
2056                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2057                 return -EINVAL;
2058         }
2059
2060         ice_init_controlq_parameter(hw);
2061
2062         ret = ice_init_hw(hw);
2063         if (ret) {
2064                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2065                 return -EINVAL;
2066         }
2067
2068         ret = ice_load_pkg(dev);
2069         if (ret) {
2070                 if (ad->devargs.safe_mode_support == 0) {
2071                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2072                                         "Use safe-mode-support=1 to enter Safe Mode");
2073                         return ret;
2074                 }
2075
2076                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2077                                         "Entering Safe Mode");
2078                 ad->is_safe_mode = 1;
2079         }
2080
2081         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2082                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2083                      hw->api_maj_ver, hw->api_min_ver);
2084
2085         ice_pf_sw_init(dev);
2086         ret = ice_init_mac_address(dev);
2087         if (ret) {
2088                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2089                 goto err_init_mac;
2090         }
2091
2092         ret = ice_res_pool_init(&pf->msix_pool, 1,
2093                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2094         if (ret) {
2095                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2096                 goto err_msix_pool_init;
2097         }
2098
2099         ret = ice_pf_setup(pf);
2100         if (ret) {
2101                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2102                 goto err_pf_setup;
2103         }
2104
2105         ret = ice_send_driver_ver(hw);
2106         if (ret) {
2107                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2108                 goto err_pf_setup;
2109         }
2110
2111         vsi = pf->main_vsi;
2112
2113         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2114         if (ret != ICE_SUCCESS)
2115                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2116         ret = ice_init_dcb(hw, true);
2117         if (ret != ICE_SUCCESS)
2118                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2119         /* Forward LLDP packets to default VSI */
2120         ret = ice_vsi_config_sw_lldp(vsi, true);
2121         if (ret != ICE_SUCCESS)
2122                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2123         /* register callback func to eal lib */
2124         rte_intr_callback_register(intr_handle,
2125                                    ice_interrupt_handler, dev);
2126
2127         ice_pf_enable_irq0(hw);
2128
2129         /* enable uio intr after callback register */
2130         rte_intr_enable(intr_handle);
2131
2132         /* get base queue pairs index  in the device */
2133         ice_base_queue_get(pf);
2134
2135         /* Initialize RSS context for gtpu_eh */
2136         ice_rss_ctx_init(pf);
2137
2138         if (!ad->is_safe_mode) {
2139                 ret = ice_flow_init(ad);
2140                 if (ret) {
2141                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2142                         return ret;
2143                 }
2144         }
2145
2146         ret = ice_reset_fxp_resource(hw);
2147         if (ret) {
2148                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2149                 return ret;
2150         }
2151
2152         pf->supported_rxdid = ice_get_supported_rxdid(hw);
2153
2154         return 0;
2155
2156 err_pf_setup:
2157         ice_res_pool_destroy(&pf->msix_pool);
2158 err_msix_pool_init:
2159         rte_free(dev->data->mac_addrs);
2160         dev->data->mac_addrs = NULL;
2161 err_init_mac:
2162         ice_sched_cleanup_all(hw);
2163         rte_free(hw->port_info);
2164         ice_shutdown_all_ctrlq(hw);
2165         rte_free(pf->proto_xtr);
2166
2167         return ret;
2168 }
2169
2170 int
2171 ice_release_vsi(struct ice_vsi *vsi)
2172 {
2173         struct ice_hw *hw;
2174         struct ice_vsi_ctx vsi_ctx;
2175         enum ice_status ret;
2176         int error = 0;
2177
2178         if (!vsi)
2179                 return error;
2180
2181         hw = ICE_VSI_TO_HW(vsi);
2182
2183         ice_remove_all_mac_vlan_filters(vsi);
2184
2185         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2186
2187         vsi_ctx.vsi_num = vsi->vsi_id;
2188         vsi_ctx.info = vsi->info;
2189         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2190         if (ret != ICE_SUCCESS) {
2191                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2192                 error = -1;
2193         }
2194
2195         rte_free(vsi->rss_lut);
2196         rte_free(vsi->rss_key);
2197         rte_free(vsi);
2198         return error;
2199 }
2200
2201 void
2202 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2203 {
2204         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2205         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2206         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2207         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2208         uint16_t msix_intr, i;
2209
2210         /* disable interrupt and also clear all the exist config */
2211         for (i = 0; i < vsi->nb_qps; i++) {
2212                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2213                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2214                 rte_wmb();
2215         }
2216
2217         if (rte_intr_allow_others(intr_handle))
2218                 /* vfio-pci */
2219                 for (i = 0; i < vsi->nb_msix; i++) {
2220                         msix_intr = vsi->msix_intr + i;
2221                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2222                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2223                 }
2224         else
2225                 /* igb_uio */
2226                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2227 }
2228
2229 static int
2230 ice_dev_stop(struct rte_eth_dev *dev)
2231 {
2232         struct rte_eth_dev_data *data = dev->data;
2233         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2234         struct ice_vsi *main_vsi = pf->main_vsi;
2235         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2236         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2237         uint16_t i;
2238
2239         /* avoid stopping again */
2240         if (pf->adapter_stopped)
2241                 return 0;
2242
2243         /* stop and clear all Rx queues */
2244         for (i = 0; i < data->nb_rx_queues; i++)
2245                 ice_rx_queue_stop(dev, i);
2246
2247         /* stop and clear all Tx queues */
2248         for (i = 0; i < data->nb_tx_queues; i++)
2249                 ice_tx_queue_stop(dev, i);
2250
2251         /* disable all queue interrupts */
2252         ice_vsi_disable_queues_intr(main_vsi);
2253
2254         if (pf->init_link_up)
2255                 ice_dev_set_link_up(dev);
2256         else
2257                 ice_dev_set_link_down(dev);
2258
2259         /* Clean datapath event and queue/vec mapping */
2260         rte_intr_efd_disable(intr_handle);
2261         if (intr_handle->intr_vec) {
2262                 rte_free(intr_handle->intr_vec);
2263                 intr_handle->intr_vec = NULL;
2264         }
2265
2266         pf->adapter_stopped = true;
2267         dev->data->dev_started = 0;
2268
2269         return 0;
2270 }
2271
2272 static int
2273 ice_dev_close(struct rte_eth_dev *dev)
2274 {
2275         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2276         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2277         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2278         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2279         struct ice_adapter *ad =
2280                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2281         int ret;
2282
2283         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2284                 return 0;
2285
2286         /* Since stop will make link down, then the link event will be
2287          * triggered, disable the irq firstly to avoid the port_infoe etc
2288          * resources deallocation causing the interrupt service thread
2289          * crash.
2290          */
2291         ice_pf_disable_irq0(hw);
2292
2293         ret = ice_dev_stop(dev);
2294
2295         if (!ad->is_safe_mode)
2296                 ice_flow_uninit(ad);
2297
2298         /* release all queue resource */
2299         ice_free_queues(dev);
2300
2301         ice_res_pool_destroy(&pf->msix_pool);
2302         ice_release_vsi(pf->main_vsi);
2303         ice_sched_cleanup_all(hw);
2304         ice_free_hw_tbls(hw);
2305         rte_free(hw->port_info);
2306         hw->port_info = NULL;
2307         ice_shutdown_all_ctrlq(hw);
2308         rte_free(pf->proto_xtr);
2309         pf->proto_xtr = NULL;
2310
2311         /* disable uio intr before callback unregister */
2312         rte_intr_disable(intr_handle);
2313
2314         /* unregister callback func from eal lib */
2315         rte_intr_callback_unregister(intr_handle,
2316                                      ice_interrupt_handler, dev);
2317
2318         return ret;
2319 }
2320
2321 static int
2322 ice_dev_uninit(struct rte_eth_dev *dev)
2323 {
2324         ice_dev_close(dev);
2325
2326         return 0;
2327 }
2328
2329 static bool
2330 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2331 {
2332         return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2333 }
2334
2335 static void
2336 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2337 {
2338         cfg->hash_flds = 0;
2339         cfg->addl_hdrs = 0;
2340         cfg->symm = 0;
2341         cfg->hdr_type = ICE_RSS_ANY_HEADERS;
2342 }
2343
2344 static int
2345 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2346 {
2347         enum ice_status status = ICE_SUCCESS;
2348         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2349         struct ice_vsi *vsi = pf->main_vsi;
2350
2351         if (!is_hash_cfg_valid(cfg))
2352                 return -ENOENT;
2353
2354         status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2355         if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2356                 PMD_DRV_LOG(ERR,
2357                             "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2358                             vsi->idx, status);
2359                 return -EBUSY;
2360         }
2361
2362         return 0;
2363 }
2364
2365 static int
2366 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2367 {
2368         enum ice_status status = ICE_SUCCESS;
2369         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2370         struct ice_vsi *vsi = pf->main_vsi;
2371
2372         if (!is_hash_cfg_valid(cfg))
2373                 return -ENOENT;
2374
2375         status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2376         if (status) {
2377                 PMD_DRV_LOG(ERR,
2378                             "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2379                             vsi->idx, status);
2380                 return -EBUSY;
2381         }
2382
2383         return 0;
2384 }
2385
2386 static int
2387 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2388 {
2389         int ret;
2390
2391         ret = ice_hash_moveout(pf, cfg);
2392         if (ret && (ret != -ENOENT))
2393                 return ret;
2394
2395         hash_cfg_reset(cfg);
2396
2397         return 0;
2398 }
2399
2400 static int
2401 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2402                          u8 ctx_idx)
2403 {
2404         int ret;
2405
2406         switch (ctx_idx) {
2407         case ICE_HASH_GTPU_CTX_EH_IP:
2408                 ret = ice_hash_remove(pf,
2409                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2410                 if (ret && (ret != -ENOENT))
2411                         return ret;
2412
2413                 ret = ice_hash_remove(pf,
2414                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2415                 if (ret && (ret != -ENOENT))
2416                         return ret;
2417
2418                 ret = ice_hash_remove(pf,
2419                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2420                 if (ret && (ret != -ENOENT))
2421                         return ret;
2422
2423                 ret = ice_hash_remove(pf,
2424                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2425                 if (ret && (ret != -ENOENT))
2426                         return ret;
2427
2428                 ret = ice_hash_remove(pf,
2429                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2430                 if (ret && (ret != -ENOENT))
2431                         return ret;
2432
2433                 ret = ice_hash_remove(pf,
2434                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2435                 if (ret && (ret != -ENOENT))
2436                         return ret;
2437
2438                 ret = ice_hash_remove(pf,
2439                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2440                 if (ret && (ret != -ENOENT))
2441                         return ret;
2442
2443                 ret = ice_hash_remove(pf,
2444                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2445                 if (ret && (ret != -ENOENT))
2446                         return ret;
2447
2448                 break;
2449         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2450                 ret = ice_hash_remove(pf,
2451                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2452                 if (ret && (ret != -ENOENT))
2453                         return ret;
2454
2455                 ret = ice_hash_remove(pf,
2456                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2457                 if (ret && (ret != -ENOENT))
2458                         return ret;
2459
2460                 ret = ice_hash_moveout(pf,
2461                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2462                 if (ret && (ret != -ENOENT))
2463                         return ret;
2464
2465                 ret = ice_hash_moveout(pf,
2466                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2467                 if (ret && (ret != -ENOENT))
2468                         return ret;
2469
2470                 ret = ice_hash_moveout(pf,
2471                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2472                 if (ret && (ret != -ENOENT))
2473                         return ret;
2474
2475                 ret = ice_hash_moveout(pf,
2476                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2477                 if (ret && (ret != -ENOENT))
2478                         return ret;
2479
2480                 break;
2481         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2482                 ret = ice_hash_remove(pf,
2483                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2484                 if (ret && (ret != -ENOENT))
2485                         return ret;
2486
2487                 ret = ice_hash_remove(pf,
2488                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2489                 if (ret && (ret != -ENOENT))
2490                         return ret;
2491
2492                 ret = ice_hash_moveout(pf,
2493                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2494                 if (ret && (ret != -ENOENT))
2495                         return ret;
2496
2497                 ret = ice_hash_moveout(pf,
2498                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2499                 if (ret && (ret != -ENOENT))
2500                         return ret;
2501
2502                 ret = ice_hash_moveout(pf,
2503                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2504                 if (ret && (ret != -ENOENT))
2505                         return ret;
2506
2507                 ret = ice_hash_moveout(pf,
2508                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2509                 if (ret && (ret != -ENOENT))
2510                         return ret;
2511
2512                 break;
2513         case ICE_HASH_GTPU_CTX_UP_IP:
2514                 ret = ice_hash_remove(pf,
2515                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2516                 if (ret && (ret != -ENOENT))
2517                         return ret;
2518
2519                 ret = ice_hash_remove(pf,
2520                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2521                 if (ret && (ret != -ENOENT))
2522                         return ret;
2523
2524                 ret = ice_hash_moveout(pf,
2525                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2526                 if (ret && (ret != -ENOENT))
2527                         return ret;
2528
2529                 ret = ice_hash_moveout(pf,
2530                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2531                 if (ret && (ret != -ENOENT))
2532                         return ret;
2533
2534                 ret = ice_hash_moveout(pf,
2535                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2536                 if (ret && (ret != -ENOENT))
2537                         return ret;
2538
2539                 break;
2540         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2541         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2542                 ret = ice_hash_moveout(pf,
2543                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2544                 if (ret && (ret != -ENOENT))
2545                         return ret;
2546
2547                 ret = ice_hash_moveout(pf,
2548                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2549                 if (ret && (ret != -ENOENT))
2550                         return ret;
2551
2552                 ret = ice_hash_moveout(pf,
2553                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2554                 if (ret && (ret != -ENOENT))
2555                         return ret;
2556
2557                 break;
2558         case ICE_HASH_GTPU_CTX_DW_IP:
2559                 ret = ice_hash_remove(pf,
2560                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2561                 if (ret && (ret != -ENOENT))
2562                         return ret;
2563
2564                 ret = ice_hash_remove(pf,
2565                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2566                 if (ret && (ret != -ENOENT))
2567                         return ret;
2568
2569                 ret = ice_hash_moveout(pf,
2570                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2571                 if (ret && (ret != -ENOENT))
2572                         return ret;
2573
2574                 ret = ice_hash_moveout(pf,
2575                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2576                 if (ret && (ret != -ENOENT))
2577                         return ret;
2578
2579                 ret = ice_hash_moveout(pf,
2580                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2581                 if (ret && (ret != -ENOENT))
2582                         return ret;
2583
2584                 break;
2585         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2586         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2587                 ret = ice_hash_moveout(pf,
2588                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2589                 if (ret && (ret != -ENOENT))
2590                         return ret;
2591
2592                 ret = ice_hash_moveout(pf,
2593                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2594                 if (ret && (ret != -ENOENT))
2595                         return ret;
2596
2597                 ret = ice_hash_moveout(pf,
2598                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2599                 if (ret && (ret != -ENOENT))
2600                         return ret;
2601
2602                 break;
2603         default:
2604                 break;
2605         }
2606
2607         return 0;
2608 }
2609
2610 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2611 {
2612         u8 eh_idx, ip_idx;
2613
2614         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2615                 eh_idx = 0;
2616         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2617                 eh_idx = 1;
2618         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2619                 eh_idx = 2;
2620         else
2621                 return ICE_HASH_GTPU_CTX_MAX;
2622
2623         ip_idx = 0;
2624         if (hdr & ICE_FLOW_SEG_HDR_UDP)
2625                 ip_idx = 1;
2626         else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2627                 ip_idx = 2;
2628
2629         if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2630                 return eh_idx * 3 + ip_idx;
2631         else
2632                 return ICE_HASH_GTPU_CTX_MAX;
2633 }
2634
2635 static int
2636 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2637 {
2638         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2639
2640         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2641                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2642                                                 gtpu_ctx_idx);
2643         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2644                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2645                                                 gtpu_ctx_idx);
2646
2647         return 0;
2648 }
2649
2650 static int
2651 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2652                           u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2653 {
2654         int ret;
2655
2656         if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2657                 ctx->ctx[ctx_idx] = *cfg;
2658
2659         switch (ctx_idx) {
2660         case ICE_HASH_GTPU_CTX_EH_IP:
2661                 break;
2662         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2663                 ret = ice_hash_moveback(pf,
2664                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2665                 if (ret && (ret != -ENOENT))
2666                         return ret;
2667
2668                 ret = ice_hash_moveback(pf,
2669                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2670                 if (ret && (ret != -ENOENT))
2671                         return ret;
2672
2673                 ret = ice_hash_moveback(pf,
2674                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2675                 if (ret && (ret != -ENOENT))
2676                         return ret;
2677
2678                 ret = ice_hash_moveback(pf,
2679                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2680                 if (ret && (ret != -ENOENT))
2681                         return ret;
2682
2683                 break;
2684         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2685                 ret = ice_hash_moveback(pf,
2686                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2687                 if (ret && (ret != -ENOENT))
2688                         return ret;
2689
2690                 ret = ice_hash_moveback(pf,
2691                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2692                 if (ret && (ret != -ENOENT))
2693                         return ret;
2694
2695                 ret = ice_hash_moveback(pf,
2696                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2697                 if (ret && (ret != -ENOENT))
2698                         return ret;
2699
2700                 ret = ice_hash_moveback(pf,
2701                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2702                 if (ret && (ret != -ENOENT))
2703                         return ret;
2704
2705                 break;
2706         case ICE_HASH_GTPU_CTX_UP_IP:
2707         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2708         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2709         case ICE_HASH_GTPU_CTX_DW_IP:
2710         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2711         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2712                 ret = ice_hash_moveback(pf,
2713                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2714                 if (ret && (ret != -ENOENT))
2715                         return ret;
2716
2717                 ret = ice_hash_moveback(pf,
2718                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2719                 if (ret && (ret != -ENOENT))
2720                         return ret;
2721
2722                 ret = ice_hash_moveback(pf,
2723                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2724                 if (ret && (ret != -ENOENT))
2725                         return ret;
2726
2727                 break;
2728         default:
2729                 break;
2730         }
2731
2732         return 0;
2733 }
2734
2735 static int
2736 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2737 {
2738         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2739
2740         if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2741                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2742                                                  gtpu_ctx_idx, cfg);
2743         else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2744                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2745                                                  gtpu_ctx_idx, cfg);
2746
2747         return 0;
2748 }
2749
2750 static void
2751 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2752 {
2753         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2754
2755         if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2756                 return;
2757
2758         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2759                 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2760         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2761                 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2762 }
2763
2764 int
2765 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2766                      struct ice_rss_hash_cfg *cfg)
2767 {
2768         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2769         int ret;
2770
2771         ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2772         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2773                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2774
2775         ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2776
2777         return 0;
2778 }
2779
2780 int
2781 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2782                      struct ice_rss_hash_cfg *cfg)
2783 {
2784         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2785         int ret;
2786
2787         ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2788         if (ret)
2789                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2790
2791         ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2792         if (ret)
2793                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2794
2795         ret = ice_add_rss_cfg_post(pf, cfg);
2796         if (ret)
2797                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2798
2799         return 0;
2800 }
2801
2802 static void
2803 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2804 {
2805         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2806         struct ice_vsi *vsi = pf->main_vsi;
2807         struct ice_rss_hash_cfg cfg;
2808         int ret;
2809
2810 #define ICE_RSS_HF_ALL ( \
2811         ETH_RSS_IPV4 | \
2812         ETH_RSS_IPV6 | \
2813         ETH_RSS_NONFRAG_IPV4_UDP | \
2814         ETH_RSS_NONFRAG_IPV6_UDP | \
2815         ETH_RSS_NONFRAG_IPV4_TCP | \
2816         ETH_RSS_NONFRAG_IPV6_TCP | \
2817         ETH_RSS_NONFRAG_IPV4_SCTP | \
2818         ETH_RSS_NONFRAG_IPV6_SCTP)
2819
2820         ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2821         if (ret)
2822                 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2823                             __func__, ret);
2824
2825         cfg.symm = 0;
2826         cfg.hdr_type = ICE_RSS_ANY_HEADERS;
2827         /* Configure RSS for IPv4 with src/dst addr as input set */
2828         if (rss_hf & ETH_RSS_IPV4) {
2829                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2830                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2831                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2832                 if (ret)
2833                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2834                                     __func__, ret);
2835         }
2836
2837         /* Configure RSS for IPv6 with src/dst addr as input set */
2838         if (rss_hf & ETH_RSS_IPV6) {
2839                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2840                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2841                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2842                 if (ret)
2843                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2844                                     __func__, ret);
2845         }
2846
2847         /* Configure RSS for udp4 with src/dst addr and port as input set */
2848         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2849                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2850                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2851                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2852                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2853                 if (ret)
2854                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2855                                     __func__, ret);
2856         }
2857
2858         /* Configure RSS for udp6 with src/dst addr and port as input set */
2859         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2860                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2861                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2862                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2863                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2864                 if (ret)
2865                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2866                                     __func__, ret);
2867         }
2868
2869         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2870         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2871                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2872                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2873                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2874                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2875                 if (ret)
2876                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2877                                     __func__, ret);
2878         }
2879
2880         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2881         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2882                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2883                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2884                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2885                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2886                 if (ret)
2887                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2888                                     __func__, ret);
2889         }
2890
2891         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2892         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2893                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
2894                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2895                 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
2896                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2897                 if (ret)
2898                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2899                                     __func__, ret);
2900         }
2901
2902         /* Configure RSS for sctp6 with src/dst addr and port as input set */
2903         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2904                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
2905                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2906                 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
2907                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2908                 if (ret)
2909                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2910                                     __func__, ret);
2911         }
2912
2913         if (rss_hf & ETH_RSS_IPV4) {
2914                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV4 |
2915                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2916                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2917                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2918                 if (ret)
2919                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4 rss flow fail %d",
2920                                     __func__, ret);
2921
2922                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV4 |
2923                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2924                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2925                 if (ret)
2926                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4 rss flow fail %d",
2927                                     __func__, ret);
2928
2929                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
2930                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2931                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2932                 if (ret)
2933                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2934                                     __func__, ret);
2935         }
2936
2937         if (rss_hf & ETH_RSS_IPV6) {
2938                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_IPV6 |
2939                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2940                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2941                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2942                 if (ret)
2943                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6 rss flow fail %d",
2944                                     __func__, ret);
2945
2946                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_IPV6 |
2947                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2948                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2949                 if (ret)
2950                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6 rss flow fail %d",
2951                                     __func__, ret);
2952
2953                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
2954                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2955                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2956                 if (ret)
2957                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2958                                     __func__, ret);
2959         }
2960
2961         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2962                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2963                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2964                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2965                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2966                 if (ret)
2967                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_UDP rss flow fail %d",
2968                                     __func__, ret);
2969
2970                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
2971                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2972                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2973                 if (ret)
2974                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_UDP rss flow fail %d",
2975                                     __func__, ret);
2976
2977                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2978                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2979                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2980                 if (ret)
2981                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2982                                     __func__, ret);
2983         }
2984
2985         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2986                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_UDP |
2987                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2988                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2989                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2990                 if (ret)
2991                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_UDP rss flow fail %d",
2992                                     __func__, ret);
2993
2994                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_UDP |
2995                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2996                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2997                 if (ret)
2998                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_UDP rss flow fail %d",
2999                                     __func__, ret);
3000
3001                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
3002                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3003                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3004                 if (ret)
3005                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
3006                                     __func__, ret);
3007         }
3008
3009         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
3010                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3011                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3012                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
3013                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3014                 if (ret)
3015                         PMD_DRV_LOG(ERR, "%s GTPU_IPV4_TCP rss flow fail %d",
3016                                     __func__, ret);
3017
3018                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3019                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3020                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3021                 if (ret)
3022                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV4_TCP rss flow fail %d",
3023                                     __func__, ret);
3024
3025                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3026                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3027                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3028                 if (ret)
3029                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
3030                                     __func__, ret);
3031         }
3032
3033         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
3034                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_IP | ICE_FLOW_SEG_HDR_TCP |
3035                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3036                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
3037                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3038                 if (ret)
3039                         PMD_DRV_LOG(ERR, "%s GTPU_IPV6_TCP rss flow fail %d",
3040                                     __func__, ret);
3041
3042                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_GTPU_EH | ICE_FLOW_SEG_HDR_TCP |
3043                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3044                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3045                 if (ret)
3046                         PMD_DRV_LOG(ERR, "%s GTPU_EH_IPV6_TCP rss flow fail %d",
3047                                     __func__, ret);
3048
3049                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
3050                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
3051                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
3052                 if (ret)
3053                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
3054                                     __func__, ret);
3055         }
3056
3057         pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3058 }
3059
3060 static int ice_init_rss(struct ice_pf *pf)
3061 {
3062         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3063         struct ice_vsi *vsi = pf->main_vsi;
3064         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3065         struct ice_aq_get_set_rss_lut_params lut_params;
3066         struct rte_eth_rss_conf *rss_conf;
3067         struct ice_aqc_get_set_rss_keys key;
3068         uint16_t i, nb_q;
3069         int ret = 0;
3070         bool is_safe_mode = pf->adapter->is_safe_mode;
3071         uint32_t reg;
3072
3073         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
3074         nb_q = dev->data->nb_rx_queues;
3075         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3076         vsi->rss_lut_size = pf->hash_lut_size;
3077
3078         if (nb_q == 0) {
3079                 PMD_DRV_LOG(WARNING,
3080                         "RSS is not supported as rx queues number is zero\n");
3081                 return 0;
3082         }
3083
3084         if (is_safe_mode) {
3085                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3086                 return 0;
3087         }
3088
3089         if (!vsi->rss_key) {
3090                 vsi->rss_key = rte_zmalloc(NULL,
3091                                            vsi->rss_key_size, 0);
3092                 if (vsi->rss_key == NULL) {
3093                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3094                         return -ENOMEM;
3095                 }
3096         }
3097         if (!vsi->rss_lut) {
3098                 vsi->rss_lut = rte_zmalloc(NULL,
3099                                            vsi->rss_lut_size, 0);
3100                 if (vsi->rss_lut == NULL) {
3101                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3102                         rte_free(vsi->rss_key);
3103                         vsi->rss_key = NULL;
3104                         return -ENOMEM;
3105                 }
3106         }
3107         /* configure RSS key */
3108         if (!rss_conf->rss_key) {
3109                 /* Calculate the default hash key */
3110                 for (i = 0; i <= vsi->rss_key_size; i++)
3111                         vsi->rss_key[i] = (uint8_t)rte_rand();
3112         } else {
3113                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3114                            RTE_MIN(rss_conf->rss_key_len,
3115                                    vsi->rss_key_size));
3116         }
3117         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3118         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3119         if (ret)
3120                 goto out;
3121
3122         /* init RSS LUT table */
3123         for (i = 0; i < vsi->rss_lut_size; i++)
3124                 vsi->rss_lut[i] = i % nb_q;
3125
3126         lut_params.vsi_handle = vsi->idx;
3127         lut_params.lut_size = vsi->rss_lut_size;
3128         lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3129         lut_params.lut = vsi->rss_lut;
3130         lut_params.global_lut_id = 0;
3131         ret = ice_aq_set_rss_lut(hw, &lut_params);
3132         if (ret)
3133                 goto out;
3134
3135         /* Enable registers for symmetric_toeplitz function. */
3136         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3137         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3138                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3139         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3140
3141         /* RSS hash configuration */
3142         ice_rss_hash_set(pf, rss_conf->rss_hf);
3143
3144         return 0;
3145 out:
3146         rte_free(vsi->rss_key);
3147         vsi->rss_key = NULL;
3148         rte_free(vsi->rss_lut);
3149         vsi->rss_lut = NULL;
3150         return -EINVAL;
3151 }
3152
3153 static int
3154 ice_dev_configure(struct rte_eth_dev *dev)
3155 {
3156         struct ice_adapter *ad =
3157                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3158         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3159         int ret;
3160
3161         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3162          * bulk allocation or vector Rx preconditions we will reset it.
3163          */
3164         ad->rx_bulk_alloc_allowed = true;
3165         ad->tx_simple_allowed = true;
3166
3167         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3168                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3169
3170         if (dev->data->nb_rx_queues) {
3171                 ret = ice_init_rss(pf);
3172                 if (ret) {
3173                         PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3174                         return ret;
3175                 }
3176         }
3177
3178         return 0;
3179 }
3180
3181 static void
3182 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3183                        int base_queue, int nb_queue)
3184 {
3185         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3186         uint32_t val, val_tx;
3187         int i;
3188
3189         for (i = 0; i < nb_queue; i++) {
3190                 /*do actual bind*/
3191                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3192                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3193                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3194                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3195
3196                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3197                             base_queue + i, msix_vect);
3198                 /* set ITR0 value */
3199                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3200                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3201                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3202         }
3203 }
3204
3205 void
3206 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3207 {
3208         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3209         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3210         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3211         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3212         uint16_t msix_vect = vsi->msix_intr;
3213         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3214         uint16_t queue_idx = 0;
3215         int record = 0;
3216         int i;
3217
3218         /* clear Rx/Tx queue interrupt */
3219         for (i = 0; i < vsi->nb_used_qps; i++) {
3220                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3221                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3222         }
3223
3224         /* PF bind interrupt */
3225         if (rte_intr_dp_is_en(intr_handle)) {
3226                 queue_idx = 0;
3227                 record = 1;
3228         }
3229
3230         for (i = 0; i < vsi->nb_used_qps; i++) {
3231                 if (nb_msix <= 1) {
3232                         if (!rte_intr_allow_others(intr_handle))
3233                                 msix_vect = ICE_MISC_VEC_ID;
3234
3235                         /* uio mapping all queue to one msix_vect */
3236                         __vsi_queues_bind_intr(vsi, msix_vect,
3237                                                vsi->base_queue + i,
3238                                                vsi->nb_used_qps - i);
3239
3240                         for (; !!record && i < vsi->nb_used_qps; i++)
3241                                 intr_handle->intr_vec[queue_idx + i] =
3242                                         msix_vect;
3243                         break;
3244                 }
3245
3246                 /* vfio 1:1 queue/msix_vect mapping */
3247                 __vsi_queues_bind_intr(vsi, msix_vect,
3248                                        vsi->base_queue + i, 1);
3249
3250                 if (!!record)
3251                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3252
3253                 msix_vect++;
3254                 nb_msix--;
3255         }
3256 }
3257
3258 void
3259 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3260 {
3261         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
3262         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3263         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3264         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3265         uint16_t msix_intr, i;
3266
3267         if (rte_intr_allow_others(intr_handle))
3268                 for (i = 0; i < vsi->nb_used_qps; i++) {
3269                         msix_intr = vsi->msix_intr + i;
3270                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3271                                       GLINT_DYN_CTL_INTENA_M |
3272                                       GLINT_DYN_CTL_CLEARPBA_M |
3273                                       GLINT_DYN_CTL_ITR_INDX_M |
3274                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3275                 }
3276         else
3277                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3278                               GLINT_DYN_CTL_INTENA_M |
3279                               GLINT_DYN_CTL_CLEARPBA_M |
3280                               GLINT_DYN_CTL_ITR_INDX_M |
3281                               GLINT_DYN_CTL_WB_ON_ITR_M);
3282 }
3283
3284 static int
3285 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3286 {
3287         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3288         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3289         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3290         struct ice_vsi *vsi = pf->main_vsi;
3291         uint32_t intr_vector = 0;
3292
3293         rte_intr_disable(intr_handle);
3294
3295         /* check and configure queue intr-vector mapping */
3296         if ((rte_intr_cap_multiple(intr_handle) ||
3297              !RTE_ETH_DEV_SRIOV(dev).active) &&
3298             dev->data->dev_conf.intr_conf.rxq != 0) {
3299                 intr_vector = dev->data->nb_rx_queues;
3300                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3301                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3302                                     ICE_MAX_INTR_QUEUE_NUM);
3303                         return -ENOTSUP;
3304                 }
3305                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3306                         return -1;
3307         }
3308
3309         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3310                 intr_handle->intr_vec =
3311                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3312                             0);
3313                 if (!intr_handle->intr_vec) {
3314                         PMD_DRV_LOG(ERR,
3315                                     "Failed to allocate %d rx_queues intr_vec",
3316                                     dev->data->nb_rx_queues);
3317                         return -ENOMEM;
3318                 }
3319         }
3320
3321         /* Map queues with MSIX interrupt */
3322         vsi->nb_used_qps = dev->data->nb_rx_queues;
3323         ice_vsi_queues_bind_intr(vsi);
3324
3325         /* Enable interrupts for all the queues */
3326         ice_vsi_enable_queues_intr(vsi);
3327
3328         rte_intr_enable(intr_handle);
3329
3330         return 0;
3331 }
3332
3333 static void
3334 ice_get_init_link_status(struct rte_eth_dev *dev)
3335 {
3336         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3337         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3338         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3339         struct ice_link_status link_status;
3340         int ret;
3341
3342         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3343                                    &link_status, NULL);
3344         if (ret != ICE_SUCCESS) {
3345                 PMD_DRV_LOG(ERR, "Failed to get link info");
3346                 pf->init_link_up = false;
3347                 return;
3348         }
3349
3350         if (link_status.link_info & ICE_AQ_LINK_UP)
3351                 pf->init_link_up = true;
3352 }
3353
3354 static int
3355 ice_dev_start(struct rte_eth_dev *dev)
3356 {
3357         struct rte_eth_dev_data *data = dev->data;
3358         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3359         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3360         struct ice_vsi *vsi = pf->main_vsi;
3361         uint16_t nb_rxq = 0;
3362         uint16_t nb_txq, i;
3363         uint16_t max_frame_size;
3364         int mask, ret;
3365
3366         /* program Tx queues' context in hardware */
3367         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3368                 ret = ice_tx_queue_start(dev, nb_txq);
3369                 if (ret) {
3370                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3371                         goto tx_err;
3372                 }
3373         }
3374
3375         /* program Rx queues' context in hardware*/
3376         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3377                 ret = ice_rx_queue_start(dev, nb_rxq);
3378                 if (ret) {
3379                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3380                         goto rx_err;
3381                 }
3382         }
3383
3384         ice_set_rx_function(dev);
3385         ice_set_tx_function(dev);
3386
3387         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3388                         ETH_VLAN_EXTEND_MASK;
3389         ret = ice_vlan_offload_set(dev, mask);
3390         if (ret) {
3391                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3392                 goto rx_err;
3393         }
3394
3395         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3396         if (ice_rxq_intr_setup(dev))
3397                 return -EIO;
3398
3399         /* Enable receiving broadcast packets and transmitting packets */
3400         ret = ice_set_vsi_promisc(hw, vsi->idx,
3401                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3402                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3403                                   0);
3404         if (ret != ICE_SUCCESS)
3405                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3406
3407         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3408                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3409                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3410                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3411                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3412                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3413                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3414                                      NULL);
3415         if (ret != ICE_SUCCESS)
3416                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3417
3418         ice_get_init_link_status(dev);
3419
3420         ice_dev_set_link_up(dev);
3421
3422         /* Call get_link_info aq commond to enable/disable LSE */
3423         ice_link_update(dev, 0);
3424
3425         pf->adapter_stopped = false;
3426
3427         /* Set the max frame size to default value*/
3428         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3429                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3430                 ICE_FRAME_SIZE_MAX;
3431
3432         /* Set the max frame size to HW*/
3433         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3434
3435         return 0;
3436
3437         /* stop the started queues if failed to start all queues */
3438 rx_err:
3439         for (i = 0; i < nb_rxq; i++)
3440                 ice_rx_queue_stop(dev, i);
3441 tx_err:
3442         for (i = 0; i < nb_txq; i++)
3443                 ice_tx_queue_stop(dev, i);
3444
3445         return -EIO;
3446 }
3447
3448 static int
3449 ice_dev_reset(struct rte_eth_dev *dev)
3450 {
3451         int ret;
3452
3453         if (dev->data->sriov.active)
3454                 return -ENOTSUP;
3455
3456         ret = ice_dev_uninit(dev);
3457         if (ret) {
3458                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3459                 return -ENXIO;
3460         }
3461
3462         ret = ice_dev_init(dev);
3463         if (ret) {
3464                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3465                 return -ENXIO;
3466         }
3467
3468         return 0;
3469 }
3470
3471 static int
3472 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3473 {
3474         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3475         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3476         struct ice_vsi *vsi = pf->main_vsi;
3477         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3478         bool is_safe_mode = pf->adapter->is_safe_mode;
3479         u64 phy_type_low;
3480         u64 phy_type_high;
3481
3482         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3483         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3484         dev_info->max_rx_queues = vsi->nb_qps;
3485         dev_info->max_tx_queues = vsi->nb_qps;
3486         dev_info->max_mac_addrs = vsi->max_macaddrs;
3487         dev_info->max_vfs = pci_dev->max_vfs;
3488         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3489         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3490
3491         dev_info->rx_offload_capa =
3492                 DEV_RX_OFFLOAD_VLAN_STRIP |
3493                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3494                 DEV_RX_OFFLOAD_KEEP_CRC |
3495                 DEV_RX_OFFLOAD_SCATTER |
3496                 DEV_RX_OFFLOAD_VLAN_FILTER;
3497         dev_info->tx_offload_capa =
3498                 DEV_TX_OFFLOAD_VLAN_INSERT |
3499                 DEV_TX_OFFLOAD_TCP_TSO |
3500                 DEV_TX_OFFLOAD_MULTI_SEGS |
3501                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3502         dev_info->flow_type_rss_offloads = 0;
3503
3504         if (!is_safe_mode) {
3505                 dev_info->rx_offload_capa |=
3506                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3507                         DEV_RX_OFFLOAD_UDP_CKSUM |
3508                         DEV_RX_OFFLOAD_TCP_CKSUM |
3509                         DEV_RX_OFFLOAD_QINQ_STRIP |
3510                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3511                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3512                         DEV_RX_OFFLOAD_RSS_HASH;
3513                 dev_info->tx_offload_capa |=
3514                         DEV_TX_OFFLOAD_QINQ_INSERT |
3515                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3516                         DEV_TX_OFFLOAD_UDP_CKSUM |
3517                         DEV_TX_OFFLOAD_TCP_CKSUM |
3518                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3519                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3520                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3521                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3522         }
3523
3524         dev_info->rx_queue_offload_capa = 0;
3525         dev_info->tx_queue_offload_capa = 0;
3526
3527         dev_info->reta_size = pf->hash_lut_size;
3528         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3529
3530         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3531                 .rx_thresh = {
3532                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3533                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3534                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3535                 },
3536                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3537                 .rx_drop_en = 0,
3538                 .offloads = 0,
3539         };
3540
3541         dev_info->default_txconf = (struct rte_eth_txconf) {
3542                 .tx_thresh = {
3543                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3544                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3545                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3546                 },
3547                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3548                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3549                 .offloads = 0,
3550         };
3551
3552         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3553                 .nb_max = ICE_MAX_RING_DESC,
3554                 .nb_min = ICE_MIN_RING_DESC,
3555                 .nb_align = ICE_ALIGN_RING_DESC,
3556         };
3557
3558         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3559                 .nb_max = ICE_MAX_RING_DESC,
3560                 .nb_min = ICE_MIN_RING_DESC,
3561                 .nb_align = ICE_ALIGN_RING_DESC,
3562         };
3563
3564         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3565                                ETH_LINK_SPEED_100M |
3566                                ETH_LINK_SPEED_1G |
3567                                ETH_LINK_SPEED_2_5G |
3568                                ETH_LINK_SPEED_5G |
3569                                ETH_LINK_SPEED_10G |
3570                                ETH_LINK_SPEED_20G |
3571                                ETH_LINK_SPEED_25G;
3572
3573         phy_type_low = hw->port_info->phy.phy_type_low;
3574         phy_type_high = hw->port_info->phy.phy_type_high;
3575
3576         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3577                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3578
3579         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3580                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3581                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3582
3583         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3584         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3585
3586         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3587         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3588         dev_info->default_rxportconf.nb_queues = 1;
3589         dev_info->default_txportconf.nb_queues = 1;
3590         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3591         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3592
3593         return 0;
3594 }
3595
3596 static inline int
3597 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3598                             struct rte_eth_link *link)
3599 {
3600         struct rte_eth_link *dst = link;
3601         struct rte_eth_link *src = &dev->data->dev_link;
3602
3603         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3604                                 *(uint64_t *)src) == 0)
3605                 return -1;
3606
3607         return 0;
3608 }
3609
3610 static inline int
3611 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3612                              struct rte_eth_link *link)
3613 {
3614         struct rte_eth_link *dst = &dev->data->dev_link;
3615         struct rte_eth_link *src = link;
3616
3617         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3618                                 *(uint64_t *)src) == 0)
3619                 return -1;
3620
3621         return 0;
3622 }
3623
3624 static int
3625 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3626 {
3627 #define CHECK_INTERVAL 100  /* 100ms */
3628 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3629         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3630         struct ice_link_status link_status;
3631         struct rte_eth_link link, old;
3632         int status;
3633         unsigned int rep_cnt = MAX_REPEAT_TIME;
3634         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3635
3636         memset(&link, 0, sizeof(link));
3637         memset(&old, 0, sizeof(old));
3638         memset(&link_status, 0, sizeof(link_status));
3639         ice_atomic_read_link_status(dev, &old);
3640
3641         do {
3642                 /* Get link status information from hardware */
3643                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3644                                               &link_status, NULL);
3645                 if (status != ICE_SUCCESS) {
3646                         link.link_speed = ETH_SPEED_NUM_100M;
3647                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3648                         PMD_DRV_LOG(ERR, "Failed to get link info");
3649                         goto out;
3650                 }
3651
3652                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3653                 if (!wait_to_complete || link.link_status)
3654                         break;
3655
3656                 rte_delay_ms(CHECK_INTERVAL);
3657         } while (--rep_cnt);
3658
3659         if (!link.link_status)
3660                 goto out;
3661
3662         /* Full-duplex operation at all supported speeds */
3663         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3664
3665         /* Parse the link status */
3666         switch (link_status.link_speed) {
3667         case ICE_AQ_LINK_SPEED_10MB:
3668                 link.link_speed = ETH_SPEED_NUM_10M;
3669                 break;
3670         case ICE_AQ_LINK_SPEED_100MB:
3671                 link.link_speed = ETH_SPEED_NUM_100M;
3672                 break;
3673         case ICE_AQ_LINK_SPEED_1000MB:
3674                 link.link_speed = ETH_SPEED_NUM_1G;
3675                 break;
3676         case ICE_AQ_LINK_SPEED_2500MB:
3677                 link.link_speed = ETH_SPEED_NUM_2_5G;
3678                 break;
3679         case ICE_AQ_LINK_SPEED_5GB:
3680                 link.link_speed = ETH_SPEED_NUM_5G;
3681                 break;
3682         case ICE_AQ_LINK_SPEED_10GB:
3683                 link.link_speed = ETH_SPEED_NUM_10G;
3684                 break;
3685         case ICE_AQ_LINK_SPEED_20GB:
3686                 link.link_speed = ETH_SPEED_NUM_20G;
3687                 break;
3688         case ICE_AQ_LINK_SPEED_25GB:
3689                 link.link_speed = ETH_SPEED_NUM_25G;
3690                 break;
3691         case ICE_AQ_LINK_SPEED_40GB:
3692                 link.link_speed = ETH_SPEED_NUM_40G;
3693                 break;
3694         case ICE_AQ_LINK_SPEED_50GB:
3695                 link.link_speed = ETH_SPEED_NUM_50G;
3696                 break;
3697         case ICE_AQ_LINK_SPEED_100GB:
3698                 link.link_speed = ETH_SPEED_NUM_100G;
3699                 break;
3700         case ICE_AQ_LINK_SPEED_UNKNOWN:
3701                 PMD_DRV_LOG(ERR, "Unknown link speed");
3702                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3703                 break;
3704         default:
3705                 PMD_DRV_LOG(ERR, "None link speed");
3706                 link.link_speed = ETH_SPEED_NUM_NONE;
3707                 break;
3708         }
3709
3710         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3711                               ETH_LINK_SPEED_FIXED);
3712
3713 out:
3714         ice_atomic_write_link_status(dev, &link);
3715         if (link.link_status == old.link_status)
3716                 return -1;
3717
3718         return 0;
3719 }
3720
3721 /* Force the physical link state by getting the current PHY capabilities from
3722  * hardware and setting the PHY config based on the determined capabilities. If
3723  * link changes, link event will be triggered because both the Enable Automatic
3724  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3725  */
3726 static enum ice_status
3727 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3728 {
3729         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3730         struct ice_aqc_get_phy_caps_data *pcaps;
3731         struct ice_port_info *pi;
3732         enum ice_status status;
3733
3734         if (!hw || !hw->port_info)
3735                 return ICE_ERR_PARAM;
3736
3737         pi = hw->port_info;
3738
3739         pcaps = (struct ice_aqc_get_phy_caps_data *)
3740                 ice_malloc(hw, sizeof(*pcaps));
3741         if (!pcaps)
3742                 return ICE_ERR_NO_MEMORY;
3743
3744         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3745                                      pcaps, NULL);
3746         if (status)
3747                 goto out;
3748
3749         /* No change in link */
3750         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3751             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3752                 goto out;
3753
3754         cfg.phy_type_low = pcaps->phy_type_low;
3755         cfg.phy_type_high = pcaps->phy_type_high;
3756         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3757         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3758         cfg.eee_cap = pcaps->eee_cap;
3759         cfg.eeer_value = pcaps->eeer_value;
3760         cfg.link_fec_opt = pcaps->link_fec_options;
3761         if (link_up)
3762                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3763         else
3764                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3765
3766         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3767
3768 out:
3769         ice_free(hw, pcaps);
3770         return status;
3771 }
3772
3773 static int
3774 ice_dev_set_link_up(struct rte_eth_dev *dev)
3775 {
3776         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3777
3778         return ice_force_phys_link_state(hw, true);
3779 }
3780
3781 static int
3782 ice_dev_set_link_down(struct rte_eth_dev *dev)
3783 {
3784         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3785
3786         return ice_force_phys_link_state(hw, false);
3787 }
3788
3789 static int
3790 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3791 {
3792         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3793         struct rte_eth_dev_data *dev_data = pf->dev_data;
3794         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3795
3796         /* check if mtu is within the allowed range */
3797         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3798                 return -EINVAL;
3799
3800         /* mtu setting is forbidden if port is start */
3801         if (dev_data->dev_started) {
3802                 PMD_DRV_LOG(ERR,
3803                             "port %d must be stopped before configuration",
3804                             dev_data->port_id);
3805                 return -EBUSY;
3806         }
3807
3808         if (frame_size > ICE_ETH_MAX_LEN)
3809                 dev_data->dev_conf.rxmode.offloads |=
3810                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3811         else
3812                 dev_data->dev_conf.rxmode.offloads &=
3813                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3814
3815         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3816
3817         return 0;
3818 }
3819
3820 static int ice_macaddr_set(struct rte_eth_dev *dev,
3821                            struct rte_ether_addr *mac_addr)
3822 {
3823         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3824         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3825         struct ice_vsi *vsi = pf->main_vsi;
3826         struct ice_mac_filter *f;
3827         uint8_t flags = 0;
3828         int ret;
3829
3830         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3831                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3832                 return -EINVAL;
3833         }
3834
3835         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3836                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3837                         break;
3838         }
3839
3840         if (!f) {
3841                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3842                 return -EIO;
3843         }
3844
3845         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3846         if (ret != ICE_SUCCESS) {
3847                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3848                 return -EIO;
3849         }
3850         ret = ice_add_mac_filter(vsi, mac_addr);
3851         if (ret != ICE_SUCCESS) {
3852                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3853                 return -EIO;
3854         }
3855         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3856
3857         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3858         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3859         if (ret != ICE_SUCCESS)
3860                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3861
3862         return 0;
3863 }
3864
3865 /* Add a MAC address, and update filters */
3866 static int
3867 ice_macaddr_add(struct rte_eth_dev *dev,
3868                 struct rte_ether_addr *mac_addr,
3869                 __rte_unused uint32_t index,
3870                 __rte_unused uint32_t pool)
3871 {
3872         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3873         struct ice_vsi *vsi = pf->main_vsi;
3874         int ret;
3875
3876         ret = ice_add_mac_filter(vsi, mac_addr);
3877         if (ret != ICE_SUCCESS) {
3878                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3879                 return -EINVAL;
3880         }
3881
3882         return ICE_SUCCESS;
3883 }
3884
3885 /* Remove a MAC address, and update filters */
3886 static void
3887 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3888 {
3889         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3890         struct ice_vsi *vsi = pf->main_vsi;
3891         struct rte_eth_dev_data *data = dev->data;
3892         struct rte_ether_addr *macaddr;
3893         int ret;
3894
3895         macaddr = &data->mac_addrs[index];
3896         ret = ice_remove_mac_filter(vsi, macaddr);
3897         if (ret) {
3898                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3899                 return;
3900         }
3901 }
3902
3903 static int
3904 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3905 {
3906         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3907         struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
3908         struct ice_vsi *vsi = pf->main_vsi;
3909         int ret;
3910
3911         PMD_INIT_FUNC_TRACE();
3912
3913         /**
3914          * Vlan 0 is the generic filter for untagged packets
3915          * and can't be removed or added by user.
3916          */
3917         if (vlan_id == 0)
3918                 return 0;
3919
3920         if (on) {
3921                 ret = ice_add_vlan_filter(vsi, &vlan);
3922                 if (ret < 0) {
3923                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3924                         return -EINVAL;
3925                 }
3926         } else {
3927                 ret = ice_remove_vlan_filter(vsi, &vlan);
3928                 if (ret < 0) {
3929                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3930                         return -EINVAL;
3931                 }
3932         }
3933
3934         return 0;
3935 }
3936
3937 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
3938  * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
3939  * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
3940  * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
3941  *
3942  * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
3943  * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
3944  * traffic in SVM, since the VLAN TPID isn't part of filtering.
3945  *
3946  * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
3947  * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
3948  * part of filtering.
3949  */
3950 static int
3951 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
3952 {
3953         struct ice_vlan vlan;
3954         int err;
3955
3956         vlan = ICE_VLAN(0, 0);
3957         err = ice_add_vlan_filter(vsi, &vlan);
3958         if (err) {
3959                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
3960                 return err;
3961         }
3962
3963         /* in SVM both VLAN 0 filters are identical */
3964         if (!ice_is_dvm_ena(&vsi->adapter->hw))
3965                 return 0;
3966
3967         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3968         err = ice_add_vlan_filter(vsi, &vlan);
3969         if (err) {
3970                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
3971                 return err;
3972         }
3973
3974         return 0;
3975 }
3976
3977 /*
3978  * Delete the VLAN 0 filters in the same manner that they were added in
3979  * ice_vsi_add_vlan_zero.
3980  */
3981 static int
3982 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
3983 {
3984         struct ice_vlan vlan;
3985         int err;
3986
3987         vlan = ICE_VLAN(0, 0);
3988         err = ice_remove_vlan_filter(vsi, &vlan);
3989         if (err) {
3990                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
3991                 return err;
3992         }
3993
3994         /* in SVM both VLAN 0 filters are identical */
3995         if (!ice_is_dvm_ena(&vsi->adapter->hw))
3996                 return 0;
3997
3998         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3999         err = ice_remove_vlan_filter(vsi, &vlan);
4000         if (err) {
4001                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
4002                 return err;
4003         }
4004
4005         return 0;
4006 }
4007
4008 /* Configure vlan filter on or off */
4009 static int
4010 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
4011 {
4012         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4013         struct ice_vsi_ctx ctxt;
4014         uint8_t sw_flags2;
4015         int ret = 0;
4016
4017         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
4018
4019         if (on)
4020                 vsi->info.sw_flags2 |= sw_flags2;
4021         else
4022                 vsi->info.sw_flags2 &= ~sw_flags2;
4023
4024         vsi->info.sw_id = hw->port_info->sw_id;
4025         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4026         ctxt.info.valid_sections =
4027                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4028                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
4029         ctxt.vsi_num = vsi->vsi_id;
4030
4031         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4032         if (ret) {
4033                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4034                             on ? "enable" : "disable");
4035                 return -EINVAL;
4036         } else {
4037                 vsi->info.valid_sections |=
4038                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4039                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
4040         }
4041
4042         /* consist with other drivers, allow untagged packet when vlan filter on */
4043         if (on)
4044                 ret = ice_vsi_add_vlan_zero(vsi);
4045         else
4046                 ret = ice_vsi_del_vlan_zero(vsi);
4047
4048         return 0;
4049 }
4050
4051 /* Manage VLAN stripping for the VSI for Rx */
4052 static int
4053 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4054 {
4055         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4056         struct ice_vsi_ctx ctxt;
4057         enum ice_status status;
4058         int err = 0;
4059
4060         /* do not allow modifying VLAN stripping when a port VLAN is configured
4061          * on this VSI
4062          */
4063         if (vsi->info.port_based_inner_vlan)
4064                 return 0;
4065
4066         memset(&ctxt, 0, sizeof(ctxt));
4067
4068         if (ena)
4069                 /* Strip VLAN tag from Rx packet and put it in the desc */
4070                 ctxt.info.inner_vlan_flags =
4071                                         ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4072         else
4073                 /* Disable stripping. Leave tag in packet */
4074                 ctxt.info.inner_vlan_flags =
4075                                         ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4076
4077         /* Allow all packets untagged/tagged */
4078         ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4079
4080         ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4081
4082         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4083         if (status) {
4084                 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4085                             ena ? "enable" : "disable");
4086                 err = -EIO;
4087         } else {
4088                 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4089         }
4090
4091         return err;
4092 }
4093
4094 static int
4095 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4096 {
4097         return ice_vsi_manage_vlan_stripping(vsi, true);
4098 }
4099
4100 static int
4101 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4102 {
4103         return ice_vsi_manage_vlan_stripping(vsi, false);
4104 }
4105
4106 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4107 {
4108         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4109         struct ice_vsi_ctx ctxt;
4110         enum ice_status status;
4111         int err = 0;
4112
4113         /* do not allow modifying VLAN stripping when a port VLAN is configured
4114          * on this VSI
4115          */
4116         if (vsi->info.port_based_outer_vlan)
4117                 return 0;
4118
4119         memset(&ctxt, 0, sizeof(ctxt));
4120
4121         ctxt.info.valid_sections =
4122                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4123         /* clear current outer VLAN strip settings */
4124         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4125                 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4126         ctxt.info.outer_vlan_flags |=
4127                 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4128                  ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4129                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4130                  ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4131
4132         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4133         if (status) {
4134                 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4135                 err = -EIO;
4136         } else {
4137                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4138         }
4139
4140         return err;
4141 }
4142
4143 static int
4144 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4145 {
4146         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4147         struct ice_vsi_ctx ctxt;
4148         enum ice_status status;
4149         int err = 0;
4150
4151         if (vsi->info.port_based_outer_vlan)
4152                 return 0;
4153
4154         memset(&ctxt, 0, sizeof(ctxt));
4155
4156         ctxt.info.valid_sections =
4157                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4158         /* clear current outer VLAN strip settings */
4159         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4160                 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4161         ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4162                 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4163
4164         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4165         if (status) {
4166                 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4167                 err = -EIO;
4168         } else {
4169                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4170         }
4171
4172         return err;
4173 }
4174
4175 static int
4176 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4177 {
4178         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4179         int ret;
4180
4181         if (ice_is_dvm_ena(hw)) {
4182                 if (ena)
4183                         ret = ice_vsi_ena_outer_stripping(vsi);
4184                 else
4185                         ret = ice_vsi_dis_outer_stripping(vsi);
4186         } else {
4187                 if (ena)
4188                         ret = ice_vsi_ena_inner_stripping(vsi);
4189                 else
4190                         ret = ice_vsi_dis_inner_stripping(vsi);
4191         }
4192
4193         return ret;
4194 }
4195
4196 static int
4197 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4198 {
4199         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4200         struct ice_vsi *vsi = pf->main_vsi;
4201         struct rte_eth_rxmode *rxmode;
4202
4203         rxmode = &dev->data->dev_conf.rxmode;
4204         if (mask & ETH_VLAN_FILTER_MASK) {
4205                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4206                         ice_vsi_config_vlan_filter(vsi, true);
4207                 else
4208                         ice_vsi_config_vlan_filter(vsi, false);
4209         }
4210
4211         if (mask & ETH_VLAN_STRIP_MASK) {
4212                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4213                         ice_vsi_config_vlan_stripping(vsi, true);
4214                 else
4215                         ice_vsi_config_vlan_stripping(vsi, false);
4216         }
4217
4218         return 0;
4219 }
4220
4221 static int
4222 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4223 {
4224         struct ice_aq_get_set_rss_lut_params lut_params;
4225         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4226         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4227         int ret;
4228
4229         if (!lut)
4230                 return -EINVAL;
4231
4232         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4233                 lut_params.vsi_handle = vsi->idx;
4234                 lut_params.lut_size = lut_size;
4235                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4236                 lut_params.lut = lut;
4237                 lut_params.global_lut_id = 0;
4238                 ret = ice_aq_get_rss_lut(hw, &lut_params);
4239                 if (ret) {
4240                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4241                         return -EINVAL;
4242                 }
4243         } else {
4244                 uint64_t *lut_dw = (uint64_t *)lut;
4245                 uint16_t i, lut_size_dw = lut_size / 4;
4246
4247                 for (i = 0; i < lut_size_dw; i++)
4248                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4249         }
4250
4251         return 0;
4252 }
4253
4254 static int
4255 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4256 {
4257         struct ice_aq_get_set_rss_lut_params lut_params;
4258         struct ice_pf *pf;
4259         struct ice_hw *hw;
4260         int ret;
4261
4262         if (!vsi || !lut)
4263                 return -EINVAL;
4264
4265         pf = ICE_VSI_TO_PF(vsi);
4266         hw = ICE_VSI_TO_HW(vsi);
4267
4268         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4269                 lut_params.vsi_handle = vsi->idx;
4270                 lut_params.lut_size = lut_size;
4271                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4272                 lut_params.lut = lut;
4273                 lut_params.global_lut_id = 0;
4274                 ret = ice_aq_set_rss_lut(hw, &lut_params);
4275                 if (ret) {
4276                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4277                         return -EINVAL;
4278                 }
4279         } else {
4280                 uint64_t *lut_dw = (uint64_t *)lut;
4281                 uint16_t i, lut_size_dw = lut_size / 4;
4282
4283                 for (i = 0; i < lut_size_dw; i++)
4284                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4285
4286                 ice_flush(hw);
4287         }
4288
4289         return 0;
4290 }
4291
4292 static int
4293 ice_rss_reta_update(struct rte_eth_dev *dev,
4294                     struct rte_eth_rss_reta_entry64 *reta_conf,
4295                     uint16_t reta_size)
4296 {
4297         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4298         uint16_t i, lut_size = pf->hash_lut_size;
4299         uint16_t idx, shift;
4300         uint8_t *lut;
4301         int ret;
4302
4303         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4304             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4305             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4306                 PMD_DRV_LOG(ERR,
4307                             "The size of hash lookup table configured (%d)"
4308                             "doesn't match the number hardware can "
4309                             "supported (128, 512, 2048)",
4310                             reta_size);
4311                 return -EINVAL;
4312         }
4313
4314         /* It MUST use the current LUT size to get the RSS lookup table,
4315          * otherwise if will fail with -100 error code.
4316          */
4317         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4318         if (!lut) {
4319                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4320                 return -ENOMEM;
4321         }
4322         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4323         if (ret)
4324                 goto out;
4325
4326         for (i = 0; i < reta_size; i++) {
4327                 idx = i / RTE_RETA_GROUP_SIZE;
4328                 shift = i % RTE_RETA_GROUP_SIZE;
4329                 if (reta_conf[idx].mask & (1ULL << shift))
4330                         lut[i] = reta_conf[idx].reta[shift];
4331         }
4332         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4333         if (ret == 0 && lut_size != reta_size) {
4334                 PMD_DRV_LOG(INFO,
4335                             "The size of hash lookup table is changed from (%d) to (%d)",
4336                             lut_size, reta_size);
4337                 pf->hash_lut_size = reta_size;
4338         }
4339
4340 out:
4341         rte_free(lut);
4342
4343         return ret;
4344 }
4345
4346 static int
4347 ice_rss_reta_query(struct rte_eth_dev *dev,
4348                    struct rte_eth_rss_reta_entry64 *reta_conf,
4349                    uint16_t reta_size)
4350 {
4351         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4352         uint16_t i, lut_size = pf->hash_lut_size;
4353         uint16_t idx, shift;
4354         uint8_t *lut;
4355         int ret;
4356
4357         if (reta_size != lut_size) {
4358                 PMD_DRV_LOG(ERR,
4359                             "The size of hash lookup table configured (%d)"
4360                             "doesn't match the number hardware can "
4361                             "supported (%d)",
4362                             reta_size, lut_size);
4363                 return -EINVAL;
4364         }
4365
4366         lut = rte_zmalloc(NULL, reta_size, 0);
4367         if (!lut) {
4368                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4369                 return -ENOMEM;
4370         }
4371
4372         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4373         if (ret)
4374                 goto out;
4375
4376         for (i = 0; i < reta_size; i++) {
4377                 idx = i / RTE_RETA_GROUP_SIZE;
4378                 shift = i % RTE_RETA_GROUP_SIZE;
4379                 if (reta_conf[idx].mask & (1ULL << shift))
4380                         reta_conf[idx].reta[shift] = lut[i];
4381         }
4382
4383 out:
4384         rte_free(lut);
4385
4386         return ret;
4387 }
4388
4389 static int
4390 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4391 {
4392         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4393         int ret = 0;
4394
4395         if (!key || key_len == 0) {
4396                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4397                 return 0;
4398         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4399                    sizeof(uint32_t)) {
4400                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4401                 return -EINVAL;
4402         }
4403
4404         struct ice_aqc_get_set_rss_keys *key_dw =
4405                 (struct ice_aqc_get_set_rss_keys *)key;
4406
4407         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4408         if (ret) {
4409                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4410                 ret = -EINVAL;
4411         }
4412
4413         return ret;
4414 }
4415
4416 static int
4417 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4418 {
4419         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4420         int ret;
4421
4422         if (!key || !key_len)
4423                 return -EINVAL;
4424
4425         ret = ice_aq_get_rss_key
4426                 (hw, vsi->idx,
4427                  (struct ice_aqc_get_set_rss_keys *)key);
4428         if (ret) {
4429                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4430                 return -EINVAL;
4431         }
4432         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4433
4434         return 0;
4435 }
4436
4437 static int
4438 ice_rss_hash_update(struct rte_eth_dev *dev,
4439                     struct rte_eth_rss_conf *rss_conf)
4440 {
4441         enum ice_status status = ICE_SUCCESS;
4442         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4443         struct ice_vsi *vsi = pf->main_vsi;
4444
4445         /* set hash key */
4446         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4447         if (status)
4448                 return status;
4449
4450         if (rss_conf->rss_hf == 0)
4451                 return 0;
4452
4453         /* RSS hash configuration */
4454         ice_rss_hash_set(pf, rss_conf->rss_hf);
4455
4456         return 0;
4457 }
4458
4459 static int
4460 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4461                       struct rte_eth_rss_conf *rss_conf)
4462 {
4463         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4464         struct ice_vsi *vsi = pf->main_vsi;
4465
4466         ice_get_rss_key(vsi, rss_conf->rss_key,
4467                         &rss_conf->rss_key_len);
4468
4469         rss_conf->rss_hf = pf->rss_hf;
4470         return 0;
4471 }
4472
4473 static int
4474 ice_promisc_enable(struct rte_eth_dev *dev)
4475 {
4476         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4477         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4478         struct ice_vsi *vsi = pf->main_vsi;
4479         enum ice_status status;
4480         uint8_t pmask;
4481         int ret = 0;
4482
4483         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4484                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4485
4486         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4487         switch (status) {
4488         case ICE_ERR_ALREADY_EXISTS:
4489                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4490         case ICE_SUCCESS:
4491                 break;
4492         default:
4493                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4494                 ret = -EAGAIN;
4495         }
4496
4497         return ret;
4498 }
4499
4500 static int
4501 ice_promisc_disable(struct rte_eth_dev *dev)
4502 {
4503         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4504         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4505         struct ice_vsi *vsi = pf->main_vsi;
4506         enum ice_status status;
4507         uint8_t pmask;
4508         int ret = 0;
4509
4510         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4511                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4512
4513         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4514         if (status != ICE_SUCCESS) {
4515                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4516                 ret = -EAGAIN;
4517         }
4518
4519         return ret;
4520 }
4521
4522 static int
4523 ice_allmulti_enable(struct rte_eth_dev *dev)
4524 {
4525         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4526         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527         struct ice_vsi *vsi = pf->main_vsi;
4528         enum ice_status status;
4529         uint8_t pmask;
4530         int ret = 0;
4531
4532         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4533
4534         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4535
4536         switch (status) {
4537         case ICE_ERR_ALREADY_EXISTS:
4538                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4539         case ICE_SUCCESS:
4540                 break;
4541         default:
4542                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4543                 ret = -EAGAIN;
4544         }
4545
4546         return ret;
4547 }
4548
4549 static int
4550 ice_allmulti_disable(struct rte_eth_dev *dev)
4551 {
4552         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4553         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4554         struct ice_vsi *vsi = pf->main_vsi;
4555         enum ice_status status;
4556         uint8_t pmask;
4557         int ret = 0;
4558
4559         if (dev->data->promiscuous == 1)
4560                 return 0; /* must remain in all_multicast mode */
4561
4562         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4563
4564         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4565         if (status != ICE_SUCCESS) {
4566                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4567                 ret = -EAGAIN;
4568         }
4569
4570         return ret;
4571 }
4572
4573 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4574                                     uint16_t queue_id)
4575 {
4576         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4577         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4578         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4579         uint32_t val;
4580         uint16_t msix_intr;
4581
4582         msix_intr = intr_handle->intr_vec[queue_id];
4583
4584         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4585               GLINT_DYN_CTL_ITR_INDX_M;
4586         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4587
4588         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4589         rte_intr_ack(&pci_dev->intr_handle);
4590
4591         return 0;
4592 }
4593
4594 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4595                                      uint16_t queue_id)
4596 {
4597         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4598         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4599         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4600         uint16_t msix_intr;
4601
4602         msix_intr = intr_handle->intr_vec[queue_id];
4603
4604         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4605
4606         return 0;
4607 }
4608
4609 static int
4610 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4611 {
4612         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4613         u8 ver, patch;
4614         u16 build;
4615         int ret;
4616
4617         ver = hw->flash.orom.major;
4618         patch = hw->flash.orom.patch;
4619         build = hw->flash.orom.build;
4620
4621         ret = snprintf(fw_version, fw_size,
4622                         "%x.%02x 0x%08x %d.%d.%d",
4623                         hw->flash.nvm.major,
4624                         hw->flash.nvm.minor,
4625                         hw->flash.nvm.eetrack,
4626                         ver, build, patch);
4627
4628         /* add the size of '\0' */
4629         ret += 1;
4630         if (fw_size < (u32)ret)
4631                 return ret;
4632         else
4633                 return 0;
4634 }
4635
4636 static int
4637 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4638 {
4639         struct ice_hw *hw;
4640         struct ice_vsi_ctx ctxt;
4641         uint8_t vlan_flags = 0;
4642         int ret;
4643
4644         if (!vsi || !info) {
4645                 PMD_DRV_LOG(ERR, "invalid parameters");
4646                 return -EINVAL;
4647         }
4648
4649         if (info->on) {
4650                 vsi->info.port_based_inner_vlan = info->config.pvid;
4651                 /**
4652                  * If insert pvid is enabled, only tagged pkts are
4653                  * allowed to be sent out.
4654                  */
4655                 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4656                              ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4657         } else {
4658                 vsi->info.port_based_inner_vlan = 0;
4659                 if (info->config.reject.tagged == 0)
4660                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4661
4662                 if (info->config.reject.untagged == 0)
4663                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4664         }
4665         vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4666                                   ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4667         vsi->info.inner_vlan_flags |= vlan_flags;
4668         memset(&ctxt, 0, sizeof(ctxt));
4669         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4670         ctxt.info.valid_sections =
4671                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4672         ctxt.vsi_num = vsi->vsi_id;
4673
4674         hw = ICE_VSI_TO_HW(vsi);
4675         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4676         if (ret != ICE_SUCCESS) {
4677                 PMD_DRV_LOG(ERR,
4678                             "update VSI for VLAN insert failed, err %d",
4679                             ret);
4680                 return -EINVAL;
4681         }
4682
4683         vsi->info.valid_sections |=
4684                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4685
4686         return ret;
4687 }
4688
4689 static int
4690 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4691 {
4692         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4693         struct ice_vsi *vsi = pf->main_vsi;
4694         struct rte_eth_dev_data *data = pf->dev_data;
4695         struct ice_vsi_vlan_pvid_info info;
4696         int ret;
4697
4698         memset(&info, 0, sizeof(info));
4699         info.on = on;
4700         if (info.on) {
4701                 info.config.pvid = pvid;
4702         } else {
4703                 info.config.reject.tagged =
4704                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4705                 info.config.reject.untagged =
4706                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4707         }
4708
4709         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4710         if (ret < 0) {
4711                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4712                 return -EINVAL;
4713         }
4714
4715         return 0;
4716 }
4717
4718 static int
4719 ice_get_eeprom_length(struct rte_eth_dev *dev)
4720 {
4721         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4722
4723         return hw->flash.flash_size;
4724 }
4725
4726 static int
4727 ice_get_eeprom(struct rte_eth_dev *dev,
4728                struct rte_dev_eeprom_info *eeprom)
4729 {
4730         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4731         enum ice_status status = ICE_SUCCESS;
4732         uint8_t *data = eeprom->data;
4733
4734         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4735
4736         status = ice_acquire_nvm(hw, ICE_RES_READ);
4737         if (status) {
4738                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4739                 return -EIO;
4740         }
4741
4742         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4743                                    data, false);
4744
4745         ice_release_nvm(hw);
4746
4747         if (status) {
4748                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4749                 return -EIO;
4750         }
4751
4752         return 0;
4753 }
4754
4755 static void
4756 ice_stat_update_32(struct ice_hw *hw,
4757                    uint32_t reg,
4758                    bool offset_loaded,
4759                    uint64_t *offset,
4760                    uint64_t *stat)
4761 {
4762         uint64_t new_data;
4763
4764         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4765         if (!offset_loaded)
4766                 *offset = new_data;
4767
4768         if (new_data >= *offset)
4769                 *stat = (uint64_t)(new_data - *offset);
4770         else
4771                 *stat = (uint64_t)((new_data +
4772                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4773                                    - *offset);
4774 }
4775
4776 static void
4777 ice_stat_update_40(struct ice_hw *hw,
4778                    uint32_t hireg,
4779                    uint32_t loreg,
4780                    bool offset_loaded,
4781                    uint64_t *offset,
4782                    uint64_t *stat)
4783 {
4784         uint64_t new_data;
4785
4786         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4787         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4788                     ICE_32_BIT_WIDTH;
4789
4790         if (!offset_loaded)
4791                 *offset = new_data;
4792
4793         if (new_data >= *offset)
4794                 *stat = new_data - *offset;
4795         else
4796                 *stat = (uint64_t)((new_data +
4797                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4798                                    *offset);
4799
4800         *stat &= ICE_40_BIT_MASK;
4801 }
4802
4803 /* Get all the statistics of a VSI */
4804 static void
4805 ice_update_vsi_stats(struct ice_vsi *vsi)
4806 {
4807         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4808         struct ice_eth_stats *nes = &vsi->eth_stats;
4809         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4810         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4811
4812         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4813                            vsi->offset_loaded, &oes->rx_bytes,
4814                            &nes->rx_bytes);
4815         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4816                            vsi->offset_loaded, &oes->rx_unicast,
4817                            &nes->rx_unicast);
4818         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4819                            vsi->offset_loaded, &oes->rx_multicast,
4820                            &nes->rx_multicast);
4821         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4822                            vsi->offset_loaded, &oes->rx_broadcast,
4823                            &nes->rx_broadcast);
4824         /* enlarge the limitation when rx_bytes overflowed */
4825         if (vsi->offset_loaded) {
4826                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4827                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4828                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4829         }
4830         vsi->old_rx_bytes = nes->rx_bytes;
4831         /* exclude CRC bytes */
4832         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4833                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4834
4835         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4836                            &oes->rx_discards, &nes->rx_discards);
4837         /* GLV_REPC not supported */
4838         /* GLV_RMPC not supported */
4839         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4840                            &oes->rx_unknown_protocol,
4841                            &nes->rx_unknown_protocol);
4842         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4843                            vsi->offset_loaded, &oes->tx_bytes,
4844                            &nes->tx_bytes);
4845         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4846                            vsi->offset_loaded, &oes->tx_unicast,
4847                            &nes->tx_unicast);
4848         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4849                            vsi->offset_loaded, &oes->tx_multicast,
4850                            &nes->tx_multicast);
4851         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4852                            vsi->offset_loaded,  &oes->tx_broadcast,
4853                            &nes->tx_broadcast);
4854         /* GLV_TDPC not supported */
4855         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4856                            &oes->tx_errors, &nes->tx_errors);
4857         /* enlarge the limitation when tx_bytes overflowed */
4858         if (vsi->offset_loaded) {
4859                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4860                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4861                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4862         }
4863         vsi->old_tx_bytes = nes->tx_bytes;
4864         vsi->offset_loaded = true;
4865
4866         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4867                     vsi->vsi_id);
4868         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4869         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4870         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4871         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4872         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4873         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4874                     nes->rx_unknown_protocol);
4875         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4876         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4877         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4878         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4879         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4880         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4881         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4882                     vsi->vsi_id);
4883 }
4884
4885 static void
4886 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4887 {
4888         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4889         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4890
4891         /* Get statistics of struct ice_eth_stats */
4892         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4893                            GLPRT_GORCL(hw->port_info->lport),
4894                            pf->offset_loaded, &os->eth.rx_bytes,
4895                            &ns->eth.rx_bytes);
4896         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4897                            GLPRT_UPRCL(hw->port_info->lport),
4898                            pf->offset_loaded, &os->eth.rx_unicast,
4899                            &ns->eth.rx_unicast);
4900         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4901                            GLPRT_MPRCL(hw->port_info->lport),
4902                            pf->offset_loaded, &os->eth.rx_multicast,
4903                            &ns->eth.rx_multicast);
4904         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4905                            GLPRT_BPRCL(hw->port_info->lport),
4906                            pf->offset_loaded, &os->eth.rx_broadcast,
4907                            &ns->eth.rx_broadcast);
4908         ice_stat_update_32(hw, PRTRPB_RDPC,
4909                            pf->offset_loaded, &os->eth.rx_discards,
4910                            &ns->eth.rx_discards);
4911         /* enlarge the limitation when rx_bytes overflowed */
4912         if (pf->offset_loaded) {
4913                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4914                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4915                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4916         }
4917         pf->old_rx_bytes = ns->eth.rx_bytes;
4918
4919         /* Workaround: CRC size should not be included in byte statistics,
4920          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4921          * packet.
4922          */
4923         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4924                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4925
4926         /* GLPRT_REPC not supported */
4927         /* GLPRT_RMPC not supported */
4928         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4929                            pf->offset_loaded,
4930                            &os->eth.rx_unknown_protocol,
4931                            &ns->eth.rx_unknown_protocol);
4932         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4933                            GLPRT_GOTCL(hw->port_info->lport),
4934                            pf->offset_loaded, &os->eth.tx_bytes,
4935                            &ns->eth.tx_bytes);
4936         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4937                            GLPRT_UPTCL(hw->port_info->lport),
4938                            pf->offset_loaded, &os->eth.tx_unicast,
4939                            &ns->eth.tx_unicast);
4940         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4941                            GLPRT_MPTCL(hw->port_info->lport),
4942                            pf->offset_loaded, &os->eth.tx_multicast,
4943                            &ns->eth.tx_multicast);
4944         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4945                            GLPRT_BPTCL(hw->port_info->lport),
4946                            pf->offset_loaded, &os->eth.tx_broadcast,
4947                            &ns->eth.tx_broadcast);
4948         /* enlarge the limitation when tx_bytes overflowed */
4949         if (pf->offset_loaded) {
4950                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4951                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4952                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4953         }
4954         pf->old_tx_bytes = ns->eth.tx_bytes;
4955         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4956                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4957
4958         /* GLPRT_TEPC not supported */
4959
4960         /* additional port specific stats */
4961         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4962                            pf->offset_loaded, &os->tx_dropped_link_down,
4963                            &ns->tx_dropped_link_down);
4964         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4965                            pf->offset_loaded, &os->crc_errors,
4966                            &ns->crc_errors);
4967         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4968                            pf->offset_loaded, &os->illegal_bytes,
4969                            &ns->illegal_bytes);
4970         /* GLPRT_ERRBC not supported */
4971         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4972                            pf->offset_loaded, &os->mac_local_faults,
4973                            &ns->mac_local_faults);
4974         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4975                            pf->offset_loaded, &os->mac_remote_faults,
4976                            &ns->mac_remote_faults);
4977
4978         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4979                            pf->offset_loaded, &os->rx_len_errors,
4980                            &ns->rx_len_errors);
4981
4982         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4983                            pf->offset_loaded, &os->link_xon_rx,
4984                            &ns->link_xon_rx);
4985         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4986                            pf->offset_loaded, &os->link_xoff_rx,
4987                            &ns->link_xoff_rx);
4988         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4989                            pf->offset_loaded, &os->link_xon_tx,
4990                            &ns->link_xon_tx);
4991         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4992                            pf->offset_loaded, &os->link_xoff_tx,
4993                            &ns->link_xoff_tx);
4994         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4995                            GLPRT_PRC64L(hw->port_info->lport),
4996                            pf->offset_loaded, &os->rx_size_64,
4997                            &ns->rx_size_64);
4998         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4999                            GLPRT_PRC127L(hw->port_info->lport),
5000                            pf->offset_loaded, &os->rx_size_127,
5001                            &ns->rx_size_127);
5002         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
5003                            GLPRT_PRC255L(hw->port_info->lport),
5004                            pf->offset_loaded, &os->rx_size_255,
5005                            &ns->rx_size_255);
5006         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
5007                            GLPRT_PRC511L(hw->port_info->lport),
5008                            pf->offset_loaded, &os->rx_size_511,
5009                            &ns->rx_size_511);
5010         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
5011                            GLPRT_PRC1023L(hw->port_info->lport),
5012                            pf->offset_loaded, &os->rx_size_1023,
5013                            &ns->rx_size_1023);
5014         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
5015                            GLPRT_PRC1522L(hw->port_info->lport),
5016                            pf->offset_loaded, &os->rx_size_1522,
5017                            &ns->rx_size_1522);
5018         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
5019                            GLPRT_PRC9522L(hw->port_info->lport),
5020                            pf->offset_loaded, &os->rx_size_big,
5021                            &ns->rx_size_big);
5022         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
5023                            pf->offset_loaded, &os->rx_undersize,
5024                            &ns->rx_undersize);
5025         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
5026                            pf->offset_loaded, &os->rx_fragments,
5027                            &ns->rx_fragments);
5028         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5029                            pf->offset_loaded, &os->rx_oversize,
5030                            &ns->rx_oversize);
5031         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5032                            pf->offset_loaded, &os->rx_jabber,
5033                            &ns->rx_jabber);
5034         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5035                            GLPRT_PTC64L(hw->port_info->lport),
5036                            pf->offset_loaded, &os->tx_size_64,
5037                            &ns->tx_size_64);
5038         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5039                            GLPRT_PTC127L(hw->port_info->lport),
5040                            pf->offset_loaded, &os->tx_size_127,
5041                            &ns->tx_size_127);
5042         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5043                            GLPRT_PTC255L(hw->port_info->lport),
5044                            pf->offset_loaded, &os->tx_size_255,
5045                            &ns->tx_size_255);
5046         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5047                            GLPRT_PTC511L(hw->port_info->lport),
5048                            pf->offset_loaded, &os->tx_size_511,
5049                            &ns->tx_size_511);
5050         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5051                            GLPRT_PTC1023L(hw->port_info->lport),
5052                            pf->offset_loaded, &os->tx_size_1023,
5053                            &ns->tx_size_1023);
5054         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5055                            GLPRT_PTC1522L(hw->port_info->lport),
5056                            pf->offset_loaded, &os->tx_size_1522,
5057                            &ns->tx_size_1522);
5058         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5059                            GLPRT_PTC9522L(hw->port_info->lport),
5060                            pf->offset_loaded, &os->tx_size_big,
5061                            &ns->tx_size_big);
5062
5063         /* GLPRT_MSPDC not supported */
5064         /* GLPRT_XEC not supported */
5065
5066         pf->offset_loaded = true;
5067
5068         if (pf->main_vsi)
5069                 ice_update_vsi_stats(pf->main_vsi);
5070 }
5071
5072 /* Get all statistics of a port */
5073 static int
5074 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5075 {
5076         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5077         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5078         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5079
5080         /* call read registers - updates values, now write them to struct */
5081         ice_read_stats_registers(pf, hw);
5082
5083         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5084                           pf->main_vsi->eth_stats.rx_multicast +
5085                           pf->main_vsi->eth_stats.rx_broadcast -
5086                           pf->main_vsi->eth_stats.rx_discards;
5087         stats->opackets = ns->eth.tx_unicast +
5088                           ns->eth.tx_multicast +
5089                           ns->eth.tx_broadcast;
5090         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
5091         stats->obytes   = ns->eth.tx_bytes;
5092         stats->oerrors  = ns->eth.tx_errors +
5093                           pf->main_vsi->eth_stats.tx_errors;
5094
5095         /* Rx Errors */
5096         stats->imissed  = ns->eth.rx_discards +
5097                           pf->main_vsi->eth_stats.rx_discards;
5098         stats->ierrors  = ns->crc_errors +
5099                           ns->rx_undersize +
5100                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5101
5102         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5103         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
5104         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5105         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5106         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5107         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5108         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5109                     pf->main_vsi->eth_stats.rx_discards);
5110         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
5111                     ns->eth.rx_unknown_protocol);
5112         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
5113         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5114         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5115         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5116         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5117         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5118                     pf->main_vsi->eth_stats.tx_discards);
5119         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
5120
5121         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
5122                     ns->tx_dropped_link_down);
5123         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5124         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
5125                     ns->illegal_bytes);
5126         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
5127         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
5128                     ns->mac_local_faults);
5129         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
5130                     ns->mac_remote_faults);
5131         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
5132         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
5133         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
5134         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
5135         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
5136         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
5137         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
5138         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
5139         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
5140         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
5141         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
5142         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
5143         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
5144         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
5145         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
5146         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
5147         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
5148         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
5149         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
5150         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
5151         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
5152         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
5153         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
5154         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5155         return 0;
5156 }
5157
5158 /* Reset the statistics */
5159 static int
5160 ice_stats_reset(struct rte_eth_dev *dev)
5161 {
5162         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5163         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5164
5165         /* Mark PF and VSI stats to update the offset, aka "reset" */
5166         pf->offset_loaded = false;
5167         if (pf->main_vsi)
5168                 pf->main_vsi->offset_loaded = false;
5169
5170         /* read the stats, reading current register values into offset */
5171         ice_read_stats_registers(pf, hw);
5172
5173         return 0;
5174 }
5175
5176 static uint32_t
5177 ice_xstats_calc_num(void)
5178 {
5179         uint32_t num;
5180
5181         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5182
5183         return num;
5184 }
5185
5186 static int
5187 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5188                unsigned int n)
5189 {
5190         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5191         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5192         unsigned int i;
5193         unsigned int count;
5194         struct ice_hw_port_stats *hw_stats = &pf->stats;
5195
5196         count = ice_xstats_calc_num();
5197         if (n < count)
5198                 return count;
5199
5200         ice_read_stats_registers(pf, hw);
5201
5202         if (!xstats)
5203                 return 0;
5204
5205         count = 0;
5206
5207         /* Get stats from ice_eth_stats struct */
5208         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5209                 xstats[count].value =
5210                         *(uint64_t *)((char *)&hw_stats->eth +
5211                                       ice_stats_strings[i].offset);
5212                 xstats[count].id = count;
5213                 count++;
5214         }
5215
5216         /* Get individiual stats from ice_hw_port struct */
5217         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5218                 xstats[count].value =
5219                         *(uint64_t *)((char *)hw_stats +
5220                                       ice_hw_port_strings[i].offset);
5221                 xstats[count].id = count;
5222                 count++;
5223         }
5224
5225         return count;
5226 }
5227
5228 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5229                                 struct rte_eth_xstat_name *xstats_names,
5230                                 __rte_unused unsigned int limit)
5231 {
5232         unsigned int count = 0;
5233         unsigned int i;
5234
5235         if (!xstats_names)
5236                 return ice_xstats_calc_num();
5237
5238         /* Note: limit checked in rte_eth_xstats_names() */
5239
5240         /* Get stats from ice_eth_stats struct */
5241         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5242                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5243                         sizeof(xstats_names[count].name));
5244                 count++;
5245         }
5246
5247         /* Get individiual stats from ice_hw_port struct */
5248         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5249                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5250                         sizeof(xstats_names[count].name));
5251                 count++;
5252         }
5253
5254         return count;
5255 }
5256
5257 static int
5258 ice_dev_filter_ctrl(struct rte_eth_dev *dev,
5259                      enum rte_filter_type filter_type,
5260                      enum rte_filter_op filter_op,
5261                      void *arg)
5262 {
5263         int ret = 0;
5264
5265         if (!dev)
5266                 return -EINVAL;
5267
5268         switch (filter_type) {
5269         case RTE_ETH_FILTER_GENERIC:
5270                 if (filter_op != RTE_ETH_FILTER_GET)
5271                         return -EINVAL;
5272                 *(const void **)arg = &ice_flow_ops;
5273                 break;
5274         default:
5275                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5276                                         filter_type);
5277                 ret = -EINVAL;
5278                 break;
5279         }
5280
5281         return ret;
5282 }
5283
5284 /* Add UDP tunneling port */
5285 static int
5286 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5287                              struct rte_eth_udp_tunnel *udp_tunnel)
5288 {
5289         int ret = 0;
5290         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5291
5292         if (udp_tunnel == NULL)
5293                 return -EINVAL;
5294
5295         switch (udp_tunnel->prot_type) {
5296         case RTE_TUNNEL_TYPE_VXLAN:
5297                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5298                 break;
5299         default:
5300                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5301                 ret = -EINVAL;
5302                 break;
5303         }
5304
5305         return ret;
5306 }
5307
5308 /* Delete UDP tunneling port */
5309 static int
5310 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5311                              struct rte_eth_udp_tunnel *udp_tunnel)
5312 {
5313         int ret = 0;
5314         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5315
5316         if (udp_tunnel == NULL)
5317                 return -EINVAL;
5318
5319         switch (udp_tunnel->prot_type) {
5320         case RTE_TUNNEL_TYPE_VXLAN:
5321                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5322                 break;
5323         default:
5324                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5325                 ret = -EINVAL;
5326                 break;
5327         }
5328
5329         return ret;
5330 }
5331
5332 static int
5333 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5334               struct rte_pci_device *pci_dev)
5335 {
5336         return rte_eth_dev_pci_generic_probe(pci_dev,
5337                                              sizeof(struct ice_adapter),
5338                                              ice_dev_init);
5339 }
5340
5341 static int
5342 ice_pci_remove(struct rte_pci_device *pci_dev)
5343 {
5344         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5345 }
5346
5347 static struct rte_pci_driver rte_ice_pmd = {
5348         .id_table = pci_id_ice_map,
5349         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5350         .probe = ice_pci_probe,
5351         .remove = ice_pci_remove,
5352 };
5353
5354 /**
5355  * Driver initialization routine.
5356  * Invoked once at EAL init time.
5357  * Register itself as the [Poll Mode] Driver of PCI devices.
5358  */
5359 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5360 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5361 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5362 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5363                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5364                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5365                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5366
5367 RTE_LOG_REGISTER(ice_logtype_init, pmd.net.ice.init, NOTICE);
5368 RTE_LOG_REGISTER(ice_logtype_driver, pmd.net.ice.driver, NOTICE);
5369 #ifdef RTE_LIBRTE_ICE_DEBUG_RX
5370 RTE_LOG_REGISTER(ice_logtype_rx, pmd.net.ice.rx, DEBUG);
5371 #endif
5372 #ifdef RTE_LIBRTE_ICE_DEBUG_TX
5373 RTE_LOG_REGISTER(ice_logtype_tx, pmd.net.ice.tx, DEBUG);
5374 #endif
5375 #ifdef RTE_LIBRTE_ICE_DEBUG_TX_FREE
5376 RTE_LOG_REGISTER(ice_logtype_tx_free, pmd.net.ice.tx_free, DEBUG);
5377 #endif