1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
8 #include <rte_kvargs.h>
10 #include <rte_ethdev_driver.h>
12 #include "base/ice_common.h"
13 #include "base/ice_adminq_cmd.h"
14 #include "base/ice_flow.h"
16 #define ICE_VLAN_TAG_SIZE 4
18 #define ICE_ADMINQ_LEN 32
19 #define ICE_SBIOQ_LEN 32
20 #define ICE_MAILBOXQ_LEN 32
21 #define ICE_ADMINQ_BUF_SZ 4096
22 #define ICE_SBIOQ_BUF_SZ 4096
23 #define ICE_MAILBOXQ_BUF_SZ 4096
24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
25 #define ICE_MAX_Q_PER_TC 64
26 #define ICE_NUM_DESC_DEFAULT 512
27 #define ICE_BUF_SIZE_MIN 1024
28 #define ICE_FRAME_SIZE_MAX 9728
29 #define ICE_QUEUE_BASE_ADDR_UNIT 128
30 /* number of VSIs and queue default setting */
31 #define ICE_MAX_QP_NUM_PER_VF 16
32 #define ICE_DEFAULT_QP_NUM_FDIR 1
33 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
34 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE)
35 /* Maximun number of MAC addresses */
36 #define ICE_NUM_MACADDR_MAX 64
37 /* Maximum number of VFs */
38 #define ICE_MAX_VF 128
39 #define ICE_MAX_INTR_QUEUE_NUM 256
41 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
42 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET
44 #define ICE_MAX_PKT_TYPE 1024
46 /* DDP package search path */
47 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
48 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
49 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
50 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
51 #define ICE_MAX_PKG_FILENAME_SIZE 256
53 #define MAX_ACL_ENTRIES 512
56 * vlan_id is a 12 bit number.
57 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
58 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
59 * The higher 7 bit val specifies VFTA array index.
61 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
62 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
64 /* Default TC traffic in case DCB is not enabled */
65 #define ICE_DEFAULT_TCMAP 0x1
66 #define ICE_FDIR_QUEUE_ID 0
68 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
69 #define ICE_VMDQ_POOL_BASE 1
71 #define ICE_DEFAULT_RX_FREE_THRESH 32
72 #define ICE_DEFAULT_RX_PTHRESH 8
73 #define ICE_DEFAULT_RX_HTHRESH 8
74 #define ICE_DEFAULT_RX_WTHRESH 0
76 #define ICE_DEFAULT_TX_FREE_THRESH 32
77 #define ICE_DEFAULT_TX_PTHRESH 32
78 #define ICE_DEFAULT_TX_HTHRESH 0
79 #define ICE_DEFAULT_TX_WTHRESH 0
80 #define ICE_DEFAULT_TX_RSBIT_THRESH 32
82 /* Bit shift and mask */
83 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2)
84 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t)
85 #define ICE_8_BIT_WIDTH CHAR_BIT
86 #define ICE_8_BIT_MASK UINT8_MAX
87 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2)
88 #define ICE_16_BIT_MASK UINT16_MAX
89 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4)
90 #define ICE_32_BIT_MASK UINT32_MAX
91 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5)
92 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t)
93 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6)
94 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t)
96 #define ICE_FLAG_RSS BIT_ULL(0)
97 #define ICE_FLAG_DCB BIT_ULL(1)
98 #define ICE_FLAG_VMDQ BIT_ULL(2)
99 #define ICE_FLAG_SRIOV BIT_ULL(3)
100 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4)
101 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5)
102 #define ICE_FLAG_FDIR BIT_ULL(6)
103 #define ICE_FLAG_VXLAN BIT_ULL(7)
104 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8)
105 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9)
106 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \
110 ICE_FLAG_HEADER_SPLIT_DISABLED | \
111 ICE_FLAG_HEADER_SPLIT_ENABLED | \
114 ICE_FLAG_RSS_AQ_CAPABLE | \
115 ICE_FLAG_VF_MAC_BY_PF)
117 #define ICE_RSS_OFFLOAD_ALL ( \
119 ETH_RSS_FRAG_IPV4 | \
120 ETH_RSS_NONFRAG_IPV4_TCP | \
121 ETH_RSS_NONFRAG_IPV4_UDP | \
122 ETH_RSS_NONFRAG_IPV4_SCTP | \
123 ETH_RSS_NONFRAG_IPV4_OTHER | \
125 ETH_RSS_FRAG_IPV6 | \
126 ETH_RSS_NONFRAG_IPV6_TCP | \
127 ETH_RSS_NONFRAG_IPV6_UDP | \
128 ETH_RSS_NONFRAG_IPV6_SCTP | \
129 ETH_RSS_NONFRAG_IPV6_OTHER | \
133 * The overhead from MTU to max frame size.
134 * Considering QinQ packet, the VLAN tag needs to be counted twice.
136 #define ICE_ETH_OVERHEAD \
137 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2)
138 #define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD)
140 #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK)
141 #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK)
143 /* Max number of flexible descriptor rxdid */
144 #define ICE_FLEX_DESC_RXDID_MAX_NUM 64
146 /* DDP package type */
148 ICE_PKG_TYPE_UNKNOWN,
149 ICE_PKG_TYPE_OS_DEFAULT,
156 * MAC filter structure
158 struct ice_mac_filter_info {
159 struct rte_ether_addr mac_addr;
162 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter);
164 /* MAC filter list structure */
165 struct ice_mac_filter {
166 TAILQ_ENTRY(ice_mac_filter) next;
167 struct ice_mac_filter_info mac_info;
171 * VLAN filter structure
173 struct ice_vlan_filter_info {
177 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter);
179 /* VLAN filter list structure */
180 struct ice_vlan_filter {
181 TAILQ_ENTRY(ice_vlan_filter) next;
182 struct ice_vlan_filter_info vlan_info;
186 LIST_ENTRY(pool_entry) next;
191 LIST_HEAD(res_list, pool_entry);
193 struct ice_res_pool_info {
194 uint32_t base; /* Resource start index */
195 uint32_t num_alloc; /* Allocated resource number */
196 uint32_t num_free; /* Total available resource number */
197 struct res_list alloc_list; /* Allocated resource list */
198 struct res_list free_list; /* Available resource list */
201 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list);
205 /* VSI list structure */
206 struct ice_vsi_list {
207 TAILQ_ENTRY(ice_vsi_list) list;
215 * Structure that defines a VSI, associated with a adapter.
218 struct ice_adapter *adapter; /* Backreference to associated adapter */
219 struct ice_aqc_vsi_props info; /* VSI properties */
221 * When drivers loaded, only a default main VSI exists. In case new VSI
222 * needs to add, HW needs to know the layout that VSIs are organized.
223 * Besides that, VSI isan element and can't switch packets, which needs
224 * to add new component VEB to perform switching. So, a new VSI needs
225 * to specify the the uplink VSI (Parent VSI) before created. The
226 * uplink VSI will check whether it had a VEB to switch packets. If no,
227 * it will try to create one. Then, uplink VSI will move the new VSI
228 * into its' sib_vsi_list to manage all the downlink VSI.
229 * sib_vsi_list: the VSI list that shared the same uplink VSI.
230 * parent_vsi : the uplink VSI. It's NULL for main VSI.
231 * veb : the VEB associates with the VSI.
233 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */
234 struct ice_vsi *parent_vsi;
235 enum ice_vsi_type type; /* VSI types */
236 uint16_t vlan_num; /* Total VLAN number */
237 uint16_t mac_num; /* Total mac number */
238 struct ice_mac_filter_list mac_list; /* macvlan filter list */
239 struct ice_vlan_filter_list vlan_list; /* vlan filter list */
240 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
241 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
242 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
243 uint16_t base_queue; /* The first queue index of this VSI */
244 uint16_t vsi_id; /* Hardware Id */
245 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */
246 /* VF number to which the VSI connects, valid when VSI is VF type */
248 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
249 uint16_t nb_msix; /* The max number of msix vector */
250 uint8_t enabled_tc; /* The traffic class enabled */
251 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
252 uint8_t vlan_filter_on; /* The VLAN filter enabled */
253 /* information about rss configuration */
258 struct ice_eth_stats eth_stats_offset;
259 struct ice_eth_stats eth_stats;
261 uint64_t old_rx_bytes;
262 uint64_t old_tx_bytes;
265 enum proto_xtr_type {
273 PROTO_XTR_MAX /* The last one */
276 enum ice_fdir_tunnel_type {
277 ICE_FDIR_TUNNEL_TYPE_NONE = 0,
278 ICE_FDIR_TUNNEL_TYPE_VXLAN,
279 ICE_FDIR_TUNNEL_TYPE_GTPU,
280 ICE_FDIR_TUNNEL_TYPE_GTPU_EH,
284 TAILQ_HEAD(ice_flow_list, rte_flow);
286 struct ice_flow_parser_node;
287 TAILQ_HEAD(ice_parser_list, ice_flow_parser_node);
289 struct ice_fdir_filter_conf {
290 struct ice_fdir_fltr input;
291 enum ice_fdir_tunnel_type tunnel_type;
293 struct ice_fdir_counter *counter; /* flow specific counter context */
294 struct rte_flow_action_count act_count;
297 uint64_t outer_input_set; /* only for tunnel packets outer fields */
301 #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16)
303 struct ice_fdir_fltr_pattern {
304 enum ice_fltr_ptype flow_type;
307 struct ice_fdir_v4 v4;
308 struct ice_fdir_v6 v6;
311 struct ice_fdir_udp_gtp gtpu_data;
312 struct ice_fdir_udp_gtp gtpu_mask;
314 struct ice_fdir_extra ext_data;
315 struct ice_fdir_extra ext_mask;
317 enum ice_fdir_tunnel_type tunnel_type;
320 #define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1
321 #define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32
322 #define ICE_FDIR_COUNTERS_PER_BLOCK 256
323 #define ICE_FDIR_COUNTER_INDEX(base_idx) \
324 ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK)
325 struct ice_fdir_counter_pool;
327 struct ice_fdir_counter {
328 TAILQ_ENTRY(ice_fdir_counter) next;
329 struct ice_fdir_counter_pool *pool;
338 TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter);
340 struct ice_fdir_counter_pool {
341 TAILQ_ENTRY(ice_fdir_counter_pool) next;
342 struct ice_fdir_counter_list counter_list;
343 struct ice_fdir_counter counters[0];
346 TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool);
348 struct ice_fdir_counter_pool_container {
349 struct ice_fdir_counter_pool_list pool_list;
350 struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE];
355 * A structure used to define fields of a FDIR related info.
357 struct ice_fdir_info {
358 struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */
359 struct ice_tx_queue *txq;
360 struct ice_rx_queue *rxq;
361 void *prg_pkt; /* memory for fdir program packet */
362 uint64_t dma_addr; /* physic address of packet memory*/
363 const struct rte_memzone *mz;
364 struct ice_fdir_filter_conf conf;
366 struct ice_fdir_filter_conf **hash_map;
367 struct rte_hash *hash_table;
369 struct ice_fdir_counter_pool_container counter;
372 #define ICE_HASH_GTPU_CTX_EH_IP 0
373 #define ICE_HASH_GTPU_CTX_EH_IP_UDP 1
374 #define ICE_HASH_GTPU_CTX_EH_IP_TCP 2
375 #define ICE_HASH_GTPU_CTX_UP_IP 3
376 #define ICE_HASH_GTPU_CTX_UP_IP_UDP 4
377 #define ICE_HASH_GTPU_CTX_UP_IP_TCP 5
378 #define ICE_HASH_GTPU_CTX_DW_IP 6
379 #define ICE_HASH_GTPU_CTX_DW_IP_UDP 7
380 #define ICE_HASH_GTPU_CTX_DW_IP_TCP 8
381 #define ICE_HASH_GTPU_CTX_MAX 9
383 struct ice_hash_gtpu_ctx {
384 struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX];
387 struct ice_hash_ctx {
388 struct ice_hash_gtpu_ctx gtpu4;
389 struct ice_hash_gtpu_ctx gtpu6;
392 struct ice_acl_conf {
393 struct ice_fdir_fltr input;
398 * A structure used to define fields of ACL related info.
400 struct ice_acl_info {
401 struct ice_acl_conf conf;
402 struct rte_bitmap *slots;
403 uint64_t hw_entry_id[MAX_ACL_ENTRIES];
407 struct ice_adapter *adapter; /* The adapter this PF associate to */
408 struct ice_vsi *main_vsi; /* pointer to main VSI structure */
409 /* Used for next free software vsi idx.
410 * To save the effort, we don't recycle the index.
411 * Suppose the indexes are more than enough.
413 uint16_t next_vsi_idx;
414 uint16_t vsis_allocated;
415 uint16_t vsis_unallocated;
416 struct ice_res_pool_info qp_pool; /*Queue pair pool */
417 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */
418 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
419 struct rte_ether_addr dev_addr; /* PF device mac address */
420 uint64_t flags; /* PF feature flags */
421 uint16_t hash_lut_size; /* The size of hash lookup table */
422 uint16_t lan_nb_qp_max;
423 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
424 uint16_t base_queue; /* The base queue pairs index in the device */
425 uint8_t *proto_xtr; /* Protocol extraction type for all queues */
426 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
427 uint16_t fdir_qp_offset;
428 struct ice_fdir_info fdir; /* flow director info */
429 struct ice_acl_info acl; /* ACL info */
430 struct ice_hash_ctx hash_ctx;
431 uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
432 uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
433 struct ice_hw_port_stats stats_offset;
434 struct ice_hw_port_stats stats;
435 /* internal packet statistics, it should be excluded from the total */
436 struct ice_eth_stats internal_stats_offset;
437 struct ice_eth_stats internal_stats;
439 bool adapter_stopped;
440 struct ice_flow_list flow_list;
441 rte_spinlock_t flow_ops_lock;
442 struct ice_parser_list rss_parser_list;
443 struct ice_parser_list perm_parser_list;
444 struct ice_parser_list dist_parser_list;
446 uint64_t old_rx_bytes;
447 uint64_t old_tx_bytes;
448 uint64_t supported_rxdid; /* bitmap for supported RXDID */
452 #define ICE_MAX_QUEUE_NUM 2048
455 * Cache devargs parse result.
458 int safe_mode_support;
459 uint8_t proto_xtr_dflt;
460 int pipe_mode_support;
461 uint8_t proto_xtr[ICE_MAX_QUEUE_NUM];
465 * Structure to store private data for each PF/VF instance.
468 /* Common for both PF and VF */
470 struct rte_eth_dev *eth_dev;
472 bool rx_bulk_alloc_allowed;
475 bool tx_simple_allowed;
476 /* ptype mapping table */
477 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned;
479 struct ice_devargs devargs;
480 enum ice_pkg_type active_pkg_type; /* loaded ddp package type */
481 uint16_t fdir_ref_cnt;
484 struct ice_vsi_vlan_pvid_info {
485 uint16_t on; /* Enable or disable pvid */
487 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
489 /* Valid in case 'on' is cleared. 'tagged' will reject
490 * tagged packets, while 'untagged' will reject
499 #define ICE_DEV_TO_PCI(eth_dev) \
500 RTE_DEV_TO_PCI((eth_dev)->device)
502 /* ICE_DEV_PRIVATE_TO */
503 #define ICE_DEV_PRIVATE_TO_PF(adapter) \
504 (&((struct ice_adapter *)adapter)->pf)
505 #define ICE_DEV_PRIVATE_TO_HW(adapter) \
506 (&((struct ice_adapter *)adapter)->hw)
507 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \
508 ((struct ice_adapter *)adapter)
511 #define ICE_VSI_TO_HW(vsi) \
512 (&(((struct ice_vsi *)vsi)->adapter->hw))
513 #define ICE_VSI_TO_PF(vsi) \
514 (&(((struct ice_vsi *)vsi)->adapter->pf))
515 #define ICE_VSI_TO_ETH_DEV(vsi) \
516 (((struct ice_vsi *)vsi)->adapter->eth_dev)
519 #define ICE_PF_TO_HW(pf) \
520 (&(((struct ice_pf *)pf)->adapter->hw))
521 #define ICE_PF_TO_ADAPTER(pf) \
522 ((struct ice_adapter *)(pf)->adapter)
523 #define ICE_PF_TO_ETH_DEV(pf) \
524 (((struct ice_pf *)pf)->adapter->eth_dev)
526 enum ice_pkg_type ice_load_pkg_type(struct ice_hw *hw);
528 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type);
530 ice_release_vsi(struct ice_vsi *vsi);
531 void ice_vsi_enable_queues_intr(struct ice_vsi *vsi);
532 void ice_vsi_disable_queues_intr(struct ice_vsi *vsi);
533 void ice_vsi_queues_bind_intr(struct ice_vsi *vsi);
534 int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
535 struct ice_rss_hash_cfg *cfg);
536 int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
537 struct ice_rss_hash_cfg *cfg);
540 ice_align_floor(int n)
544 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
547 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \
548 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \
549 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \
550 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \
551 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \
552 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \
553 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \
554 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \
555 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \
556 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \
557 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \
558 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \
559 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \
560 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \
561 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \
562 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1))
564 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \
565 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \
566 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \
567 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \
568 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \
569 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \
570 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \
571 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \
572 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \
573 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \
574 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \
575 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \
576 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \
577 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR))
579 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \
580 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \
581 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \
582 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \
583 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \
584 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2))
586 #endif /* _ICE_ETHDEV_H_ */