1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
8 #include <rte_kvargs.h>
10 #include "base/ice_common.h"
11 #include "base/ice_adminq_cmd.h"
13 #define ICE_VLAN_TAG_SIZE 4
15 #define ICE_ADMINQ_LEN 32
16 #define ICE_SBIOQ_LEN 32
17 #define ICE_MAILBOXQ_LEN 32
18 #define ICE_ADMINQ_BUF_SZ 4096
19 #define ICE_SBIOQ_BUF_SZ 4096
20 #define ICE_MAILBOXQ_BUF_SZ 4096
21 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
22 #define ICE_MAX_Q_PER_TC 64
23 #define ICE_NUM_DESC_DEFAULT 512
24 #define ICE_BUF_SIZE_MIN 1024
25 #define ICE_FRAME_SIZE_MAX 9728
26 #define ICE_QUEUE_BASE_ADDR_UNIT 128
27 /* number of VSIs and queue default setting */
28 #define ICE_MAX_QP_NUM_PER_VF 16
29 #define ICE_DEFAULT_QP_NUM_FDIR 1
30 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
31 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE)
32 /* Maximun number of MAC addresses */
33 #define ICE_NUM_MACADDR_MAX 64
34 /* Maximum number of VFs */
35 #define ICE_MAX_VF 128
36 #define ICE_MAX_INTR_QUEUE_NUM 256
38 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
39 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET
41 #define ICE_MAX_PKT_TYPE 1024
44 * vlan_id is a 12 bit number.
45 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
46 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
47 * The higher 7 bit val specifies VFTA array index.
49 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
50 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
52 /* Default TC traffic in case DCB is not enabled */
53 #define ICE_DEFAULT_TCMAP 0x1
54 #define ICE_FDIR_QUEUE_ID 0
56 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
57 #define ICE_VMDQ_POOL_BASE 1
59 #define ICE_DEFAULT_RX_FREE_THRESH 32
60 #define ICE_DEFAULT_RX_PTHRESH 8
61 #define ICE_DEFAULT_RX_HTHRESH 8
62 #define ICE_DEFAULT_RX_WTHRESH 0
64 #define ICE_DEFAULT_TX_FREE_THRESH 32
65 #define ICE_DEFAULT_TX_PTHRESH 32
66 #define ICE_DEFAULT_TX_HTHRESH 0
67 #define ICE_DEFAULT_TX_WTHRESH 0
68 #define ICE_DEFAULT_TX_RSBIT_THRESH 32
70 /* Bit shift and mask */
71 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2)
72 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t)
73 #define ICE_8_BIT_WIDTH CHAR_BIT
74 #define ICE_8_BIT_MASK UINT8_MAX
75 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2)
76 #define ICE_16_BIT_MASK UINT16_MAX
77 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4)
78 #define ICE_32_BIT_MASK UINT32_MAX
79 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5)
80 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t)
81 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6)
82 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t)
84 #define ICE_FLAG_RSS BIT_ULL(0)
85 #define ICE_FLAG_DCB BIT_ULL(1)
86 #define ICE_FLAG_VMDQ BIT_ULL(2)
87 #define ICE_FLAG_SRIOV BIT_ULL(3)
88 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4)
89 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5)
90 #define ICE_FLAG_FDIR BIT_ULL(6)
91 #define ICE_FLAG_VXLAN BIT_ULL(7)
92 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8)
93 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9)
94 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \
98 ICE_FLAG_HEADER_SPLIT_DISABLED | \
99 ICE_FLAG_HEADER_SPLIT_ENABLED | \
102 ICE_FLAG_RSS_AQ_CAPABLE | \
103 ICE_FLAG_VF_MAC_BY_PF)
108 * MAC filter structure
110 struct ice_mac_filter_info {
111 struct ether_addr mac_addr;
114 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter);
116 /* MAC filter list structure */
117 struct ice_mac_filter {
118 TAILQ_ENTRY(ice_mac_filter) next;
119 struct ice_mac_filter_info mac_info;
123 * VLAN filter structure
125 struct ice_vlan_filter_info {
129 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter);
131 /* VLAN filter list structure */
132 struct ice_vlan_filter {
133 TAILQ_ENTRY(ice_vlan_filter) next;
134 struct ice_vlan_filter_info vlan_info;
138 LIST_ENTRY(pool_entry) next;
143 LIST_HEAD(res_list, pool_entry);
145 struct ice_res_pool_info {
146 uint32_t base; /* Resource start index */
147 uint32_t num_alloc; /* Allocated resource number */
148 uint32_t num_free; /* Total available resource number */
149 struct res_list alloc_list; /* Allocated resource list */
150 struct res_list free_list; /* Available resource list */
153 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list);
157 /* VSI list structure */
158 struct ice_vsi_list {
159 TAILQ_ENTRY(ice_vsi_list) list;
167 * Structure that defines a VSI, associated with a adapter.
170 struct ice_adapter *adapter; /* Backreference to associated adapter */
171 struct ice_aqc_vsi_props info; /* VSI properties */
173 * When drivers loaded, only a default main VSI exists. In case new VSI
174 * needs to add, HW needs to know the layout that VSIs are organized.
175 * Besides that, VSI isan element and can't switch packets, which needs
176 * to add new component VEB to perform switching. So, a new VSI needs
177 * to specify the the uplink VSI (Parent VSI) before created. The
178 * uplink VSI will check whether it had a VEB to switch packets. If no,
179 * it will try to create one. Then, uplink VSI will move the new VSI
180 * into its' sib_vsi_list to manage all the downlink VSI.
181 * sib_vsi_list: the VSI list that shared the same uplink VSI.
182 * parent_vsi : the uplink VSI. It's NULL for main VSI.
183 * veb : the VEB associates with the VSI.
185 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */
186 struct ice_vsi *parent_vsi;
187 enum ice_vsi_type type; /* VSI types */
188 uint16_t vlan_num; /* Total VLAN number */
189 uint16_t mac_num; /* Total mac number */
190 struct ice_mac_filter_list mac_list; /* macvlan filter list */
191 struct ice_vlan_filter_list vlan_list; /* vlan filter list */
192 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
193 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
194 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
195 uint16_t base_queue; /* The first queue index of this VSI */
196 uint16_t vsi_id; /* Hardware Id */
197 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */
198 /* VF number to which the VSI connects, valid when VSI is VF type */
200 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
201 uint16_t nb_msix; /* The max number of msix vector */
202 uint8_t enabled_tc; /* The traffic class enabled */
203 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
204 uint8_t vlan_filter_on; /* The VLAN filter enabled */
205 /* information about rss configuration */
210 struct ice_eth_stats eth_stats_offset;
211 struct ice_eth_stats eth_stats;
216 struct ice_adapter *adapter; /* The adapter this PF associate to */
217 struct ice_vsi *main_vsi; /* pointer to main VSI structure */
218 /* Used for next free software vsi idx.
219 * To save the effort, we don't recycle the index.
220 * Suppose the indexes are more than enough.
222 uint16_t next_vsi_idx;
223 uint16_t vsis_allocated;
224 uint16_t vsis_unallocated;
225 struct ice_res_pool_info qp_pool; /*Queue pair pool */
226 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */
227 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
228 struct ether_addr dev_addr; /* PF device mac address */
229 uint64_t flags; /* PF feature flags */
230 uint16_t hash_lut_size; /* The size of hash lookup table */
231 uint16_t lan_nb_qp_max;
232 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
233 struct ice_hw_port_stats stats_offset;
234 struct ice_hw_port_stats stats;
235 /* internal packet statistics, it should be excluded from the total */
236 struct ice_eth_stats internal_stats_offset;
237 struct ice_eth_stats internal_stats;
239 bool adapter_stopped;
243 * Structure to store private data for each PF/VF instance.
246 /* Common for both PF and VF */
248 struct rte_eth_dev *eth_dev;
250 bool rx_bulk_alloc_allowed;
251 bool tx_simple_allowed;
252 /* ptype mapping table */
253 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned;
256 struct ice_vsi_vlan_pvid_info {
257 uint16_t on; /* Enable or disable pvid */
259 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
261 /* Valid in case 'on' is cleared. 'tagged' will reject
262 * tagged packets, while 'untagged' will reject
271 #define ICE_DEV_TO_PCI(eth_dev) \
272 RTE_DEV_TO_PCI((eth_dev)->device)
274 /* ICE_DEV_PRIVATE_TO */
275 #define ICE_DEV_PRIVATE_TO_PF(adapter) \
276 (&((struct ice_adapter *)adapter)->pf)
277 #define ICE_DEV_PRIVATE_TO_HW(adapter) \
278 (&((struct ice_adapter *)adapter)->hw)
279 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \
280 ((struct ice_adapter *)adapter)
283 #define ICE_VSI_TO_HW(vsi) \
284 (&(((struct ice_vsi *)vsi)->adapter->hw))
285 #define ICE_VSI_TO_PF(vsi) \
286 (&(((struct ice_vsi *)vsi)->adapter->pf))
287 #define ICE_VSI_TO_ETH_DEV(vsi) \
288 (((struct ice_vsi *)vsi)->adapter->eth_dev)
291 #define ICE_PF_TO_HW(pf) \
292 (&(((struct ice_pf *)pf)->adapter->hw))
293 #define ICE_PF_TO_ADAPTER(pf) \
294 ((struct ice_adapter *)(pf)->adapter)
295 #define ICE_PF_TO_ETH_DEV(pf) \
296 (((struct ice_pf *)pf)->adapter->eth_dev)
299 ice_align_floor(int n)
303 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
305 #endif /* _ICE_ETHDEV_H_ */