1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
8 #include <rte_kvargs.h>
10 #include <ethdev_driver.h>
12 #include "base/ice_common.h"
13 #include "base/ice_adminq_cmd.h"
14 #include "base/ice_flow.h"
16 #define ICE_VLAN_TAG_SIZE 4
18 #define ICE_ADMINQ_LEN 32
19 #define ICE_SBIOQ_LEN 32
20 #define ICE_MAILBOXQ_LEN 32
21 #define ICE_ADMINQ_BUF_SZ 4096
22 #define ICE_SBIOQ_BUF_SZ 4096
23 #define ICE_MAILBOXQ_BUF_SZ 4096
24 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
25 #define ICE_MAX_Q_PER_TC 64
26 #define ICE_NUM_DESC_DEFAULT 512
27 #define ICE_BUF_SIZE_MIN 1024
28 #define ICE_FRAME_SIZE_MAX 9728
29 #define ICE_QUEUE_BASE_ADDR_UNIT 128
30 /* number of VSIs and queue default setting */
31 #define ICE_MAX_QP_NUM_PER_VF 16
32 #define ICE_DEFAULT_QP_NUM_FDIR 1
33 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
34 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE)
35 /* Maximun number of MAC addresses */
36 #define ICE_NUM_MACADDR_MAX 64
37 /* Maximum number of VFs */
38 #define ICE_MAX_VF 128
39 #define ICE_MAX_INTR_QUEUE_NUM 256
41 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
42 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET
44 #define ICE_MAX_PKT_TYPE 1024
46 /* DDP package search path */
47 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
48 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
49 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
50 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
51 #define ICE_MAX_PKG_FILENAME_SIZE 256
53 #define MAX_ACL_NORMAL_ENTRIES 256
56 * vlan_id is a 12 bit number.
57 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
58 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
59 * The higher 7 bit val specifies VFTA array index.
61 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
62 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
64 /* Default TC traffic in case DCB is not enabled */
65 #define ICE_DEFAULT_TCMAP 0x1
66 #define ICE_FDIR_QUEUE_ID 0
68 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
69 #define ICE_VMDQ_POOL_BASE 1
71 #define ICE_DEFAULT_RX_FREE_THRESH 32
72 #define ICE_DEFAULT_RX_PTHRESH 8
73 #define ICE_DEFAULT_RX_HTHRESH 8
74 #define ICE_DEFAULT_RX_WTHRESH 0
76 #define ICE_DEFAULT_TX_FREE_THRESH 32
77 #define ICE_DEFAULT_TX_PTHRESH 32
78 #define ICE_DEFAULT_TX_HTHRESH 0
79 #define ICE_DEFAULT_TX_WTHRESH 0
80 #define ICE_DEFAULT_TX_RSBIT_THRESH 32
82 /* Bit shift and mask */
83 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2)
84 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t)
85 #define ICE_8_BIT_WIDTH CHAR_BIT
86 #define ICE_8_BIT_MASK UINT8_MAX
87 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2)
88 #define ICE_16_BIT_MASK UINT16_MAX
89 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4)
90 #define ICE_32_BIT_MASK UINT32_MAX
91 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5)
92 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t)
93 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6)
94 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t)
96 #define ICE_FLAG_RSS BIT_ULL(0)
97 #define ICE_FLAG_DCB BIT_ULL(1)
98 #define ICE_FLAG_VMDQ BIT_ULL(2)
99 #define ICE_FLAG_SRIOV BIT_ULL(3)
100 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4)
101 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5)
102 #define ICE_FLAG_FDIR BIT_ULL(6)
103 #define ICE_FLAG_VXLAN BIT_ULL(7)
104 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8)
105 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9)
106 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \
110 ICE_FLAG_HEADER_SPLIT_DISABLED | \
111 ICE_FLAG_HEADER_SPLIT_ENABLED | \
114 ICE_FLAG_RSS_AQ_CAPABLE | \
115 ICE_FLAG_VF_MAC_BY_PF)
117 #define ICE_RSS_OFFLOAD_ALL ( \
119 ETH_RSS_FRAG_IPV4 | \
120 ETH_RSS_NONFRAG_IPV4_TCP | \
121 ETH_RSS_NONFRAG_IPV4_UDP | \
122 ETH_RSS_NONFRAG_IPV4_SCTP | \
123 ETH_RSS_NONFRAG_IPV4_OTHER | \
125 ETH_RSS_FRAG_IPV6 | \
126 ETH_RSS_NONFRAG_IPV6_TCP | \
127 ETH_RSS_NONFRAG_IPV6_UDP | \
128 ETH_RSS_NONFRAG_IPV6_SCTP | \
129 ETH_RSS_NONFRAG_IPV6_OTHER | \
133 * The overhead from MTU to max frame size.
134 * Considering QinQ packet, the VLAN tag needs to be counted twice.
136 #define ICE_ETH_OVERHEAD \
137 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2)
138 #define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD)
140 #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK)
141 #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK)
143 /* Max number of flexible descriptor rxdid */
144 #define ICE_FLEX_DESC_RXDID_MAX_NUM 64
146 /* DDP package type */
148 ICE_PKG_TYPE_UNKNOWN,
149 ICE_PKG_TYPE_OS_DEFAULT,
156 * MAC filter structure
158 struct ice_mac_filter_info {
159 struct rte_ether_addr mac_addr;
162 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter);
164 /* MAC filter list structure */
165 struct ice_mac_filter {
166 TAILQ_ENTRY(ice_mac_filter) next;
167 struct ice_mac_filter_info mac_info;
175 #define ICE_VLAN(tpid, vid) \
176 ((struct ice_vlan){ tpid, vid })
179 * VLAN filter structure
181 struct ice_vlan_filter_info {
182 struct ice_vlan vlan;
185 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter);
187 /* VLAN filter list structure */
188 struct ice_vlan_filter {
189 TAILQ_ENTRY(ice_vlan_filter) next;
190 struct ice_vlan_filter_info vlan_info;
194 LIST_ENTRY(pool_entry) next;
199 LIST_HEAD(res_list, pool_entry);
201 struct ice_res_pool_info {
202 uint32_t base; /* Resource start index */
203 uint32_t num_alloc; /* Allocated resource number */
204 uint32_t num_free; /* Total available resource number */
205 struct res_list alloc_list; /* Allocated resource list */
206 struct res_list free_list; /* Available resource list */
209 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list);
213 /* VSI list structure */
214 struct ice_vsi_list {
215 TAILQ_ENTRY(ice_vsi_list) list;
223 * Structure that defines a VSI, associated with a adapter.
226 struct ice_adapter *adapter; /* Backreference to associated adapter */
227 struct ice_aqc_vsi_props info; /* VSI properties */
229 * When drivers loaded, only a default main VSI exists. In case new VSI
230 * needs to add, HW needs to know the layout that VSIs are organized.
231 * Besides that, VSI isan element and can't switch packets, which needs
232 * to add new component VEB to perform switching. So, a new VSI needs
233 * to specify the the uplink VSI (Parent VSI) before created. The
234 * uplink VSI will check whether it had a VEB to switch packets. If no,
235 * it will try to create one. Then, uplink VSI will move the new VSI
236 * into its' sib_vsi_list to manage all the downlink VSI.
237 * sib_vsi_list: the VSI list that shared the same uplink VSI.
238 * parent_vsi : the uplink VSI. It's NULL for main VSI.
239 * veb : the VEB associates with the VSI.
241 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */
242 struct ice_vsi *parent_vsi;
243 enum ice_vsi_type type; /* VSI types */
244 uint16_t vlan_num; /* Total VLAN number */
245 uint16_t mac_num; /* Total mac number */
246 struct ice_mac_filter_list mac_list; /* macvlan filter list */
247 struct ice_vlan_filter_list vlan_list; /* vlan filter list */
248 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
249 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
250 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
251 uint16_t base_queue; /* The first queue index of this VSI */
252 uint16_t vsi_id; /* Hardware Id */
253 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */
254 /* VF number to which the VSI connects, valid when VSI is VF type */
256 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
257 uint16_t nb_msix; /* The max number of msix vector */
258 uint8_t enabled_tc; /* The traffic class enabled */
259 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
260 uint8_t vlan_filter_on; /* The VLAN filter enabled */
261 /* information about rss configuration */
266 struct ice_eth_stats eth_stats_offset;
267 struct ice_eth_stats eth_stats;
269 uint64_t old_rx_bytes;
270 uint64_t old_tx_bytes;
273 enum proto_xtr_type {
281 PROTO_XTR_MAX /* The last one */
284 enum ice_fdir_tunnel_type {
285 ICE_FDIR_TUNNEL_TYPE_NONE = 0,
286 ICE_FDIR_TUNNEL_TYPE_VXLAN,
287 ICE_FDIR_TUNNEL_TYPE_GTPU,
288 ICE_FDIR_TUNNEL_TYPE_GTPU_EH,
292 TAILQ_HEAD(ice_flow_list, rte_flow);
294 struct ice_flow_parser_node;
295 TAILQ_HEAD(ice_parser_list, ice_flow_parser_node);
297 struct ice_fdir_filter_conf {
298 struct ice_fdir_fltr input;
299 enum ice_fdir_tunnel_type tunnel_type;
301 struct ice_fdir_counter *counter; /* flow specific counter context */
302 struct rte_flow_action_count act_count;
304 uint64_t input_set_o; /* used for non-tunnel or tunnel outer fields */
305 uint64_t input_set_i; /* only for tunnel inner fields */
309 #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16)
311 struct ice_fdir_fltr_pattern {
312 enum ice_fltr_ptype flow_type;
315 struct ice_fdir_v4 v4;
316 struct ice_fdir_v6 v6;
319 struct ice_fdir_udp_gtp gtpu_data;
320 struct ice_fdir_udp_gtp gtpu_mask;
322 struct ice_fdir_extra ext_data;
323 struct ice_fdir_extra ext_mask;
325 enum ice_fdir_tunnel_type tunnel_type;
328 #define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1
329 #define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32
330 #define ICE_FDIR_COUNTERS_PER_BLOCK 256
331 #define ICE_FDIR_COUNTER_INDEX(base_idx) \
332 ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK)
333 struct ice_fdir_counter_pool;
335 struct ice_fdir_counter {
336 TAILQ_ENTRY(ice_fdir_counter) next;
337 struct ice_fdir_counter_pool *pool;
346 TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter);
348 struct ice_fdir_counter_pool {
349 TAILQ_ENTRY(ice_fdir_counter_pool) next;
350 struct ice_fdir_counter_list counter_list;
351 struct ice_fdir_counter counters[0];
354 TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool);
356 struct ice_fdir_counter_pool_container {
357 struct ice_fdir_counter_pool_list pool_list;
358 struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE];
363 * A structure used to define fields of a FDIR related info.
365 struct ice_fdir_info {
366 struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */
367 struct ice_tx_queue *txq;
368 struct ice_rx_queue *rxq;
369 void *prg_pkt; /* memory for fdir program packet */
370 uint64_t dma_addr; /* physic address of packet memory*/
371 const struct rte_memzone *mz;
372 struct ice_fdir_filter_conf conf;
374 struct ice_fdir_filter_conf **hash_map;
375 struct rte_hash *hash_table;
377 struct ice_fdir_counter_pool_container counter;
380 #define ICE_HASH_GTPU_CTX_EH_IP 0
381 #define ICE_HASH_GTPU_CTX_EH_IP_UDP 1
382 #define ICE_HASH_GTPU_CTX_EH_IP_TCP 2
383 #define ICE_HASH_GTPU_CTX_UP_IP 3
384 #define ICE_HASH_GTPU_CTX_UP_IP_UDP 4
385 #define ICE_HASH_GTPU_CTX_UP_IP_TCP 5
386 #define ICE_HASH_GTPU_CTX_DW_IP 6
387 #define ICE_HASH_GTPU_CTX_DW_IP_UDP 7
388 #define ICE_HASH_GTPU_CTX_DW_IP_TCP 8
389 #define ICE_HASH_GTPU_CTX_MAX 9
391 struct ice_hash_gtpu_ctx {
392 struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX];
395 struct ice_hash_ctx {
396 struct ice_hash_gtpu_ctx gtpu4;
397 struct ice_hash_gtpu_ctx gtpu6;
400 struct ice_acl_conf {
401 struct ice_fdir_fltr input;
406 * A structure used to define fields of ACL related info.
408 struct ice_acl_info {
409 struct ice_acl_conf conf;
410 struct rte_bitmap *slots;
411 uint64_t hw_entry_id[MAX_ACL_NORMAL_ENTRIES];
415 struct ice_adapter *adapter; /* The adapter this PF associate to */
416 struct ice_vsi *main_vsi; /* pointer to main VSI structure */
417 /* Used for next free software vsi idx.
418 * To save the effort, we don't recycle the index.
419 * Suppose the indexes are more than enough.
421 uint16_t next_vsi_idx;
422 uint16_t vsis_allocated;
423 uint16_t vsis_unallocated;
424 struct ice_res_pool_info qp_pool; /*Queue pair pool */
425 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */
426 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
427 struct rte_ether_addr dev_addr; /* PF device mac address */
428 uint64_t flags; /* PF feature flags */
429 uint16_t hash_lut_size; /* The size of hash lookup table */
430 uint16_t lan_nb_qp_max;
431 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
432 uint16_t base_queue; /* The base queue pairs index in the device */
433 uint8_t *proto_xtr; /* Protocol extraction type for all queues */
434 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
435 uint16_t fdir_qp_offset;
436 struct ice_fdir_info fdir; /* flow director info */
437 struct ice_acl_info acl; /* ACL info */
438 struct ice_hash_ctx hash_ctx;
439 uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
440 uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
441 struct ice_hw_port_stats stats_offset;
442 struct ice_hw_port_stats stats;
443 /* internal packet statistics, it should be excluded from the total */
444 struct ice_eth_stats internal_stats_offset;
445 struct ice_eth_stats internal_stats;
447 bool adapter_stopped;
448 struct ice_flow_list flow_list;
449 rte_spinlock_t flow_ops_lock;
450 struct ice_parser_list rss_parser_list;
451 struct ice_parser_list perm_parser_list;
452 struct ice_parser_list dist_parser_list;
454 uint64_t old_rx_bytes;
455 uint64_t old_tx_bytes;
456 uint64_t supported_rxdid; /* bitmap for supported RXDID */
460 #define ICE_MAX_QUEUE_NUM 2048
463 * Cache devargs parse result.
466 int safe_mode_support;
467 uint8_t proto_xtr_dflt;
468 int pipe_mode_support;
469 uint8_t proto_xtr[ICE_MAX_QUEUE_NUM];
473 * Structure to store private data for each PF/VF instance.
476 /* Common for both PF and VF */
479 bool rx_bulk_alloc_allowed;
482 bool tx_simple_allowed;
483 /* ptype mapping table */
484 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned;
486 struct ice_devargs devargs;
487 enum ice_pkg_type active_pkg_type; /* loaded ddp package type */
488 uint16_t fdir_ref_cnt;
497 struct ice_vsi_vlan_pvid_info {
498 uint16_t on; /* Enable or disable pvid */
500 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
502 /* Valid in case 'on' is cleared. 'tagged' will reject
503 * tagged packets, while 'untagged' will reject
512 #define ICE_DEV_TO_PCI(eth_dev) \
513 RTE_DEV_TO_PCI((eth_dev)->device)
515 /* ICE_DEV_PRIVATE_TO */
516 #define ICE_DEV_PRIVATE_TO_PF(adapter) \
517 (&((struct ice_adapter *)adapter)->pf)
518 #define ICE_DEV_PRIVATE_TO_HW(adapter) \
519 (&((struct ice_adapter *)adapter)->hw)
520 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \
521 ((struct ice_adapter *)adapter)
524 #define ICE_VSI_TO_HW(vsi) \
525 (&(((struct ice_vsi *)vsi)->adapter->hw))
526 #define ICE_VSI_TO_PF(vsi) \
527 (&(((struct ice_vsi *)vsi)->adapter->pf))
530 #define ICE_PF_TO_HW(pf) \
531 (&(((struct ice_pf *)pf)->adapter->hw))
532 #define ICE_PF_TO_ADAPTER(pf) \
533 ((struct ice_adapter *)(pf)->adapter)
534 #define ICE_PF_TO_ETH_DEV(pf) \
535 (((struct ice_pf *)pf)->adapter->eth_dev)
538 ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn);
540 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type);
542 ice_release_vsi(struct ice_vsi *vsi);
543 void ice_vsi_enable_queues_intr(struct ice_vsi *vsi);
544 void ice_vsi_disable_queues_intr(struct ice_vsi *vsi);
545 void ice_vsi_queues_bind_intr(struct ice_vsi *vsi);
546 int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
547 struct ice_rss_hash_cfg *cfg);
548 int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
549 struct ice_rss_hash_cfg *cfg);
552 ice_align_floor(int n)
556 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
559 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \
560 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \
561 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \
562 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \
563 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \
564 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \
565 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \
566 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \
567 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \
568 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \
569 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \
570 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \
571 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \
572 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \
573 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \
574 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1))
576 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \
577 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \
578 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \
579 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \
580 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \
581 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \
582 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \
583 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \
584 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \
585 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \
586 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \
587 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \
588 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \
589 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR))
591 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \
592 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \
593 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \
594 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \
595 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \
596 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2))
598 #endif /* _ICE_ETHDEV_H_ */