1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
8 #include <rte_kvargs.h>
11 #include <ethdev_driver.h>
12 #include <rte_tm_driver.h>
14 #include "base/ice_common.h"
15 #include "base/ice_adminq_cmd.h"
16 #include "base/ice_flow.h"
17 #include "base/ice_sched.h"
19 #define ICE_ADMINQ_LEN 32
20 #define ICE_SBIOQ_LEN 32
21 #define ICE_MAILBOXQ_LEN 32
22 #define ICE_SBQ_LEN 64
23 #define ICE_ADMINQ_BUF_SZ 4096
24 #define ICE_SBIOQ_BUF_SZ 4096
25 #define ICE_MAILBOXQ_BUF_SZ 4096
26 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64, 128, 256 */
27 #define ICE_MAX_Q_PER_TC 256
28 #define ICE_NUM_DESC_DEFAULT 512
29 #define ICE_BUF_SIZE_MIN 1024
30 #define ICE_FRAME_SIZE_MAX 9728
31 #define ICE_QUEUE_BASE_ADDR_UNIT 128
32 /* number of VSIs and queue default setting */
33 #define ICE_MAX_QP_NUM_PER_VF 16
34 #define ICE_DEFAULT_QP_NUM_FDIR 1
35 #define ICE_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
36 #define ICE_VFTA_SIZE (4096 / ICE_UINT32_BIT_SIZE)
37 /* Maximun number of MAC addresses */
38 #define ICE_NUM_MACADDR_MAX 64
39 /* Maximum number of VFs */
40 #define ICE_MAX_VF 128
41 #define ICE_MAX_INTR_QUEUE_NUM 256
43 #define ICE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
44 #define ICE_RX_VEC_ID RTE_INTR_VEC_RXTX_OFFSET
46 #define ICE_MAX_PKT_TYPE 1024
48 /* DDP package search path */
49 #define ICE_PKG_FILE_DEFAULT "/lib/firmware/intel/ice/ddp/ice.pkg"
50 #define ICE_PKG_FILE_UPDATES "/lib/firmware/updates/intel/ice/ddp/ice.pkg"
51 #define ICE_PKG_FILE_SEARCH_PATH_DEFAULT "/lib/firmware/intel/ice/ddp/"
52 #define ICE_PKG_FILE_SEARCH_PATH_UPDATES "/lib/firmware/updates/intel/ice/ddp/"
53 #define ICE_MAX_PKG_FILENAME_SIZE 256
55 #define MAX_ACL_NORMAL_ENTRIES 256
58 * vlan_id is a 12 bit number.
59 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
60 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
61 * The higher 7 bit val specifies VFTA array index.
63 #define ICE_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
64 #define ICE_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
66 /* Default TC traffic in case DCB is not enabled */
67 #define ICE_DEFAULT_TCMAP 0x1
68 #define ICE_FDIR_QUEUE_ID 0
70 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
71 #define ICE_VMDQ_POOL_BASE 1
73 #define ICE_DEFAULT_RX_FREE_THRESH 32
74 #define ICE_DEFAULT_RX_PTHRESH 8
75 #define ICE_DEFAULT_RX_HTHRESH 8
76 #define ICE_DEFAULT_RX_WTHRESH 0
78 #define ICE_DEFAULT_TX_FREE_THRESH 32
79 #define ICE_DEFAULT_TX_PTHRESH 32
80 #define ICE_DEFAULT_TX_HTHRESH 0
81 #define ICE_DEFAULT_TX_WTHRESH 0
82 #define ICE_DEFAULT_TX_RSBIT_THRESH 32
84 /* Bit shift and mask */
85 #define ICE_4_BIT_WIDTH (CHAR_BIT / 2)
86 #define ICE_4_BIT_MASK RTE_LEN2MASK(ICE_4_BIT_WIDTH, uint8_t)
87 #define ICE_8_BIT_WIDTH CHAR_BIT
88 #define ICE_8_BIT_MASK UINT8_MAX
89 #define ICE_16_BIT_WIDTH (CHAR_BIT * 2)
90 #define ICE_16_BIT_MASK UINT16_MAX
91 #define ICE_32_BIT_WIDTH (CHAR_BIT * 4)
92 #define ICE_32_BIT_MASK UINT32_MAX
93 #define ICE_40_BIT_WIDTH (CHAR_BIT * 5)
94 #define ICE_40_BIT_MASK RTE_LEN2MASK(ICE_40_BIT_WIDTH, uint64_t)
95 #define ICE_48_BIT_WIDTH (CHAR_BIT * 6)
96 #define ICE_48_BIT_MASK RTE_LEN2MASK(ICE_48_BIT_WIDTH, uint64_t)
98 #define ICE_FLAG_RSS BIT_ULL(0)
99 #define ICE_FLAG_DCB BIT_ULL(1)
100 #define ICE_FLAG_VMDQ BIT_ULL(2)
101 #define ICE_FLAG_SRIOV BIT_ULL(3)
102 #define ICE_FLAG_HEADER_SPLIT_DISABLED BIT_ULL(4)
103 #define ICE_FLAG_HEADER_SPLIT_ENABLED BIT_ULL(5)
104 #define ICE_FLAG_FDIR BIT_ULL(6)
105 #define ICE_FLAG_VXLAN BIT_ULL(7)
106 #define ICE_FLAG_RSS_AQ_CAPABLE BIT_ULL(8)
107 #define ICE_FLAG_VF_MAC_BY_PF BIT_ULL(9)
108 #define ICE_FLAG_ALL (ICE_FLAG_RSS | \
112 ICE_FLAG_HEADER_SPLIT_DISABLED | \
113 ICE_FLAG_HEADER_SPLIT_ENABLED | \
116 ICE_FLAG_RSS_AQ_CAPABLE | \
117 ICE_FLAG_VF_MAC_BY_PF)
119 #define ICE_RSS_OFFLOAD_ALL ( \
121 RTE_ETH_RSS_FRAG_IPV4 | \
122 RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
123 RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
124 RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \
125 RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \
127 RTE_ETH_RSS_FRAG_IPV6 | \
128 RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
129 RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
130 RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
131 RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \
132 RTE_ETH_RSS_L2_PAYLOAD)
135 * The overhead from MTU to max frame size.
136 * Considering QinQ packet, the VLAN tag needs to be counted twice.
138 #define ICE_ETH_OVERHEAD \
139 (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + RTE_VLAN_HLEN * 2)
140 #define ICE_ETH_MAX_LEN (RTE_ETHER_MTU + ICE_ETH_OVERHEAD)
142 #define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK)
143 #define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK)
145 /* Max number of flexible descriptor rxdid */
146 #define ICE_FLEX_DESC_RXDID_MAX_NUM 64
148 #define ICE_I2C_EEPROM_DEV_ADDR 0xA0
149 #define ICE_I2C_EEPROM_DEV_ADDR2 0xA2
150 #define ICE_MODULE_TYPE_SFP 0x03
151 #define ICE_MODULE_TYPE_QSFP_PLUS 0x0D
152 #define ICE_MODULE_TYPE_QSFP28 0x11
153 #define ICE_MODULE_SFF_ADDR_MODE 0x04
154 #define ICE_MODULE_SFF_DIAG_CAPAB 0x40
155 #define ICE_MODULE_REVISION_ADDR 0x01
156 #define ICE_MODULE_SFF_8472_COMP 0x5E
157 #define ICE_MODULE_SFF_8472_SWAP 0x5C
158 #define ICE_MODULE_QSFP_MAX_LEN 640
160 /* EEPROM Standards for plug in modules */
161 #define ICE_MODULE_SFF_8079 0x1
162 #define ICE_MODULE_SFF_8079_LEN 256
163 #define ICE_MODULE_SFF_8472 0x2
164 #define ICE_MODULE_SFF_8472_LEN 512
165 #define ICE_MODULE_SFF_8636 0x3
166 #define ICE_MODULE_SFF_8636_LEN 256
167 #define ICE_MODULE_SFF_8636_MAX_LEN 640
168 #define ICE_MODULE_SFF_8436 0x4
169 #define ICE_MODULE_SFF_8436_LEN 256
170 #define ICE_MODULE_SFF_8436_MAX_LEN 640
173 /* Per-channel register definitions */
174 #define GLTSYN_AUX_OUT(_chan, _idx) (GLTSYN_AUX_OUT_0(_idx) + ((_chan) * 8))
175 #define GLTSYN_CLKO(_chan, _idx) (GLTSYN_CLKO_0(_idx) + ((_chan) * 8))
176 #define GLTSYN_TGT_L(_chan, _idx) (GLTSYN_TGT_L_0(_idx) + ((_chan) * 16))
177 #define GLTSYN_TGT_H(_chan, _idx) (GLTSYN_TGT_H_0(_idx) + ((_chan) * 16))
179 /* DDP package type */
181 ICE_PKG_TYPE_UNKNOWN,
182 ICE_PKG_TYPE_OS_DEFAULT,
195 * MAC filter structure
197 struct ice_mac_filter_info {
198 struct rte_ether_addr mac_addr;
201 TAILQ_HEAD(ice_mac_filter_list, ice_mac_filter);
203 /* MAC filter list structure */
204 struct ice_mac_filter {
205 TAILQ_ENTRY(ice_mac_filter) next;
206 struct ice_mac_filter_info mac_info;
214 #define ICE_VLAN(tpid, vid) \
215 ((struct ice_vlan){ tpid, vid })
218 * VLAN filter structure
220 struct ice_vlan_filter_info {
221 struct ice_vlan vlan;
224 TAILQ_HEAD(ice_vlan_filter_list, ice_vlan_filter);
226 /* VLAN filter list structure */
227 struct ice_vlan_filter {
228 TAILQ_ENTRY(ice_vlan_filter) next;
229 struct ice_vlan_filter_info vlan_info;
233 LIST_ENTRY(pool_entry) next;
238 LIST_HEAD(res_list, pool_entry);
240 struct ice_res_pool_info {
241 uint32_t base; /* Resource start index */
242 uint32_t num_alloc; /* Allocated resource number */
243 uint32_t num_free; /* Total available resource number */
244 struct res_list alloc_list; /* Allocated resource list */
245 struct res_list free_list; /* Available resource list */
248 TAILQ_HEAD(ice_vsi_list_head, ice_vsi_list);
252 /* VSI list structure */
253 struct ice_vsi_list {
254 TAILQ_ENTRY(ice_vsi_list) list;
262 * Structure that defines a VSI, associated with a adapter.
265 struct ice_adapter *adapter; /* Backreference to associated adapter */
266 struct ice_aqc_vsi_props info; /* VSI properties */
268 * When drivers loaded, only a default main VSI exists. In case new VSI
269 * needs to add, HW needs to know the layout that VSIs are organized.
270 * Besides that, VSI isan element and can't switch packets, which needs
271 * to add new component VEB to perform switching. So, a new VSI needs
272 * to specify the uplink VSI (Parent VSI) before created. The
273 * uplink VSI will check whether it had a VEB to switch packets. If no,
274 * it will try to create one. Then, uplink VSI will move the new VSI
275 * into its' sib_vsi_list to manage all the downlink VSI.
276 * sib_vsi_list: the VSI list that shared the same uplink VSI.
277 * parent_vsi : the uplink VSI. It's NULL for main VSI.
278 * veb : the VEB associates with the VSI.
280 struct ice_vsi_list sib_vsi_list; /* sibling vsi list */
281 struct ice_vsi *parent_vsi;
282 enum ice_vsi_type type; /* VSI types */
283 uint16_t vlan_num; /* Total VLAN number */
284 uint16_t mac_num; /* Total mac number */
285 struct ice_mac_filter_list mac_list; /* macvlan filter list */
286 struct ice_vlan_filter_list vlan_list; /* vlan filter list */
287 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
288 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
289 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
290 uint16_t base_queue; /* The first queue index of this VSI */
291 uint16_t vsi_id; /* Hardware Id */
292 uint16_t idx; /* vsi_handle: SW index in hw->vsi_ctx */
293 /* VF number to which the VSI connects, valid when VSI is VF type */
295 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
296 uint16_t nb_msix; /* The max number of msix vector */
297 uint8_t enabled_tc; /* The traffic class enabled */
298 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
299 uint8_t vlan_filter_on; /* The VLAN filter enabled */
300 /* information about rss configuration */
305 struct ice_eth_stats eth_stats_offset;
306 struct ice_eth_stats eth_stats;
308 uint64_t old_rx_bytes;
309 uint64_t old_tx_bytes;
312 enum proto_xtr_type {
320 PROTO_XTR_MAX /* The last one */
323 enum ice_fdir_tunnel_type {
324 ICE_FDIR_TUNNEL_TYPE_NONE = 0,
325 ICE_FDIR_TUNNEL_TYPE_VXLAN,
326 ICE_FDIR_TUNNEL_TYPE_GTPU,
327 ICE_FDIR_TUNNEL_TYPE_GTPU_EH,
331 TAILQ_HEAD(ice_flow_list, rte_flow);
333 struct ice_flow_parser_node;
334 TAILQ_HEAD(ice_parser_list, ice_flow_parser_node);
336 struct ice_fdir_filter_conf {
337 struct ice_fdir_fltr input;
338 enum ice_fdir_tunnel_type tunnel_type;
340 struct ice_fdir_counter *counter; /* flow specific counter context */
341 struct rte_flow_action_count act_count;
343 uint64_t input_set_o; /* used for non-tunnel or tunnel outer fields */
344 uint64_t input_set_i; /* only for tunnel inner fields */
347 struct ice_parser_profile *prof;
353 #define ICE_MAX_FDIR_FILTER_NUM (1024 * 16)
355 struct ice_fdir_fltr_pattern {
356 enum ice_fltr_ptype flow_type;
359 struct ice_fdir_v4 v4;
360 struct ice_fdir_v6 v6;
363 struct ice_fdir_udp_gtp gtpu_data;
364 struct ice_fdir_udp_gtp gtpu_mask;
366 struct ice_fdir_extra ext_data;
367 struct ice_fdir_extra ext_mask;
369 enum ice_fdir_tunnel_type tunnel_type;
372 #define ICE_FDIR_COUNTER_DEFAULT_POOL_SIZE 1
373 #define ICE_FDIR_COUNTER_MAX_POOL_SIZE 32
374 #define ICE_FDIR_COUNTERS_PER_BLOCK 256
375 #define ICE_FDIR_COUNTER_INDEX(base_idx) \
376 ((base_idx) * ICE_FDIR_COUNTERS_PER_BLOCK)
377 struct ice_fdir_counter_pool;
379 struct ice_fdir_counter {
380 TAILQ_ENTRY(ice_fdir_counter) next;
381 struct ice_fdir_counter_pool *pool;
390 TAILQ_HEAD(ice_fdir_counter_list, ice_fdir_counter);
392 struct ice_fdir_counter_pool {
393 TAILQ_ENTRY(ice_fdir_counter_pool) next;
394 struct ice_fdir_counter_list counter_list;
395 struct ice_fdir_counter counters[0];
398 TAILQ_HEAD(ice_fdir_counter_pool_list, ice_fdir_counter_pool);
400 struct ice_fdir_counter_pool_container {
401 struct ice_fdir_counter_pool_list pool_list;
402 struct ice_fdir_counter_pool *pools[ICE_FDIR_COUNTER_MAX_POOL_SIZE];
407 * A structure used to define fields of a FDIR related info.
409 struct ice_fdir_info {
410 struct ice_vsi *fdir_vsi; /* pointer to fdir VSI structure */
411 struct ice_tx_queue *txq;
412 struct ice_rx_queue *rxq;
413 void *prg_pkt; /* memory for fdir program packet */
414 uint64_t dma_addr; /* physic address of packet memory*/
415 const struct rte_memzone *mz;
416 struct ice_fdir_filter_conf conf;
418 struct ice_fdir_filter_conf **hash_map;
419 struct rte_hash *hash_table;
421 struct ice_fdir_counter_pool_container counter;
424 #define ICE_HASH_GTPU_CTX_EH_IP 0
425 #define ICE_HASH_GTPU_CTX_EH_IP_UDP 1
426 #define ICE_HASH_GTPU_CTX_EH_IP_TCP 2
427 #define ICE_HASH_GTPU_CTX_UP_IP 3
428 #define ICE_HASH_GTPU_CTX_UP_IP_UDP 4
429 #define ICE_HASH_GTPU_CTX_UP_IP_TCP 5
430 #define ICE_HASH_GTPU_CTX_DW_IP 6
431 #define ICE_HASH_GTPU_CTX_DW_IP_UDP 7
432 #define ICE_HASH_GTPU_CTX_DW_IP_TCP 8
433 #define ICE_HASH_GTPU_CTX_MAX 9
435 struct ice_hash_gtpu_ctx {
436 struct ice_rss_hash_cfg ctx[ICE_HASH_GTPU_CTX_MAX];
439 struct ice_hash_ctx {
440 struct ice_hash_gtpu_ctx gtpu4;
441 struct ice_hash_gtpu_ctx gtpu6;
444 struct ice_acl_conf {
445 struct ice_fdir_fltr input;
450 * A structure used to define fields of ACL related info.
452 struct ice_acl_info {
453 struct ice_acl_conf conf;
454 struct rte_bitmap *slots;
455 uint64_t hw_entry_id[MAX_ACL_NORMAL_ENTRIES];
458 TAILQ_HEAD(ice_shaper_profile_list, ice_tm_shaper_profile);
459 TAILQ_HEAD(ice_tm_node_list, ice_tm_node);
461 struct ice_tm_shaper_profile {
462 TAILQ_ENTRY(ice_tm_shaper_profile) node;
463 uint32_t shaper_profile_id;
464 uint32_t reference_count;
465 struct rte_tm_shaper_params profile;
468 /* Struct to store Traffic Manager node configuration. */
470 TAILQ_ENTRY(ice_tm_node) node;
475 uint32_t reference_count;
476 struct ice_tm_node *parent;
477 struct ice_tm_node **children;
478 struct ice_tm_shaper_profile *shaper_profile;
479 struct rte_tm_node_params params;
482 /* node type of Traffic Manager */
483 enum ice_tm_node_type {
484 ICE_TM_NODE_TYPE_PORT,
486 ICE_TM_NODE_TYPE_VSI,
487 ICE_TM_NODE_TYPE_QGROUP,
488 ICE_TM_NODE_TYPE_QUEUE,
489 ICE_TM_NODE_TYPE_MAX,
492 /* Struct to store all the Traffic Manager configuration. */
494 struct ice_shaper_profile_list shaper_profile_list;
495 struct ice_tm_node *root; /* root node - port */
496 struct ice_tm_node_list tc_list; /* node list for all the TCs */
497 struct ice_tm_node_list vsi_list; /* node list for all the VSIs */
498 struct ice_tm_node_list qgroup_list; /* node list for all the queue groups */
499 struct ice_tm_node_list queue_list; /* node list for all the queues */
501 uint32_t nb_vsi_node;
502 uint32_t nb_qgroup_node;
503 uint32_t nb_queue_node;
508 struct ice_adapter *adapter; /* The adapter this PF associate to */
509 struct ice_vsi *main_vsi; /* pointer to main VSI structure */
510 /* Used for next free software vsi idx.
511 * To save the effort, we don't recycle the index.
512 * Suppose the indexes are more than enough.
514 uint16_t next_vsi_idx;
515 uint16_t vsis_allocated;
516 uint16_t vsis_unallocated;
517 struct ice_res_pool_info qp_pool; /*Queue pair pool */
518 struct ice_res_pool_info msix_pool; /* MSIX interrupt pool */
519 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
520 struct rte_ether_addr dev_addr; /* PF device mac address */
521 uint64_t flags; /* PF feature flags */
522 uint16_t hash_lut_size; /* The size of hash lookup table */
523 uint16_t lan_nb_qp_max;
524 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
525 uint16_t base_queue; /* The base queue pairs index in the device */
526 uint8_t *proto_xtr; /* Protocol extraction type for all queues */
527 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
528 uint16_t fdir_qp_offset;
529 struct ice_fdir_info fdir; /* flow director info */
530 struct ice_acl_info acl; /* ACL info */
531 struct ice_hash_ctx hash_ctx;
532 uint16_t hw_prof_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
533 uint16_t fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX][ICE_FD_HW_SEG_MAX];
534 struct ice_hw_port_stats stats_offset;
535 struct ice_hw_port_stats stats;
536 /* internal packet statistics, it should be excluded from the total */
537 struct ice_eth_stats internal_stats_offset;
538 struct ice_eth_stats internal_stats;
540 bool adapter_stopped;
541 struct ice_flow_list flow_list;
542 rte_spinlock_t flow_ops_lock;
543 struct ice_parser_list rss_parser_list;
544 struct ice_parser_list perm_parser_list;
545 struct ice_parser_list dist_parser_list;
547 uint64_t old_rx_bytes;
548 uint64_t old_tx_bytes;
549 uint64_t supported_rxdid; /* bitmap for supported RXDID */
551 struct ice_tm_conf tm_conf;
554 #define ICE_MAX_QUEUE_NUM 2048
555 #define ICE_MAX_PIN_NUM 4
558 * Cache devargs parse result.
562 int safe_mode_support;
563 uint8_t proto_xtr_dflt;
564 int pipe_mode_support;
565 uint8_t proto_xtr[ICE_MAX_QUEUE_NUM];
571 * Structure to store fdir fv entry.
573 struct ice_fdir_prof_info {
574 struct ice_parser_profile prof;
575 u64 fdir_actived_cnt;
579 * Structure to store rss fv entry.
581 struct ice_rss_prof_info {
582 struct ice_parser_profile prof;
587 * Structure to store private data for each PF/VF instance.
590 /* Common for both PF and VF */
593 bool rx_bulk_alloc_allowed;
596 bool tx_simple_allowed;
597 /* ptype mapping table */
598 uint32_t ptype_tbl[ICE_MAX_PKT_TYPE] __rte_cache_min_aligned;
600 struct ice_devargs devargs;
601 enum ice_pkg_type active_pkg_type; /* loaded ddp package type */
602 uint16_t fdir_ref_cnt;
604 struct rte_timecounter systime_tc;
605 struct rte_timecounter rx_tstamp_tc;
606 struct rte_timecounter tx_tstamp_tc;
609 struct ice_fdir_prof_info fdir_prof_info[ICE_MAX_PTGS];
610 struct ice_rss_prof_info rss_prof_info[ICE_MAX_PTGS];
611 /* True if DCF state of the associated PF is on */
613 struct ice_parser *psr;
619 bool rx_vec_offload_support;
623 struct ice_vsi_vlan_pvid_info {
624 uint16_t on; /* Enable or disable pvid */
626 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
628 /* Valid in case 'on' is cleared. 'tagged' will reject
629 * tagged packets, while 'untagged' will reject
638 #define ICE_DEV_TO_PCI(eth_dev) \
639 RTE_DEV_TO_PCI((eth_dev)->device)
641 /* ICE_DEV_PRIVATE_TO */
642 #define ICE_DEV_PRIVATE_TO_PF(adapter) \
643 (&((struct ice_adapter *)adapter)->pf)
644 #define ICE_DEV_PRIVATE_TO_HW(adapter) \
645 (&((struct ice_adapter *)adapter)->hw)
646 #define ICE_DEV_PRIVATE_TO_ADAPTER(adapter) \
647 ((struct ice_adapter *)adapter)
650 #define ICE_VSI_TO_HW(vsi) \
651 (&(((struct ice_vsi *)vsi)->adapter->hw))
652 #define ICE_VSI_TO_PF(vsi) \
653 (&(((struct ice_vsi *)vsi)->adapter->pf))
656 #define ICE_PF_TO_HW(pf) \
657 (&(((struct ice_pf *)pf)->adapter->hw))
658 #define ICE_PF_TO_ADAPTER(pf) \
659 ((struct ice_adapter *)(pf)->adapter)
660 #define ICE_PF_TO_ETH_DEV(pf) \
661 (((struct ice_pf *)pf)->adapter->eth_dev)
663 bool is_ice_supported(struct rte_eth_dev *dev);
665 ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn);
667 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type);
669 ice_release_vsi(struct ice_vsi *vsi);
670 void ice_vsi_enable_queues_intr(struct ice_vsi *vsi);
671 void ice_vsi_disable_queues_intr(struct ice_vsi *vsi);
672 void ice_vsi_queues_bind_intr(struct ice_vsi *vsi);
673 int ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
674 struct ice_rss_hash_cfg *cfg);
675 int ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
676 struct ice_rss_hash_cfg *cfg);
677 void ice_tm_conf_init(struct rte_eth_dev *dev);
678 void ice_tm_conf_uninit(struct rte_eth_dev *dev);
679 extern const struct rte_tm_ops ice_tm_ops;
682 ice_align_floor(int n)
686 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
689 #define ICE_PHY_TYPE_SUPPORT_50G(phy_type) \
690 (((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CR2) || \
691 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR2) || \
692 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR2) || \
693 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR2) || \
694 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC) || \
695 ((phy_type) & ICE_PHY_TYPE_LOW_50G_LAUI2) || \
696 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC) || \
697 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI2) || \
698 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_CP) || \
699 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_SR) || \
700 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_FR) || \
701 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_LR) || \
702 ((phy_type) & ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4) || \
703 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC) || \
704 ((phy_type) & ICE_PHY_TYPE_LOW_50G_AUI1))
706 #define ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type) \
707 (((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR4) || \
708 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR4) || \
709 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_LR4) || \
710 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR4) || \
711 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC) || \
712 ((phy_type) & ICE_PHY_TYPE_LOW_100G_CAUI4) || \
713 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC) || \
714 ((phy_type) & ICE_PHY_TYPE_LOW_100G_AUI4) || \
715 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4) || \
716 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4) || \
717 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_CP2) || \
718 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_SR2) || \
719 ((phy_type) & ICE_PHY_TYPE_LOW_100GBASE_DR))
721 #define ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type) \
722 (((phy_type) & ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4) || \
723 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC) || \
724 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_CAUI2) || \
725 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC) || \
726 ((phy_type) & ICE_PHY_TYPE_HIGH_100G_AUI2))
728 #endif /* _ICE_ETHDEV_H_ */