drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <ethdev_driver.h>
   6 #include <rte_net.h>
   7 #include <rte_vect.h>
   8
   9 #include "rte_pmd_ice.h"
  10 #include "ice_rxtx.h"
  11 #include "ice_rxtx_vec_common.h"
  12
  13 #define ICE_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM |              \
  14                 RTE_MBUF_F_TX_L4_MASK |          \
  15                 RTE_MBUF_F_TX_TCP_SEG |          \
  16                 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
  17
  18 /* Offset of mbuf dynamic field for protocol extraction data */
  19 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  20
  21 /* Mask of mbuf dynamic flags for protocol extraction type */
  22 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  27 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  28
  29 static int
  30 ice_monitor_callback(const uint64_t value,
  31                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  32 {
  33         const uint64_t m = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
  34         /*
  35          * we expect the DD bit to be set to 1 if this descriptor was already
  36          * written to.
  37          */
  38         return (value & m) == m ? -1 : 0;
  39 }
  40
  41 int
  42 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  43 {
  44         volatile union ice_rx_flex_desc *rxdp;
  45         struct ice_rx_queue *rxq = rx_queue;
  46         uint16_t desc;
  47
  48         desc = rxq->rx_tail;
  49         rxdp = &rxq->rx_ring[desc];
  50         /* watch for changes in status bit */
  51         pmc->addr = &rxdp->wb.status_error0;
  52
  53         /* comparison callback */
  54         pmc->fn = ice_monitor_callback;
  55
  56         /* register is 16-bit */
  57         pmc->size = sizeof(uint16_t);
  58
  59         return 0;
  60 }
  61
  62
  63 static inline uint8_t
  64 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  65 {
  66         static uint8_t rxdid_map[] = {
  67                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_OVS,
  68                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  69                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  70                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  71                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  72                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  73                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  74         };
  75
  76         return xtr_type < RTE_DIM(rxdid_map) ?
  77                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
  78 }
  79
  80 static inline void
  81 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
  82                                        struct rte_mbuf *mb,
  83                                        volatile union ice_rx_flex_desc *rxdp)
  84 {
  85         volatile struct ice_32b_rx_flex_desc_comms *desc =
  86                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
  87         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
  88
  89         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  90                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
  91                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  92         }
  93
  94 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  95         if (desc->flow_id != 0xFFFFFFFF) {
  96                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
  97                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  98         }
  99 #endif
 100 }
 101
 102 static inline void
 103 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
 104                                    struct rte_mbuf *mb,
 105                                    volatile union ice_rx_flex_desc *rxdp)
 106 {
 107         volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
 108                         (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
 109 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 110         uint16_t stat_err;
 111 #endif
 112
 113         if (desc->flow_id != 0xFFFFFFFF) {
 114                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 115                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 116         }
 117
 118 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 119         stat_err = rte_le_to_cpu_16(desc->status_error0);
 120         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 121                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 122                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 123         }
 124 #endif
 125 }
 126
 127 static inline void
 128 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
 129                                       struct rte_mbuf *mb,
 130                                       volatile union ice_rx_flex_desc *rxdp)
 131 {
 132         volatile struct ice_32b_rx_flex_desc_comms *desc =
 133                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 134         uint16_t stat_err;
 135
 136         stat_err = rte_le_to_cpu_16(desc->status_error0);
 137         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 138                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 139                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 140         }
 141
 142 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 143         if (desc->flow_id != 0xFFFFFFFF) {
 144                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 145                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 146         }
 147
 148         if (rxq->xtr_ol_flag) {
 149                 uint32_t metadata = 0;
 150
 151                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 152
 153                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 154                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 155
 156                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 157                         metadata |=
 158                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 159
 160                 if (metadata) {
 161                         mb->ol_flags |= rxq->xtr_ol_flag;
 162
 163                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 164                 }
 165         }
 166 #else
 167         RTE_SET_USED(rxq);
 168 #endif
 169 }
 170
 171 static inline void
 172 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
 173                                       struct rte_mbuf *mb,
 174                                       volatile union ice_rx_flex_desc *rxdp)
 175 {
 176         volatile struct ice_32b_rx_flex_desc_comms *desc =
 177                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 178         uint16_t stat_err;
 179
 180         stat_err = rte_le_to_cpu_16(desc->status_error0);
 181         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 182                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 183                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 184         }
 185
 186 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 187         if (desc->flow_id != 0xFFFFFFFF) {
 188                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 189                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 190         }
 191
 192         if (rxq->xtr_ol_flag) {
 193                 uint32_t metadata = 0;
 194
 195                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 196                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 197                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 198                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 199
 200                 if (metadata) {
 201                         mb->ol_flags |= rxq->xtr_ol_flag;
 202
 203                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 204                 }
 205         }
 206 #else
 207         RTE_SET_USED(rxq);
 208 #endif
 209 }
 210
 211 static const ice_rxd_to_pkt_fields_t rxd_to_pkt_fields_ops[] = {
 212         [ICE_RXDID_COMMS_AUX_VLAN] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 213         [ICE_RXDID_COMMS_AUX_IPV4] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 214         [ICE_RXDID_COMMS_AUX_IPV6] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 215         [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 216         [ICE_RXDID_COMMS_AUX_TCP] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 217         [ICE_RXDID_COMMS_AUX_IP_OFFSET] = ice_rxd_to_pkt_fields_by_comms_aux_v2,
 218         [ICE_RXDID_COMMS_GENERIC] = ice_rxd_to_pkt_fields_by_comms_generic,
 219         [ICE_RXDID_COMMS_OVS] = ice_rxd_to_pkt_fields_by_comms_ovs,
 220 };
 221
 222 void
 223 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
 224 {
 225         rxq->rxdid = rxdid;
 226
 227         switch (rxdid) {
 228         case ICE_RXDID_COMMS_AUX_VLAN:
 229                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
 230                 break;
 231
 232         case ICE_RXDID_COMMS_AUX_IPV4:
 233                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
 234                 break;
 235
 236         case ICE_RXDID_COMMS_AUX_IPV6:
 237                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
 238                 break;
 239
 240         case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
 241                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
 242                 break;
 243
 244         case ICE_RXDID_COMMS_AUX_TCP:
 245                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
 246                 break;
 247
 248         case ICE_RXDID_COMMS_AUX_IP_OFFSET:
 249                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
 250                 break;
 251
 252         case ICE_RXDID_COMMS_GENERIC:
 253                 /* fallthrough */
 254         case ICE_RXDID_COMMS_OVS:
 255                 break;
 256
 257         default:
 258                 /* update this according to the RXDID for PROTO_XTR_NONE */
 259                 rxq->rxdid = ICE_RXDID_COMMS_OVS;
 260                 break;
 261         }
 262
 263         if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
 264                 rxq->xtr_ol_flag = 0;
 265 }
 266
 267 static enum ice_status
 268 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
 269 {
 270         struct ice_vsi *vsi = rxq->vsi;
 271         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 272         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
 273         struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
 274         struct ice_rlan_ctx rx_ctx;
 275         enum ice_status err;
 276         uint16_t buf_size;
 277         uint32_t rxdid = ICE_RXDID_COMMS_OVS;
 278         uint32_t regval;
 279         struct ice_adapter *ad = rxq->vsi->adapter;
 280         uint32_t frame_size = dev_data->mtu + ICE_ETH_OVERHEAD;
 281
 282         /* Set buffer size as the head split is disabled. */
 283         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 284                               RTE_PKTMBUF_HEADROOM);
 285         rxq->rx_hdr_len = 0;
 286         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
 287         rxq->max_pkt_len =
 288                 RTE_MIN((uint32_t)ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
 289                         frame_size);
 290
 291         if (rxq->max_pkt_len <= RTE_ETHER_MIN_LEN ||
 292             rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 293                 PMD_DRV_LOG(ERR, "maximum packet length must "
 294                             "be larger than %u and smaller than %u",
 295                             (uint32_t)RTE_ETHER_MIN_LEN,
 296                             (uint32_t)ICE_FRAME_SIZE_MAX);
 297                 return -EINVAL;
 298         }
 299
 300         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
 301                 /* Register mbuf field and flag for Rx timestamp */
 302                 err = rte_mbuf_dyn_rx_timestamp_register(
 303                                 &ice_timestamp_dynfield_offset,
 304                                 &ice_timestamp_dynflag);
 305                 if (err) {
 306                         PMD_DRV_LOG(ERR,
 307                                 "Cannot register mbuf field/flag for timestamp");
 308                         return -EINVAL;
 309                 }
 310         }
 311
 312         memset(&rx_ctx, 0, sizeof(rx_ctx));
 313
 314         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 315         rx_ctx.qlen = rxq->nb_rx_desc;
 316         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 317         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 318         rx_ctx.dtype = 0; /* No Header Split mode */
 319 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 320         rx_ctx.dsize = 1; /* 32B descriptors */
 321 #endif
 322         rx_ctx.rxmax = rxq->max_pkt_len;
 323         /* TPH: Transaction Layer Packet (TLP) processing hints */
 324         rx_ctx.tphrdesc_ena = 1;
 325         rx_ctx.tphwdesc_ena = 1;
 326         rx_ctx.tphdata_ena = 1;
 327         rx_ctx.tphhead_ena = 1;
 328         /* Low Receive Queue Threshold defined in 64 descriptors units.
 329          * When the number of free descriptors goes below the lrxqthresh,
 330          * an immediate interrupt is triggered.
 331          */
 332         rx_ctx.lrxqthresh = 2;
 333         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 334         rx_ctx.l2tsel = 1;
 335         rx_ctx.showiv = 0;
 336         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 337
 338         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 339
 340         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 341                     rxq->port_id, rxq->queue_id, rxdid);
 342
 343         if (!(pf->supported_rxdid & BIT(rxdid))) {
 344                 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
 345                             rxdid);
 346                 return -EINVAL;
 347         }
 348
 349         ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
 350
 351         /* Enable Flexible Descriptors in the queue context which
 352          * allows this driver to select a specific receive descriptor format
 353          */
 354         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 355                 QRXFLXP_CNTXT_RXDID_IDX_M;
 356
 357         /* increasing context priority to pick up profile ID;
 358          * default is 0x01; setting to 0x03 to ensure profile
 359          * is programming if prev context is of same priority
 360          */
 361         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 362                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 363
 364         if (ad->ptp_ena || rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
 365                 regval |= QRXFLXP_CNTXT_TS_M;
 366
 367         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 368
 369         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 370         if (err) {
 371                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 372                             rxq->queue_id);
 373                 return -EINVAL;
 374         }
 375         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 376         if (err) {
 377                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 378                             rxq->queue_id);
 379                 return -EINVAL;
 380         }
 381
 382         /* Check if scattered RX needs to be used. */
 383         if (frame_size > buf_size)
 384                 dev_data->scattered_rx = 1;
 385
 386         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 387
 388         /* Init the Rx tail register*/
 389         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 390
 391         return 0;
 392 }
 393
 394 /* Allocate mbufs for all descriptors in rx queue */
 395 static int
 396 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 397 {
 398         struct ice_rx_entry *rxe = rxq->sw_ring;
 399         uint64_t dma_addr;
 400         uint16_t i;
 401
 402         for (i = 0; i < rxq->nb_rx_desc; i++) {
 403                 volatile union ice_rx_flex_desc *rxd;
 404                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 405
 406                 if (unlikely(!mbuf)) {
 407                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 408                         return -ENOMEM;
 409                 }
 410
 411                 rte_mbuf_refcnt_set(mbuf, 1);
 412                 mbuf->next = NULL;
 413                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 414                 mbuf->nb_segs = 1;
 415                 mbuf->port = rxq->port_id;
 416
 417                 dma_addr =
 418                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 419
 420                 rxd = &rxq->rx_ring[i];
 421                 rxd->read.pkt_addr = dma_addr;
 422                 rxd->read.hdr_addr = 0;
 423 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 424                 rxd->read.rsvd1 = 0;
 425                 rxd->read.rsvd2 = 0;
 426 #endif
 427                 rxe[i].mbuf = mbuf;
 428         }
 429
 430         return 0;
 431 }
 432
 433 /* Free all mbufs for descriptors in rx queue */
 434 static void
 435 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 436 {
 437         uint16_t i;
 438
 439         if (!rxq || !rxq->sw_ring) {
 440                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 441                 return;
 442         }
 443
 444         for (i = 0; i < rxq->nb_rx_desc; i++) {
 445                 if (rxq->sw_ring[i].mbuf) {
 446                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 447                         rxq->sw_ring[i].mbuf = NULL;
 448                 }
 449         }
 450         if (rxq->rx_nb_avail == 0)
 451                 return;
 452         for (i = 0; i < rxq->rx_nb_avail; i++)
 453                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 454
 455         rxq->rx_nb_avail = 0;
 456 }
 457
 458 /* turn on or off rx queue
 459  * @q_idx: queue index in pf scope
 460  * @on: turn on or off the queue
 461  */
 462 static int
 463 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 464 {
 465         uint32_t reg;
 466         uint16_t j;
 467
 468         /* QRX_CTRL = QRX_ENA */
 469         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 470
 471         if (on) {
 472                 if (reg & QRX_CTRL_QENA_STAT_M)
 473                         return 0; /* Already on, skip */
 474                 reg |= QRX_CTRL_QENA_REQ_M;
 475         } else {
 476                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 477                         return 0; /* Already off, skip */
 478                 reg &= ~QRX_CTRL_QENA_REQ_M;
 479         }
 480
 481         /* Write the register */
 482         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 483         /* Check the result. It is said that QENA_STAT
 484          * follows the QENA_REQ not more than 10 use.
 485          * TODO: need to change the wait counter later
 486          */
 487         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 488                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 489                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 490                 if (on) {
 491                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 492                             (reg & QRX_CTRL_QENA_STAT_M))
 493                                 break;
 494                 } else {
 495                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 496                             !(reg & QRX_CTRL_QENA_STAT_M))
 497                                 break;
 498                 }
 499         }
 500
 501         /* Check if it is timeout */
 502         if (j >= ICE_CHK_Q_ENA_COUNT) {
 503                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 504                             (on ? "enable" : "disable"), q_idx);
 505                 return -ETIMEDOUT;
 506         }
 507
 508         return 0;
 509 }
 510
 511 static inline int
 512 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 513 {
 514         int ret = 0;
 515
 516         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 517                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 518                              "rxq->rx_free_thresh=%d, "
 519                              "ICE_RX_MAX_BURST=%d",
 520                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 521                 ret = -EINVAL;
 522         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 523                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 524                              "rxq->rx_free_thresh=%d, "
 525                              "rxq->nb_rx_desc=%d",
 526                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 527                 ret = -EINVAL;
 528         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 529                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 530                              "rxq->nb_rx_desc=%d, "
 531                              "rxq->rx_free_thresh=%d",
 532                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 533                 ret = -EINVAL;
 534         }
 535
 536         return ret;
 537 }
 538
 539 /* reset fields in ice_rx_queue back to default */
 540 static void
 541 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 542 {
 543         unsigned int i;
 544         uint16_t len;
 545
 546         if (!rxq) {
 547                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 548                 return;
 549         }
 550
 551         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 552
 553         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 554                 ((volatile char *)rxq->rx_ring)[i] = 0;
 555
 556         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 557         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 558                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 559
 560         rxq->rx_nb_avail = 0;
 561         rxq->rx_next_avail = 0;
 562         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 563
 564         rxq->rx_tail = 0;
 565         rxq->nb_rx_hold = 0;
 566         rxq->pkt_first_seg = NULL;
 567         rxq->pkt_last_seg = NULL;
 568
 569         rxq->rxrearm_start = 0;
 570         rxq->rxrearm_nb = 0;
 571 }
 572
 573 int
 574 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 575 {
 576         struct ice_rx_queue *rxq;
 577         int err;
 578         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 579
 580         PMD_INIT_FUNC_TRACE();
 581
 582         if (rx_queue_id >= dev->data->nb_rx_queues) {
 583                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 584                             rx_queue_id, dev->data->nb_rx_queues);
 585                 return -EINVAL;
 586         }
 587
 588         rxq = dev->data->rx_queues[rx_queue_id];
 589         if (!rxq || !rxq->q_set) {
 590                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 591                             rx_queue_id);
 592                 return -EINVAL;
 593         }
 594
 595         err = ice_program_hw_rx_queue(rxq);
 596         if (err) {
 597                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 598                             rx_queue_id);
 599                 return -EIO;
 600         }
 601
 602         err = ice_alloc_rx_queue_mbufs(rxq);
 603         if (err) {
 604                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 605                 return -ENOMEM;
 606         }
 607
 608         /* Init the RX tail register. */
 609         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 610
 611         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 612         if (err) {
 613                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 614                             rx_queue_id);
 615
 616                 rxq->rx_rel_mbufs(rxq);
 617                 ice_reset_rx_queue(rxq);
 618                 return -EINVAL;
 619         }
 620
 621         dev->data->rx_queue_state[rx_queue_id] =
 622                 RTE_ETH_QUEUE_STATE_STARTED;
 623
 624         return 0;
 625 }
 626
 627 int
 628 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 629 {
 630         struct ice_rx_queue *rxq;
 631         int err;
 632         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 633
 634         if (rx_queue_id < dev->data->nb_rx_queues) {
 635                 rxq = dev->data->rx_queues[rx_queue_id];
 636
 637                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 638                 if (err) {
 639                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 640                                     rx_queue_id);
 641                         return -EINVAL;
 642                 }
 643                 rxq->rx_rel_mbufs(rxq);
 644                 ice_reset_rx_queue(rxq);
 645                 dev->data->rx_queue_state[rx_queue_id] =
 646                         RTE_ETH_QUEUE_STATE_STOPPED;
 647         }
 648
 649         return 0;
 650 }
 651
 652 int
 653 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 654 {
 655         struct ice_tx_queue *txq;
 656         int err;
 657         struct ice_vsi *vsi;
 658         struct ice_hw *hw;
 659         struct ice_aqc_add_tx_qgrp *txq_elem;
 660         struct ice_tlan_ctx tx_ctx;
 661         int buf_len;
 662
 663         PMD_INIT_FUNC_TRACE();
 664
 665         if (tx_queue_id >= dev->data->nb_tx_queues) {
 666                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 667                             tx_queue_id, dev->data->nb_tx_queues);
 668                 return -EINVAL;
 669         }
 670
 671         txq = dev->data->tx_queues[tx_queue_id];
 672         if (!txq || !txq->q_set) {
 673                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 674                             tx_queue_id);
 675                 return -EINVAL;
 676         }
 677
 678         buf_len = ice_struct_size(txq_elem, txqs, 1);
 679         txq_elem = ice_malloc(hw, buf_len);
 680         if (!txq_elem)
 681                 return -ENOMEM;
 682
 683         vsi = txq->vsi;
 684         hw = ICE_VSI_TO_HW(vsi);
 685
 686         memset(&tx_ctx, 0, sizeof(tx_ctx));
 687         txq_elem->num_txqs = 1;
 688         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 689
 690         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 691         tx_ctx.qlen = txq->nb_tx_desc;
 692         tx_ctx.pf_num = hw->pf_id;
 693         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 694         tx_ctx.src_vsi = vsi->vsi_id;
 695         tx_ctx.port_num = hw->port_info->lport;
 696         tx_ctx.tso_ena = 1; /* tso enable */
 697         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 698         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 699         tx_ctx.tsyn_ena = 1;
 700
 701         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 702                     ice_tlan_ctx_info);
 703
 704         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 705
 706         /* Init the Tx tail register*/
 707         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 708
 709         /* Fix me, we assume TC always 0 here */
 710         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 711                         txq_elem, buf_len, NULL);
 712         if (err) {
 713                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 714                 rte_free(txq_elem);
 715                 return -EIO;
 716         }
 717         /* store the schedule node id */
 718         txq->q_teid = txq_elem->txqs[0].q_teid;
 719
 720         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 721
 722         rte_free(txq_elem);
 723         return 0;
 724 }
 725
 726 static enum ice_status
 727 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 728 {
 729         struct ice_vsi *vsi = rxq->vsi;
 730         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 731         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 732         struct ice_rlan_ctx rx_ctx;
 733         enum ice_status err;
 734         uint32_t regval;
 735
 736         rxq->rx_hdr_len = 0;
 737         rxq->rx_buf_len = 1024;
 738
 739         memset(&rx_ctx, 0, sizeof(rx_ctx));
 740
 741         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 742         rx_ctx.qlen = rxq->nb_rx_desc;
 743         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 744         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 745         rx_ctx.dtype = 0; /* No Header Split mode */
 746         rx_ctx.dsize = 1; /* 32B descriptors */
 747         rx_ctx.rxmax = ICE_ETH_MAX_LEN;
 748         /* TPH: Transaction Layer Packet (TLP) processing hints */
 749         rx_ctx.tphrdesc_ena = 1;
 750         rx_ctx.tphwdesc_ena = 1;
 751         rx_ctx.tphdata_ena = 1;
 752         rx_ctx.tphhead_ena = 1;
 753         /* Low Receive Queue Threshold defined in 64 descriptors units.
 754          * When the number of free descriptors goes below the lrxqthresh,
 755          * an immediate interrupt is triggered.
 756          */
 757         rx_ctx.lrxqthresh = 2;
 758         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 759         rx_ctx.l2tsel = 1;
 760         rx_ctx.showiv = 0;
 761         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 762
 763         /* Enable Flexible Descriptors in the queue context which
 764          * allows this driver to select a specific receive descriptor format
 765          */
 766         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 767                 QRXFLXP_CNTXT_RXDID_IDX_M;
 768
 769         /* increasing context priority to pick up profile ID;
 770          * default is 0x01; setting to 0x03 to ensure profile
 771          * is programming if prev context is of same priority
 772          */
 773         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 774                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 775
 776         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 777
 778         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 779         if (err) {
 780                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 781                             rxq->queue_id);
 782                 return -EINVAL;
 783         }
 784         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 785         if (err) {
 786                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 787                             rxq->queue_id);
 788                 return -EINVAL;
 789         }
 790
 791         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 792
 793         /* Init the Rx tail register*/
 794         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 795
 796         return 0;
 797 }
 798
 799 int
 800 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 801 {
 802         struct ice_rx_queue *rxq;
 803         int err;
 804         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 805         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 806
 807         PMD_INIT_FUNC_TRACE();
 808
 809         rxq = pf->fdir.rxq;
 810         if (!rxq || !rxq->q_set) {
 811                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 812                             rx_queue_id);
 813                 return -EINVAL;
 814         }
 815
 816         err = ice_fdir_program_hw_rx_queue(rxq);
 817         if (err) {
 818                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 819                             rx_queue_id);
 820                 return -EIO;
 821         }
 822
 823         /* Init the RX tail register. */
 824         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 825
 826         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 827         if (err) {
 828                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 829                             rx_queue_id);
 830
 831                 ice_reset_rx_queue(rxq);
 832                 return -EINVAL;
 833         }
 834
 835         return 0;
 836 }
 837
 838 int
 839 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 840 {
 841         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 842         struct ice_tx_queue *txq;
 843         int err;
 844         struct ice_vsi *vsi;
 845         struct ice_hw *hw;
 846         struct ice_aqc_add_tx_qgrp *txq_elem;
 847         struct ice_tlan_ctx tx_ctx;
 848         int buf_len;
 849
 850         PMD_INIT_FUNC_TRACE();
 851
 852         txq = pf->fdir.txq;
 853         if (!txq || !txq->q_set) {
 854                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 855                             tx_queue_id);
 856                 return -EINVAL;
 857         }
 858
 859         buf_len = ice_struct_size(txq_elem, txqs, 1);
 860         txq_elem = ice_malloc(hw, buf_len);
 861         if (!txq_elem)
 862                 return -ENOMEM;
 863
 864         vsi = txq->vsi;
 865         hw = ICE_VSI_TO_HW(vsi);
 866
 867         memset(&tx_ctx, 0, sizeof(tx_ctx));
 868         txq_elem->num_txqs = 1;
 869         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 870
 871         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 872         tx_ctx.qlen = txq->nb_tx_desc;
 873         tx_ctx.pf_num = hw->pf_id;
 874         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 875         tx_ctx.src_vsi = vsi->vsi_id;
 876         tx_ctx.port_num = hw->port_info->lport;
 877         tx_ctx.tso_ena = 1; /* tso enable */
 878         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 879         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 880
 881         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 882                     ice_tlan_ctx_info);
 883
 884         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 885
 886         /* Init the Tx tail register*/
 887         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 888
 889         /* Fix me, we assume TC always 0 here */
 890         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 891                               txq_elem, buf_len, NULL);
 892         if (err) {
 893                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 894                 rte_free(txq_elem);
 895                 return -EIO;
 896         }
 897         /* store the schedule node id */
 898         txq->q_teid = txq_elem->txqs[0].q_teid;
 899
 900         rte_free(txq_elem);
 901         return 0;
 902 }
 903
 904 /* Free all mbufs for descriptors in tx queue */
 905 static void
 906 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 907 {
 908         uint16_t i;
 909
 910         if (!txq || !txq->sw_ring) {
 911                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 912                 return;
 913         }
 914
 915         for (i = 0; i < txq->nb_tx_desc; i++) {
 916                 if (txq->sw_ring[i].mbuf) {
 917                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 918                         txq->sw_ring[i].mbuf = NULL;
 919                 }
 920         }
 921 }
 922
 923 static void
 924 ice_reset_tx_queue(struct ice_tx_queue *txq)
 925 {
 926         struct ice_tx_entry *txe;
 927         uint16_t i, prev, size;
 928
 929         if (!txq) {
 930                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 931                 return;
 932         }
 933
 934         txe = txq->sw_ring;
 935         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 936         for (i = 0; i < size; i++)
 937                 ((volatile char *)txq->tx_ring)[i] = 0;
 938
 939         prev = (uint16_t)(txq->nb_tx_desc - 1);
 940         for (i = 0; i < txq->nb_tx_desc; i++) {
 941                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 942
 943                 txd->cmd_type_offset_bsz =
 944                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 945                 txe[i].mbuf =  NULL;
 946                 txe[i].last_id = i;
 947                 txe[prev].next_id = i;
 948                 prev = i;
 949         }
 950
 951         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 952         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 953
 954         txq->tx_tail = 0;
 955         txq->nb_tx_used = 0;
 956
 957         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 958         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 959 }
 960
 961 int
 962 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 963 {
 964         struct ice_tx_queue *txq;
 965         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 967         struct ice_vsi *vsi = pf->main_vsi;
 968         enum ice_status status;
 969         uint16_t q_ids[1];
 970         uint32_t q_teids[1];
 971         uint16_t q_handle = tx_queue_id;
 972
 973         if (tx_queue_id >= dev->data->nb_tx_queues) {
 974                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 975                             tx_queue_id, dev->data->nb_tx_queues);
 976                 return -EINVAL;
 977         }
 978
 979         txq = dev->data->tx_queues[tx_queue_id];
 980         if (!txq) {
 981                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 982                             tx_queue_id);
 983                 return -EINVAL;
 984         }
 985
 986         q_ids[0] = txq->reg_idx;
 987         q_teids[0] = txq->q_teid;
 988
 989         /* Fix me, we assume TC always 0 here */
 990         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 991                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 992         if (status != ICE_SUCCESS) {
 993                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 994                 return -EINVAL;
 995         }
 996
 997         txq->tx_rel_mbufs(txq);
 998         ice_reset_tx_queue(txq);
 999         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1000
1001         return 0;
1002 }
1003
1004 int
1005 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1006 {
1007         struct ice_rx_queue *rxq;
1008         int err;
1009         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1010         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1011
1012         rxq = pf->fdir.rxq;
1013
1014         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1015         if (err) {
1016                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1017                             rx_queue_id);
1018                 return -EINVAL;
1019         }
1020         rxq->rx_rel_mbufs(rxq);
1021
1022         return 0;
1023 }
1024
1025 int
1026 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1027 {
1028         struct ice_tx_queue *txq;
1029         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031         struct ice_vsi *vsi = pf->main_vsi;
1032         enum ice_status status;
1033         uint16_t q_ids[1];
1034         uint32_t q_teids[1];
1035         uint16_t q_handle = tx_queue_id;
1036
1037         txq = pf->fdir.txq;
1038         if (!txq) {
1039                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1040                             tx_queue_id);
1041                 return -EINVAL;
1042         }
1043         vsi = txq->vsi;
1044
1045         q_ids[0] = txq->reg_idx;
1046         q_teids[0] = txq->q_teid;
1047
1048         /* Fix me, we assume TC always 0 here */
1049         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1050                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1051         if (status != ICE_SUCCESS) {
1052                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1053                 return -EINVAL;
1054         }
1055
1056         txq->tx_rel_mbufs(txq);
1057
1058         return 0;
1059 }
1060
1061 int
1062 ice_rx_queue_setup(struct rte_eth_dev *dev,
1063                    uint16_t queue_idx,
1064                    uint16_t nb_desc,
1065                    unsigned int socket_id,
1066                    const struct rte_eth_rxconf *rx_conf,
1067                    struct rte_mempool *mp)
1068 {
1069         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1070         struct ice_adapter *ad =
1071                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1072         struct ice_vsi *vsi = pf->main_vsi;
1073         struct ice_rx_queue *rxq;
1074         const struct rte_memzone *rz;
1075         uint32_t ring_size;
1076         uint16_t len;
1077         int use_def_burst_func = 1;
1078         uint64_t offloads;
1079
1080         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1081             nb_desc > ICE_MAX_RING_DESC ||
1082             nb_desc < ICE_MIN_RING_DESC) {
1083                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1084                              "invalid", nb_desc);
1085                 return -EINVAL;
1086         }
1087
1088         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1089
1090         /* Free memory if needed */
1091         if (dev->data->rx_queues[queue_idx]) {
1092                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1093                 dev->data->rx_queues[queue_idx] = NULL;
1094         }
1095
1096         /* Allocate the rx queue data structure */
1097         rxq = rte_zmalloc_socket(NULL,
1098                                  sizeof(struct ice_rx_queue),
1099                                  RTE_CACHE_LINE_SIZE,
1100                                  socket_id);
1101         if (!rxq) {
1102                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1103                              "rx queue data structure");
1104                 return -ENOMEM;
1105         }
1106         rxq->mp = mp;
1107         rxq->nb_rx_desc = nb_desc;
1108         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1109         rxq->queue_id = queue_idx;
1110         rxq->offloads = offloads;
1111
1112         rxq->reg_idx = vsi->base_queue + queue_idx;
1113         rxq->port_id = dev->data->port_id;
1114         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1115                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1116         else
1117                 rxq->crc_len = 0;
1118
1119         rxq->drop_en = rx_conf->rx_drop_en;
1120         rxq->vsi = vsi;
1121         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1122         rxq->proto_xtr = pf->proto_xtr != NULL ?
1123                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1124
1125         /* Allocate the maximum number of RX ring hardware descriptor. */
1126         len = ICE_MAX_RING_DESC;
1127
1128         /**
1129          * Allocating a little more memory because vectorized/bulk_alloc Rx
1130          * functions doesn't check boundaries each time.
1131          */
1132         len += ICE_RX_MAX_BURST;
1133
1134         /* Allocate the maximum number of RX ring hardware descriptor. */
1135         ring_size = sizeof(union ice_rx_flex_desc) * len;
1136         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1137         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1138                                       ring_size, ICE_RING_BASE_ALIGN,
1139                                       socket_id);
1140         if (!rz) {
1141                 ice_rx_queue_release(rxq);
1142                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1143                 return -ENOMEM;
1144         }
1145
1146         rxq->mz = rz;
1147         /* Zero all the descriptors in the ring. */
1148         memset(rz->addr, 0, ring_size);
1149
1150         rxq->rx_ring_dma = rz->iova;
1151         rxq->rx_ring = rz->addr;
1152
1153         /* always reserve more for bulk alloc */
1154         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1155
1156         /* Allocate the software ring. */
1157         rxq->sw_ring = rte_zmalloc_socket(NULL,
1158                                           sizeof(struct ice_rx_entry) * len,
1159                                           RTE_CACHE_LINE_SIZE,
1160                                           socket_id);
1161         if (!rxq->sw_ring) {
1162                 ice_rx_queue_release(rxq);
1163                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1164                 return -ENOMEM;
1165         }
1166
1167         ice_reset_rx_queue(rxq);
1168         rxq->q_set = true;
1169         dev->data->rx_queues[queue_idx] = rxq;
1170         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1171
1172         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1173
1174         if (!use_def_burst_func) {
1175                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1176                              "satisfied. Rx Burst Bulk Alloc function will be "
1177                              "used on port=%d, queue=%d.",
1178                              rxq->port_id, rxq->queue_id);
1179         } else {
1180                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1181                              "not satisfied, Scattered Rx is requested. "
1182                              "on port=%d, queue=%d.",
1183                              rxq->port_id, rxq->queue_id);
1184                 ad->rx_bulk_alloc_allowed = false;
1185         }
1186
1187         return 0;
1188 }
1189
1190 void
1191 ice_rx_queue_release(void *rxq)
1192 {
1193         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1194
1195         if (!q) {
1196                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1197                 return;
1198         }
1199
1200         q->rx_rel_mbufs(q);
1201         rte_free(q->sw_ring);
1202         rte_memzone_free(q->mz);
1203         rte_free(q);
1204 }
1205
1206 int
1207 ice_tx_queue_setup(struct rte_eth_dev *dev,
1208                    uint16_t queue_idx,
1209                    uint16_t nb_desc,
1210                    unsigned int socket_id,
1211                    const struct rte_eth_txconf *tx_conf)
1212 {
1213         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1214         struct ice_vsi *vsi = pf->main_vsi;
1215         struct ice_tx_queue *txq;
1216         const struct rte_memzone *tz;
1217         uint32_t ring_size;
1218         uint16_t tx_rs_thresh, tx_free_thresh;
1219         uint64_t offloads;
1220
1221         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1222
1223         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1224             nb_desc > ICE_MAX_RING_DESC ||
1225             nb_desc < ICE_MIN_RING_DESC) {
1226                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1227                              "invalid", nb_desc);
1228                 return -EINVAL;
1229         }
1230
1231         /**
1232          * The following two parameters control the setting of the RS bit on
1233          * transmit descriptors. TX descriptors will have their RS bit set
1234          * after txq->tx_rs_thresh descriptors have been used. The TX
1235          * descriptor ring will be cleaned after txq->tx_free_thresh
1236          * descriptors are used or if the number of descriptors required to
1237          * transmit a packet is greater than the number of free TX descriptors.
1238          *
1239          * The following constraints must be satisfied:
1240          *  - tx_rs_thresh must be greater than 0.
1241          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1242          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1243          *  - tx_rs_thresh must be a divisor of the ring size.
1244          *  - tx_free_thresh must be greater than 0.
1245          *  - tx_free_thresh must be less than the size of the ring minus 3.
1246          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1247          *
1248          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1249          * race condition, hence the maximum threshold constraints. When set
1250          * to zero use default values.
1251          */
1252         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1253                                     tx_conf->tx_free_thresh :
1254                                     ICE_DEFAULT_TX_FREE_THRESH);
1255         /* force tx_rs_thresh to adapt an aggressive tx_free_thresh */
1256         tx_rs_thresh =
1257                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1258                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1259         if (tx_conf->tx_rs_thresh)
1260                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1261         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1262                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1263                                 "exceed nb_desc. (tx_rs_thresh=%u "
1264                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1265                                 (unsigned int)tx_rs_thresh,
1266                                 (unsigned int)tx_free_thresh,
1267                                 (unsigned int)nb_desc,
1268                                 (int)dev->data->port_id,
1269                                 (int)queue_idx);
1270                 return -EINVAL;
1271         }
1272         if (tx_rs_thresh >= (nb_desc - 2)) {
1273                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1274                              "number of TX descriptors minus 2. "
1275                              "(tx_rs_thresh=%u port=%d queue=%d)",
1276                              (unsigned int)tx_rs_thresh,
1277                              (int)dev->data->port_id,
1278                              (int)queue_idx);
1279                 return -EINVAL;
1280         }
1281         if (tx_free_thresh >= (nb_desc - 3)) {
1282                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1283                              "tx_free_thresh must be less than the "
1284                              "number of TX descriptors minus 3. "
1285                              "(tx_free_thresh=%u port=%d queue=%d)",
1286                              (unsigned int)tx_free_thresh,
1287                              (int)dev->data->port_id,
1288                              (int)queue_idx);
1289                 return -EINVAL;
1290         }
1291         if (tx_rs_thresh > tx_free_thresh) {
1292                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1293                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1294                              " tx_rs_thresh=%u port=%d queue=%d)",
1295                              (unsigned int)tx_free_thresh,
1296                              (unsigned int)tx_rs_thresh,
1297                              (int)dev->data->port_id,
1298                              (int)queue_idx);
1299                 return -EINVAL;
1300         }
1301         if ((nb_desc % tx_rs_thresh) != 0) {
1302                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1303                              "number of TX descriptors. (tx_rs_thresh=%u"
1304                              " port=%d queue=%d)",
1305                              (unsigned int)tx_rs_thresh,
1306                              (int)dev->data->port_id,
1307                              (int)queue_idx);
1308                 return -EINVAL;
1309         }
1310         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1311                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1312                              "tx_rs_thresh is greater than 1. "
1313                              "(tx_rs_thresh=%u port=%d queue=%d)",
1314                              (unsigned int)tx_rs_thresh,
1315                              (int)dev->data->port_id,
1316                              (int)queue_idx);
1317                 return -EINVAL;
1318         }
1319
1320         /* Free memory if needed. */
1321         if (dev->data->tx_queues[queue_idx]) {
1322                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1323                 dev->data->tx_queues[queue_idx] = NULL;
1324         }
1325
1326         /* Allocate the TX queue data structure. */
1327         txq = rte_zmalloc_socket(NULL,
1328                                  sizeof(struct ice_tx_queue),
1329                                  RTE_CACHE_LINE_SIZE,
1330                                  socket_id);
1331         if (!txq) {
1332                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1333                              "tx queue structure");
1334                 return -ENOMEM;
1335         }
1336
1337         /* Allocate TX hardware ring descriptors. */
1338         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1339         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1340         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1341                                       ring_size, ICE_RING_BASE_ALIGN,
1342                                       socket_id);
1343         if (!tz) {
1344                 ice_tx_queue_release(txq);
1345                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1346                 return -ENOMEM;
1347         }
1348
1349         txq->mz = tz;
1350         txq->nb_tx_desc = nb_desc;
1351         txq->tx_rs_thresh = tx_rs_thresh;
1352         txq->tx_free_thresh = tx_free_thresh;
1353         txq->pthresh = tx_conf->tx_thresh.pthresh;
1354         txq->hthresh = tx_conf->tx_thresh.hthresh;
1355         txq->wthresh = tx_conf->tx_thresh.wthresh;
1356         txq->queue_id = queue_idx;
1357
1358         txq->reg_idx = vsi->base_queue + queue_idx;
1359         txq->port_id = dev->data->port_id;
1360         txq->offloads = offloads;
1361         txq->vsi = vsi;
1362         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1363
1364         txq->tx_ring_dma = tz->iova;
1365         txq->tx_ring = tz->addr;
1366
1367         /* Allocate software ring */
1368         txq->sw_ring =
1369                 rte_zmalloc_socket(NULL,
1370                                    sizeof(struct ice_tx_entry) * nb_desc,
1371                                    RTE_CACHE_LINE_SIZE,
1372                                    socket_id);
1373         if (!txq->sw_ring) {
1374                 ice_tx_queue_release(txq);
1375                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1376                 return -ENOMEM;
1377         }
1378
1379         ice_reset_tx_queue(txq);
1380         txq->q_set = true;
1381         dev->data->tx_queues[queue_idx] = txq;
1382         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1383         ice_set_tx_function_flag(dev, txq);
1384
1385         return 0;
1386 }
1387
1388 void
1389 ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1390 {
1391         ice_rx_queue_release(dev->data->rx_queues[qid]);
1392 }
1393
1394 void
1395 ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1396 {
1397         ice_tx_queue_release(dev->data->tx_queues[qid]);
1398 }
1399
1400 void
1401 ice_tx_queue_release(void *txq)
1402 {
1403         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1404
1405         if (!q) {
1406                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1407                 return;
1408         }
1409
1410         q->tx_rel_mbufs(q);
1411         rte_free(q->sw_ring);
1412         rte_memzone_free(q->mz);
1413         rte_free(q);
1414 }
1415
1416 void
1417 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1418                  struct rte_eth_rxq_info *qinfo)
1419 {
1420         struct ice_rx_queue *rxq;
1421
1422         rxq = dev->data->rx_queues[queue_id];
1423
1424         qinfo->mp = rxq->mp;
1425         qinfo->scattered_rx = dev->data->scattered_rx;
1426         qinfo->nb_desc = rxq->nb_rx_desc;
1427
1428         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1429         qinfo->conf.rx_drop_en = rxq->drop_en;
1430         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1431 }
1432
1433 void
1434 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1435                  struct rte_eth_txq_info *qinfo)
1436 {
1437         struct ice_tx_queue *txq;
1438
1439         txq = dev->data->tx_queues[queue_id];
1440
1441         qinfo->nb_desc = txq->nb_tx_desc;
1442
1443         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1444         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1445         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1446
1447         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1448         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1449         qinfo->conf.offloads = txq->offloads;
1450         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1451 }
1452
1453 uint32_t
1454 ice_rx_queue_count(void *rx_queue)
1455 {
1456 #define ICE_RXQ_SCAN_INTERVAL 4
1457         volatile union ice_rx_flex_desc *rxdp;
1458         struct ice_rx_queue *rxq;
1459         uint16_t desc = 0;
1460
1461         rxq = rx_queue;
1462         rxdp = &rxq->rx_ring[rxq->rx_tail];
1463         while ((desc < rxq->nb_rx_desc) &&
1464                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1465                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1466                 /**
1467                  * Check the DD bit of a rx descriptor of each 4 in a group,
1468                  * to avoid checking too frequently and downgrading performance
1469                  * too much.
1470                  */
1471                 desc += ICE_RXQ_SCAN_INTERVAL;
1472                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1473                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1474                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1475                                  desc - rxq->nb_rx_desc]);
1476         }
1477
1478         return desc;
1479 }
1480
1481 #define ICE_RX_FLEX_ERR0_BITS   \
1482         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1483          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1484          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1485          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1486          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1487          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1488
1489 /* Rx L3/L4 checksum */
1490 static inline uint64_t
1491 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1492 {
1493         uint64_t flags = 0;
1494
1495         /* check if HW has decoded the packet and checksum */
1496         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1497                 return 0;
1498
1499         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1500                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1501                 return flags;
1502         }
1503
1504         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1505                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1506         else
1507                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1508
1509         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1510                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1511         else
1512                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1513
1514         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1515                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1516
1517         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1518                 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;
1519         else
1520                 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD;
1521
1522         return flags;
1523 }
1524
1525 static inline void
1526 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1527 {
1528         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1529             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1530                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1531                 mb->vlan_tci =
1532                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1533                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1534                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1535         } else {
1536                 mb->vlan_tci = 0;
1537         }
1538
1539 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1540         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1541             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1542                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
1543                                 RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
1544                 mb->vlan_tci_outer = mb->vlan_tci;
1545                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1546                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1547                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1548                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1549         } else {
1550                 mb->vlan_tci_outer = 0;
1551         }
1552 #endif
1553         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1554                    mb->vlan_tci, mb->vlan_tci_outer);
1555 }
1556
1557 #define ICE_LOOK_AHEAD 8
1558 #if (ICE_LOOK_AHEAD != 8)
1559 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1560 #endif
1561
1562 #define ICE_PTP_TS_VALID 0x1
1563
1564 static inline int
1565 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1566 {
1567         volatile union ice_rx_flex_desc *rxdp;
1568         struct ice_rx_entry *rxep;
1569         struct rte_mbuf *mb;
1570         uint16_t stat_err0;
1571         uint16_t pkt_len;
1572         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1573         int32_t i, j, nb_rx = 0;
1574         uint64_t pkt_flags = 0;
1575         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1576 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1577         struct ice_vsi *vsi = rxq->vsi;
1578         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1579         uint64_t ts_ns;
1580         struct ice_adapter *ad = rxq->vsi->adapter;
1581 #endif
1582         rxdp = &rxq->rx_ring[rxq->rx_tail];
1583         rxep = &rxq->sw_ring[rxq->rx_tail];
1584
1585         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1586
1587         /* Make sure there is at least 1 packet to receive */
1588         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1589                 return 0;
1590
1591         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
1592                 rxq->hw_register_set = 1;
1593
1594         /**
1595          * Scan LOOK_AHEAD descriptors at a time to determine which
1596          * descriptors reference packets that are ready to be received.
1597          */
1598         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1599              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1600                 /* Read desc statuses backwards to avoid race condition */
1601                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1602                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1603
1604                 rte_smp_rmb();
1605
1606                 /* Compute how many status bits were set */
1607                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1608                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1609
1610                 nb_rx += nb_dd;
1611
1612                 /* Translate descriptor info to mbuf parameters */
1613                 for (j = 0; j < nb_dd; j++) {
1614                         mb = rxep[j].mbuf;
1615                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1616                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1617                         mb->data_len = pkt_len;
1618                         mb->pkt_len = pkt_len;
1619                         mb->ol_flags = 0;
1620                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1621                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1622                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1623                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1624                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1625                         rxd_to_pkt_fields_ops[rxq->rxdid](rxq, mb, &rxdp[j]);
1626 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1627                         if (ice_timestamp_dynflag > 0) {
1628                                 ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
1629                                         rxq->hw_register_set,
1630                                         rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high));
1631                                 rxq->hw_register_set = 0;
1632                                 *RTE_MBUF_DYNFIELD(mb,
1633                                         ice_timestamp_dynfield_offset,
1634                                         rte_mbuf_timestamp_t *) = ts_ns;
1635                                 mb->ol_flags |= ice_timestamp_dynflag;
1636                         }
1637
1638                         if (ad->ptp_ena && ((mb->packet_type &
1639                             RTE_PTYPE_L2_MASK) == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1640                                 rxq->time_high =
1641                                    rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high);
1642                                 mb->timesync = rxq->queue_id;
1643                                 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1644                                 if (rxdp[j].wb.time_stamp_low &
1645                                     ICE_PTP_TS_VALID)
1646                                         pkt_flags |=
1647                                                 RTE_MBUF_F_RX_IEEE1588_TMST;
1648                         }
1649 #endif
1650                         mb->ol_flags |= pkt_flags;
1651                 }
1652
1653                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1654                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1655
1656                 if (nb_dd != ICE_LOOK_AHEAD)
1657                         break;
1658         }
1659
1660         /* Clear software ring entries */
1661         for (i = 0; i < nb_rx; i++)
1662                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1663
1664         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1665                    "port_id=%u, queue_id=%u, nb_rx=%d",
1666                    rxq->port_id, rxq->queue_id, nb_rx);
1667
1668         return nb_rx;
1669 }
1670
1671 static inline uint16_t
1672 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1673                        struct rte_mbuf **rx_pkts,
1674                        uint16_t nb_pkts)
1675 {
1676         uint16_t i;
1677         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1678
1679         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1680
1681         for (i = 0; i < nb_pkts; i++)
1682                 rx_pkts[i] = stage[i];
1683
1684         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1685         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1686
1687         return nb_pkts;
1688 }
1689
1690 static inline int
1691 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1692 {
1693         volatile union ice_rx_flex_desc *rxdp;
1694         struct ice_rx_entry *rxep;
1695         struct rte_mbuf *mb;
1696         uint16_t alloc_idx, i;
1697         uint64_t dma_addr;
1698         int diag;
1699
1700         /* Allocate buffers in bulk */
1701         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1702                                (rxq->rx_free_thresh - 1));
1703         rxep = &rxq->sw_ring[alloc_idx];
1704         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1705                                     rxq->rx_free_thresh);
1706         if (unlikely(diag != 0)) {
1707                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1708                 return -ENOMEM;
1709         }
1710
1711         rxdp = &rxq->rx_ring[alloc_idx];
1712         for (i = 0; i < rxq->rx_free_thresh; i++) {
1713                 if (likely(i < (rxq->rx_free_thresh - 1)))
1714                         /* Prefetch next mbuf */
1715                         rte_prefetch0(rxep[i + 1].mbuf);
1716
1717                 mb = rxep[i].mbuf;
1718                 rte_mbuf_refcnt_set(mb, 1);
1719                 mb->next = NULL;
1720                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1721                 mb->nb_segs = 1;
1722                 mb->port = rxq->port_id;
1723                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1724                 rxdp[i].read.hdr_addr = 0;
1725                 rxdp[i].read.pkt_addr = dma_addr;
1726         }
1727
1728         /* Update Rx tail register */
1729         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1730
1731         rxq->rx_free_trigger =
1732                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1733         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1734                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1735
1736         return 0;
1737 }
1738
1739 static inline uint16_t
1740 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1741 {
1742         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1743         uint16_t nb_rx = 0;
1744
1745         if (!nb_pkts)
1746                 return 0;
1747
1748         if (rxq->rx_nb_avail)
1749                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1750
1751         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1752         rxq->rx_next_avail = 0;
1753         rxq->rx_nb_avail = nb_rx;
1754         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1755
1756         if (rxq->rx_tail > rxq->rx_free_trigger) {
1757                 if (ice_rx_alloc_bufs(rxq) != 0) {
1758                         uint16_t i, j;
1759
1760                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1761                                 rxq->rx_free_thresh;
1762                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1763                                    "port_id=%u, queue_id=%u",
1764                                    rxq->port_id, rxq->queue_id);
1765                         rxq->rx_nb_avail = 0;
1766                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1767                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1768                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1769
1770                         return 0;
1771                 }
1772         }
1773
1774         if (rxq->rx_tail >= rxq->nb_rx_desc)
1775                 rxq->rx_tail = 0;
1776
1777         if (rxq->rx_nb_avail)
1778                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1779
1780         return 0;
1781 }
1782
1783 static uint16_t
1784 ice_recv_pkts_bulk_alloc(void *rx_queue,
1785                          struct rte_mbuf **rx_pkts,
1786                          uint16_t nb_pkts)
1787 {
1788         uint16_t nb_rx = 0;
1789         uint16_t n;
1790         uint16_t count;
1791
1792         if (unlikely(nb_pkts == 0))
1793                 return nb_rx;
1794
1795         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1796                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1797
1798         while (nb_pkts) {
1799                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1800                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1801                 nb_rx = (uint16_t)(nb_rx + count);
1802                 nb_pkts = (uint16_t)(nb_pkts - count);
1803                 if (count < n)
1804                         break;
1805         }
1806
1807         return nb_rx;
1808 }
1809
1810 static uint16_t
1811 ice_recv_scattered_pkts(void *rx_queue,
1812                         struct rte_mbuf **rx_pkts,
1813                         uint16_t nb_pkts)
1814 {
1815         struct ice_rx_queue *rxq = rx_queue;
1816         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1817         volatile union ice_rx_flex_desc *rxdp;
1818         union ice_rx_flex_desc rxd;
1819         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1820         struct ice_rx_entry *rxe;
1821         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1822         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1823         struct rte_mbuf *nmb; /* new allocated mbuf */
1824         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1825         uint16_t rx_id = rxq->rx_tail;
1826         uint16_t nb_rx = 0;
1827         uint16_t nb_hold = 0;
1828         uint16_t rx_packet_len;
1829         uint16_t rx_stat_err0;
1830         uint64_t dma_addr;
1831         uint64_t pkt_flags;
1832         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1833 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1834         struct ice_vsi *vsi = rxq->vsi;
1835         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1836         uint64_t ts_ns;
1837         struct ice_adapter *ad = rxq->vsi->adapter;
1838 #endif
1839
1840         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
1841                 rxq->hw_register_set = 1;
1842
1843         while (nb_rx < nb_pkts) {
1844                 rxdp = &rx_ring[rx_id];
1845                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1846
1847                 /* Check the DD bit first */
1848                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1849                         break;
1850
1851                 /* allocate mbuf */
1852                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1853                 if (unlikely(!nmb)) {
1854                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1855                         break;
1856                 }
1857                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1858
1859                 nb_hold++;
1860                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1861                 rx_id++;
1862                 if (unlikely(rx_id == rxq->nb_rx_desc))
1863                         rx_id = 0;
1864
1865                 /* Prefetch next mbuf */
1866                 rte_prefetch0(sw_ring[rx_id].mbuf);
1867
1868                 /**
1869                  * When next RX descriptor is on a cache line boundary,
1870                  * prefetch the next 4 RX descriptors and next 8 pointers
1871                  * to mbufs.
1872                  */
1873                 if ((rx_id & 0x3) == 0) {
1874                         rte_prefetch0(&rx_ring[rx_id]);
1875                         rte_prefetch0(&sw_ring[rx_id]);
1876                 }
1877
1878                 rxm = rxe->mbuf;
1879                 rxe->mbuf = nmb;
1880                 dma_addr =
1881                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1882
1883                 /* Set data buffer address and data length of the mbuf */
1884                 rxdp->read.hdr_addr = 0;
1885                 rxdp->read.pkt_addr = dma_addr;
1886                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1887                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1888                 rxm->data_len = rx_packet_len;
1889                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1890
1891                 /**
1892                  * If this is the first buffer of the received packet, set the
1893                  * pointer to the first mbuf of the packet and initialize its
1894                  * context. Otherwise, update the total length and the number
1895                  * of segments of the current scattered packet, and update the
1896                  * pointer to the last mbuf of the current packet.
1897                  */
1898                 if (!first_seg) {
1899                         first_seg = rxm;
1900                         first_seg->nb_segs = 1;
1901                         first_seg->pkt_len = rx_packet_len;
1902                 } else {
1903                         first_seg->pkt_len =
1904                                 (uint16_t)(first_seg->pkt_len +
1905                                            rx_packet_len);
1906                         first_seg->nb_segs++;
1907                         last_seg->next = rxm;
1908                 }
1909
1910                 /**
1911                  * If this is not the last buffer of the received packet,
1912                  * update the pointer to the last mbuf of the current scattered
1913                  * packet and continue to parse the RX ring.
1914                  */
1915                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1916                         last_seg = rxm;
1917                         continue;
1918                 }
1919
1920                 /**
1921                  * This is the last buffer of the received packet. If the CRC
1922                  * is not stripped by the hardware:
1923                  *  - Subtract the CRC length from the total packet length.
1924                  *  - If the last buffer only contains the whole CRC or a part
1925                  *  of it, free the mbuf associated to the last buffer. If part
1926                  *  of the CRC is also contained in the previous mbuf, subtract
1927                  *  the length of that CRC part from the data length of the
1928                  *  previous mbuf.
1929                  */
1930                 rxm->next = NULL;
1931                 if (unlikely(rxq->crc_len > 0)) {
1932                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1933                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1934                                 rte_pktmbuf_free_seg(rxm);
1935                                 first_seg->nb_segs--;
1936                                 last_seg->data_len =
1937                                         (uint16_t)(last_seg->data_len -
1938                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1939                                 last_seg->next = NULL;
1940                         } else
1941                                 rxm->data_len = (uint16_t)(rx_packet_len -
1942                                                            RTE_ETHER_CRC_LEN);
1943                 }
1944
1945                 first_seg->port = rxq->port_id;
1946                 first_seg->ol_flags = 0;
1947                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1948                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1949                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1950                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, first_seg, &rxd);
1951                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1952 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1953                 if (ice_timestamp_dynflag > 0) {
1954                         ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
1955                                 rxq->hw_register_set,
1956                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1957                         rxq->hw_register_set = 0;
1958                         *RTE_MBUF_DYNFIELD(first_seg,
1959                                 ice_timestamp_dynfield_offset,
1960                                 rte_mbuf_timestamp_t *) = ts_ns;
1961                         first_seg->ol_flags |= ice_timestamp_dynflag;
1962                 }
1963
1964                 if (ad->ptp_ena && ((first_seg->packet_type & RTE_PTYPE_L2_MASK)
1965                     == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1966                         rxq->time_high =
1967                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
1968                         first_seg->timesync = rxq->queue_id;
1969                         pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1970                 }
1971 #endif
1972                 first_seg->ol_flags |= pkt_flags;
1973                 /* Prefetch data of first segment, if configured to do so. */
1974                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1975                                           first_seg->data_off));
1976                 rx_pkts[nb_rx++] = first_seg;
1977                 first_seg = NULL;
1978         }
1979
1980         /* Record index of the next RX descriptor to probe. */
1981         rxq->rx_tail = rx_id;
1982         rxq->pkt_first_seg = first_seg;
1983         rxq->pkt_last_seg = last_seg;
1984
1985         /**
1986          * If the number of free RX descriptors is greater than the RX free
1987          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1988          * register. Update the RDT with the value of the last processed RX
1989          * descriptor minus 1, to guarantee that the RDT register is never
1990          * equal to the RDH register, which creates a "full" ring situation
1991          * from the hardware point of view.
1992          */
1993         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1994         if (nb_hold > rxq->rx_free_thresh) {
1995                 rx_id = (uint16_t)(rx_id == 0 ?
1996                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1997                 /* write TAIL register */
1998                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1999                 nb_hold = 0;
2000         }
2001         rxq->nb_rx_hold = nb_hold;
2002
2003         /* return received packet in the burst */
2004         return nb_rx;
2005 }
2006
2007 const uint32_t *
2008 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2009 {
2010         struct ice_adapter *ad =
2011                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2012         const uint32_t *ptypes;
2013
2014         static const uint32_t ptypes_os[] = {
2015                 /* refers to ice_get_default_pkt_type() */
2016                 RTE_PTYPE_L2_ETHER,
2017                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2018                 RTE_PTYPE_L2_ETHER_LLDP,
2019                 RTE_PTYPE_L2_ETHER_ARP,
2020                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2021                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2022                 RTE_PTYPE_L4_FRAG,
2023                 RTE_PTYPE_L4_ICMP,
2024                 RTE_PTYPE_L4_NONFRAG,
2025                 RTE_PTYPE_L4_SCTP,
2026                 RTE_PTYPE_L4_TCP,
2027                 RTE_PTYPE_L4_UDP,
2028                 RTE_PTYPE_TUNNEL_GRENAT,
2029                 RTE_PTYPE_TUNNEL_IP,
2030                 RTE_PTYPE_INNER_L2_ETHER,
2031                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2032                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2033                 RTE_PTYPE_INNER_L4_FRAG,
2034                 RTE_PTYPE_INNER_L4_ICMP,
2035                 RTE_PTYPE_INNER_L4_NONFRAG,
2036                 RTE_PTYPE_INNER_L4_SCTP,
2037                 RTE_PTYPE_INNER_L4_TCP,
2038                 RTE_PTYPE_INNER_L4_UDP,
2039                 RTE_PTYPE_UNKNOWN
2040         };
2041
2042         static const uint32_t ptypes_comms[] = {
2043                 /* refers to ice_get_default_pkt_type() */
2044                 RTE_PTYPE_L2_ETHER,
2045                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2046                 RTE_PTYPE_L2_ETHER_LLDP,
2047                 RTE_PTYPE_L2_ETHER_ARP,
2048                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2049                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2050                 RTE_PTYPE_L4_FRAG,
2051                 RTE_PTYPE_L4_ICMP,
2052                 RTE_PTYPE_L4_NONFRAG,
2053                 RTE_PTYPE_L4_SCTP,
2054                 RTE_PTYPE_L4_TCP,
2055                 RTE_PTYPE_L4_UDP,
2056                 RTE_PTYPE_TUNNEL_GRENAT,
2057                 RTE_PTYPE_TUNNEL_IP,
2058                 RTE_PTYPE_INNER_L2_ETHER,
2059                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2060                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2061                 RTE_PTYPE_INNER_L4_FRAG,
2062                 RTE_PTYPE_INNER_L4_ICMP,
2063                 RTE_PTYPE_INNER_L4_NONFRAG,
2064                 RTE_PTYPE_INNER_L4_SCTP,
2065                 RTE_PTYPE_INNER_L4_TCP,
2066                 RTE_PTYPE_INNER_L4_UDP,
2067                 RTE_PTYPE_TUNNEL_GTPC,
2068                 RTE_PTYPE_TUNNEL_GTPU,
2069                 RTE_PTYPE_L2_ETHER_PPPOE,
2070                 RTE_PTYPE_UNKNOWN
2071         };
2072
2073         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
2074                 ptypes = ptypes_comms;
2075         else
2076                 ptypes = ptypes_os;
2077
2078         if (dev->rx_pkt_burst == ice_recv_pkts ||
2079             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
2080             dev->rx_pkt_burst == ice_recv_scattered_pkts)
2081                 return ptypes;
2082
2083 #ifdef RTE_ARCH_X86
2084         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
2085             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
2086 #ifdef CC_AVX512_SUPPORT
2087             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
2088             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
2089             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
2090             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
2091 #endif
2092             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
2093             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
2094             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2095             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2096                 return ptypes;
2097 #endif
2098
2099         return NULL;
2100 }
2101
2102 int
2103 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2104 {
2105         volatile union ice_rx_flex_desc *rxdp;
2106         struct ice_rx_queue *rxq = rx_queue;
2107         uint32_t desc;
2108
2109         if (unlikely(offset >= rxq->nb_rx_desc))
2110                 return -EINVAL;
2111
2112         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2113                 return RTE_ETH_RX_DESC_UNAVAIL;
2114
2115         desc = rxq->rx_tail + offset;
2116         if (desc >= rxq->nb_rx_desc)
2117                 desc -= rxq->nb_rx_desc;
2118
2119         rxdp = &rxq->rx_ring[desc];
2120         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2121             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2122                 return RTE_ETH_RX_DESC_DONE;
2123
2124         return RTE_ETH_RX_DESC_AVAIL;
2125 }
2126
2127 int
2128 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2129 {
2130         struct ice_tx_queue *txq = tx_queue;
2131         volatile uint64_t *status;
2132         uint64_t mask, expect;
2133         uint32_t desc;
2134
2135         if (unlikely(offset >= txq->nb_tx_desc))
2136                 return -EINVAL;
2137
2138         desc = txq->tx_tail + offset;
2139         /* go to next desc that has the RS bit */
2140         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2141                 txq->tx_rs_thresh;
2142         if (desc >= txq->nb_tx_desc) {
2143                 desc -= txq->nb_tx_desc;
2144                 if (desc >= txq->nb_tx_desc)
2145                         desc -= txq->nb_tx_desc;
2146         }
2147
2148         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2149         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2150         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2151                                   ICE_TXD_QW1_DTYPE_S);
2152         if ((*status & mask) == expect)
2153                 return RTE_ETH_TX_DESC_DONE;
2154
2155         return RTE_ETH_TX_DESC_FULL;
2156 }
2157
2158 void
2159 ice_free_queues(struct rte_eth_dev *dev)
2160 {
2161         uint16_t i;
2162
2163         PMD_INIT_FUNC_TRACE();
2164
2165         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2166                 if (!dev->data->rx_queues[i])
2167                         continue;
2168                 ice_rx_queue_release(dev->data->rx_queues[i]);
2169                 dev->data->rx_queues[i] = NULL;
2170         }
2171         dev->data->nb_rx_queues = 0;
2172
2173         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2174                 if (!dev->data->tx_queues[i])
2175                         continue;
2176                 ice_tx_queue_release(dev->data->tx_queues[i]);
2177                 dev->data->tx_queues[i] = NULL;
2178         }
2179         dev->data->nb_tx_queues = 0;
2180 }
2181
2182 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
2183 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
2184
2185 int
2186 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2187 {
2188         struct ice_tx_queue *txq;
2189         const struct rte_memzone *tz = NULL;
2190         uint32_t ring_size;
2191         struct rte_eth_dev *dev;
2192
2193         if (!pf) {
2194                 PMD_DRV_LOG(ERR, "PF is not available");
2195                 return -EINVAL;
2196         }
2197
2198         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2199
2200         /* Allocate the TX queue data structure. */
2201         txq = rte_zmalloc_socket("ice fdir tx queue",
2202                                  sizeof(struct ice_tx_queue),
2203                                  RTE_CACHE_LINE_SIZE,
2204                                  SOCKET_ID_ANY);
2205         if (!txq) {
2206                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2207                             "tx queue structure.");
2208                 return -ENOMEM;
2209         }
2210
2211         /* Allocate TX hardware ring descriptors. */
2212         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2213         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2214
2215         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2216                                       ICE_FDIR_QUEUE_ID, ring_size,
2217                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2218         if (!tz) {
2219                 ice_tx_queue_release(txq);
2220                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2221                 return -ENOMEM;
2222         }
2223
2224         txq->mz = tz;
2225         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2226         txq->queue_id = ICE_FDIR_QUEUE_ID;
2227         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2228         txq->vsi = pf->fdir.fdir_vsi;
2229
2230         txq->tx_ring_dma = tz->iova;
2231         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2232         /*
2233          * don't need to allocate software ring and reset for the fdir
2234          * program queue just set the queue has been configured.
2235          */
2236         txq->q_set = true;
2237         pf->fdir.txq = txq;
2238
2239         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2240
2241         return ICE_SUCCESS;
2242 }
2243
2244 int
2245 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2246 {
2247         struct ice_rx_queue *rxq;
2248         const struct rte_memzone *rz = NULL;
2249         uint32_t ring_size;
2250         struct rte_eth_dev *dev;
2251
2252         if (!pf) {
2253                 PMD_DRV_LOG(ERR, "PF is not available");
2254                 return -EINVAL;
2255         }
2256
2257         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2258
2259         /* Allocate the RX queue data structure. */
2260         rxq = rte_zmalloc_socket("ice fdir rx queue",
2261                                  sizeof(struct ice_rx_queue),
2262                                  RTE_CACHE_LINE_SIZE,
2263                                  SOCKET_ID_ANY);
2264         if (!rxq) {
2265                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2266                             "rx queue structure.");
2267                 return -ENOMEM;
2268         }
2269
2270         /* Allocate RX hardware ring descriptors. */
2271         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2272         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2273
2274         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2275                                       ICE_FDIR_QUEUE_ID, ring_size,
2276                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2277         if (!rz) {
2278                 ice_rx_queue_release(rxq);
2279                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2280                 return -ENOMEM;
2281         }
2282
2283         rxq->mz = rz;
2284         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2285         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2286         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2287         rxq->vsi = pf->fdir.fdir_vsi;
2288
2289         rxq->rx_ring_dma = rz->iova;
2290         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2291                sizeof(union ice_32byte_rx_desc));
2292         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2293
2294         /*
2295          * Don't need to allocate software ring and reset for the fdir
2296          * rx queue, just set the queue has been configured.
2297          */
2298         rxq->q_set = true;
2299         pf->fdir.rxq = rxq;
2300
2301         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2302
2303         return ICE_SUCCESS;
2304 }
2305
2306 uint16_t
2307 ice_recv_pkts(void *rx_queue,
2308               struct rte_mbuf **rx_pkts,
2309               uint16_t nb_pkts)
2310 {
2311         struct ice_rx_queue *rxq = rx_queue;
2312         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2313         volatile union ice_rx_flex_desc *rxdp;
2314         union ice_rx_flex_desc rxd;
2315         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2316         struct ice_rx_entry *rxe;
2317         struct rte_mbuf *nmb; /* new allocated mbuf */
2318         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2319         uint16_t rx_id = rxq->rx_tail;
2320         uint16_t nb_rx = 0;
2321         uint16_t nb_hold = 0;
2322         uint16_t rx_packet_len;
2323         uint16_t rx_stat_err0;
2324         uint64_t dma_addr;
2325         uint64_t pkt_flags;
2326         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2327 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2328         struct ice_vsi *vsi = rxq->vsi;
2329         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2330         uint64_t ts_ns;
2331         struct ice_adapter *ad = rxq->vsi->adapter;
2332 #endif
2333
2334         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
2335                 rxq->hw_register_set = 1;
2336
2337         while (nb_rx < nb_pkts) {
2338                 rxdp = &rx_ring[rx_id];
2339                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2340
2341                 /* Check the DD bit first */
2342                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2343                         break;
2344
2345                 /* allocate mbuf */
2346                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2347                 if (unlikely(!nmb)) {
2348                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2349                         break;
2350                 }
2351                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2352
2353                 nb_hold++;
2354                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2355                 rx_id++;
2356                 if (unlikely(rx_id == rxq->nb_rx_desc))
2357                         rx_id = 0;
2358                 rxm = rxe->mbuf;
2359                 rxe->mbuf = nmb;
2360                 dma_addr =
2361                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2362
2363                 /**
2364                  * fill the read format of descriptor with physic address in
2365                  * new allocated mbuf: nmb
2366                  */
2367                 rxdp->read.hdr_addr = 0;
2368                 rxdp->read.pkt_addr = dma_addr;
2369
2370                 /* calculate rx_packet_len of the received pkt */
2371                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2372                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2373
2374                 /* fill old mbuf with received descriptor: rxd */
2375                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2376                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2377                 rxm->nb_segs = 1;
2378                 rxm->next = NULL;
2379                 rxm->pkt_len = rx_packet_len;
2380                 rxm->data_len = rx_packet_len;
2381                 rxm->port = rxq->port_id;
2382                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2383                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2384                 ice_rxd_to_vlan_tci(rxm, &rxd);
2385                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, rxm, &rxd);
2386                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2387 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2388                 if (ice_timestamp_dynflag > 0) {
2389                         ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
2390                                 rxq->hw_register_set,
2391                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
2392                         rxq->hw_register_set = 0;
2393                         *RTE_MBUF_DYNFIELD(rxm,
2394                                 ice_timestamp_dynfield_offset,
2395                                 rte_mbuf_timestamp_t *) = ts_ns;
2396                         rxm->ol_flags |= ice_timestamp_dynflag;
2397                 }
2398
2399                 if (ad->ptp_ena && ((rxm->packet_type & RTE_PTYPE_L2_MASK) ==
2400                     RTE_PTYPE_L2_ETHER_TIMESYNC)) {
2401                         rxq->time_high =
2402                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2403                         rxm->timesync = rxq->queue_id;
2404                         pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
2405                 }
2406 #endif
2407                 rxm->ol_flags |= pkt_flags;
2408                 /* copy old mbuf to rx_pkts */
2409                 rx_pkts[nb_rx++] = rxm;
2410         }
2411         rxq->rx_tail = rx_id;
2412         /**
2413          * If the number of free RX descriptors is greater than the RX free
2414          * threshold of the queue, advance the receive tail register of queue.
2415          * Update that register with the value of the last processed RX
2416          * descriptor minus 1.
2417          */
2418         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2419         if (nb_hold > rxq->rx_free_thresh) {
2420                 rx_id = (uint16_t)(rx_id == 0 ?
2421                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2422                 /* write TAIL register */
2423                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2424                 nb_hold = 0;
2425         }
2426         rxq->nb_rx_hold = nb_hold;
2427
2428         /* return received packet in the burst */
2429         return nb_rx;
2430 }
2431
2432 static inline void
2433 ice_parse_tunneling_params(uint64_t ol_flags,
2434                             union ice_tx_offload tx_offload,
2435                             uint32_t *cd_tunneling)
2436 {
2437         /* EIPT: External (outer) IP header type */
2438         if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
2439                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2440         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
2441                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2442         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
2443                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2444
2445         /* EIPLEN: External (outer) IP header length, in DWords */
2446         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2447                 ICE_TXD_CTX_QW0_EIPLEN_S;
2448
2449         /* L4TUNT: L4 Tunneling Type */
2450         switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
2451         case RTE_MBUF_F_TX_TUNNEL_IPIP:
2452                 /* for non UDP / GRE tunneling, set to 00b */
2453                 break;
2454         case RTE_MBUF_F_TX_TUNNEL_VXLAN:
2455         case RTE_MBUF_F_TX_TUNNEL_GTP:
2456         case RTE_MBUF_F_TX_TUNNEL_GENEVE:
2457                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2458                 break;
2459         case RTE_MBUF_F_TX_TUNNEL_GRE:
2460                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2461                 break;
2462         default:
2463                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2464                 return;
2465         }
2466
2467         /* L4TUNLEN: L4 Tunneling Length, in Words
2468          *
2469          * We depend on app to set rte_mbuf.l2_len correctly.
2470          * For IP in GRE it should be set to the length of the GRE
2471          * header;
2472          * For MAC in GRE or MAC in UDP it should be set to the length
2473          * of the GRE or UDP headers plus the inner MAC up to including
2474          * its last Ethertype.
2475          * If MPLS labels exists, it should include them as well.
2476          */
2477         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2478                 ICE_TXD_CTX_QW0_NATLEN_S;
2479
2480         /**
2481          * Calculate the tunneling UDP checksum.
2482          * Shall be set only if L4TUNT = 01b and EIPT is not zero
2483          */
2484         if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2485             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2486                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2487 }
2488
2489 static inline void
2490 ice_txd_enable_checksum(uint64_t ol_flags,
2491                         uint32_t *td_cmd,
2492                         uint32_t *td_offset,
2493                         union ice_tx_offload tx_offload)
2494 {
2495         /* Set MACLEN */
2496         if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2497                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2498                         << ICE_TX_DESC_LEN_MACLEN_S;
2499         else
2500                 *td_offset |= (tx_offload.l2_len >> 1)
2501                         << ICE_TX_DESC_LEN_MACLEN_S;
2502
2503         /* Enable L3 checksum offloads */
2504         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
2505                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2506                 *td_offset |= (tx_offload.l3_len >> 2) <<
2507                         ICE_TX_DESC_LEN_IPLEN_S;
2508         } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2509                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2510                 *td_offset |= (tx_offload.l3_len >> 2) <<
2511                         ICE_TX_DESC_LEN_IPLEN_S;
2512         } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2513                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2514                 *td_offset |= (tx_offload.l3_len >> 2) <<
2515                         ICE_TX_DESC_LEN_IPLEN_S;
2516         }
2517
2518         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2519                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2520                 *td_offset |= (tx_offload.l4_len >> 2) <<
2521                               ICE_TX_DESC_LEN_L4_LEN_S;
2522                 return;
2523         }
2524
2525         /* Enable L4 checksum offloads */
2526         switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2527         case RTE_MBUF_F_TX_TCP_CKSUM:
2528                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2529                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2530                               ICE_TX_DESC_LEN_L4_LEN_S;
2531                 break;
2532         case RTE_MBUF_F_TX_SCTP_CKSUM:
2533                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2534                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2535                               ICE_TX_DESC_LEN_L4_LEN_S;
2536                 break;
2537         case RTE_MBUF_F_TX_UDP_CKSUM:
2538                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2539                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2540                               ICE_TX_DESC_LEN_L4_LEN_S;
2541                 break;
2542         default:
2543                 break;
2544         }
2545 }
2546
2547 static inline int
2548 ice_xmit_cleanup(struct ice_tx_queue *txq)
2549 {
2550         struct ice_tx_entry *sw_ring = txq->sw_ring;
2551         volatile struct ice_tx_desc *txd = txq->tx_ring;
2552         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2553         uint16_t nb_tx_desc = txq->nb_tx_desc;
2554         uint16_t desc_to_clean_to;
2555         uint16_t nb_tx_to_clean;
2556
2557         /* Determine the last descriptor needing to be cleaned */
2558         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2559         if (desc_to_clean_to >= nb_tx_desc)
2560                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2561
2562         /* Check to make sure the last descriptor to clean is done */
2563         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2564         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2565             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2566                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2567                            "(port=%d queue=%d) value=0x%"PRIx64"\n",
2568                            desc_to_clean_to,
2569                            txq->port_id, txq->queue_id,
2570                            txd[desc_to_clean_to].cmd_type_offset_bsz);
2571                 /* Failed to clean any descriptors */
2572                 return -1;
2573         }
2574
2575         /* Figure out how many descriptors will be cleaned */
2576         if (last_desc_cleaned > desc_to_clean_to)
2577                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2578                                             desc_to_clean_to);
2579         else
2580                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2581                                             last_desc_cleaned);
2582
2583         /* The last descriptor to clean is done, so that means all the
2584          * descriptors from the last descriptor that was cleaned
2585          * up to the last descriptor with the RS bit set
2586          * are done. Only reset the threshold descriptor.
2587          */
2588         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2589
2590         /* Update the txq to reflect the last descriptor that was cleaned */
2591         txq->last_desc_cleaned = desc_to_clean_to;
2592         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2593
2594         return 0;
2595 }
2596
2597 /* Construct the tx flags */
2598 static inline uint64_t
2599 ice_build_ctob(uint32_t td_cmd,
2600                uint32_t td_offset,
2601                uint16_t size,
2602                uint32_t td_tag)
2603 {
2604         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2605                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2606                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2607                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2608                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2609 }
2610
2611 /* Check if the context descriptor is needed for TX offloading */
2612 static inline uint16_t
2613 ice_calc_context_desc(uint64_t flags)
2614 {
2615         static uint64_t mask = RTE_MBUF_F_TX_TCP_SEG |
2616                 RTE_MBUF_F_TX_QINQ |
2617                 RTE_MBUF_F_TX_OUTER_IP_CKSUM |
2618                 RTE_MBUF_F_TX_TUNNEL_MASK |
2619                 RTE_MBUF_F_TX_IEEE1588_TMST;
2620
2621         return (flags & mask) ? 1 : 0;
2622 }
2623
2624 /* set ice TSO context descriptor */
2625 static inline uint64_t
2626 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2627 {
2628         uint64_t ctx_desc = 0;
2629         uint32_t cd_cmd, hdr_len, cd_tso_len;
2630
2631         if (!tx_offload.l4_len) {
2632                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2633                 return ctx_desc;
2634         }
2635
2636         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2637         hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
2638                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2639
2640         cd_cmd = ICE_TX_CTX_DESC_TSO;
2641         cd_tso_len = mbuf->pkt_len - hdr_len;
2642         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2643                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2644                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2645
2646         return ctx_desc;
2647 }
2648
2649 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2650 #define ICE_MAX_DATA_PER_TXD \
2651         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2652 /* Calculate the number of TX descriptors needed for each pkt */
2653 static inline uint16_t
2654 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2655 {
2656         struct rte_mbuf *txd = tx_pkt;
2657         uint16_t count = 0;
2658
2659         while (txd != NULL) {
2660                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2661                 txd = txd->next;
2662         }
2663
2664         return count;
2665 }
2666
2667 uint16_t
2668 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2669 {
2670         struct ice_tx_queue *txq;
2671         volatile struct ice_tx_desc *tx_ring;
2672         volatile struct ice_tx_desc *txd;
2673         struct ice_tx_entry *sw_ring;
2674         struct ice_tx_entry *txe, *txn;
2675         struct rte_mbuf *tx_pkt;
2676         struct rte_mbuf *m_seg;
2677         uint32_t cd_tunneling_params;
2678         uint16_t tx_id;
2679         uint16_t nb_tx;
2680         uint16_t nb_used;
2681         uint16_t nb_ctx;
2682         uint32_t td_cmd = 0;
2683         uint32_t td_offset = 0;
2684         uint32_t td_tag = 0;
2685         uint16_t tx_last;
2686         uint16_t slen;
2687         uint64_t buf_dma_addr;
2688         uint64_t ol_flags;
2689         union ice_tx_offload tx_offload = {0};
2690
2691         txq = tx_queue;
2692         sw_ring = txq->sw_ring;
2693         tx_ring = txq->tx_ring;
2694         tx_id = txq->tx_tail;
2695         txe = &sw_ring[tx_id];
2696
2697         /* Check if the descriptor ring needs to be cleaned. */
2698         if (txq->nb_tx_free < txq->tx_free_thresh)
2699                 (void)ice_xmit_cleanup(txq);
2700
2701         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2702                 tx_pkt = *tx_pkts++;
2703
2704                 td_cmd = 0;
2705                 td_tag = 0;
2706                 td_offset = 0;
2707                 ol_flags = tx_pkt->ol_flags;
2708                 tx_offload.l2_len = tx_pkt->l2_len;
2709                 tx_offload.l3_len = tx_pkt->l3_len;
2710                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2711                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2712                 tx_offload.l4_len = tx_pkt->l4_len;
2713                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2714                 /* Calculate the number of context descriptors needed. */
2715                 nb_ctx = ice_calc_context_desc(ol_flags);
2716
2717                 /* The number of descriptors that must be allocated for
2718                  * a packet equals to the number of the segments of that
2719                  * packet plus the number of context descriptor if needed.
2720                  * Recalculate the needed tx descs when TSO enabled in case
2721                  * the mbuf data size exceeds max data size that hw allows
2722                  * per tx desc.
2723                  */
2724                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2725                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2726                                              nb_ctx);
2727                 else
2728                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2729                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2730
2731                 /* Circular ring */
2732                 if (tx_last >= txq->nb_tx_desc)
2733                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2734
2735                 if (nb_used > txq->nb_tx_free) {
2736                         if (ice_xmit_cleanup(txq) != 0) {
2737                                 if (nb_tx == 0)
2738                                         return 0;
2739                                 goto end_of_tx;
2740                         }
2741                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2742                                 while (nb_used > txq->nb_tx_free) {
2743                                         if (ice_xmit_cleanup(txq) != 0) {
2744                                                 if (nb_tx == 0)
2745                                                         return 0;
2746                                                 goto end_of_tx;
2747                                         }
2748                                 }
2749                         }
2750                 }
2751
2752                 /* Descriptor based VLAN insertion */
2753                 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
2754                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2755                         td_tag = tx_pkt->vlan_tci;
2756                 }
2757
2758                 /* Fill in tunneling parameters if necessary */
2759                 cd_tunneling_params = 0;
2760                 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2761                         ice_parse_tunneling_params(ol_flags, tx_offload,
2762                                                    &cd_tunneling_params);
2763
2764                 /* Enable checksum offloading */
2765                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2766                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2767                                                 &td_offset, tx_offload);
2768
2769                 if (nb_ctx) {
2770                         /* Setup TX context descriptor if required */
2771                         volatile struct ice_tx_ctx_desc *ctx_txd =
2772                                 (volatile struct ice_tx_ctx_desc *)
2773                                         &tx_ring[tx_id];
2774                         uint16_t cd_l2tag2 = 0;
2775                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2776
2777                         txn = &sw_ring[txe->next_id];
2778                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2779                         if (txe->mbuf) {
2780                                 rte_pktmbuf_free_seg(txe->mbuf);
2781                                 txe->mbuf = NULL;
2782                         }
2783
2784                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2785                                 cd_type_cmd_tso_mss |=
2786                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2787                         else if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
2788                                 cd_type_cmd_tso_mss |=
2789                                         ((uint64_t)ICE_TX_CTX_DESC_TSYN <<
2790                                         ICE_TXD_CTX_QW1_CMD_S);
2791
2792                         ctx_txd->tunneling_params =
2793                                 rte_cpu_to_le_32(cd_tunneling_params);
2794
2795                         /* TX context descriptor based double VLAN insert */
2796                         if (ol_flags & RTE_MBUF_F_TX_QINQ) {
2797                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2798                                 cd_type_cmd_tso_mss |=
2799                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2800                                          ICE_TXD_CTX_QW1_CMD_S);
2801                         }
2802                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2803                         ctx_txd->qw1 =
2804                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2805
2806                         txe->last_id = tx_last;
2807                         tx_id = txe->next_id;
2808                         txe = txn;
2809                 }
2810                 m_seg = tx_pkt;
2811
2812                 do {
2813                         txd = &tx_ring[tx_id];
2814                         txn = &sw_ring[txe->next_id];
2815
2816                         if (txe->mbuf)
2817                                 rte_pktmbuf_free_seg(txe->mbuf);
2818                         txe->mbuf = m_seg;
2819
2820                         /* Setup TX Descriptor */
2821                         slen = m_seg->data_len;
2822                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2823
2824                         while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
2825                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2826                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2827                                 txd->cmd_type_offset_bsz =
2828                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2829                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2830                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2831                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2832                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2833                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2834
2835                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2836                                 slen -= ICE_MAX_DATA_PER_TXD;
2837
2838                                 txe->last_id = tx_last;
2839                                 tx_id = txe->next_id;
2840                                 txe = txn;
2841                                 txd = &tx_ring[tx_id];
2842                                 txn = &sw_ring[txe->next_id];
2843                         }
2844
2845                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2846                         txd->cmd_type_offset_bsz =
2847                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2848                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2849                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2850                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2851                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2852
2853                         txe->last_id = tx_last;
2854                         tx_id = txe->next_id;
2855                         txe = txn;
2856                         m_seg = m_seg->next;
2857                 } while (m_seg);
2858
2859                 /* fill the last descriptor with End of Packet (EOP) bit */
2860                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2861                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2862                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2863
2864                 /* set RS bit on the last descriptor of one packet */
2865                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2866                         PMD_TX_LOG(DEBUG,
2867                                    "Setting RS bit on TXD id="
2868                                    "%4u (port=%d queue=%d)",
2869                                    tx_last, txq->port_id, txq->queue_id);
2870
2871                         td_cmd |= ICE_TX_DESC_CMD_RS;
2872
2873                         /* Update txq RS bit counters */
2874                         txq->nb_tx_used = 0;
2875                 }
2876                 txd->cmd_type_offset_bsz |=
2877                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2878                                          ICE_TXD_QW1_CMD_S);
2879         }
2880 end_of_tx:
2881         /* update Tail register */
2882         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2883         txq->tx_tail = tx_id;
2884
2885         return nb_tx;
2886 }
2887
2888 static __rte_always_inline int
2889 ice_tx_free_bufs(struct ice_tx_queue *txq)
2890 {
2891         struct ice_tx_entry *txep;
2892         uint16_t i;
2893
2894         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2895              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2896             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2897                 return 0;
2898
2899         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2900
2901         for (i = 0; i < txq->tx_rs_thresh; i++)
2902                 rte_prefetch0((txep + i)->mbuf);
2903
2904         if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
2905                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2906                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2907                         txep->mbuf = NULL;
2908                 }
2909         } else {
2910                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2911                         rte_pktmbuf_free_seg(txep->mbuf);
2912                         txep->mbuf = NULL;
2913                 }
2914         }
2915
2916         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2917         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2918         if (txq->tx_next_dd >= txq->nb_tx_desc)
2919                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2920
2921         return txq->tx_rs_thresh;
2922 }
2923
2924 static int
2925 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2926                         uint32_t free_cnt)
2927 {
2928         struct ice_tx_entry *swr_ring = txq->sw_ring;
2929         uint16_t i, tx_last, tx_id;
2930         uint16_t nb_tx_free_last;
2931         uint16_t nb_tx_to_clean;
2932         uint32_t pkt_cnt;
2933
2934         /* Start free mbuf from the next of tx_tail */
2935         tx_last = txq->tx_tail;
2936         tx_id  = swr_ring[tx_last].next_id;
2937
2938         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2939                 return 0;
2940
2941         nb_tx_to_clean = txq->nb_tx_free;
2942         nb_tx_free_last = txq->nb_tx_free;
2943         if (!free_cnt)
2944                 free_cnt = txq->nb_tx_desc;
2945
2946         /* Loop through swr_ring to count the amount of
2947          * freeable mubfs and packets.
2948          */
2949         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2950                 for (i = 0; i < nb_tx_to_clean &&
2951                         pkt_cnt < free_cnt &&
2952                         tx_id != tx_last; i++) {
2953                         if (swr_ring[tx_id].mbuf != NULL) {
2954                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2955                                 swr_ring[tx_id].mbuf = NULL;
2956
2957                                 /*
2958                                  * last segment in the packet,
2959                                  * increment packet count
2960                                  */
2961                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2962                         }
2963
2964                         tx_id = swr_ring[tx_id].next_id;
2965                 }
2966
2967                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2968                         txq->nb_tx_free || tx_id == tx_last)
2969                         break;
2970
2971                 if (pkt_cnt < free_cnt) {
2972                         if (ice_xmit_cleanup(txq))
2973                                 break;
2974
2975                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2976                         nb_tx_free_last = txq->nb_tx_free;
2977                 }
2978         }
2979
2980         return (int)pkt_cnt;
2981 }
2982
2983 #ifdef RTE_ARCH_X86
2984 static int
2985 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2986                         uint32_t free_cnt __rte_unused)
2987 {
2988         return -ENOTSUP;
2989 }
2990 #endif
2991
2992 static int
2993 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2994                         uint32_t free_cnt)
2995 {
2996         int i, n, cnt;
2997
2998         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2999                 free_cnt = txq->nb_tx_desc;
3000
3001         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
3002
3003         for (i = 0; i < cnt; i += n) {
3004                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
3005                         break;
3006
3007                 n = ice_tx_free_bufs(txq);
3008
3009                 if (n == 0)
3010                         break;
3011         }
3012
3013         return i;
3014 }
3015
3016 int
3017 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
3018 {
3019         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
3020         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
3021         struct ice_adapter *ad =
3022                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3023
3024 #ifdef RTE_ARCH_X86
3025         if (ad->tx_vec_allowed)
3026                 return ice_tx_done_cleanup_vec(q, free_cnt);
3027 #endif
3028         if (ad->tx_simple_allowed)
3029                 return ice_tx_done_cleanup_simple(q, free_cnt);
3030         else
3031                 return ice_tx_done_cleanup_full(q, free_cnt);
3032 }
3033
3034 /* Populate 4 descriptors with data from 4 mbufs */
3035 static inline void
3036 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3037 {
3038         uint64_t dma_addr;
3039         uint32_t i;
3040
3041         for (i = 0; i < 4; i++, txdp++, pkts++) {
3042                 dma_addr = rte_mbuf_data_iova(*pkts);
3043                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3044                 txdp->cmd_type_offset_bsz =
3045                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3046                                        (*pkts)->data_len, 0);
3047         }
3048 }
3049
3050 /* Populate 1 descriptor with data from 1 mbuf */
3051 static inline void
3052 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3053 {
3054         uint64_t dma_addr;
3055
3056         dma_addr = rte_mbuf_data_iova(*pkts);
3057         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3058         txdp->cmd_type_offset_bsz =
3059                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3060                                (*pkts)->data_len, 0);
3061 }
3062
3063 static inline void
3064 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
3065                     uint16_t nb_pkts)
3066 {
3067         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
3068         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
3069         const int N_PER_LOOP = 4;
3070         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
3071         int mainpart, leftover;
3072         int i, j;
3073
3074         /**
3075          * Process most of the packets in chunks of N pkts.  Any
3076          * leftover packets will get processed one at a time.
3077          */
3078         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
3079         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
3080         for (i = 0; i < mainpart; i += N_PER_LOOP) {
3081                 /* Copy N mbuf pointers to the S/W ring */
3082                 for (j = 0; j < N_PER_LOOP; ++j)
3083                         (txep + i + j)->mbuf = *(pkts + i + j);
3084                 tx4(txdp + i, pkts + i);
3085         }
3086
3087         if (unlikely(leftover > 0)) {
3088                 for (i = 0; i < leftover; ++i) {
3089                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
3090                         tx1(txdp + mainpart + i, pkts + mainpart + i);
3091                 }
3092         }
3093 }
3094
3095 static inline uint16_t
3096 tx_xmit_pkts(struct ice_tx_queue *txq,
3097              struct rte_mbuf **tx_pkts,
3098              uint16_t nb_pkts)
3099 {
3100         volatile struct ice_tx_desc *txr = txq->tx_ring;
3101         uint16_t n = 0;
3102
3103         /**
3104          * Begin scanning the H/W ring for done descriptors when the number
3105          * of available descriptors drops below tx_free_thresh. For each done
3106          * descriptor, free the associated buffer.
3107          */
3108         if (txq->nb_tx_free < txq->tx_free_thresh)
3109                 ice_tx_free_bufs(txq);
3110
3111         /* Use available descriptor only */
3112         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
3113         if (unlikely(!nb_pkts))
3114                 return 0;
3115
3116         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
3117         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
3118                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
3119                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
3120                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3121                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3122                                          ICE_TXD_QW1_CMD_S);
3123                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3124                 txq->tx_tail = 0;
3125         }
3126
3127         /* Fill hardware descriptor ring with mbuf data */
3128         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3129         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3130
3131         /* Determine if RS bit needs to be set */
3132         if (txq->tx_tail > txq->tx_next_rs) {
3133                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3134                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3135                                          ICE_TXD_QW1_CMD_S);
3136                 txq->tx_next_rs =
3137                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3138                 if (txq->tx_next_rs >= txq->nb_tx_desc)
3139                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3140         }
3141
3142         if (txq->tx_tail >= txq->nb_tx_desc)
3143                 txq->tx_tail = 0;
3144
3145         /* Update the tx tail register */
3146         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3147
3148         return nb_pkts;
3149 }
3150
3151 static uint16_t
3152 ice_xmit_pkts_simple(void *tx_queue,
3153                      struct rte_mbuf **tx_pkts,
3154                      uint16_t nb_pkts)
3155 {
3156         uint16_t nb_tx = 0;
3157
3158         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3159                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3160                                     tx_pkts, nb_pkts);
3161
3162         while (nb_pkts) {
3163                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3164                                                       ICE_TX_MAX_BURST);
3165
3166                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3167                                    &tx_pkts[nb_tx], num);
3168                 nb_tx = (uint16_t)(nb_tx + ret);
3169                 nb_pkts = (uint16_t)(nb_pkts - ret);
3170                 if (ret < num)
3171                         break;
3172         }
3173
3174         return nb_tx;
3175 }
3176
3177 void __rte_cold
3178 ice_set_rx_function(struct rte_eth_dev *dev)
3179 {
3180         PMD_INIT_FUNC_TRACE();
3181         struct ice_adapter *ad =
3182                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3183 #ifdef RTE_ARCH_X86
3184         struct ice_rx_queue *rxq;
3185         int i;
3186         int rx_check_ret = -1;
3187
3188         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3189                 ad->rx_use_avx512 = false;
3190                 ad->rx_use_avx2 = false;
3191                 rx_check_ret = ice_rx_vec_dev_check(dev);
3192                 if (ad->ptp_ena)
3193                         rx_check_ret = -1;
3194                 ad->rx_vec_offload_support =
3195                                 (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH);
3196                 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3197                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3198                         ad->rx_vec_allowed = true;
3199                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3200                                 rxq = dev->data->rx_queues[i];
3201                                 if (rxq && ice_rxq_vec_setup(rxq)) {
3202                                         ad->rx_vec_allowed = false;
3203                                         break;
3204                                 }
3205                         }
3206
3207                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3208                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3209                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3210 #ifdef CC_AVX512_SUPPORT
3211                                 ad->rx_use_avx512 = true;
3212 #else
3213                         PMD_DRV_LOG(NOTICE,
3214                                 "AVX512 is not supported in build env");
3215 #endif
3216                         if (!ad->rx_use_avx512 &&
3217                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3218                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3219                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3220                                 ad->rx_use_avx2 = true;
3221
3222                 } else {
3223                         ad->rx_vec_allowed = false;
3224                 }
3225         }
3226
3227         if (ad->rx_vec_allowed) {
3228                 if (dev->data->scattered_rx) {
3229                         if (ad->rx_use_avx512) {
3230 #ifdef CC_AVX512_SUPPORT
3231                                 if (ad->rx_vec_offload_support) {
3232                                         PMD_DRV_LOG(NOTICE,
3233                                                 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3234                                                 dev->data->port_id);
3235                                         dev->rx_pkt_burst =
3236                                                 ice_recv_scattered_pkts_vec_avx512_offload;
3237                                 } else {
3238                                         PMD_DRV_LOG(NOTICE,
3239                                                 "Using AVX512 Vector Scattered Rx (port %d).",
3240                                                 dev->data->port_id);
3241                                         dev->rx_pkt_burst =
3242                                                 ice_recv_scattered_pkts_vec_avx512;
3243                                 }
3244 #endif
3245                         } else if (ad->rx_use_avx2) {
3246                                 if (ad->rx_vec_offload_support) {
3247                                         PMD_DRV_LOG(NOTICE,
3248                                                     "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3249                                                     dev->data->port_id);
3250                                         dev->rx_pkt_burst =
3251                                                 ice_recv_scattered_pkts_vec_avx2_offload;
3252                                 } else {
3253                                         PMD_DRV_LOG(NOTICE,
3254                                                     "Using AVX2 Vector Scattered Rx (port %d).",
3255                                                     dev->data->port_id);
3256                                         dev->rx_pkt_burst =
3257                                                 ice_recv_scattered_pkts_vec_avx2;
3258                                 }
3259                         } else {
3260                                 PMD_DRV_LOG(DEBUG,
3261                                         "Using Vector Scattered Rx (port %d).",
3262                                         dev->data->port_id);
3263                                 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3264                         }
3265                 } else {
3266                         if (ad->rx_use_avx512) {
3267 #ifdef CC_AVX512_SUPPORT
3268                                 if (ad->rx_vec_offload_support) {
3269                                         PMD_DRV_LOG(NOTICE,
3270                                                 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3271                                                 dev->data->port_id);
3272                                         dev->rx_pkt_burst =
3273                                                 ice_recv_pkts_vec_avx512_offload;
3274                                 } else {
3275                                         PMD_DRV_LOG(NOTICE,
3276                                                 "Using AVX512 Vector Rx (port %d).",
3277                                                 dev->data->port_id);
3278                                         dev->rx_pkt_burst =
3279                                                 ice_recv_pkts_vec_avx512;
3280                                 }
3281 #endif
3282                         } else if (ad->rx_use_avx2) {
3283                                 if (ad->rx_vec_offload_support) {
3284                                         PMD_DRV_LOG(NOTICE,
3285                                                     "Using AVX2 OFFLOAD Vector Rx (port %d).",
3286                                                     dev->data->port_id);
3287                                         dev->rx_pkt_burst =
3288                                                 ice_recv_pkts_vec_avx2_offload;
3289                                 } else {
3290                                         PMD_DRV_LOG(NOTICE,
3291                                                     "Using AVX2 Vector Rx (port %d).",
3292                                                     dev->data->port_id);
3293                                         dev->rx_pkt_burst =
3294                                                 ice_recv_pkts_vec_avx2;
3295                                 }
3296                         } else {
3297                                 PMD_DRV_LOG(DEBUG,
3298                                         "Using Vector Rx (port %d).",
3299                                         dev->data->port_id);
3300                                 dev->rx_pkt_burst = ice_recv_pkts_vec;
3301                         }
3302                 }
3303                 return;
3304         }
3305
3306 #endif
3307
3308         if (dev->data->scattered_rx) {
3309                 /* Set the non-LRO scattered function */
3310                 PMD_INIT_LOG(DEBUG,
3311                              "Using a Scattered function on port %d.",
3312                              dev->data->port_id);
3313                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3314         } else if (ad->rx_bulk_alloc_allowed) {
3315                 PMD_INIT_LOG(DEBUG,
3316                              "Rx Burst Bulk Alloc Preconditions are "
3317                              "satisfied. Rx Burst Bulk Alloc function "
3318                              "will be used on port %d.",
3319                              dev->data->port_id);
3320                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3321         } else {
3322                 PMD_INIT_LOG(DEBUG,
3323                              "Rx Burst Bulk Alloc Preconditions are not "
3324                              "satisfied, Normal Rx will be used on port %d.",
3325                              dev->data->port_id);
3326                 dev->rx_pkt_burst = ice_recv_pkts;
3327         }
3328 }
3329
3330 static const struct {
3331         eth_rx_burst_t pkt_burst;
3332         const char *info;
3333 } ice_rx_burst_infos[] = {
3334         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3335         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3336         { ice_recv_pkts,                    "Scalar" },
3337 #ifdef RTE_ARCH_X86
3338 #ifdef CC_AVX512_SUPPORT
3339         { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3340         { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3341         { ice_recv_pkts_vec_avx512,           "Vector AVX512" },
3342         { ice_recv_pkts_vec_avx512_offload,   "Offload Vector AVX512" },
3343 #endif
3344         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3345         { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3346         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3347         { ice_recv_pkts_vec_avx2_offload,   "Offload Vector AVX2" },
3348         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3349         { ice_recv_pkts_vec,                "Vector SSE" },
3350 #endif
3351 };
3352
3353 int
3354 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3355                       struct rte_eth_burst_mode *mode)
3356 {
3357         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3358         int ret = -EINVAL;
3359         unsigned int i;
3360
3361         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3362                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3363                         snprintf(mode->info, sizeof(mode->info), "%s",
3364                                  ice_rx_burst_infos[i].info);
3365                         ret = 0;
3366                         break;
3367                 }
3368         }
3369
3370         return ret;
3371 }
3372
3373 void __rte_cold
3374 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3375 {
3376         struct ice_adapter *ad =
3377                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3378
3379         /* Use a simple Tx queue if possible (only fast free is allowed) */
3380         ad->tx_simple_allowed =
3381                 (txq->offloads ==
3382                 (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3383                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3384
3385         if (ad->tx_simple_allowed)
3386                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3387                              txq->queue_id);
3388         else
3389                 PMD_INIT_LOG(DEBUG,
3390                              "Simple Tx can NOT be enabled on Tx queue %u.",
3391                              txq->queue_id);
3392 }
3393
3394 /*********************************************************************
3395  *
3396  *  TX prep functions
3397  *
3398  **********************************************************************/
3399 /* The default values of TSO MSS */
3400 #define ICE_MIN_TSO_MSS            64
3401 #define ICE_MAX_TSO_MSS            9728
3402 #define ICE_MAX_TSO_FRAME_SIZE     262144
3403 uint16_t
3404 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3405               uint16_t nb_pkts)
3406 {
3407         int i, ret;
3408         uint64_t ol_flags;
3409         struct rte_mbuf *m;
3410
3411         for (i = 0; i < nb_pkts; i++) {
3412                 m = tx_pkts[i];
3413                 ol_flags = m->ol_flags;
3414
3415                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
3416                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3417                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3418                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3419                         /**
3420                          * MSS outside the range are considered malicious
3421                          */
3422                         rte_errno = EINVAL;
3423                         return i;
3424                 }
3425
3426 #ifdef RTE_ETHDEV_DEBUG_TX
3427                 ret = rte_validate_tx_offload(m);
3428                 if (ret != 0) {
3429                         rte_errno = -ret;
3430                         return i;
3431                 }
3432 #endif
3433                 ret = rte_net_intel_cksum_prepare(m);
3434                 if (ret != 0) {
3435                         rte_errno = -ret;
3436                         return i;
3437                 }
3438         }
3439         return i;
3440 }
3441
3442 void __rte_cold
3443 ice_set_tx_function(struct rte_eth_dev *dev)
3444 {
3445         struct ice_adapter *ad =
3446                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3447 #ifdef RTE_ARCH_X86
3448         struct ice_tx_queue *txq;
3449         int i;
3450         int tx_check_ret = -1;
3451
3452         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3453                 ad->tx_use_avx2 = false;
3454                 ad->tx_use_avx512 = false;
3455                 tx_check_ret = ice_tx_vec_dev_check(dev);
3456                 if (tx_check_ret >= 0 &&
3457                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3458                         ad->tx_vec_allowed = true;
3459
3460                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3461                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3462                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3463 #ifdef CC_AVX512_SUPPORT
3464                                 ad->tx_use_avx512 = true;
3465 #else
3466                         PMD_DRV_LOG(NOTICE,
3467                                 "AVX512 is not supported in build env");
3468 #endif
3469                         if (!ad->tx_use_avx512 &&
3470                                 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3471                                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3472                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3473                                 ad->tx_use_avx2 = true;
3474
3475                         if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3476                                 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3477                                 ad->tx_vec_allowed = false;
3478
3479                         if (ad->tx_vec_allowed) {
3480                                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3481                                         txq = dev->data->tx_queues[i];
3482                                         if (txq && ice_txq_vec_setup(txq)) {
3483                                                 ad->tx_vec_allowed = false;
3484                                                 break;
3485                                         }
3486                                 }
3487                         }
3488                 } else {
3489                         ad->tx_vec_allowed = false;
3490                 }
3491         }
3492
3493         if (ad->tx_vec_allowed) {
3494                 dev->tx_pkt_prepare = NULL;
3495                 if (ad->tx_use_avx512) {
3496 #ifdef CC_AVX512_SUPPORT
3497                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3498                                 PMD_DRV_LOG(NOTICE,
3499                                             "Using AVX512 OFFLOAD Vector Tx (port %d).",
3500                                             dev->data->port_id);
3501                                 dev->tx_pkt_burst =
3502                                         ice_xmit_pkts_vec_avx512_offload;
3503                                 dev->tx_pkt_prepare = ice_prep_pkts;
3504                         } else {
3505                                 PMD_DRV_LOG(NOTICE,
3506                                             "Using AVX512 Vector Tx (port %d).",
3507                                             dev->data->port_id);
3508                                 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3509                         }
3510 #endif
3511                 } else {
3512                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3513                                 PMD_DRV_LOG(NOTICE,
3514                                             "Using AVX2 OFFLOAD Vector Tx (port %d).",
3515                                             dev->data->port_id);
3516                                 dev->tx_pkt_burst =
3517                                         ice_xmit_pkts_vec_avx2_offload;
3518                                 dev->tx_pkt_prepare = ice_prep_pkts;
3519                         } else {
3520                                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3521                                             ad->tx_use_avx2 ? "avx2 " : "",
3522                                             dev->data->port_id);
3523                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3524                                                     ice_xmit_pkts_vec_avx2 :
3525                                                     ice_xmit_pkts_vec;
3526                         }
3527                 }
3528
3529                 return;
3530         }
3531 #endif
3532
3533         if (ad->tx_simple_allowed) {
3534                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3535                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3536                 dev->tx_pkt_prepare = NULL;
3537         } else {
3538                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3539                 dev->tx_pkt_burst = ice_xmit_pkts;
3540                 dev->tx_pkt_prepare = ice_prep_pkts;
3541         }
3542 }
3543
3544 static const struct {
3545         eth_tx_burst_t pkt_burst;
3546         const char *info;
3547 } ice_tx_burst_infos[] = {
3548         { ice_xmit_pkts_simple,   "Scalar Simple" },
3549         { ice_xmit_pkts,          "Scalar" },
3550 #ifdef RTE_ARCH_X86
3551 #ifdef CC_AVX512_SUPPORT
3552         { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3553         { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3554 #endif
3555         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3556         { ice_xmit_pkts_vec,      "Vector SSE" },
3557 #endif
3558 };
3559
3560 int
3561 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3562                       struct rte_eth_burst_mode *mode)
3563 {
3564         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3565         int ret = -EINVAL;
3566         unsigned int i;
3567
3568         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3569                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3570                         snprintf(mode->info, sizeof(mode->info), "%s",
3571                                  ice_tx_burst_infos[i].info);
3572                         ret = 0;
3573                         break;
3574                 }
3575         }
3576
3577         return ret;
3578 }
3579
3580 /* For each value it means, datasheet of hardware can tell more details
3581  *
3582  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3583  */
3584 static inline uint32_t
3585 ice_get_default_pkt_type(uint16_t ptype)
3586 {
3587         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3588                 __rte_cache_aligned = {
3589                 /* L2 types */
3590                 /* [0] reserved */
3591                 [1] = RTE_PTYPE_L2_ETHER,
3592                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3593                 /* [3] - [5] reserved */
3594                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3595                 /* [7] - [10] reserved */
3596                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3597                 /* [12] - [21] reserved */
3598
3599                 /* Non tunneled IPv4 */
3600                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3601                        RTE_PTYPE_L4_FRAG,
3602                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3603                        RTE_PTYPE_L4_NONFRAG,
3604                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3605                        RTE_PTYPE_L4_UDP,
3606                 /* [25] reserved */
3607                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3608                        RTE_PTYPE_L4_TCP,
3609                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3610                        RTE_PTYPE_L4_SCTP,
3611                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3612                        RTE_PTYPE_L4_ICMP,
3613
3614                 /* IPv4 --> IPv4 */
3615                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3616                        RTE_PTYPE_TUNNEL_IP |
3617                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3618                        RTE_PTYPE_INNER_L4_FRAG,
3619                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3620                        RTE_PTYPE_TUNNEL_IP |
3621                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3622                        RTE_PTYPE_INNER_L4_NONFRAG,
3623                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3624                        RTE_PTYPE_TUNNEL_IP |
3625                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3626                        RTE_PTYPE_INNER_L4_UDP,
3627                 /* [32] reserved */
3628                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3629                        RTE_PTYPE_TUNNEL_IP |
3630                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3631                        RTE_PTYPE_INNER_L4_TCP,
3632                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3633                        RTE_PTYPE_TUNNEL_IP |
3634                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3635                        RTE_PTYPE_INNER_L4_SCTP,
3636                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3637                        RTE_PTYPE_TUNNEL_IP |
3638                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3639                        RTE_PTYPE_INNER_L4_ICMP,
3640
3641                 /* IPv4 --> IPv6 */
3642                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3643                        RTE_PTYPE_TUNNEL_IP |
3644                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3645                        RTE_PTYPE_INNER_L4_FRAG,
3646                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3647                        RTE_PTYPE_TUNNEL_IP |
3648                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3649                        RTE_PTYPE_INNER_L4_NONFRAG,
3650                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3651                        RTE_PTYPE_TUNNEL_IP |
3652                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3653                        RTE_PTYPE_INNER_L4_UDP,
3654                 /* [39] reserved */
3655                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3656                        RTE_PTYPE_TUNNEL_IP |
3657                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3658                        RTE_PTYPE_INNER_L4_TCP,
3659                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3660                        RTE_PTYPE_TUNNEL_IP |
3661                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3662                        RTE_PTYPE_INNER_L4_SCTP,
3663                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3664                        RTE_PTYPE_TUNNEL_IP |
3665                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3666                        RTE_PTYPE_INNER_L4_ICMP,
3667
3668                 /* IPv4 --> GRE/Teredo/VXLAN */
3669                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3670                        RTE_PTYPE_TUNNEL_GRENAT,
3671
3672                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3673                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3674                        RTE_PTYPE_TUNNEL_GRENAT |
3675                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3676                        RTE_PTYPE_INNER_L4_FRAG,
3677                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3678                        RTE_PTYPE_TUNNEL_GRENAT |
3679                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3680                        RTE_PTYPE_INNER_L4_NONFRAG,
3681                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3682                        RTE_PTYPE_TUNNEL_GRENAT |
3683                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3684                        RTE_PTYPE_INNER_L4_UDP,
3685                 /* [47] reserved */
3686                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3687                        RTE_PTYPE_TUNNEL_GRENAT |
3688                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3689                        RTE_PTYPE_INNER_L4_TCP,
3690                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3691                        RTE_PTYPE_TUNNEL_GRENAT |
3692                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3693                        RTE_PTYPE_INNER_L4_SCTP,
3694                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3695                        RTE_PTYPE_TUNNEL_GRENAT |
3696                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3697                        RTE_PTYPE_INNER_L4_ICMP,
3698
3699                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3700                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3701                        RTE_PTYPE_TUNNEL_GRENAT |
3702                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3703                        RTE_PTYPE_INNER_L4_FRAG,
3704                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3705                        RTE_PTYPE_TUNNEL_GRENAT |
3706                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3707                        RTE_PTYPE_INNER_L4_NONFRAG,
3708                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3709                        RTE_PTYPE_TUNNEL_GRENAT |
3710                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3711                        RTE_PTYPE_INNER_L4_UDP,
3712                 /* [54] reserved */
3713                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3714                        RTE_PTYPE_TUNNEL_GRENAT |
3715                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3716                        RTE_PTYPE_INNER_L4_TCP,
3717                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3718                        RTE_PTYPE_TUNNEL_GRENAT |
3719                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3720                        RTE_PTYPE_INNER_L4_SCTP,
3721                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3722                        RTE_PTYPE_TUNNEL_GRENAT |
3723                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3724                        RTE_PTYPE_INNER_L4_ICMP,
3725
3726                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3727                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3728                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3729
3730                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3731                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3732                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3733                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3734                        RTE_PTYPE_INNER_L4_FRAG,
3735                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3736                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3737                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3738                        RTE_PTYPE_INNER_L4_NONFRAG,
3739                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3740                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3741                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3742                        RTE_PTYPE_INNER_L4_UDP,
3743                 /* [62] reserved */
3744                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3745                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3746                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3747                        RTE_PTYPE_INNER_L4_TCP,
3748                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3749                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3750                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3751                        RTE_PTYPE_INNER_L4_SCTP,
3752                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3753                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3754                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3755                        RTE_PTYPE_INNER_L4_ICMP,
3756
3757                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3758                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3759                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3760                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3761                        RTE_PTYPE_INNER_L4_FRAG,
3762                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3763                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3764                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3765                        RTE_PTYPE_INNER_L4_NONFRAG,
3766                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3767                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3768                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3769                        RTE_PTYPE_INNER_L4_UDP,
3770                 /* [69] reserved */
3771                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3772                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3773                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3774                        RTE_PTYPE_INNER_L4_TCP,
3775                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3776                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3777                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3778                        RTE_PTYPE_INNER_L4_SCTP,
3779                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3780                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3781                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3782                        RTE_PTYPE_INNER_L4_ICMP,
3783                 /* [73] - [87] reserved */
3784
3785                 /* Non tunneled IPv6 */
3786                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3787                        RTE_PTYPE_L4_FRAG,
3788                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3789                        RTE_PTYPE_L4_NONFRAG,
3790                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3791                        RTE_PTYPE_L4_UDP,
3792                 /* [91] reserved */
3793                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3794                        RTE_PTYPE_L4_TCP,
3795                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3796                        RTE_PTYPE_L4_SCTP,
3797                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3798                        RTE_PTYPE_L4_ICMP,
3799
3800                 /* IPv6 --> IPv4 */
3801                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3802                        RTE_PTYPE_TUNNEL_IP |
3803                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3804                        RTE_PTYPE_INNER_L4_FRAG,
3805                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3806                        RTE_PTYPE_TUNNEL_IP |
3807                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3808                        RTE_PTYPE_INNER_L4_NONFRAG,
3809                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3810                        RTE_PTYPE_TUNNEL_IP |
3811                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3812                        RTE_PTYPE_INNER_L4_UDP,
3813                 /* [98] reserved */
3814                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3815                        RTE_PTYPE_TUNNEL_IP |
3816                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3817                        RTE_PTYPE_INNER_L4_TCP,
3818                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3819                         RTE_PTYPE_TUNNEL_IP |
3820                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3821                         RTE_PTYPE_INNER_L4_SCTP,
3822                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3823                         RTE_PTYPE_TUNNEL_IP |
3824                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3825                         RTE_PTYPE_INNER_L4_ICMP,
3826
3827                 /* IPv6 --> IPv6 */
3828                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3829                         RTE_PTYPE_TUNNEL_IP |
3830                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3831                         RTE_PTYPE_INNER_L4_FRAG,
3832                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3833                         RTE_PTYPE_TUNNEL_IP |
3834                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3835                         RTE_PTYPE_INNER_L4_NONFRAG,
3836                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3837                         RTE_PTYPE_TUNNEL_IP |
3838                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3839                         RTE_PTYPE_INNER_L4_UDP,
3840                 /* [105] reserved */
3841                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3842                         RTE_PTYPE_TUNNEL_IP |
3843                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3844                         RTE_PTYPE_INNER_L4_TCP,
3845                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3846                         RTE_PTYPE_TUNNEL_IP |
3847                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3848                         RTE_PTYPE_INNER_L4_SCTP,
3849                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3850                         RTE_PTYPE_TUNNEL_IP |
3851                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3852                         RTE_PTYPE_INNER_L4_ICMP,
3853
3854                 /* IPv6 --> GRE/Teredo/VXLAN */
3855                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3856                         RTE_PTYPE_TUNNEL_GRENAT,
3857
3858                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3859                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3860                         RTE_PTYPE_TUNNEL_GRENAT |
3861                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3862                         RTE_PTYPE_INNER_L4_FRAG,
3863                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3864                         RTE_PTYPE_TUNNEL_GRENAT |
3865                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3866                         RTE_PTYPE_INNER_L4_NONFRAG,
3867                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3868                         RTE_PTYPE_TUNNEL_GRENAT |
3869                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3870                         RTE_PTYPE_INNER_L4_UDP,
3871                 /* [113] reserved */
3872                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3873                         RTE_PTYPE_TUNNEL_GRENAT |
3874                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3875                         RTE_PTYPE_INNER_L4_TCP,
3876                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3877                         RTE_PTYPE_TUNNEL_GRENAT |
3878                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3879                         RTE_PTYPE_INNER_L4_SCTP,
3880                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3881                         RTE_PTYPE_TUNNEL_GRENAT |
3882                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3883                         RTE_PTYPE_INNER_L4_ICMP,
3884
3885                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3886                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3887                         RTE_PTYPE_TUNNEL_GRENAT |
3888                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3889                         RTE_PTYPE_INNER_L4_FRAG,
3890                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3891                         RTE_PTYPE_TUNNEL_GRENAT |
3892                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3893                         RTE_PTYPE_INNER_L4_NONFRAG,
3894                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3895                         RTE_PTYPE_TUNNEL_GRENAT |
3896                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3897                         RTE_PTYPE_INNER_L4_UDP,
3898                 /* [120] reserved */
3899                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3900                         RTE_PTYPE_TUNNEL_GRENAT |
3901                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3902                         RTE_PTYPE_INNER_L4_TCP,
3903                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3904                         RTE_PTYPE_TUNNEL_GRENAT |
3905                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3906                         RTE_PTYPE_INNER_L4_SCTP,
3907                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3908                         RTE_PTYPE_TUNNEL_GRENAT |
3909                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3910                         RTE_PTYPE_INNER_L4_ICMP,
3911
3912                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3913                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3914                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3915
3916                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3917                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3918                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3919                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3920                         RTE_PTYPE_INNER_L4_FRAG,
3921                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3922                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3923                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3924                         RTE_PTYPE_INNER_L4_NONFRAG,
3925                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3926                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3927                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3928                         RTE_PTYPE_INNER_L4_UDP,
3929                 /* [128] reserved */
3930                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3931                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3932                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3933                         RTE_PTYPE_INNER_L4_TCP,
3934                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3935                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3936                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3937                         RTE_PTYPE_INNER_L4_SCTP,
3938                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3939                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3940                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3941                         RTE_PTYPE_INNER_L4_ICMP,
3942
3943                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3944                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3945                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3946                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3947                         RTE_PTYPE_INNER_L4_FRAG,
3948                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3949                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3950                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3951                         RTE_PTYPE_INNER_L4_NONFRAG,
3952                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3953                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3954                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3955                         RTE_PTYPE_INNER_L4_UDP,
3956                 /* [135] reserved */
3957                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3958                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3959                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3960                         RTE_PTYPE_INNER_L4_TCP,
3961                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3962                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3963                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3964                         RTE_PTYPE_INNER_L4_SCTP,
3965                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3966                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3967                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3968                         RTE_PTYPE_INNER_L4_ICMP,
3969                 /* [139] - [299] reserved */
3970
3971                 /* PPPoE */
3972                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3973                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3974
3975                 /* PPPoE --> IPv4 */
3976                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3977                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3978                         RTE_PTYPE_L4_FRAG,
3979                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3980                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3981                         RTE_PTYPE_L4_NONFRAG,
3982                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3983                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3984                         RTE_PTYPE_L4_UDP,
3985                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3986                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3987                         RTE_PTYPE_L4_TCP,
3988                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3989                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3990                         RTE_PTYPE_L4_SCTP,
3991                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3992                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3993                         RTE_PTYPE_L4_ICMP,
3994
3995                 /* PPPoE --> IPv6 */
3996                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3997                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3998                         RTE_PTYPE_L4_FRAG,
3999                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
4000                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4001                         RTE_PTYPE_L4_NONFRAG,
4002                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
4003                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4004                         RTE_PTYPE_L4_UDP,
4005                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
4006                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4007                         RTE_PTYPE_L4_TCP,
4008                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
4009                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4010                         RTE_PTYPE_L4_SCTP,
4011                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
4012                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4013                         RTE_PTYPE_L4_ICMP,
4014                 /* [314] - [324] reserved */
4015
4016                 /* IPv4/IPv6 --> GTPC/GTPU */
4017                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4018                         RTE_PTYPE_TUNNEL_GTPC,
4019                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4020                         RTE_PTYPE_TUNNEL_GTPC,
4021                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4022                         RTE_PTYPE_TUNNEL_GTPC,
4023                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4024                         RTE_PTYPE_TUNNEL_GTPC,
4025                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4026                         RTE_PTYPE_TUNNEL_GTPU,
4027                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4028                         RTE_PTYPE_TUNNEL_GTPU,
4029
4030                 /* IPv4 --> GTPU --> IPv4 */
4031                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4032                         RTE_PTYPE_TUNNEL_GTPU |
4033                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4034                         RTE_PTYPE_INNER_L4_FRAG,
4035                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4036                         RTE_PTYPE_TUNNEL_GTPU |
4037                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4038                         RTE_PTYPE_INNER_L4_NONFRAG,
4039                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4040                         RTE_PTYPE_TUNNEL_GTPU |
4041                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4042                         RTE_PTYPE_INNER_L4_UDP,
4043                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4044                         RTE_PTYPE_TUNNEL_GTPU |
4045                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4046                         RTE_PTYPE_INNER_L4_TCP,
4047                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4048                         RTE_PTYPE_TUNNEL_GTPU |
4049                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4050                         RTE_PTYPE_INNER_L4_ICMP,
4051
4052                 /* IPv6 --> GTPU --> IPv4 */
4053                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4054                         RTE_PTYPE_TUNNEL_GTPU |
4055                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4056                         RTE_PTYPE_INNER_L4_FRAG,
4057                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4058                         RTE_PTYPE_TUNNEL_GTPU |
4059                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4060                         RTE_PTYPE_INNER_L4_NONFRAG,
4061                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4062                         RTE_PTYPE_TUNNEL_GTPU |
4063                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4064                         RTE_PTYPE_INNER_L4_UDP,
4065                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4066                         RTE_PTYPE_TUNNEL_GTPU |
4067                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4068                         RTE_PTYPE_INNER_L4_TCP,
4069                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4070                         RTE_PTYPE_TUNNEL_GTPU |
4071                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4072                         RTE_PTYPE_INNER_L4_ICMP,
4073
4074                 /* IPv4 --> GTPU --> IPv6 */
4075                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4076                         RTE_PTYPE_TUNNEL_GTPU |
4077                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4078                         RTE_PTYPE_INNER_L4_FRAG,
4079                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4080                         RTE_PTYPE_TUNNEL_GTPU |
4081                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4082                         RTE_PTYPE_INNER_L4_NONFRAG,
4083                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4084                         RTE_PTYPE_TUNNEL_GTPU |
4085                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4086                         RTE_PTYPE_INNER_L4_UDP,
4087                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4088                         RTE_PTYPE_TUNNEL_GTPU |
4089                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4090                         RTE_PTYPE_INNER_L4_TCP,
4091                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4092                         RTE_PTYPE_TUNNEL_GTPU |
4093                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4094                         RTE_PTYPE_INNER_L4_ICMP,
4095
4096                 /* IPv6 --> GTPU --> IPv6 */
4097                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4098                         RTE_PTYPE_TUNNEL_GTPU |
4099                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4100                         RTE_PTYPE_INNER_L4_FRAG,
4101                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4102                         RTE_PTYPE_TUNNEL_GTPU |
4103                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4104                         RTE_PTYPE_INNER_L4_NONFRAG,
4105                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4106                         RTE_PTYPE_TUNNEL_GTPU |
4107                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4108                         RTE_PTYPE_INNER_L4_UDP,
4109                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4110                         RTE_PTYPE_TUNNEL_GTPU |
4111                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4112                         RTE_PTYPE_INNER_L4_TCP,
4113                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4114                         RTE_PTYPE_TUNNEL_GTPU |
4115                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4116                         RTE_PTYPE_INNER_L4_ICMP,
4117
4118                 /* IPv4 --> UDP ECPRI */
4119                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4120                         RTE_PTYPE_L4_UDP,
4121                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4122                         RTE_PTYPE_L4_UDP,
4123                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4124                         RTE_PTYPE_L4_UDP,
4125                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4126                         RTE_PTYPE_L4_UDP,
4127                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4128                         RTE_PTYPE_L4_UDP,
4129                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4130                         RTE_PTYPE_L4_UDP,
4131                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4132                         RTE_PTYPE_L4_UDP,
4133                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4134                         RTE_PTYPE_L4_UDP,
4135                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4136                         RTE_PTYPE_L4_UDP,
4137                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4138                         RTE_PTYPE_L4_UDP,
4139
4140                 /* IPV6 --> UDP ECPRI */
4141                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4142                         RTE_PTYPE_L4_UDP,
4143                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4144                         RTE_PTYPE_L4_UDP,
4145                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4146                         RTE_PTYPE_L4_UDP,
4147                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4148                         RTE_PTYPE_L4_UDP,
4149                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4150                         RTE_PTYPE_L4_UDP,
4151                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4152                         RTE_PTYPE_L4_UDP,
4153                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4154                         RTE_PTYPE_L4_UDP,
4155                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4156                         RTE_PTYPE_L4_UDP,
4157                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4158                         RTE_PTYPE_L4_UDP,
4159                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4160                         RTE_PTYPE_L4_UDP,
4161                 /* All others reserved */
4162         };
4163
4164         return type_table[ptype];
4165 }
4166
4167 void __rte_cold
4168 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4169 {
4170         struct ice_adapter *ad =
4171                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4172         int i;
4173
4174         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4175                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4176 }
4177
4178 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4179 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4180                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4181 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4182 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4183
4184 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
4185 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
4186         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4187 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
4188 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
4189         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4190
4191 /*
4192  * check the programming status descriptor in rx queue.
4193  * done after Programming Flow Director is programmed on
4194  * tx queue
4195  */
4196 static inline int
4197 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4198 {
4199         volatile union ice_32byte_rx_desc *rxdp;
4200         uint64_t qword1;
4201         uint32_t rx_status;
4202         uint32_t error;
4203         uint32_t id;
4204         int ret = -EAGAIN;
4205
4206         rxdp = (volatile union ice_32byte_rx_desc *)
4207                 (&rxq->rx_ring[rxq->rx_tail]);
4208         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4209         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4210                         >> ICE_RXD_QW1_STATUS_S;
4211
4212         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4213                 ret = 0;
4214                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4215                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4216                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4217                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4218                 if (error) {
4219                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4220                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4221                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4222                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4223                         ret = -EINVAL;
4224                         goto err;
4225                 }
4226                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4227                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4228                 if (error) {
4229                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4230                         ret = -EINVAL;
4231                 }
4232 err:
4233                 rxdp->wb.qword1.status_error_len = 0;
4234                 rxq->rx_tail++;
4235                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4236                         rxq->rx_tail = 0;
4237                 if (rxq->rx_tail == 0)
4238                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4239                 else
4240                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4241         }
4242
4243         return ret;
4244 }
4245
4246 #define ICE_FDIR_MAX_WAIT_US 10000
4247
4248 int
4249 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4250 {
4251         struct ice_tx_queue *txq = pf->fdir.txq;
4252         struct ice_rx_queue *rxq = pf->fdir.rxq;
4253         volatile struct ice_fltr_desc *fdirdp;
4254         volatile struct ice_tx_desc *txdp;
4255         uint32_t td_cmd;
4256         uint16_t i;
4257
4258         fdirdp = (volatile struct ice_fltr_desc *)
4259                 (&txq->tx_ring[txq->tx_tail]);
4260         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4261         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4262
4263         txdp = &txq->tx_ring[txq->tx_tail + 1];
4264         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4265         td_cmd = ICE_TX_DESC_CMD_EOP |
4266                 ICE_TX_DESC_CMD_RS  |
4267                 ICE_TX_DESC_CMD_DUMMY;
4268
4269         txdp->cmd_type_offset_bsz =
4270                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4271
4272         txq->tx_tail += 2;
4273         if (txq->tx_tail >= txq->nb_tx_desc)
4274                 txq->tx_tail = 0;
4275         /* Update the tx tail register */
4276         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4277         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4278                 if ((txdp->cmd_type_offset_bsz &
4279                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4280                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4281                         break;
4282                 rte_delay_us(1);
4283         }
4284         if (i >= ICE_FDIR_MAX_WAIT_US) {
4285                 PMD_DRV_LOG(ERR,
4286                             "Failed to program FDIR filter: time out to get DD on tx queue.");
4287                 return -ETIMEDOUT;
4288         }
4289
4290         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4291                 int ret;
4292
4293                 ret = ice_check_fdir_programming_status(rxq);
4294                 if (ret == -EAGAIN)
4295                         rte_delay_us(1);
4296                 else
4297                         return ret;
4298         }
4299
4300         PMD_DRV_LOG(ERR,
4301                     "Failed to program FDIR filter: programming status reported.");
4302         return -ETIMEDOUT;
4303
4304
4305 }