drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7 #include <rte_vect.h>
   8
   9 #include "rte_pmd_ice.h"
  10 #include "ice_rxtx.h"
  11
  12 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  13                 PKT_TX_IP_CKSUM |                \
  14                 PKT_TX_L4_MASK |                 \
  15                 PKT_TX_TCP_SEG |                 \
  16                 PKT_TX_OUTER_IP_CKSUM)
  17
  18 /* Offset of mbuf dynamic field for protocol extraction data */
  19 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  20
  21 /* Mask of mbuf dynamic flags for protocol extraction type */
  22 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  27 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  28
  29 static inline uint8_t
  30 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  31 {
  32         static uint8_t rxdid_map[] = {
  33                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_OVS,
  34                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  35                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  36                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  37                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  38                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  39                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  40         };
  41
  42         return xtr_type < RTE_DIM(rxdid_map) ?
  43                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
  44 }
  45
  46 static inline void
  47 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
  48                                    struct rte_mbuf *mb,
  49                                    volatile union ice_rx_flex_desc *rxdp)
  50 {
  51         volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
  52                         (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
  53 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  54         uint16_t stat_err;
  55 #endif
  56
  57         if (desc->flow_id != 0xFFFFFFFF) {
  58                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
  59                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  60         }
  61
  62 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  63         stat_err = rte_le_to_cpu_16(desc->status_error0);
  64         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  65                 mb->ol_flags |= PKT_RX_RSS_HASH;
  66                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  67         }
  68 #endif
  69 }
  70
  71 static inline void
  72 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
  73                                       struct rte_mbuf *mb,
  74                                       volatile union ice_rx_flex_desc *rxdp)
  75 {
  76         volatile struct ice_32b_rx_flex_desc_comms *desc =
  77                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
  78         uint16_t stat_err;
  79
  80         stat_err = rte_le_to_cpu_16(desc->status_error0);
  81         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  82                 mb->ol_flags |= PKT_RX_RSS_HASH;
  83                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  84         }
  85
  86 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  87         if (desc->flow_id != 0xFFFFFFFF) {
  88                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
  89                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  90         }
  91
  92         if (rxq->xtr_ol_flag) {
  93                 uint32_t metadata = 0;
  94
  95                 stat_err = rte_le_to_cpu_16(desc->status_error1);
  96
  97                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
  98                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
  99
 100                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 101                         metadata |=
 102                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 103
 104                 if (metadata) {
 105                         mb->ol_flags |= rxq->xtr_ol_flag;
 106
 107                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 108                 }
 109         }
 110 #endif
 111 }
 112
 113 static inline void
 114 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
 115                                       struct rte_mbuf *mb,
 116                                       volatile union ice_rx_flex_desc *rxdp)
 117 {
 118         volatile struct ice_32b_rx_flex_desc_comms *desc =
 119                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 120         uint16_t stat_err;
 121
 122         stat_err = rte_le_to_cpu_16(desc->status_error0);
 123         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 124                 mb->ol_flags |= PKT_RX_RSS_HASH;
 125                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 126         }
 127
 128 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 129         if (desc->flow_id != 0xFFFFFFFF) {
 130                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 131                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 132         }
 133
 134         if (rxq->xtr_ol_flag) {
 135                 uint32_t metadata = 0;
 136
 137                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 138                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 139                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 140                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 141
 142                 if (metadata) {
 143                         mb->ol_flags |= rxq->xtr_ol_flag;
 144
 145                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 146                 }
 147         }
 148 #endif
 149 }
 150
 151 static void
 152 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
 153 {
 154         switch (rxdid) {
 155         case ICE_RXDID_COMMS_AUX_VLAN:
 156                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
 157                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 158                 break;
 159
 160         case ICE_RXDID_COMMS_AUX_IPV4:
 161                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
 162                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 163                 break;
 164
 165         case ICE_RXDID_COMMS_AUX_IPV6:
 166                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
 167                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 168                 break;
 169
 170         case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
 171                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
 172                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 173                 break;
 174
 175         case ICE_RXDID_COMMS_AUX_TCP:
 176                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
 177                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 178                 break;
 179
 180         case ICE_RXDID_COMMS_AUX_IP_OFFSET:
 181                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
 182                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v2;
 183                 break;
 184
 185         case ICE_RXDID_COMMS_OVS:
 186                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 187                 break;
 188
 189         default:
 190                 /* update this according to the RXDID for PROTO_XTR_NONE */
 191                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 192                 break;
 193         }
 194
 195         if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
 196                 rxq->xtr_ol_flag = 0;
 197 }
 198
 199 static enum ice_status
 200 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
 201 {
 202         struct ice_vsi *vsi = rxq->vsi;
 203         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 204         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
 205         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
 206         struct ice_rlan_ctx rx_ctx;
 207         enum ice_status err;
 208         uint16_t buf_size, len;
 209         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 210         uint32_t rxdid = ICE_RXDID_COMMS_OVS;
 211         uint32_t regval;
 212
 213         /* Set buffer size as the head split is disabled. */
 214         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 215                               RTE_PKTMBUF_HEADROOM);
 216         rxq->rx_hdr_len = 0;
 217         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
 218         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
 219         rxq->max_pkt_len = RTE_MIN(len,
 220                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
 221
 222         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 223                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
 224                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 225                         PMD_DRV_LOG(ERR, "maximum packet length must "
 226                                     "be larger than %u and smaller than %u,"
 227                                     "as jumbo frame is enabled",
 228                                     (uint32_t)RTE_ETHER_MAX_LEN,
 229                                     (uint32_t)ICE_FRAME_SIZE_MAX);
 230                         return -EINVAL;
 231                 }
 232         } else {
 233                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
 234                     rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
 235                         PMD_DRV_LOG(ERR, "maximum packet length must be "
 236                                     "larger than %u and smaller than %u, "
 237                                     "as jumbo frame is disabled",
 238                                     (uint32_t)RTE_ETHER_MIN_LEN,
 239                                     (uint32_t)RTE_ETHER_MAX_LEN);
 240                         return -EINVAL;
 241                 }
 242         }
 243
 244         memset(&rx_ctx, 0, sizeof(rx_ctx));
 245
 246         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 247         rx_ctx.qlen = rxq->nb_rx_desc;
 248         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 249         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 250         rx_ctx.dtype = 0; /* No Header Split mode */
 251 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 252         rx_ctx.dsize = 1; /* 32B descriptors */
 253 #endif
 254         rx_ctx.rxmax = rxq->max_pkt_len;
 255         /* TPH: Transaction Layer Packet (TLP) processing hints */
 256         rx_ctx.tphrdesc_ena = 1;
 257         rx_ctx.tphwdesc_ena = 1;
 258         rx_ctx.tphdata_ena = 1;
 259         rx_ctx.tphhead_ena = 1;
 260         /* Low Receive Queue Threshold defined in 64 descriptors units.
 261          * When the number of free descriptors goes below the lrxqthresh,
 262          * an immediate interrupt is triggered.
 263          */
 264         rx_ctx.lrxqthresh = 2;
 265         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 266         rx_ctx.l2tsel = 1;
 267         rx_ctx.showiv = 0;
 268         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 269
 270         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 271
 272         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 273                     rxq->port_id, rxq->queue_id, rxdid);
 274
 275         if (!(pf->supported_rxdid & BIT(rxdid))) {
 276                 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
 277                             rxdid);
 278                 return -EINVAL;
 279         }
 280
 281         ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
 282
 283         /* Enable Flexible Descriptors in the queue context which
 284          * allows this driver to select a specific receive descriptor format
 285          */
 286         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 287                 QRXFLXP_CNTXT_RXDID_IDX_M;
 288
 289         /* increasing context priority to pick up profile ID;
 290          * default is 0x01; setting to 0x03 to ensure profile
 291          * is programming if prev context is of same priority
 292          */
 293         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 294                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 295
 296         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 297
 298         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 299         if (err) {
 300                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 301                             rxq->queue_id);
 302                 return -EINVAL;
 303         }
 304         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 305         if (err) {
 306                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 307                             rxq->queue_id);
 308                 return -EINVAL;
 309         }
 310
 311         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 312                               RTE_PKTMBUF_HEADROOM);
 313
 314         /* Check if scattered RX needs to be used. */
 315         if (rxq->max_pkt_len > buf_size)
 316                 dev->data->scattered_rx = 1;
 317
 318         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 319
 320         /* Init the Rx tail register*/
 321         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 322
 323         return 0;
 324 }
 325
 326 /* Allocate mbufs for all descriptors in rx queue */
 327 static int
 328 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 329 {
 330         struct ice_rx_entry *rxe = rxq->sw_ring;
 331         uint64_t dma_addr;
 332         uint16_t i;
 333
 334         for (i = 0; i < rxq->nb_rx_desc; i++) {
 335                 volatile union ice_rx_flex_desc *rxd;
 336                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 337
 338                 if (unlikely(!mbuf)) {
 339                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 340                         return -ENOMEM;
 341                 }
 342
 343                 rte_mbuf_refcnt_set(mbuf, 1);
 344                 mbuf->next = NULL;
 345                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 346                 mbuf->nb_segs = 1;
 347                 mbuf->port = rxq->port_id;
 348
 349                 dma_addr =
 350                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 351
 352                 rxd = &rxq->rx_ring[i];
 353                 rxd->read.pkt_addr = dma_addr;
 354                 rxd->read.hdr_addr = 0;
 355 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 356                 rxd->read.rsvd1 = 0;
 357                 rxd->read.rsvd2 = 0;
 358 #endif
 359                 rxe[i].mbuf = mbuf;
 360         }
 361
 362         return 0;
 363 }
 364
 365 /* Free all mbufs for descriptors in rx queue */
 366 static void
 367 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 368 {
 369         uint16_t i;
 370
 371         if (!rxq || !rxq->sw_ring) {
 372                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 373                 return;
 374         }
 375
 376         for (i = 0; i < rxq->nb_rx_desc; i++) {
 377                 if (rxq->sw_ring[i].mbuf) {
 378                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 379                         rxq->sw_ring[i].mbuf = NULL;
 380                 }
 381         }
 382         if (rxq->rx_nb_avail == 0)
 383                 return;
 384         for (i = 0; i < rxq->rx_nb_avail; i++)
 385                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 386
 387         rxq->rx_nb_avail = 0;
 388 }
 389
 390 /* turn on or off rx queue
 391  * @q_idx: queue index in pf scope
 392  * @on: turn on or off the queue
 393  */
 394 static int
 395 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 396 {
 397         uint32_t reg;
 398         uint16_t j;
 399
 400         /* QRX_CTRL = QRX_ENA */
 401         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 402
 403         if (on) {
 404                 if (reg & QRX_CTRL_QENA_STAT_M)
 405                         return 0; /* Already on, skip */
 406                 reg |= QRX_CTRL_QENA_REQ_M;
 407         } else {
 408                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 409                         return 0; /* Already off, skip */
 410                 reg &= ~QRX_CTRL_QENA_REQ_M;
 411         }
 412
 413         /* Write the register */
 414         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 415         /* Check the result. It is said that QENA_STAT
 416          * follows the QENA_REQ not more than 10 use.
 417          * TODO: need to change the wait counter later
 418          */
 419         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 420                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 421                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 422                 if (on) {
 423                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 424                             (reg & QRX_CTRL_QENA_STAT_M))
 425                                 break;
 426                 } else {
 427                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 428                             !(reg & QRX_CTRL_QENA_STAT_M))
 429                                 break;
 430                 }
 431         }
 432
 433         /* Check if it is timeout */
 434         if (j >= ICE_CHK_Q_ENA_COUNT) {
 435                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 436                             (on ? "enable" : "disable"), q_idx);
 437                 return -ETIMEDOUT;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static inline int
 444 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 445 {
 446         int ret = 0;
 447
 448         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 449                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 450                              "rxq->rx_free_thresh=%d, "
 451                              "ICE_RX_MAX_BURST=%d",
 452                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 453                 ret = -EINVAL;
 454         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 455                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 456                              "rxq->rx_free_thresh=%d, "
 457                              "rxq->nb_rx_desc=%d",
 458                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 459                 ret = -EINVAL;
 460         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 461                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 462                              "rxq->nb_rx_desc=%d, "
 463                              "rxq->rx_free_thresh=%d",
 464                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 465                 ret = -EINVAL;
 466         }
 467
 468         return ret;
 469 }
 470
 471 /* reset fields in ice_rx_queue back to default */
 472 static void
 473 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 474 {
 475         unsigned int i;
 476         uint16_t len;
 477
 478         if (!rxq) {
 479                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 480                 return;
 481         }
 482
 483         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 484
 485         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 486                 ((volatile char *)rxq->rx_ring)[i] = 0;
 487
 488         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 489         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 490                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 491
 492         rxq->rx_nb_avail = 0;
 493         rxq->rx_next_avail = 0;
 494         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 495
 496         rxq->rx_tail = 0;
 497         rxq->nb_rx_hold = 0;
 498         rxq->pkt_first_seg = NULL;
 499         rxq->pkt_last_seg = NULL;
 500
 501         rxq->rxrearm_start = 0;
 502         rxq->rxrearm_nb = 0;
 503 }
 504
 505 int
 506 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 507 {
 508         struct ice_rx_queue *rxq;
 509         int err;
 510         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 511
 512         PMD_INIT_FUNC_TRACE();
 513
 514         if (rx_queue_id >= dev->data->nb_rx_queues) {
 515                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 516                             rx_queue_id, dev->data->nb_rx_queues);
 517                 return -EINVAL;
 518         }
 519
 520         rxq = dev->data->rx_queues[rx_queue_id];
 521         if (!rxq || !rxq->q_set) {
 522                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 523                             rx_queue_id);
 524                 return -EINVAL;
 525         }
 526
 527         err = ice_program_hw_rx_queue(rxq);
 528         if (err) {
 529                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 530                             rx_queue_id);
 531                 return -EIO;
 532         }
 533
 534         err = ice_alloc_rx_queue_mbufs(rxq);
 535         if (err) {
 536                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 537                 return -ENOMEM;
 538         }
 539
 540         /* Init the RX tail register. */
 541         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 542
 543         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 544         if (err) {
 545                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 546                             rx_queue_id);
 547
 548                 rxq->rx_rel_mbufs(rxq);
 549                 ice_reset_rx_queue(rxq);
 550                 return -EINVAL;
 551         }
 552
 553         dev->data->rx_queue_state[rx_queue_id] =
 554                 RTE_ETH_QUEUE_STATE_STARTED;
 555
 556         return 0;
 557 }
 558
 559 int
 560 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 561 {
 562         struct ice_rx_queue *rxq;
 563         int err;
 564         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 565
 566         if (rx_queue_id < dev->data->nb_rx_queues) {
 567                 rxq = dev->data->rx_queues[rx_queue_id];
 568
 569                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 570                 if (err) {
 571                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 572                                     rx_queue_id);
 573                         return -EINVAL;
 574                 }
 575                 rxq->rx_rel_mbufs(rxq);
 576                 ice_reset_rx_queue(rxq);
 577                 dev->data->rx_queue_state[rx_queue_id] =
 578                         RTE_ETH_QUEUE_STATE_STOPPED;
 579         }
 580
 581         return 0;
 582 }
 583
 584 int
 585 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 586 {
 587         struct ice_tx_queue *txq;
 588         int err;
 589         struct ice_vsi *vsi;
 590         struct ice_hw *hw;
 591         struct ice_aqc_add_tx_qgrp *txq_elem;
 592         struct ice_tlan_ctx tx_ctx;
 593         int buf_len;
 594
 595         PMD_INIT_FUNC_TRACE();
 596
 597         if (tx_queue_id >= dev->data->nb_tx_queues) {
 598                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 599                             tx_queue_id, dev->data->nb_tx_queues);
 600                 return -EINVAL;
 601         }
 602
 603         txq = dev->data->tx_queues[tx_queue_id];
 604         if (!txq || !txq->q_set) {
 605                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 606                             tx_queue_id);
 607                 return -EINVAL;
 608         }
 609
 610         buf_len = ice_struct_size(txq_elem, txqs, 1);
 611         txq_elem = ice_malloc(hw, buf_len);
 612         if (!txq_elem)
 613                 return -ENOMEM;
 614
 615         vsi = txq->vsi;
 616         hw = ICE_VSI_TO_HW(vsi);
 617
 618         memset(&tx_ctx, 0, sizeof(tx_ctx));
 619         txq_elem->num_txqs = 1;
 620         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 621
 622         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 623         tx_ctx.qlen = txq->nb_tx_desc;
 624         tx_ctx.pf_num = hw->pf_id;
 625         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 626         tx_ctx.src_vsi = vsi->vsi_id;
 627         tx_ctx.port_num = hw->port_info->lport;
 628         tx_ctx.tso_ena = 1; /* tso enable */
 629         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 630         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 631
 632         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 633                     ice_tlan_ctx_info);
 634
 635         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 636
 637         /* Init the Tx tail register*/
 638         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 639
 640         /* Fix me, we assume TC always 0 here */
 641         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 642                         txq_elem, buf_len, NULL);
 643         if (err) {
 644                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 645                 rte_free(txq_elem);
 646                 return -EIO;
 647         }
 648         /* store the schedule node id */
 649         txq->q_teid = txq_elem->txqs[0].q_teid;
 650
 651         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 652
 653         rte_free(txq_elem);
 654         return 0;
 655 }
 656
 657 static enum ice_status
 658 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 659 {
 660         struct ice_vsi *vsi = rxq->vsi;
 661         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 662         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 663         struct ice_rlan_ctx rx_ctx;
 664         enum ice_status err;
 665         uint32_t regval;
 666
 667         rxq->rx_hdr_len = 0;
 668         rxq->rx_buf_len = 1024;
 669
 670         memset(&rx_ctx, 0, sizeof(rx_ctx));
 671
 672         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 673         rx_ctx.qlen = rxq->nb_rx_desc;
 674         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 675         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 676         rx_ctx.dtype = 0; /* No Header Split mode */
 677         rx_ctx.dsize = 1; /* 32B descriptors */
 678         rx_ctx.rxmax = RTE_ETHER_MAX_LEN;
 679         /* TPH: Transaction Layer Packet (TLP) processing hints */
 680         rx_ctx.tphrdesc_ena = 1;
 681         rx_ctx.tphwdesc_ena = 1;
 682         rx_ctx.tphdata_ena = 1;
 683         rx_ctx.tphhead_ena = 1;
 684         /* Low Receive Queue Threshold defined in 64 descriptors units.
 685          * When the number of free descriptors goes below the lrxqthresh,
 686          * an immediate interrupt is triggered.
 687          */
 688         rx_ctx.lrxqthresh = 2;
 689         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 690         rx_ctx.l2tsel = 1;
 691         rx_ctx.showiv = 0;
 692         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 693
 694         /* Enable Flexible Descriptors in the queue context which
 695          * allows this driver to select a specific receive descriptor format
 696          */
 697         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 698                 QRXFLXP_CNTXT_RXDID_IDX_M;
 699
 700         /* increasing context priority to pick up profile ID;
 701          * default is 0x01; setting to 0x03 to ensure profile
 702          * is programming if prev context is of same priority
 703          */
 704         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 705                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 706
 707         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 708
 709         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 710         if (err) {
 711                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 712                             rxq->queue_id);
 713                 return -EINVAL;
 714         }
 715         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 716         if (err) {
 717                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 718                             rxq->queue_id);
 719                 return -EINVAL;
 720         }
 721
 722         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 723
 724         /* Init the Rx tail register*/
 725         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 726
 727         return 0;
 728 }
 729
 730 int
 731 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 732 {
 733         struct ice_rx_queue *rxq;
 734         int err;
 735         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 736         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 737
 738         PMD_INIT_FUNC_TRACE();
 739
 740         rxq = pf->fdir.rxq;
 741         if (!rxq || !rxq->q_set) {
 742                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 743                             rx_queue_id);
 744                 return -EINVAL;
 745         }
 746
 747         err = ice_fdir_program_hw_rx_queue(rxq);
 748         if (err) {
 749                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 750                             rx_queue_id);
 751                 return -EIO;
 752         }
 753
 754         /* Init the RX tail register. */
 755         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 756
 757         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 758         if (err) {
 759                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 760                             rx_queue_id);
 761
 762                 ice_reset_rx_queue(rxq);
 763                 return -EINVAL;
 764         }
 765
 766         return 0;
 767 }
 768
 769 int
 770 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 771 {
 772         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 773         struct ice_tx_queue *txq;
 774         int err;
 775         struct ice_vsi *vsi;
 776         struct ice_hw *hw;
 777         struct ice_aqc_add_tx_qgrp *txq_elem;
 778         struct ice_tlan_ctx tx_ctx;
 779         int buf_len;
 780
 781         PMD_INIT_FUNC_TRACE();
 782
 783         txq = pf->fdir.txq;
 784         if (!txq || !txq->q_set) {
 785                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 786                             tx_queue_id);
 787                 return -EINVAL;
 788         }
 789
 790         buf_len = ice_struct_size(txq_elem, txqs, 1);
 791         txq_elem = ice_malloc(hw, buf_len);
 792         if (!txq_elem)
 793                 return -ENOMEM;
 794
 795         vsi = txq->vsi;
 796         hw = ICE_VSI_TO_HW(vsi);
 797
 798         memset(&tx_ctx, 0, sizeof(tx_ctx));
 799         txq_elem->num_txqs = 1;
 800         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 801
 802         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 803         tx_ctx.qlen = txq->nb_tx_desc;
 804         tx_ctx.pf_num = hw->pf_id;
 805         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 806         tx_ctx.src_vsi = vsi->vsi_id;
 807         tx_ctx.port_num = hw->port_info->lport;
 808         tx_ctx.tso_ena = 1; /* tso enable */
 809         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 810         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 811
 812         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 813                     ice_tlan_ctx_info);
 814
 815         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 816
 817         /* Init the Tx tail register*/
 818         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 819
 820         /* Fix me, we assume TC always 0 here */
 821         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 822                               txq_elem, buf_len, NULL);
 823         if (err) {
 824                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 825                 rte_free(txq_elem);
 826                 return -EIO;
 827         }
 828         /* store the schedule node id */
 829         txq->q_teid = txq_elem->txqs[0].q_teid;
 830
 831         rte_free(txq_elem);
 832         return 0;
 833 }
 834
 835 /* Free all mbufs for descriptors in tx queue */
 836 static void
 837 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 838 {
 839         uint16_t i;
 840
 841         if (!txq || !txq->sw_ring) {
 842                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 843                 return;
 844         }
 845
 846         for (i = 0; i < txq->nb_tx_desc; i++) {
 847                 if (txq->sw_ring[i].mbuf) {
 848                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 849                         txq->sw_ring[i].mbuf = NULL;
 850                 }
 851         }
 852 }
 853
 854 static void
 855 ice_reset_tx_queue(struct ice_tx_queue *txq)
 856 {
 857         struct ice_tx_entry *txe;
 858         uint16_t i, prev, size;
 859
 860         if (!txq) {
 861                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 862                 return;
 863         }
 864
 865         txe = txq->sw_ring;
 866         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 867         for (i = 0; i < size; i++)
 868                 ((volatile char *)txq->tx_ring)[i] = 0;
 869
 870         prev = (uint16_t)(txq->nb_tx_desc - 1);
 871         for (i = 0; i < txq->nb_tx_desc; i++) {
 872                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 873
 874                 txd->cmd_type_offset_bsz =
 875                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 876                 txe[i].mbuf =  NULL;
 877                 txe[i].last_id = i;
 878                 txe[prev].next_id = i;
 879                 prev = i;
 880         }
 881
 882         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 883         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 884
 885         txq->tx_tail = 0;
 886         txq->nb_tx_used = 0;
 887
 888         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 889         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 890 }
 891
 892 int
 893 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 894 {
 895         struct ice_tx_queue *txq;
 896         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 897         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 898         struct ice_vsi *vsi = pf->main_vsi;
 899         enum ice_status status;
 900         uint16_t q_ids[1];
 901         uint32_t q_teids[1];
 902         uint16_t q_handle = tx_queue_id;
 903
 904         if (tx_queue_id >= dev->data->nb_tx_queues) {
 905                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 906                             tx_queue_id, dev->data->nb_tx_queues);
 907                 return -EINVAL;
 908         }
 909
 910         txq = dev->data->tx_queues[tx_queue_id];
 911         if (!txq) {
 912                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 913                             tx_queue_id);
 914                 return -EINVAL;
 915         }
 916
 917         q_ids[0] = txq->reg_idx;
 918         q_teids[0] = txq->q_teid;
 919
 920         /* Fix me, we assume TC always 0 here */
 921         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 922                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 923         if (status != ICE_SUCCESS) {
 924                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 925                 return -EINVAL;
 926         }
 927
 928         txq->tx_rel_mbufs(txq);
 929         ice_reset_tx_queue(txq);
 930         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 931
 932         return 0;
 933 }
 934
 935 int
 936 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 937 {
 938         struct ice_rx_queue *rxq;
 939         int err;
 940         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 941         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 942
 943         rxq = pf->fdir.rxq;
 944
 945         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 946         if (err) {
 947                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
 948                             rx_queue_id);
 949                 return -EINVAL;
 950         }
 951         rxq->rx_rel_mbufs(rxq);
 952
 953         return 0;
 954 }
 955
 956 int
 957 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 958 {
 959         struct ice_tx_queue *txq;
 960         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 961         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 962         struct ice_vsi *vsi = pf->main_vsi;
 963         enum ice_status status;
 964         uint16_t q_ids[1];
 965         uint32_t q_teids[1];
 966         uint16_t q_handle = tx_queue_id;
 967
 968         txq = pf->fdir.txq;
 969         if (!txq) {
 970                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 971                             tx_queue_id);
 972                 return -EINVAL;
 973         }
 974         vsi = txq->vsi;
 975
 976         q_ids[0] = txq->reg_idx;
 977         q_teids[0] = txq->q_teid;
 978
 979         /* Fix me, we assume TC always 0 here */
 980         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 981                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 982         if (status != ICE_SUCCESS) {
 983                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 984                 return -EINVAL;
 985         }
 986
 987         txq->tx_rel_mbufs(txq);
 988
 989         return 0;
 990 }
 991
 992 int
 993 ice_rx_queue_setup(struct rte_eth_dev *dev,
 994                    uint16_t queue_idx,
 995                    uint16_t nb_desc,
 996                    unsigned int socket_id,
 997                    const struct rte_eth_rxconf *rx_conf,
 998                    struct rte_mempool *mp)
 999 {
1000         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1001         struct ice_adapter *ad =
1002                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1003         struct ice_vsi *vsi = pf->main_vsi;
1004         struct ice_rx_queue *rxq;
1005         const struct rte_memzone *rz;
1006         uint32_t ring_size;
1007         uint16_t len;
1008         int use_def_burst_func = 1;
1009
1010         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1011             nb_desc > ICE_MAX_RING_DESC ||
1012             nb_desc < ICE_MIN_RING_DESC) {
1013                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1014                              "invalid", nb_desc);
1015                 return -EINVAL;
1016         }
1017
1018         /* Free memory if needed */
1019         if (dev->data->rx_queues[queue_idx]) {
1020                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1021                 dev->data->rx_queues[queue_idx] = NULL;
1022         }
1023
1024         /* Allocate the rx queue data structure */
1025         rxq = rte_zmalloc_socket(NULL,
1026                                  sizeof(struct ice_rx_queue),
1027                                  RTE_CACHE_LINE_SIZE,
1028                                  socket_id);
1029         if (!rxq) {
1030                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1031                              "rx queue data structure");
1032                 return -ENOMEM;
1033         }
1034         rxq->mp = mp;
1035         rxq->nb_rx_desc = nb_desc;
1036         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1037         rxq->queue_id = queue_idx;
1038
1039         rxq->reg_idx = vsi->base_queue + queue_idx;
1040         rxq->port_id = dev->data->port_id;
1041         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1042                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1043         else
1044                 rxq->crc_len = 0;
1045
1046         rxq->drop_en = rx_conf->rx_drop_en;
1047         rxq->vsi = vsi;
1048         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1049         rxq->proto_xtr = pf->proto_xtr != NULL ?
1050                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1051
1052         /* Allocate the maximun number of RX ring hardware descriptor. */
1053         len = ICE_MAX_RING_DESC;
1054
1055         /**
1056          * Allocating a little more memory because vectorized/bulk_alloc Rx
1057          * functions doesn't check boundaries each time.
1058          */
1059         len += ICE_RX_MAX_BURST;
1060
1061         /* Allocate the maximum number of RX ring hardware descriptor. */
1062         ring_size = sizeof(union ice_rx_flex_desc) * len;
1063         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1064         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1065                                       ring_size, ICE_RING_BASE_ALIGN,
1066                                       socket_id);
1067         if (!rz) {
1068                 ice_rx_queue_release(rxq);
1069                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1070                 return -ENOMEM;
1071         }
1072
1073         /* Zero all the descriptors in the ring. */
1074         memset(rz->addr, 0, ring_size);
1075
1076         rxq->rx_ring_dma = rz->iova;
1077         rxq->rx_ring = rz->addr;
1078
1079         /* always reserve more for bulk alloc */
1080         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1081
1082         /* Allocate the software ring. */
1083         rxq->sw_ring = rte_zmalloc_socket(NULL,
1084                                           sizeof(struct ice_rx_entry) * len,
1085                                           RTE_CACHE_LINE_SIZE,
1086                                           socket_id);
1087         if (!rxq->sw_ring) {
1088                 ice_rx_queue_release(rxq);
1089                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1090                 return -ENOMEM;
1091         }
1092
1093         ice_reset_rx_queue(rxq);
1094         rxq->q_set = true;
1095         dev->data->rx_queues[queue_idx] = rxq;
1096         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1097
1098         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1099
1100         if (!use_def_burst_func) {
1101                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1102                              "satisfied. Rx Burst Bulk Alloc function will be "
1103                              "used on port=%d, queue=%d.",
1104                              rxq->port_id, rxq->queue_id);
1105         } else {
1106                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1107                              "not satisfied, Scattered Rx is requested. "
1108                              "on port=%d, queue=%d.",
1109                              rxq->port_id, rxq->queue_id);
1110                 ad->rx_bulk_alloc_allowed = false;
1111         }
1112
1113         return 0;
1114 }
1115
1116 void
1117 ice_rx_queue_release(void *rxq)
1118 {
1119         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1120
1121         if (!q) {
1122                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1123                 return;
1124         }
1125
1126         q->rx_rel_mbufs(q);
1127         rte_free(q->sw_ring);
1128         rte_free(q);
1129 }
1130
1131 int
1132 ice_tx_queue_setup(struct rte_eth_dev *dev,
1133                    uint16_t queue_idx,
1134                    uint16_t nb_desc,
1135                    unsigned int socket_id,
1136                    const struct rte_eth_txconf *tx_conf)
1137 {
1138         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1139         struct ice_vsi *vsi = pf->main_vsi;
1140         struct ice_tx_queue *txq;
1141         const struct rte_memzone *tz;
1142         uint32_t ring_size;
1143         uint16_t tx_rs_thresh, tx_free_thresh;
1144         uint64_t offloads;
1145
1146         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1147
1148         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1149             nb_desc > ICE_MAX_RING_DESC ||
1150             nb_desc < ICE_MIN_RING_DESC) {
1151                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1152                              "invalid", nb_desc);
1153                 return -EINVAL;
1154         }
1155
1156         /**
1157          * The following two parameters control the setting of the RS bit on
1158          * transmit descriptors. TX descriptors will have their RS bit set
1159          * after txq->tx_rs_thresh descriptors have been used. The TX
1160          * descriptor ring will be cleaned after txq->tx_free_thresh
1161          * descriptors are used or if the number of descriptors required to
1162          * transmit a packet is greater than the number of free TX descriptors.
1163          *
1164          * The following constraints must be satisfied:
1165          *  - tx_rs_thresh must be greater than 0.
1166          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1167          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1168          *  - tx_rs_thresh must be a divisor of the ring size.
1169          *  - tx_free_thresh must be greater than 0.
1170          *  - tx_free_thresh must be less than the size of the ring minus 3.
1171          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1172          *
1173          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1174          * race condition, hence the maximum threshold constraints. When set
1175          * to zero use default values.
1176          */
1177         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1178                                     tx_conf->tx_free_thresh :
1179                                     ICE_DEFAULT_TX_FREE_THRESH);
1180         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1181         tx_rs_thresh =
1182                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1183                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1184         if (tx_conf->tx_rs_thresh)
1185                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1186         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1187                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1188                                 "exceed nb_desc. (tx_rs_thresh=%u "
1189                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1190                                 (unsigned int)tx_rs_thresh,
1191                                 (unsigned int)tx_free_thresh,
1192                                 (unsigned int)nb_desc,
1193                                 (int)dev->data->port_id,
1194                                 (int)queue_idx);
1195                 return -EINVAL;
1196         }
1197         if (tx_rs_thresh >= (nb_desc - 2)) {
1198                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1199                              "number of TX descriptors minus 2. "
1200                              "(tx_rs_thresh=%u port=%d queue=%d)",
1201                              (unsigned int)tx_rs_thresh,
1202                              (int)dev->data->port_id,
1203                              (int)queue_idx);
1204                 return -EINVAL;
1205         }
1206         if (tx_free_thresh >= (nb_desc - 3)) {
1207                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1208                              "tx_free_thresh must be less than the "
1209                              "number of TX descriptors minus 3. "
1210                              "(tx_free_thresh=%u port=%d queue=%d)",
1211                              (unsigned int)tx_free_thresh,
1212                              (int)dev->data->port_id,
1213                              (int)queue_idx);
1214                 return -EINVAL;
1215         }
1216         if (tx_rs_thresh > tx_free_thresh) {
1217                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1218                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1219                              " tx_rs_thresh=%u port=%d queue=%d)",
1220                              (unsigned int)tx_free_thresh,
1221                              (unsigned int)tx_rs_thresh,
1222                              (int)dev->data->port_id,
1223                              (int)queue_idx);
1224                 return -EINVAL;
1225         }
1226         if ((nb_desc % tx_rs_thresh) != 0) {
1227                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1228                              "number of TX descriptors. (tx_rs_thresh=%u"
1229                              " port=%d queue=%d)",
1230                              (unsigned int)tx_rs_thresh,
1231                              (int)dev->data->port_id,
1232                              (int)queue_idx);
1233                 return -EINVAL;
1234         }
1235         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1236                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1237                              "tx_rs_thresh is greater than 1. "
1238                              "(tx_rs_thresh=%u port=%d queue=%d)",
1239                              (unsigned int)tx_rs_thresh,
1240                              (int)dev->data->port_id,
1241                              (int)queue_idx);
1242                 return -EINVAL;
1243         }
1244
1245         /* Free memory if needed. */
1246         if (dev->data->tx_queues[queue_idx]) {
1247                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1248                 dev->data->tx_queues[queue_idx] = NULL;
1249         }
1250
1251         /* Allocate the TX queue data structure. */
1252         txq = rte_zmalloc_socket(NULL,
1253                                  sizeof(struct ice_tx_queue),
1254                                  RTE_CACHE_LINE_SIZE,
1255                                  socket_id);
1256         if (!txq) {
1257                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1258                              "tx queue structure");
1259                 return -ENOMEM;
1260         }
1261
1262         /* Allocate TX hardware ring descriptors. */
1263         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1264         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1265         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1266                                       ring_size, ICE_RING_BASE_ALIGN,
1267                                       socket_id);
1268         if (!tz) {
1269                 ice_tx_queue_release(txq);
1270                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1271                 return -ENOMEM;
1272         }
1273
1274         txq->nb_tx_desc = nb_desc;
1275         txq->tx_rs_thresh = tx_rs_thresh;
1276         txq->tx_free_thresh = tx_free_thresh;
1277         txq->pthresh = tx_conf->tx_thresh.pthresh;
1278         txq->hthresh = tx_conf->tx_thresh.hthresh;
1279         txq->wthresh = tx_conf->tx_thresh.wthresh;
1280         txq->queue_id = queue_idx;
1281
1282         txq->reg_idx = vsi->base_queue + queue_idx;
1283         txq->port_id = dev->data->port_id;
1284         txq->offloads = offloads;
1285         txq->vsi = vsi;
1286         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1287
1288         txq->tx_ring_dma = tz->iova;
1289         txq->tx_ring = tz->addr;
1290
1291         /* Allocate software ring */
1292         txq->sw_ring =
1293                 rte_zmalloc_socket(NULL,
1294                                    sizeof(struct ice_tx_entry) * nb_desc,
1295                                    RTE_CACHE_LINE_SIZE,
1296                                    socket_id);
1297         if (!txq->sw_ring) {
1298                 ice_tx_queue_release(txq);
1299                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1300                 return -ENOMEM;
1301         }
1302
1303         ice_reset_tx_queue(txq);
1304         txq->q_set = true;
1305         dev->data->tx_queues[queue_idx] = txq;
1306         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1307         ice_set_tx_function_flag(dev, txq);
1308
1309         return 0;
1310 }
1311
1312 void
1313 ice_tx_queue_release(void *txq)
1314 {
1315         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1316
1317         if (!q) {
1318                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1319                 return;
1320         }
1321
1322         q->tx_rel_mbufs(q);
1323         rte_free(q->sw_ring);
1324         rte_free(q);
1325 }
1326
1327 void
1328 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1329                  struct rte_eth_rxq_info *qinfo)
1330 {
1331         struct ice_rx_queue *rxq;
1332
1333         rxq = dev->data->rx_queues[queue_id];
1334
1335         qinfo->mp = rxq->mp;
1336         qinfo->scattered_rx = dev->data->scattered_rx;
1337         qinfo->nb_desc = rxq->nb_rx_desc;
1338
1339         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1340         qinfo->conf.rx_drop_en = rxq->drop_en;
1341         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1342 }
1343
1344 void
1345 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1346                  struct rte_eth_txq_info *qinfo)
1347 {
1348         struct ice_tx_queue *txq;
1349
1350         txq = dev->data->tx_queues[queue_id];
1351
1352         qinfo->nb_desc = txq->nb_tx_desc;
1353
1354         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1355         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1356         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1357
1358         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1359         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1360         qinfo->conf.offloads = txq->offloads;
1361         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1362 }
1363
1364 uint32_t
1365 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1366 {
1367 #define ICE_RXQ_SCAN_INTERVAL 4
1368         volatile union ice_rx_flex_desc *rxdp;
1369         struct ice_rx_queue *rxq;
1370         uint16_t desc = 0;
1371
1372         rxq = dev->data->rx_queues[rx_queue_id];
1373         rxdp = &rxq->rx_ring[rxq->rx_tail];
1374         while ((desc < rxq->nb_rx_desc) &&
1375                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1376                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1377                 /**
1378                  * Check the DD bit of a rx descriptor of each 4 in a group,
1379                  * to avoid checking too frequently and downgrading performance
1380                  * too much.
1381                  */
1382                 desc += ICE_RXQ_SCAN_INTERVAL;
1383                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1384                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1385                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1386                                  desc - rxq->nb_rx_desc]);
1387         }
1388
1389         return desc;
1390 }
1391
1392 #define ICE_RX_FLEX_ERR0_BITS   \
1393         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1394          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1395          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1396          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1397          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1398          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1399
1400 /* Rx L3/L4 checksum */
1401 static inline uint64_t
1402 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1403 {
1404         uint64_t flags = 0;
1405
1406         /* check if HW has decoded the packet and checksum */
1407         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1408                 return 0;
1409
1410         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1411                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1412                 return flags;
1413         }
1414
1415         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1416                 flags |= PKT_RX_IP_CKSUM_BAD;
1417         else
1418                 flags |= PKT_RX_IP_CKSUM_GOOD;
1419
1420         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1421                 flags |= PKT_RX_L4_CKSUM_BAD;
1422         else
1423                 flags |= PKT_RX_L4_CKSUM_GOOD;
1424
1425         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1426                 flags |= PKT_RX_EIP_CKSUM_BAD;
1427
1428         return flags;
1429 }
1430
1431 static inline void
1432 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1433 {
1434         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1435             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1436                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1437                 mb->vlan_tci =
1438                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1439                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1440                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1441         } else {
1442                 mb->vlan_tci = 0;
1443         }
1444
1445 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1446         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1447             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1448                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1449                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1450                 mb->vlan_tci_outer = mb->vlan_tci;
1451                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1452                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1453                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1454                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1455         } else {
1456                 mb->vlan_tci_outer = 0;
1457         }
1458 #endif
1459         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1460                    mb->vlan_tci, mb->vlan_tci_outer);
1461 }
1462
1463 #define ICE_LOOK_AHEAD 8
1464 #if (ICE_LOOK_AHEAD != 8)
1465 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1466 #endif
1467 static inline int
1468 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1469 {
1470         volatile union ice_rx_flex_desc *rxdp;
1471         struct ice_rx_entry *rxep;
1472         struct rte_mbuf *mb;
1473         uint16_t stat_err0;
1474         uint16_t pkt_len;
1475         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1476         int32_t i, j, nb_rx = 0;
1477         uint64_t pkt_flags = 0;
1478         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1479
1480         rxdp = &rxq->rx_ring[rxq->rx_tail];
1481         rxep = &rxq->sw_ring[rxq->rx_tail];
1482
1483         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1484
1485         /* Make sure there is at least 1 packet to receive */
1486         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1487                 return 0;
1488
1489         /**
1490          * Scan LOOK_AHEAD descriptors at a time to determine which
1491          * descriptors reference packets that are ready to be received.
1492          */
1493         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1494              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1495                 /* Read desc statuses backwards to avoid race condition */
1496                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1497                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1498
1499                 rte_smp_rmb();
1500
1501                 /* Compute how many status bits were set */
1502                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1503                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1504
1505                 nb_rx += nb_dd;
1506
1507                 /* Translate descriptor info to mbuf parameters */
1508                 for (j = 0; j < nb_dd; j++) {
1509                         mb = rxep[j].mbuf;
1510                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1511                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1512                         mb->data_len = pkt_len;
1513                         mb->pkt_len = pkt_len;
1514                         mb->ol_flags = 0;
1515                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1516                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1517                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1518                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1519                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1520                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1521
1522                         mb->ol_flags |= pkt_flags;
1523                 }
1524
1525                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1526                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1527
1528                 if (nb_dd != ICE_LOOK_AHEAD)
1529                         break;
1530         }
1531
1532         /* Clear software ring entries */
1533         for (i = 0; i < nb_rx; i++)
1534                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1535
1536         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1537                    "port_id=%u, queue_id=%u, nb_rx=%d",
1538                    rxq->port_id, rxq->queue_id, nb_rx);
1539
1540         return nb_rx;
1541 }
1542
1543 static inline uint16_t
1544 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1545                        struct rte_mbuf **rx_pkts,
1546                        uint16_t nb_pkts)
1547 {
1548         uint16_t i;
1549         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1550
1551         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1552
1553         for (i = 0; i < nb_pkts; i++)
1554                 rx_pkts[i] = stage[i];
1555
1556         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1557         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1558
1559         return nb_pkts;
1560 }
1561
1562 static inline int
1563 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1564 {
1565         volatile union ice_rx_flex_desc *rxdp;
1566         struct ice_rx_entry *rxep;
1567         struct rte_mbuf *mb;
1568         uint16_t alloc_idx, i;
1569         uint64_t dma_addr;
1570         int diag;
1571
1572         /* Allocate buffers in bulk */
1573         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1574                                (rxq->rx_free_thresh - 1));
1575         rxep = &rxq->sw_ring[alloc_idx];
1576         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1577                                     rxq->rx_free_thresh);
1578         if (unlikely(diag != 0)) {
1579                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1580                 return -ENOMEM;
1581         }
1582
1583         rxdp = &rxq->rx_ring[alloc_idx];
1584         for (i = 0; i < rxq->rx_free_thresh; i++) {
1585                 if (likely(i < (rxq->rx_free_thresh - 1)))
1586                         /* Prefetch next mbuf */
1587                         rte_prefetch0(rxep[i + 1].mbuf);
1588
1589                 mb = rxep[i].mbuf;
1590                 rte_mbuf_refcnt_set(mb, 1);
1591                 mb->next = NULL;
1592                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1593                 mb->nb_segs = 1;
1594                 mb->port = rxq->port_id;
1595                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1596                 rxdp[i].read.hdr_addr = 0;
1597                 rxdp[i].read.pkt_addr = dma_addr;
1598         }
1599
1600         /* Update rx tail regsiter */
1601         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1602
1603         rxq->rx_free_trigger =
1604                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1605         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1606                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1607
1608         return 0;
1609 }
1610
1611 static inline uint16_t
1612 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1613 {
1614         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1615         uint16_t nb_rx = 0;
1616         struct rte_eth_dev *dev;
1617
1618         if (!nb_pkts)
1619                 return 0;
1620
1621         if (rxq->rx_nb_avail)
1622                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1623
1624         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1625         rxq->rx_next_avail = 0;
1626         rxq->rx_nb_avail = nb_rx;
1627         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1628
1629         if (rxq->rx_tail > rxq->rx_free_trigger) {
1630                 if (ice_rx_alloc_bufs(rxq) != 0) {
1631                         uint16_t i, j;
1632
1633                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1634                         dev->data->rx_mbuf_alloc_failed +=
1635                                 rxq->rx_free_thresh;
1636                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1637                                    "port_id=%u, queue_id=%u",
1638                                    rxq->port_id, rxq->queue_id);
1639                         rxq->rx_nb_avail = 0;
1640                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1641                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1642                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1643
1644                         return 0;
1645                 }
1646         }
1647
1648         if (rxq->rx_tail >= rxq->nb_rx_desc)
1649                 rxq->rx_tail = 0;
1650
1651         if (rxq->rx_nb_avail)
1652                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1653
1654         return 0;
1655 }
1656
1657 static uint16_t
1658 ice_recv_pkts_bulk_alloc(void *rx_queue,
1659                          struct rte_mbuf **rx_pkts,
1660                          uint16_t nb_pkts)
1661 {
1662         uint16_t nb_rx = 0;
1663         uint16_t n;
1664         uint16_t count;
1665
1666         if (unlikely(nb_pkts == 0))
1667                 return nb_rx;
1668
1669         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1670                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1671
1672         while (nb_pkts) {
1673                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1674                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1675                 nb_rx = (uint16_t)(nb_rx + count);
1676                 nb_pkts = (uint16_t)(nb_pkts - count);
1677                 if (count < n)
1678                         break;
1679         }
1680
1681         return nb_rx;
1682 }
1683
1684 static uint16_t
1685 ice_recv_scattered_pkts(void *rx_queue,
1686                         struct rte_mbuf **rx_pkts,
1687                         uint16_t nb_pkts)
1688 {
1689         struct ice_rx_queue *rxq = rx_queue;
1690         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1691         volatile union ice_rx_flex_desc *rxdp;
1692         union ice_rx_flex_desc rxd;
1693         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1694         struct ice_rx_entry *rxe;
1695         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1696         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1697         struct rte_mbuf *nmb; /* new allocated mbuf */
1698         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1699         uint16_t rx_id = rxq->rx_tail;
1700         uint16_t nb_rx = 0;
1701         uint16_t nb_hold = 0;
1702         uint16_t rx_packet_len;
1703         uint16_t rx_stat_err0;
1704         uint64_t dma_addr;
1705         uint64_t pkt_flags;
1706         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1707         struct rte_eth_dev *dev;
1708
1709         while (nb_rx < nb_pkts) {
1710                 rxdp = &rx_ring[rx_id];
1711                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1712
1713                 /* Check the DD bit first */
1714                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1715                         break;
1716
1717                 /* allocate mbuf */
1718                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1719                 if (unlikely(!nmb)) {
1720                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1721                         dev->data->rx_mbuf_alloc_failed++;
1722                         break;
1723                 }
1724                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1725
1726                 nb_hold++;
1727                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1728                 rx_id++;
1729                 if (unlikely(rx_id == rxq->nb_rx_desc))
1730                         rx_id = 0;
1731
1732                 /* Prefetch next mbuf */
1733                 rte_prefetch0(sw_ring[rx_id].mbuf);
1734
1735                 /**
1736                  * When next RX descriptor is on a cache line boundary,
1737                  * prefetch the next 4 RX descriptors and next 8 pointers
1738                  * to mbufs.
1739                  */
1740                 if ((rx_id & 0x3) == 0) {
1741                         rte_prefetch0(&rx_ring[rx_id]);
1742                         rte_prefetch0(&sw_ring[rx_id]);
1743                 }
1744
1745                 rxm = rxe->mbuf;
1746                 rxe->mbuf = nmb;
1747                 dma_addr =
1748                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1749
1750                 /* Set data buffer address and data length of the mbuf */
1751                 rxdp->read.hdr_addr = 0;
1752                 rxdp->read.pkt_addr = dma_addr;
1753                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1754                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1755                 rxm->data_len = rx_packet_len;
1756                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1757
1758                 /**
1759                  * If this is the first buffer of the received packet, set the
1760                  * pointer to the first mbuf of the packet and initialize its
1761                  * context. Otherwise, update the total length and the number
1762                  * of segments of the current scattered packet, and update the
1763                  * pointer to the last mbuf of the current packet.
1764                  */
1765                 if (!first_seg) {
1766                         first_seg = rxm;
1767                         first_seg->nb_segs = 1;
1768                         first_seg->pkt_len = rx_packet_len;
1769                 } else {
1770                         first_seg->pkt_len =
1771                                 (uint16_t)(first_seg->pkt_len +
1772                                            rx_packet_len);
1773                         first_seg->nb_segs++;
1774                         last_seg->next = rxm;
1775                 }
1776
1777                 /**
1778                  * If this is not the last buffer of the received packet,
1779                  * update the pointer to the last mbuf of the current scattered
1780                  * packet and continue to parse the RX ring.
1781                  */
1782                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1783                         last_seg = rxm;
1784                         continue;
1785                 }
1786
1787                 /**
1788                  * This is the last buffer of the received packet. If the CRC
1789                  * is not stripped by the hardware:
1790                  *  - Subtract the CRC length from the total packet length.
1791                  *  - If the last buffer only contains the whole CRC or a part
1792                  *  of it, free the mbuf associated to the last buffer. If part
1793                  *  of the CRC is also contained in the previous mbuf, subtract
1794                  *  the length of that CRC part from the data length of the
1795                  *  previous mbuf.
1796                  */
1797                 rxm->next = NULL;
1798                 if (unlikely(rxq->crc_len > 0)) {
1799                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1800                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1801                                 rte_pktmbuf_free_seg(rxm);
1802                                 first_seg->nb_segs--;
1803                                 last_seg->data_len =
1804                                         (uint16_t)(last_seg->data_len -
1805                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1806                                 last_seg->next = NULL;
1807                         } else
1808                                 rxm->data_len = (uint16_t)(rx_packet_len -
1809                                                            RTE_ETHER_CRC_LEN);
1810                 }
1811
1812                 first_seg->port = rxq->port_id;
1813                 first_seg->ol_flags = 0;
1814                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1815                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1816                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1817                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1818                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1819                 first_seg->ol_flags |= pkt_flags;
1820                 /* Prefetch data of first segment, if configured to do so. */
1821                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1822                                           first_seg->data_off));
1823                 rx_pkts[nb_rx++] = first_seg;
1824                 first_seg = NULL;
1825         }
1826
1827         /* Record index of the next RX descriptor to probe. */
1828         rxq->rx_tail = rx_id;
1829         rxq->pkt_first_seg = first_seg;
1830         rxq->pkt_last_seg = last_seg;
1831
1832         /**
1833          * If the number of free RX descriptors is greater than the RX free
1834          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1835          * register. Update the RDT with the value of the last processed RX
1836          * descriptor minus 1, to guarantee that the RDT register is never
1837          * equal to the RDH register, which creates a "full" ring situtation
1838          * from the hardware point of view.
1839          */
1840         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1841         if (nb_hold > rxq->rx_free_thresh) {
1842                 rx_id = (uint16_t)(rx_id == 0 ?
1843                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1844                 /* write TAIL register */
1845                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1846                 nb_hold = 0;
1847         }
1848         rxq->nb_rx_hold = nb_hold;
1849
1850         /* return received packet in the burst */
1851         return nb_rx;
1852 }
1853
1854 const uint32_t *
1855 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1856 {
1857         struct ice_adapter *ad =
1858                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1859         const uint32_t *ptypes;
1860
1861         static const uint32_t ptypes_os[] = {
1862                 /* refers to ice_get_default_pkt_type() */
1863                 RTE_PTYPE_L2_ETHER,
1864                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1865                 RTE_PTYPE_L2_ETHER_LLDP,
1866                 RTE_PTYPE_L2_ETHER_ARP,
1867                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1868                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1869                 RTE_PTYPE_L4_FRAG,
1870                 RTE_PTYPE_L4_ICMP,
1871                 RTE_PTYPE_L4_NONFRAG,
1872                 RTE_PTYPE_L4_SCTP,
1873                 RTE_PTYPE_L4_TCP,
1874                 RTE_PTYPE_L4_UDP,
1875                 RTE_PTYPE_TUNNEL_GRENAT,
1876                 RTE_PTYPE_TUNNEL_IP,
1877                 RTE_PTYPE_INNER_L2_ETHER,
1878                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1879                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1880                 RTE_PTYPE_INNER_L4_FRAG,
1881                 RTE_PTYPE_INNER_L4_ICMP,
1882                 RTE_PTYPE_INNER_L4_NONFRAG,
1883                 RTE_PTYPE_INNER_L4_SCTP,
1884                 RTE_PTYPE_INNER_L4_TCP,
1885                 RTE_PTYPE_INNER_L4_UDP,
1886                 RTE_PTYPE_UNKNOWN
1887         };
1888
1889         static const uint32_t ptypes_comms[] = {
1890                 /* refers to ice_get_default_pkt_type() */
1891                 RTE_PTYPE_L2_ETHER,
1892                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1893                 RTE_PTYPE_L2_ETHER_LLDP,
1894                 RTE_PTYPE_L2_ETHER_ARP,
1895                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1896                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1897                 RTE_PTYPE_L4_FRAG,
1898                 RTE_PTYPE_L4_ICMP,
1899                 RTE_PTYPE_L4_NONFRAG,
1900                 RTE_PTYPE_L4_SCTP,
1901                 RTE_PTYPE_L4_TCP,
1902                 RTE_PTYPE_L4_UDP,
1903                 RTE_PTYPE_TUNNEL_GRENAT,
1904                 RTE_PTYPE_TUNNEL_IP,
1905                 RTE_PTYPE_INNER_L2_ETHER,
1906                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1907                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1908                 RTE_PTYPE_INNER_L4_FRAG,
1909                 RTE_PTYPE_INNER_L4_ICMP,
1910                 RTE_PTYPE_INNER_L4_NONFRAG,
1911                 RTE_PTYPE_INNER_L4_SCTP,
1912                 RTE_PTYPE_INNER_L4_TCP,
1913                 RTE_PTYPE_INNER_L4_UDP,
1914                 RTE_PTYPE_TUNNEL_GTPC,
1915                 RTE_PTYPE_TUNNEL_GTPU,
1916                 RTE_PTYPE_L2_ETHER_PPPOE,
1917                 RTE_PTYPE_UNKNOWN
1918         };
1919
1920         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
1921                 ptypes = ptypes_comms;
1922         else
1923                 ptypes = ptypes_os;
1924
1925         if (dev->rx_pkt_burst == ice_recv_pkts ||
1926             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1927             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1928                 return ptypes;
1929
1930 #ifdef RTE_ARCH_X86
1931         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1932             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1933 #ifdef CC_AVX512_SUPPORT
1934             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
1935             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
1936 #endif
1937             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1938             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1939                 return ptypes;
1940 #endif
1941
1942         return NULL;
1943 }
1944
1945 int
1946 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1947 {
1948         volatile union ice_rx_flex_desc *rxdp;
1949         struct ice_rx_queue *rxq = rx_queue;
1950         uint32_t desc;
1951
1952         if (unlikely(offset >= rxq->nb_rx_desc))
1953                 return -EINVAL;
1954
1955         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1956                 return RTE_ETH_RX_DESC_UNAVAIL;
1957
1958         desc = rxq->rx_tail + offset;
1959         if (desc >= rxq->nb_rx_desc)
1960                 desc -= rxq->nb_rx_desc;
1961
1962         rxdp = &rxq->rx_ring[desc];
1963         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1964             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1965                 return RTE_ETH_RX_DESC_DONE;
1966
1967         return RTE_ETH_RX_DESC_AVAIL;
1968 }
1969
1970 int
1971 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1972 {
1973         struct ice_tx_queue *txq = tx_queue;
1974         volatile uint64_t *status;
1975         uint64_t mask, expect;
1976         uint32_t desc;
1977
1978         if (unlikely(offset >= txq->nb_tx_desc))
1979                 return -EINVAL;
1980
1981         desc = txq->tx_tail + offset;
1982         /* go to next desc that has the RS bit */
1983         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1984                 txq->tx_rs_thresh;
1985         if (desc >= txq->nb_tx_desc) {
1986                 desc -= txq->nb_tx_desc;
1987                 if (desc >= txq->nb_tx_desc)
1988                         desc -= txq->nb_tx_desc;
1989         }
1990
1991         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1992         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1993         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1994                                   ICE_TXD_QW1_DTYPE_S);
1995         if ((*status & mask) == expect)
1996                 return RTE_ETH_TX_DESC_DONE;
1997
1998         return RTE_ETH_TX_DESC_FULL;
1999 }
2000
2001 void
2002 ice_free_queues(struct rte_eth_dev *dev)
2003 {
2004         uint16_t i;
2005
2006         PMD_INIT_FUNC_TRACE();
2007
2008         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2009                 if (!dev->data->rx_queues[i])
2010                         continue;
2011                 ice_rx_queue_release(dev->data->rx_queues[i]);
2012                 dev->data->rx_queues[i] = NULL;
2013                 rte_eth_dma_zone_free(dev, "rx_ring", i);
2014         }
2015         dev->data->nb_rx_queues = 0;
2016
2017         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2018                 if (!dev->data->tx_queues[i])
2019                         continue;
2020                 ice_tx_queue_release(dev->data->tx_queues[i]);
2021                 dev->data->tx_queues[i] = NULL;
2022                 rte_eth_dma_zone_free(dev, "tx_ring", i);
2023         }
2024         dev->data->nb_tx_queues = 0;
2025 }
2026
2027 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
2028 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
2029
2030 int
2031 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2032 {
2033         struct ice_tx_queue *txq;
2034         const struct rte_memzone *tz = NULL;
2035         uint32_t ring_size;
2036         struct rte_eth_dev *dev;
2037
2038         if (!pf) {
2039                 PMD_DRV_LOG(ERR, "PF is not available");
2040                 return -EINVAL;
2041         }
2042
2043         dev = pf->adapter->eth_dev;
2044
2045         /* Allocate the TX queue data structure. */
2046         txq = rte_zmalloc_socket("ice fdir tx queue",
2047                                  sizeof(struct ice_tx_queue),
2048                                  RTE_CACHE_LINE_SIZE,
2049                                  SOCKET_ID_ANY);
2050         if (!txq) {
2051                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2052                             "tx queue structure.");
2053                 return -ENOMEM;
2054         }
2055
2056         /* Allocate TX hardware ring descriptors. */
2057         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2058         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2059
2060         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2061                                       ICE_FDIR_QUEUE_ID, ring_size,
2062                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2063         if (!tz) {
2064                 ice_tx_queue_release(txq);
2065                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2066                 return -ENOMEM;
2067         }
2068
2069         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2070         txq->queue_id = ICE_FDIR_QUEUE_ID;
2071         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2072         txq->vsi = pf->fdir.fdir_vsi;
2073
2074         txq->tx_ring_dma = tz->iova;
2075         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2076         /*
2077          * don't need to allocate software ring and reset for the fdir
2078          * program queue just set the queue has been configured.
2079          */
2080         txq->q_set = true;
2081         pf->fdir.txq = txq;
2082
2083         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2084
2085         return ICE_SUCCESS;
2086 }
2087
2088 int
2089 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2090 {
2091         struct ice_rx_queue *rxq;
2092         const struct rte_memzone *rz = NULL;
2093         uint32_t ring_size;
2094         struct rte_eth_dev *dev;
2095
2096         if (!pf) {
2097                 PMD_DRV_LOG(ERR, "PF is not available");
2098                 return -EINVAL;
2099         }
2100
2101         dev = pf->adapter->eth_dev;
2102
2103         /* Allocate the RX queue data structure. */
2104         rxq = rte_zmalloc_socket("ice fdir rx queue",
2105                                  sizeof(struct ice_rx_queue),
2106                                  RTE_CACHE_LINE_SIZE,
2107                                  SOCKET_ID_ANY);
2108         if (!rxq) {
2109                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2110                             "rx queue structure.");
2111                 return -ENOMEM;
2112         }
2113
2114         /* Allocate RX hardware ring descriptors. */
2115         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2116         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2117
2118         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2119                                       ICE_FDIR_QUEUE_ID, ring_size,
2120                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2121         if (!rz) {
2122                 ice_rx_queue_release(rxq);
2123                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2124                 return -ENOMEM;
2125         }
2126
2127         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2128         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2129         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2130         rxq->vsi = pf->fdir.fdir_vsi;
2131
2132         rxq->rx_ring_dma = rz->iova;
2133         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2134                sizeof(union ice_32byte_rx_desc));
2135         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2136
2137         /*
2138          * Don't need to allocate software ring and reset for the fdir
2139          * rx queue, just set the queue has been configured.
2140          */
2141         rxq->q_set = true;
2142         pf->fdir.rxq = rxq;
2143
2144         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2145
2146         return ICE_SUCCESS;
2147 }
2148
2149 uint16_t
2150 ice_recv_pkts(void *rx_queue,
2151               struct rte_mbuf **rx_pkts,
2152               uint16_t nb_pkts)
2153 {
2154         struct ice_rx_queue *rxq = rx_queue;
2155         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2156         volatile union ice_rx_flex_desc *rxdp;
2157         union ice_rx_flex_desc rxd;
2158         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2159         struct ice_rx_entry *rxe;
2160         struct rte_mbuf *nmb; /* new allocated mbuf */
2161         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2162         uint16_t rx_id = rxq->rx_tail;
2163         uint16_t nb_rx = 0;
2164         uint16_t nb_hold = 0;
2165         uint16_t rx_packet_len;
2166         uint16_t rx_stat_err0;
2167         uint64_t dma_addr;
2168         uint64_t pkt_flags;
2169         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2170         struct rte_eth_dev *dev;
2171
2172         while (nb_rx < nb_pkts) {
2173                 rxdp = &rx_ring[rx_id];
2174                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2175
2176                 /* Check the DD bit first */
2177                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2178                         break;
2179
2180                 /* allocate mbuf */
2181                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2182                 if (unlikely(!nmb)) {
2183                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
2184                         dev->data->rx_mbuf_alloc_failed++;
2185                         break;
2186                 }
2187                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2188
2189                 nb_hold++;
2190                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2191                 rx_id++;
2192                 if (unlikely(rx_id == rxq->nb_rx_desc))
2193                         rx_id = 0;
2194                 rxm = rxe->mbuf;
2195                 rxe->mbuf = nmb;
2196                 dma_addr =
2197                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2198
2199                 /**
2200                  * fill the read format of descriptor with physic address in
2201                  * new allocated mbuf: nmb
2202                  */
2203                 rxdp->read.hdr_addr = 0;
2204                 rxdp->read.pkt_addr = dma_addr;
2205
2206                 /* calculate rx_packet_len of the received pkt */
2207                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2208                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2209
2210                 /* fill old mbuf with received descriptor: rxd */
2211                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2212                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2213                 rxm->nb_segs = 1;
2214                 rxm->next = NULL;
2215                 rxm->pkt_len = rx_packet_len;
2216                 rxm->data_len = rx_packet_len;
2217                 rxm->port = rxq->port_id;
2218                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2219                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2220                 ice_rxd_to_vlan_tci(rxm, &rxd);
2221                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
2222                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2223                 rxm->ol_flags |= pkt_flags;
2224                 /* copy old mbuf to rx_pkts */
2225                 rx_pkts[nb_rx++] = rxm;
2226         }
2227         rxq->rx_tail = rx_id;
2228         /**
2229          * If the number of free RX descriptors is greater than the RX free
2230          * threshold of the queue, advance the receive tail register of queue.
2231          * Update that register with the value of the last processed RX
2232          * descriptor minus 1.
2233          */
2234         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2235         if (nb_hold > rxq->rx_free_thresh) {
2236                 rx_id = (uint16_t)(rx_id == 0 ?
2237                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2238                 /* write TAIL register */
2239                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2240                 nb_hold = 0;
2241         }
2242         rxq->nb_rx_hold = nb_hold;
2243
2244         /* return received packet in the burst */
2245         return nb_rx;
2246 }
2247
2248 static inline void
2249 ice_parse_tunneling_params(uint64_t ol_flags,
2250                             union ice_tx_offload tx_offload,
2251                             uint32_t *cd_tunneling)
2252 {
2253         /* EIPT: External (outer) IP header type */
2254         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2255                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2256         else if (ol_flags & PKT_TX_OUTER_IPV4)
2257                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2258         else if (ol_flags & PKT_TX_OUTER_IPV6)
2259                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2260
2261         /* EIPLEN: External (outer) IP header length, in DWords */
2262         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2263                 ICE_TXD_CTX_QW0_EIPLEN_S;
2264
2265         /* L4TUNT: L4 Tunneling Type */
2266         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2267         case PKT_TX_TUNNEL_IPIP:
2268                 /* for non UDP / GRE tunneling, set to 00b */
2269                 break;
2270         case PKT_TX_TUNNEL_VXLAN:
2271         case PKT_TX_TUNNEL_GTP:
2272         case PKT_TX_TUNNEL_GENEVE:
2273                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2274                 break;
2275         case PKT_TX_TUNNEL_GRE:
2276                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2277                 break;
2278         default:
2279                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2280                 return;
2281         }
2282
2283         /* L4TUNLEN: L4 Tunneling Length, in Words
2284          *
2285          * We depend on app to set rte_mbuf.l2_len correctly.
2286          * For IP in GRE it should be set to the length of the GRE
2287          * header;
2288          * For MAC in GRE or MAC in UDP it should be set to the length
2289          * of the GRE or UDP headers plus the inner MAC up to including
2290          * its last Ethertype.
2291          * If MPLS labels exists, it should include them as well.
2292          */
2293         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2294                 ICE_TXD_CTX_QW0_NATLEN_S;
2295
2296         if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
2297             (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
2298             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2299                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2300 }
2301
2302 static inline void
2303 ice_txd_enable_checksum(uint64_t ol_flags,
2304                         uint32_t *td_cmd,
2305                         uint32_t *td_offset,
2306                         union ice_tx_offload tx_offload)
2307 {
2308         /* Set MACLEN */
2309         if (ol_flags & PKT_TX_TUNNEL_MASK)
2310                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2311                         << ICE_TX_DESC_LEN_MACLEN_S;
2312         else
2313                 *td_offset |= (tx_offload.l2_len >> 1)
2314                         << ICE_TX_DESC_LEN_MACLEN_S;
2315
2316         /* Enable L3 checksum offloads */
2317         if (ol_flags & PKT_TX_IP_CKSUM) {
2318                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2319                 *td_offset |= (tx_offload.l3_len >> 2) <<
2320                               ICE_TX_DESC_LEN_IPLEN_S;
2321         } else if (ol_flags & PKT_TX_IPV4) {
2322                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2323                 *td_offset |= (tx_offload.l3_len >> 2) <<
2324                               ICE_TX_DESC_LEN_IPLEN_S;
2325         } else if (ol_flags & PKT_TX_IPV6) {
2326                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2327                 *td_offset |= (tx_offload.l3_len >> 2) <<
2328                               ICE_TX_DESC_LEN_IPLEN_S;
2329         }
2330
2331         if (ol_flags & PKT_TX_TCP_SEG) {
2332                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2333                 *td_offset |= (tx_offload.l4_len >> 2) <<
2334                               ICE_TX_DESC_LEN_L4_LEN_S;
2335                 return;
2336         }
2337
2338         /* Enable L4 checksum offloads */
2339         switch (ol_flags & PKT_TX_L4_MASK) {
2340         case PKT_TX_TCP_CKSUM:
2341                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2342                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2343                               ICE_TX_DESC_LEN_L4_LEN_S;
2344                 break;
2345         case PKT_TX_SCTP_CKSUM:
2346                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2347                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2348                               ICE_TX_DESC_LEN_L4_LEN_S;
2349                 break;
2350         case PKT_TX_UDP_CKSUM:
2351                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2352                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2353                               ICE_TX_DESC_LEN_L4_LEN_S;
2354                 break;
2355         default:
2356                 break;
2357         }
2358 }
2359
2360 static inline int
2361 ice_xmit_cleanup(struct ice_tx_queue *txq)
2362 {
2363         struct ice_tx_entry *sw_ring = txq->sw_ring;
2364         volatile struct ice_tx_desc *txd = txq->tx_ring;
2365         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2366         uint16_t nb_tx_desc = txq->nb_tx_desc;
2367         uint16_t desc_to_clean_to;
2368         uint16_t nb_tx_to_clean;
2369
2370         /* Determine the last descriptor needing to be cleaned */
2371         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2372         if (desc_to_clean_to >= nb_tx_desc)
2373                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2374
2375         /* Check to make sure the last descriptor to clean is done */
2376         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2377         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2378             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2379                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
2380                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2381                                 desc_to_clean_to,
2382                                 txq->port_id, txq->queue_id,
2383                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
2384                 /* Failed to clean any descriptors */
2385                 return -1;
2386         }
2387
2388         /* Figure out how many descriptors will be cleaned */
2389         if (last_desc_cleaned > desc_to_clean_to)
2390                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2391                                             desc_to_clean_to);
2392         else
2393                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2394                                             last_desc_cleaned);
2395
2396         /* The last descriptor to clean is done, so that means all the
2397          * descriptors from the last descriptor that was cleaned
2398          * up to the last descriptor with the RS bit set
2399          * are done. Only reset the threshold descriptor.
2400          */
2401         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2402
2403         /* Update the txq to reflect the last descriptor that was cleaned */
2404         txq->last_desc_cleaned = desc_to_clean_to;
2405         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2406
2407         return 0;
2408 }
2409
2410 /* Construct the tx flags */
2411 static inline uint64_t
2412 ice_build_ctob(uint32_t td_cmd,
2413                uint32_t td_offset,
2414                uint16_t size,
2415                uint32_t td_tag)
2416 {
2417         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2418                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2419                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2420                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2421                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2422 }
2423
2424 /* Check if the context descriptor is needed for TX offloading */
2425 static inline uint16_t
2426 ice_calc_context_desc(uint64_t flags)
2427 {
2428         static uint64_t mask = PKT_TX_TCP_SEG |
2429                 PKT_TX_QINQ |
2430                 PKT_TX_OUTER_IP_CKSUM |
2431                 PKT_TX_TUNNEL_MASK;
2432
2433         return (flags & mask) ? 1 : 0;
2434 }
2435
2436 /* set ice TSO context descriptor */
2437 static inline uint64_t
2438 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2439 {
2440         uint64_t ctx_desc = 0;
2441         uint32_t cd_cmd, hdr_len, cd_tso_len;
2442
2443         if (!tx_offload.l4_len) {
2444                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2445                 return ctx_desc;
2446         }
2447
2448         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2449         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2450                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2451
2452         cd_cmd = ICE_TX_CTX_DESC_TSO;
2453         cd_tso_len = mbuf->pkt_len - hdr_len;
2454         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2455                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2456                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2457
2458         return ctx_desc;
2459 }
2460
2461 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2462 #define ICE_MAX_DATA_PER_TXD \
2463         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2464 /* Calculate the number of TX descriptors needed for each pkt */
2465 static inline uint16_t
2466 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2467 {
2468         struct rte_mbuf *txd = tx_pkt;
2469         uint16_t count = 0;
2470
2471         while (txd != NULL) {
2472                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2473                 txd = txd->next;
2474         }
2475
2476         return count;
2477 }
2478
2479 uint16_t
2480 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2481 {
2482         struct ice_tx_queue *txq;
2483         volatile struct ice_tx_desc *tx_ring;
2484         volatile struct ice_tx_desc *txd;
2485         struct ice_tx_entry *sw_ring;
2486         struct ice_tx_entry *txe, *txn;
2487         struct rte_mbuf *tx_pkt;
2488         struct rte_mbuf *m_seg;
2489         uint32_t cd_tunneling_params;
2490         uint16_t tx_id;
2491         uint16_t nb_tx;
2492         uint16_t nb_used;
2493         uint16_t nb_ctx;
2494         uint32_t td_cmd = 0;
2495         uint32_t td_offset = 0;
2496         uint32_t td_tag = 0;
2497         uint16_t tx_last;
2498         uint16_t slen;
2499         uint64_t buf_dma_addr;
2500         uint64_t ol_flags;
2501         union ice_tx_offload tx_offload = {0};
2502
2503         txq = tx_queue;
2504         sw_ring = txq->sw_ring;
2505         tx_ring = txq->tx_ring;
2506         tx_id = txq->tx_tail;
2507         txe = &sw_ring[tx_id];
2508
2509         /* Check if the descriptor ring needs to be cleaned. */
2510         if (txq->nb_tx_free < txq->tx_free_thresh)
2511                 (void)ice_xmit_cleanup(txq);
2512
2513         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2514                 tx_pkt = *tx_pkts++;
2515
2516                 td_cmd = 0;
2517                 td_tag = 0;
2518                 td_offset = 0;
2519                 ol_flags = tx_pkt->ol_flags;
2520                 tx_offload.l2_len = tx_pkt->l2_len;
2521                 tx_offload.l3_len = tx_pkt->l3_len;
2522                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2523                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2524                 tx_offload.l4_len = tx_pkt->l4_len;
2525                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2526                 /* Calculate the number of context descriptors needed. */
2527                 nb_ctx = ice_calc_context_desc(ol_flags);
2528
2529                 /* The number of descriptors that must be allocated for
2530                  * a packet equals to the number of the segments of that
2531                  * packet plus the number of context descriptor if needed.
2532                  * Recalculate the needed tx descs when TSO enabled in case
2533                  * the mbuf data size exceeds max data size that hw allows
2534                  * per tx desc.
2535                  */
2536                 if (ol_flags & PKT_TX_TCP_SEG)
2537                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2538                                              nb_ctx);
2539                 else
2540                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2541                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2542
2543                 /* Circular ring */
2544                 if (tx_last >= txq->nb_tx_desc)
2545                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2546
2547                 if (nb_used > txq->nb_tx_free) {
2548                         if (ice_xmit_cleanup(txq) != 0) {
2549                                 if (nb_tx == 0)
2550                                         return 0;
2551                                 goto end_of_tx;
2552                         }
2553                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2554                                 while (nb_used > txq->nb_tx_free) {
2555                                         if (ice_xmit_cleanup(txq) != 0) {
2556                                                 if (nb_tx == 0)
2557                                                         return 0;
2558                                                 goto end_of_tx;
2559                                         }
2560                                 }
2561                         }
2562                 }
2563
2564                 /* Descriptor based VLAN insertion */
2565                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2566                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2567                         td_tag = tx_pkt->vlan_tci;
2568                 }
2569
2570                 /* Fill in tunneling parameters if necessary */
2571                 cd_tunneling_params = 0;
2572                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2573                         ice_parse_tunneling_params(ol_flags, tx_offload,
2574                                                    &cd_tunneling_params);
2575
2576                 /* Enable checksum offloading */
2577                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2578                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2579                                                 &td_offset, tx_offload);
2580
2581                 if (nb_ctx) {
2582                         /* Setup TX context descriptor if required */
2583                         volatile struct ice_tx_ctx_desc *ctx_txd =
2584                                 (volatile struct ice_tx_ctx_desc *)
2585                                         &tx_ring[tx_id];
2586                         uint16_t cd_l2tag2 = 0;
2587                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2588
2589                         txn = &sw_ring[txe->next_id];
2590                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2591                         if (txe->mbuf) {
2592                                 rte_pktmbuf_free_seg(txe->mbuf);
2593                                 txe->mbuf = NULL;
2594                         }
2595
2596                         if (ol_flags & PKT_TX_TCP_SEG)
2597                                 cd_type_cmd_tso_mss |=
2598                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2599
2600                         ctx_txd->tunneling_params =
2601                                 rte_cpu_to_le_32(cd_tunneling_params);
2602
2603                         /* TX context descriptor based double VLAN insert */
2604                         if (ol_flags & PKT_TX_QINQ) {
2605                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2606                                 cd_type_cmd_tso_mss |=
2607                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2608                                          ICE_TXD_CTX_QW1_CMD_S);
2609                         }
2610                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2611                         ctx_txd->qw1 =
2612                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2613
2614                         txe->last_id = tx_last;
2615                         tx_id = txe->next_id;
2616                         txe = txn;
2617                 }
2618                 m_seg = tx_pkt;
2619
2620                 do {
2621                         txd = &tx_ring[tx_id];
2622                         txn = &sw_ring[txe->next_id];
2623
2624                         if (txe->mbuf)
2625                                 rte_pktmbuf_free_seg(txe->mbuf);
2626                         txe->mbuf = m_seg;
2627
2628                         /* Setup TX Descriptor */
2629                         slen = m_seg->data_len;
2630                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2631
2632                         while ((ol_flags & PKT_TX_TCP_SEG) &&
2633                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2634                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2635                                 txd->cmd_type_offset_bsz =
2636                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2637                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2638                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2639                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2640                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2641                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2642
2643                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2644                                 slen -= ICE_MAX_DATA_PER_TXD;
2645
2646                                 txe->last_id = tx_last;
2647                                 tx_id = txe->next_id;
2648                                 txe = txn;
2649                                 txd = &tx_ring[tx_id];
2650                                 txn = &sw_ring[txe->next_id];
2651                         }
2652
2653                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2654                         txd->cmd_type_offset_bsz =
2655                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2656                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2657                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2658                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2659                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2660
2661                         txe->last_id = tx_last;
2662                         tx_id = txe->next_id;
2663                         txe = txn;
2664                         m_seg = m_seg->next;
2665                 } while (m_seg);
2666
2667                 /* fill the last descriptor with End of Packet (EOP) bit */
2668                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2669                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2670                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2671
2672                 /* set RS bit on the last descriptor of one packet */
2673                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2674                         PMD_TX_FREE_LOG(DEBUG,
2675                                         "Setting RS bit on TXD id="
2676                                         "%4u (port=%d queue=%d)",
2677                                         tx_last, txq->port_id, txq->queue_id);
2678
2679                         td_cmd |= ICE_TX_DESC_CMD_RS;
2680
2681                         /* Update txq RS bit counters */
2682                         txq->nb_tx_used = 0;
2683                 }
2684                 txd->cmd_type_offset_bsz |=
2685                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2686                                          ICE_TXD_QW1_CMD_S);
2687         }
2688 end_of_tx:
2689         /* update Tail register */
2690         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2691         txq->tx_tail = tx_id;
2692
2693         return nb_tx;
2694 }
2695
2696 static __rte_always_inline int
2697 ice_tx_free_bufs(struct ice_tx_queue *txq)
2698 {
2699         struct ice_tx_entry *txep;
2700         uint16_t i;
2701
2702         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2703              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2704             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2705                 return 0;
2706
2707         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2708
2709         for (i = 0; i < txq->tx_rs_thresh; i++)
2710                 rte_prefetch0((txep + i)->mbuf);
2711
2712         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2713                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2714                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2715                         txep->mbuf = NULL;
2716                 }
2717         } else {
2718                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2719                         rte_pktmbuf_free_seg(txep->mbuf);
2720                         txep->mbuf = NULL;
2721                 }
2722         }
2723
2724         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2725         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2726         if (txq->tx_next_dd >= txq->nb_tx_desc)
2727                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2728
2729         return txq->tx_rs_thresh;
2730 }
2731
2732 static int
2733 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2734                         uint32_t free_cnt)
2735 {
2736         struct ice_tx_entry *swr_ring = txq->sw_ring;
2737         uint16_t i, tx_last, tx_id;
2738         uint16_t nb_tx_free_last;
2739         uint16_t nb_tx_to_clean;
2740         uint32_t pkt_cnt;
2741
2742         /* Start free mbuf from the next of tx_tail */
2743         tx_last = txq->tx_tail;
2744         tx_id  = swr_ring[tx_last].next_id;
2745
2746         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2747                 return 0;
2748
2749         nb_tx_to_clean = txq->nb_tx_free;
2750         nb_tx_free_last = txq->nb_tx_free;
2751         if (!free_cnt)
2752                 free_cnt = txq->nb_tx_desc;
2753
2754         /* Loop through swr_ring to count the amount of
2755          * freeable mubfs and packets.
2756          */
2757         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2758                 for (i = 0; i < nb_tx_to_clean &&
2759                         pkt_cnt < free_cnt &&
2760                         tx_id != tx_last; i++) {
2761                         if (swr_ring[tx_id].mbuf != NULL) {
2762                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2763                                 swr_ring[tx_id].mbuf = NULL;
2764
2765                                 /*
2766                                  * last segment in the packet,
2767                                  * increment packet count
2768                                  */
2769                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2770                         }
2771
2772                         tx_id = swr_ring[tx_id].next_id;
2773                 }
2774
2775                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2776                         txq->nb_tx_free || tx_id == tx_last)
2777                         break;
2778
2779                 if (pkt_cnt < free_cnt) {
2780                         if (ice_xmit_cleanup(txq))
2781                                 break;
2782
2783                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2784                         nb_tx_free_last = txq->nb_tx_free;
2785                 }
2786         }
2787
2788         return (int)pkt_cnt;
2789 }
2790
2791 #ifdef RTE_ARCH_X86
2792 static int
2793 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2794                         uint32_t free_cnt __rte_unused)
2795 {
2796         return -ENOTSUP;
2797 }
2798 #endif
2799
2800 static int
2801 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2802                         uint32_t free_cnt)
2803 {
2804         int i, n, cnt;
2805
2806         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2807                 free_cnt = txq->nb_tx_desc;
2808
2809         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2810
2811         for (i = 0; i < cnt; i += n) {
2812                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2813                         break;
2814
2815                 n = ice_tx_free_bufs(txq);
2816
2817                 if (n == 0)
2818                         break;
2819         }
2820
2821         return i;
2822 }
2823
2824 int
2825 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2826 {
2827         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2828         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2829         struct ice_adapter *ad =
2830                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2831
2832 #ifdef RTE_ARCH_X86
2833         if (ad->tx_vec_allowed)
2834                 return ice_tx_done_cleanup_vec(q, free_cnt);
2835 #endif
2836         if (ad->tx_simple_allowed)
2837                 return ice_tx_done_cleanup_simple(q, free_cnt);
2838         else
2839                 return ice_tx_done_cleanup_full(q, free_cnt);
2840 }
2841
2842 /* Populate 4 descriptors with data from 4 mbufs */
2843 static inline void
2844 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2845 {
2846         uint64_t dma_addr;
2847         uint32_t i;
2848
2849         for (i = 0; i < 4; i++, txdp++, pkts++) {
2850                 dma_addr = rte_mbuf_data_iova(*pkts);
2851                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2852                 txdp->cmd_type_offset_bsz =
2853                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2854                                        (*pkts)->data_len, 0);
2855         }
2856 }
2857
2858 /* Populate 1 descriptor with data from 1 mbuf */
2859 static inline void
2860 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2861 {
2862         uint64_t dma_addr;
2863
2864         dma_addr = rte_mbuf_data_iova(*pkts);
2865         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2866         txdp->cmd_type_offset_bsz =
2867                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2868                                (*pkts)->data_len, 0);
2869 }
2870
2871 static inline void
2872 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2873                     uint16_t nb_pkts)
2874 {
2875         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2876         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2877         const int N_PER_LOOP = 4;
2878         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2879         int mainpart, leftover;
2880         int i, j;
2881
2882         /**
2883          * Process most of the packets in chunks of N pkts.  Any
2884          * leftover packets will get processed one at a time.
2885          */
2886         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2887         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2888         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2889                 /* Copy N mbuf pointers to the S/W ring */
2890                 for (j = 0; j < N_PER_LOOP; ++j)
2891                         (txep + i + j)->mbuf = *(pkts + i + j);
2892                 tx4(txdp + i, pkts + i);
2893         }
2894
2895         if (unlikely(leftover > 0)) {
2896                 for (i = 0; i < leftover; ++i) {
2897                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2898                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2899                 }
2900         }
2901 }
2902
2903 static inline uint16_t
2904 tx_xmit_pkts(struct ice_tx_queue *txq,
2905              struct rte_mbuf **tx_pkts,
2906              uint16_t nb_pkts)
2907 {
2908         volatile struct ice_tx_desc *txr = txq->tx_ring;
2909         uint16_t n = 0;
2910
2911         /**
2912          * Begin scanning the H/W ring for done descriptors when the number
2913          * of available descriptors drops below tx_free_thresh. For each done
2914          * descriptor, free the associated buffer.
2915          */
2916         if (txq->nb_tx_free < txq->tx_free_thresh)
2917                 ice_tx_free_bufs(txq);
2918
2919         /* Use available descriptor only */
2920         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2921         if (unlikely(!nb_pkts))
2922                 return 0;
2923
2924         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2925         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2926                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2927                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2928                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2929                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2930                                          ICE_TXD_QW1_CMD_S);
2931                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2932                 txq->tx_tail = 0;
2933         }
2934
2935         /* Fill hardware descriptor ring with mbuf data */
2936         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2937         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2938
2939         /* Determin if RS bit needs to be set */
2940         if (txq->tx_tail > txq->tx_next_rs) {
2941                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2942                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2943                                          ICE_TXD_QW1_CMD_S);
2944                 txq->tx_next_rs =
2945                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2946                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2947                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2948         }
2949
2950         if (txq->tx_tail >= txq->nb_tx_desc)
2951                 txq->tx_tail = 0;
2952
2953         /* Update the tx tail register */
2954         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
2955
2956         return nb_pkts;
2957 }
2958
2959 static uint16_t
2960 ice_xmit_pkts_simple(void *tx_queue,
2961                      struct rte_mbuf **tx_pkts,
2962                      uint16_t nb_pkts)
2963 {
2964         uint16_t nb_tx = 0;
2965
2966         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2967                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2968                                     tx_pkts, nb_pkts);
2969
2970         while (nb_pkts) {
2971                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2972                                                       ICE_TX_MAX_BURST);
2973
2974                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2975                                    &tx_pkts[nb_tx], num);
2976                 nb_tx = (uint16_t)(nb_tx + ret);
2977                 nb_pkts = (uint16_t)(nb_pkts - ret);
2978                 if (ret < num)
2979                         break;
2980         }
2981
2982         return nb_tx;
2983 }
2984
2985 void __rte_cold
2986 ice_set_rx_function(struct rte_eth_dev *dev)
2987 {
2988         PMD_INIT_FUNC_TRACE();
2989         struct ice_adapter *ad =
2990                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2991 #ifdef RTE_ARCH_X86
2992         struct ice_rx_queue *rxq;
2993         int i;
2994         bool use_avx512 = false;
2995         bool use_avx2 = false;
2996
2997         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2998                 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed &&
2999                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3000                         ad->rx_vec_allowed = true;
3001                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3002                                 rxq = dev->data->rx_queues[i];
3003                                 if (rxq && ice_rxq_vec_setup(rxq)) {
3004                                         ad->rx_vec_allowed = false;
3005                                         break;
3006                                 }
3007                         }
3008
3009                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3010                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3011                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3012 #ifdef CC_AVX512_SUPPORT
3013                                 use_avx512 = true;
3014 #else
3015                         PMD_DRV_LOG(NOTICE,
3016                                 "AVX512 is not supported in build env");
3017 #endif
3018                         if (!use_avx512 &&
3019                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3020                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3021                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3022                                 use_avx2 = true;
3023
3024                 } else {
3025                         ad->rx_vec_allowed = false;
3026                 }
3027         }
3028
3029         if (ad->rx_vec_allowed) {
3030                 if (dev->data->scattered_rx) {
3031                         if (use_avx512) {
3032 #ifdef CC_AVX512_SUPPORT
3033                                 PMD_DRV_LOG(NOTICE,
3034                                         "Using AVX512 Vector Scattered Rx (port %d).",
3035                                         dev->data->port_id);
3036                                 dev->rx_pkt_burst =
3037                                         ice_recv_scattered_pkts_vec_avx512;
3038 #endif
3039                         } else {
3040                                 PMD_DRV_LOG(DEBUG,
3041                                         "Using %sVector Scattered Rx (port %d).",
3042                                         use_avx2 ? "avx2 " : "",
3043                                         dev->data->port_id);
3044                                 dev->rx_pkt_burst = use_avx2 ?
3045                                         ice_recv_scattered_pkts_vec_avx2 :
3046                                         ice_recv_scattered_pkts_vec;
3047                         }
3048                 } else {
3049                         if (use_avx512) {
3050 #ifdef CC_AVX512_SUPPORT
3051                                 PMD_DRV_LOG(NOTICE,
3052                                         "Using AVX512 Vector Rx (port %d).",
3053                                         dev->data->port_id);
3054                                 dev->rx_pkt_burst =
3055                                         ice_recv_pkts_vec_avx512;
3056 #endif
3057                         } else {
3058                                 PMD_DRV_LOG(DEBUG,
3059                                         "Using %sVector Rx (port %d).",
3060                                         use_avx2 ? "avx2 " : "",
3061                                         dev->data->port_id);
3062                                 dev->rx_pkt_burst = use_avx2 ?
3063                                         ice_recv_pkts_vec_avx2 :
3064                                         ice_recv_pkts_vec;
3065                         }
3066                 }
3067                 return;
3068         }
3069
3070 #endif
3071
3072         if (dev->data->scattered_rx) {
3073                 /* Set the non-LRO scattered function */
3074                 PMD_INIT_LOG(DEBUG,
3075                              "Using a Scattered function on port %d.",
3076                              dev->data->port_id);
3077                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3078         } else if (ad->rx_bulk_alloc_allowed) {
3079                 PMD_INIT_LOG(DEBUG,
3080                              "Rx Burst Bulk Alloc Preconditions are "
3081                              "satisfied. Rx Burst Bulk Alloc function "
3082                              "will be used on port %d.",
3083                              dev->data->port_id);
3084                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3085         } else {
3086                 PMD_INIT_LOG(DEBUG,
3087                              "Rx Burst Bulk Alloc Preconditions are not "
3088                              "satisfied, Normal Rx will be used on port %d.",
3089                              dev->data->port_id);
3090                 dev->rx_pkt_burst = ice_recv_pkts;
3091         }
3092 }
3093
3094 static const struct {
3095         eth_rx_burst_t pkt_burst;
3096         const char *info;
3097 } ice_rx_burst_infos[] = {
3098         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3099         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3100         { ice_recv_pkts,                    "Scalar" },
3101 #ifdef RTE_ARCH_X86
3102 #ifdef CC_AVX512_SUPPORT
3103         { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3104         { ice_recv_pkts_vec_avx512,           "Vector AVX512" },
3105 #endif
3106         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3107         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3108         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3109         { ice_recv_pkts_vec,                "Vector SSE" },
3110 #endif
3111 };
3112
3113 int
3114 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3115                       struct rte_eth_burst_mode *mode)
3116 {
3117         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3118         int ret = -EINVAL;
3119         unsigned int i;
3120
3121         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3122                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3123                         snprintf(mode->info, sizeof(mode->info), "%s",
3124                                  ice_rx_burst_infos[i].info);
3125                         ret = 0;
3126                         break;
3127                 }
3128         }
3129
3130         return ret;
3131 }
3132
3133 void __rte_cold
3134 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3135 {
3136         struct ice_adapter *ad =
3137                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3138
3139         /* Use a simple Tx queue if possible (only fast free is allowed) */
3140         ad->tx_simple_allowed =
3141                 (txq->offloads ==
3142                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3143                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3144
3145         if (ad->tx_simple_allowed)
3146                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3147                              txq->queue_id);
3148         else
3149                 PMD_INIT_LOG(DEBUG,
3150                              "Simple Tx can NOT be enabled on Tx queue %u.",
3151                              txq->queue_id);
3152 }
3153
3154 /*********************************************************************
3155  *
3156  *  TX prep functions
3157  *
3158  **********************************************************************/
3159 /* The default values of TSO MSS */
3160 #define ICE_MIN_TSO_MSS            64
3161 #define ICE_MAX_TSO_MSS            9728
3162 #define ICE_MAX_TSO_FRAME_SIZE     262144
3163 uint16_t
3164 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3165               uint16_t nb_pkts)
3166 {
3167         int i, ret;
3168         uint64_t ol_flags;
3169         struct rte_mbuf *m;
3170
3171         for (i = 0; i < nb_pkts; i++) {
3172                 m = tx_pkts[i];
3173                 ol_flags = m->ol_flags;
3174
3175                 if (ol_flags & PKT_TX_TCP_SEG &&
3176                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3177                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3178                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3179                         /**
3180                          * MSS outside the range are considered malicious
3181                          */
3182                         rte_errno = EINVAL;
3183                         return i;
3184                 }
3185
3186 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3187                 ret = rte_validate_tx_offload(m);
3188                 if (ret != 0) {
3189                         rte_errno = -ret;
3190                         return i;
3191                 }
3192 #endif
3193                 ret = rte_net_intel_cksum_prepare(m);
3194                 if (ret != 0) {
3195                         rte_errno = -ret;
3196                         return i;
3197                 }
3198         }
3199         return i;
3200 }
3201
3202 void __rte_cold
3203 ice_set_tx_function(struct rte_eth_dev *dev)
3204 {
3205         struct ice_adapter *ad =
3206                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3207 #ifdef RTE_ARCH_X86
3208         struct ice_tx_queue *txq;
3209         int i;
3210         bool use_avx512 = false;
3211         bool use_avx2 = false;
3212
3213         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3214                 if (!ice_tx_vec_dev_check(dev) &&
3215                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3216                         ad->tx_vec_allowed = true;
3217                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3218                                 txq = dev->data->tx_queues[i];
3219                                 if (txq && ice_txq_vec_setup(txq)) {
3220                                         ad->tx_vec_allowed = false;
3221                                         break;
3222                                 }
3223                         }
3224
3225                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3226                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3227                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3228 #ifdef CC_AVX512_SUPPORT
3229                                 use_avx512 = true;
3230 #else
3231                         PMD_DRV_LOG(NOTICE,
3232                                 "AVX512 is not supported in build env");
3233 #endif
3234                         if (!use_avx512 &&
3235                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3236                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3237                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3238                                 use_avx2 = true;
3239
3240                 } else {
3241                         ad->tx_vec_allowed = false;
3242                 }
3243         }
3244
3245         if (ad->tx_vec_allowed) {
3246                 if (use_avx512) {
3247 #ifdef CC_AVX512_SUPPORT
3248                         PMD_DRV_LOG(NOTICE, "Using AVX512 Vector Tx (port %d).",
3249                                     dev->data->port_id);
3250                         dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3251 #endif
3252                 } else {
3253                         PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3254                                     use_avx2 ? "avx2 " : "",
3255                                     dev->data->port_id);
3256                         dev->tx_pkt_burst = use_avx2 ?
3257                                             ice_xmit_pkts_vec_avx2 :
3258                                             ice_xmit_pkts_vec;
3259                 }
3260                 dev->tx_pkt_prepare = NULL;
3261
3262                 return;
3263         }
3264 #endif
3265
3266         if (ad->tx_simple_allowed) {
3267                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3268                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3269                 dev->tx_pkt_prepare = NULL;
3270         } else {
3271                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3272                 dev->tx_pkt_burst = ice_xmit_pkts;
3273                 dev->tx_pkt_prepare = ice_prep_pkts;
3274         }
3275 }
3276
3277 static const struct {
3278         eth_tx_burst_t pkt_burst;
3279         const char *info;
3280 } ice_tx_burst_infos[] = {
3281         { ice_xmit_pkts_simple,   "Scalar Simple" },
3282         { ice_xmit_pkts,          "Scalar" },
3283 #ifdef RTE_ARCH_X86
3284 #ifdef CC_AVX512_SUPPORT
3285         { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3286 #endif
3287         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3288         { ice_xmit_pkts_vec,      "Vector SSE" },
3289 #endif
3290 };
3291
3292 int
3293 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3294                       struct rte_eth_burst_mode *mode)
3295 {
3296         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3297         int ret = -EINVAL;
3298         unsigned int i;
3299
3300         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3301                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3302                         snprintf(mode->info, sizeof(mode->info), "%s",
3303                                  ice_tx_burst_infos[i].info);
3304                         ret = 0;
3305                         break;
3306                 }
3307         }
3308
3309         return ret;
3310 }
3311
3312 /* For each value it means, datasheet of hardware can tell more details
3313  *
3314  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3315  */
3316 static inline uint32_t
3317 ice_get_default_pkt_type(uint16_t ptype)
3318 {
3319         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3320                 __rte_cache_aligned = {
3321                 /* L2 types */
3322                 /* [0] reserved */
3323                 [1] = RTE_PTYPE_L2_ETHER,
3324                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3325                 /* [3] - [5] reserved */
3326                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3327                 /* [7] - [10] reserved */
3328                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3329                 /* [12] - [21] reserved */
3330
3331                 /* Non tunneled IPv4 */
3332                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3333                        RTE_PTYPE_L4_FRAG,
3334                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3335                        RTE_PTYPE_L4_NONFRAG,
3336                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3337                        RTE_PTYPE_L4_UDP,
3338                 /* [25] reserved */
3339                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3340                        RTE_PTYPE_L4_TCP,
3341                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3342                        RTE_PTYPE_L4_SCTP,
3343                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3344                        RTE_PTYPE_L4_ICMP,
3345
3346                 /* IPv4 --> IPv4 */
3347                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3348                        RTE_PTYPE_TUNNEL_IP |
3349                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3350                        RTE_PTYPE_INNER_L4_FRAG,
3351                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3352                        RTE_PTYPE_TUNNEL_IP |
3353                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3354                        RTE_PTYPE_INNER_L4_NONFRAG,
3355                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3356                        RTE_PTYPE_TUNNEL_IP |
3357                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3358                        RTE_PTYPE_INNER_L4_UDP,
3359                 /* [32] reserved */
3360                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3361                        RTE_PTYPE_TUNNEL_IP |
3362                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3363                        RTE_PTYPE_INNER_L4_TCP,
3364                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3365                        RTE_PTYPE_TUNNEL_IP |
3366                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3367                        RTE_PTYPE_INNER_L4_SCTP,
3368                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3369                        RTE_PTYPE_TUNNEL_IP |
3370                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3371                        RTE_PTYPE_INNER_L4_ICMP,
3372
3373                 /* IPv4 --> IPv6 */
3374                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3375                        RTE_PTYPE_TUNNEL_IP |
3376                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3377                        RTE_PTYPE_INNER_L4_FRAG,
3378                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3379                        RTE_PTYPE_TUNNEL_IP |
3380                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3381                        RTE_PTYPE_INNER_L4_NONFRAG,
3382                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3383                        RTE_PTYPE_TUNNEL_IP |
3384                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3385                        RTE_PTYPE_INNER_L4_UDP,
3386                 /* [39] reserved */
3387                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3388                        RTE_PTYPE_TUNNEL_IP |
3389                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3390                        RTE_PTYPE_INNER_L4_TCP,
3391                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3392                        RTE_PTYPE_TUNNEL_IP |
3393                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3394                        RTE_PTYPE_INNER_L4_SCTP,
3395                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3396                        RTE_PTYPE_TUNNEL_IP |
3397                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3398                        RTE_PTYPE_INNER_L4_ICMP,
3399
3400                 /* IPv4 --> GRE/Teredo/VXLAN */
3401                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3402                        RTE_PTYPE_TUNNEL_GRENAT,
3403
3404                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3405                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3406                        RTE_PTYPE_TUNNEL_GRENAT |
3407                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3408                        RTE_PTYPE_INNER_L4_FRAG,
3409                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3410                        RTE_PTYPE_TUNNEL_GRENAT |
3411                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3412                        RTE_PTYPE_INNER_L4_NONFRAG,
3413                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3414                        RTE_PTYPE_TUNNEL_GRENAT |
3415                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3416                        RTE_PTYPE_INNER_L4_UDP,
3417                 /* [47] reserved */
3418                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3419                        RTE_PTYPE_TUNNEL_GRENAT |
3420                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3421                        RTE_PTYPE_INNER_L4_TCP,
3422                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3423                        RTE_PTYPE_TUNNEL_GRENAT |
3424                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3425                        RTE_PTYPE_INNER_L4_SCTP,
3426                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3427                        RTE_PTYPE_TUNNEL_GRENAT |
3428                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3429                        RTE_PTYPE_INNER_L4_ICMP,
3430
3431                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3432                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3433                        RTE_PTYPE_TUNNEL_GRENAT |
3434                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3435                        RTE_PTYPE_INNER_L4_FRAG,
3436                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3437                        RTE_PTYPE_TUNNEL_GRENAT |
3438                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3439                        RTE_PTYPE_INNER_L4_NONFRAG,
3440                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3441                        RTE_PTYPE_TUNNEL_GRENAT |
3442                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3443                        RTE_PTYPE_INNER_L4_UDP,
3444                 /* [54] reserved */
3445                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3446                        RTE_PTYPE_TUNNEL_GRENAT |
3447                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3448                        RTE_PTYPE_INNER_L4_TCP,
3449                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3450                        RTE_PTYPE_TUNNEL_GRENAT |
3451                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3452                        RTE_PTYPE_INNER_L4_SCTP,
3453                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3454                        RTE_PTYPE_TUNNEL_GRENAT |
3455                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3456                        RTE_PTYPE_INNER_L4_ICMP,
3457
3458                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3459                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3460                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3461
3462                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3463                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3464                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3465                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3466                        RTE_PTYPE_INNER_L4_FRAG,
3467                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3468                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3469                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3470                        RTE_PTYPE_INNER_L4_NONFRAG,
3471                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3472                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3473                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3474                        RTE_PTYPE_INNER_L4_UDP,
3475                 /* [62] reserved */
3476                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3477                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3478                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3479                        RTE_PTYPE_INNER_L4_TCP,
3480                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3481                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3482                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3483                        RTE_PTYPE_INNER_L4_SCTP,
3484                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3485                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3486                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3487                        RTE_PTYPE_INNER_L4_ICMP,
3488
3489                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3490                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3491                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3492                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3493                        RTE_PTYPE_INNER_L4_FRAG,
3494                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3495                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3496                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3497                        RTE_PTYPE_INNER_L4_NONFRAG,
3498                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3499                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3500                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3501                        RTE_PTYPE_INNER_L4_UDP,
3502                 /* [69] reserved */
3503                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3504                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3505                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3506                        RTE_PTYPE_INNER_L4_TCP,
3507                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3508                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3509                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3510                        RTE_PTYPE_INNER_L4_SCTP,
3511                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3512                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3513                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3514                        RTE_PTYPE_INNER_L4_ICMP,
3515                 /* [73] - [87] reserved */
3516
3517                 /* Non tunneled IPv6 */
3518                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3519                        RTE_PTYPE_L4_FRAG,
3520                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3521                        RTE_PTYPE_L4_NONFRAG,
3522                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3523                        RTE_PTYPE_L4_UDP,
3524                 /* [91] reserved */
3525                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3526                        RTE_PTYPE_L4_TCP,
3527                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3528                        RTE_PTYPE_L4_SCTP,
3529                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3530                        RTE_PTYPE_L4_ICMP,
3531
3532                 /* IPv6 --> IPv4 */
3533                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3534                        RTE_PTYPE_TUNNEL_IP |
3535                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3536                        RTE_PTYPE_INNER_L4_FRAG,
3537                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3538                        RTE_PTYPE_TUNNEL_IP |
3539                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3540                        RTE_PTYPE_INNER_L4_NONFRAG,
3541                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3542                        RTE_PTYPE_TUNNEL_IP |
3543                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3544                        RTE_PTYPE_INNER_L4_UDP,
3545                 /* [98] reserved */
3546                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3547                        RTE_PTYPE_TUNNEL_IP |
3548                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3549                        RTE_PTYPE_INNER_L4_TCP,
3550                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3551                         RTE_PTYPE_TUNNEL_IP |
3552                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3553                         RTE_PTYPE_INNER_L4_SCTP,
3554                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3555                         RTE_PTYPE_TUNNEL_IP |
3556                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3557                         RTE_PTYPE_INNER_L4_ICMP,
3558
3559                 /* IPv6 --> IPv6 */
3560                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3561                         RTE_PTYPE_TUNNEL_IP |
3562                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3563                         RTE_PTYPE_INNER_L4_FRAG,
3564                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3565                         RTE_PTYPE_TUNNEL_IP |
3566                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3567                         RTE_PTYPE_INNER_L4_NONFRAG,
3568                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3569                         RTE_PTYPE_TUNNEL_IP |
3570                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3571                         RTE_PTYPE_INNER_L4_UDP,
3572                 /* [105] reserved */
3573                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3574                         RTE_PTYPE_TUNNEL_IP |
3575                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3576                         RTE_PTYPE_INNER_L4_TCP,
3577                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3578                         RTE_PTYPE_TUNNEL_IP |
3579                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3580                         RTE_PTYPE_INNER_L4_SCTP,
3581                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3582                         RTE_PTYPE_TUNNEL_IP |
3583                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3584                         RTE_PTYPE_INNER_L4_ICMP,
3585
3586                 /* IPv6 --> GRE/Teredo/VXLAN */
3587                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3588                         RTE_PTYPE_TUNNEL_GRENAT,
3589
3590                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3591                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3592                         RTE_PTYPE_TUNNEL_GRENAT |
3593                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3594                         RTE_PTYPE_INNER_L4_FRAG,
3595                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3596                         RTE_PTYPE_TUNNEL_GRENAT |
3597                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3598                         RTE_PTYPE_INNER_L4_NONFRAG,
3599                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3600                         RTE_PTYPE_TUNNEL_GRENAT |
3601                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3602                         RTE_PTYPE_INNER_L4_UDP,
3603                 /* [113] reserved */
3604                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3605                         RTE_PTYPE_TUNNEL_GRENAT |
3606                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3607                         RTE_PTYPE_INNER_L4_TCP,
3608                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3609                         RTE_PTYPE_TUNNEL_GRENAT |
3610                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3611                         RTE_PTYPE_INNER_L4_SCTP,
3612                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3613                         RTE_PTYPE_TUNNEL_GRENAT |
3614                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3615                         RTE_PTYPE_INNER_L4_ICMP,
3616
3617                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3618                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3619                         RTE_PTYPE_TUNNEL_GRENAT |
3620                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3621                         RTE_PTYPE_INNER_L4_FRAG,
3622                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3623                         RTE_PTYPE_TUNNEL_GRENAT |
3624                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3625                         RTE_PTYPE_INNER_L4_NONFRAG,
3626                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3627                         RTE_PTYPE_TUNNEL_GRENAT |
3628                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3629                         RTE_PTYPE_INNER_L4_UDP,
3630                 /* [120] reserved */
3631                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3632                         RTE_PTYPE_TUNNEL_GRENAT |
3633                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3634                         RTE_PTYPE_INNER_L4_TCP,
3635                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3636                         RTE_PTYPE_TUNNEL_GRENAT |
3637                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3638                         RTE_PTYPE_INNER_L4_SCTP,
3639                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3640                         RTE_PTYPE_TUNNEL_GRENAT |
3641                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3642                         RTE_PTYPE_INNER_L4_ICMP,
3643
3644                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3645                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3646                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3647
3648                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3649                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3650                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3651                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3652                         RTE_PTYPE_INNER_L4_FRAG,
3653                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3654                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3655                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3656                         RTE_PTYPE_INNER_L4_NONFRAG,
3657                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3658                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3659                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3660                         RTE_PTYPE_INNER_L4_UDP,
3661                 /* [128] reserved */
3662                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3663                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3664                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3665                         RTE_PTYPE_INNER_L4_TCP,
3666                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3667                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3668                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3669                         RTE_PTYPE_INNER_L4_SCTP,
3670                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3671                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3672                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3673                         RTE_PTYPE_INNER_L4_ICMP,
3674
3675                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3676                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3677                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3678                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3679                         RTE_PTYPE_INNER_L4_FRAG,
3680                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3681                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3682                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3683                         RTE_PTYPE_INNER_L4_NONFRAG,
3684                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3685                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3686                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3687                         RTE_PTYPE_INNER_L4_UDP,
3688                 /* [135] reserved */
3689                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3690                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3691                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3692                         RTE_PTYPE_INNER_L4_TCP,
3693                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3694                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3695                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3696                         RTE_PTYPE_INNER_L4_SCTP,
3697                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3698                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3699                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3700                         RTE_PTYPE_INNER_L4_ICMP,
3701                 /* [139] - [299] reserved */
3702
3703                 /* PPPoE */
3704                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3705                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3706
3707                 /* PPPoE --> IPv4 */
3708                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3709                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3710                         RTE_PTYPE_L4_FRAG,
3711                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3712                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3713                         RTE_PTYPE_L4_NONFRAG,
3714                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3715                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3716                         RTE_PTYPE_L4_UDP,
3717                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3718                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3719                         RTE_PTYPE_L4_TCP,
3720                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3721                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3722                         RTE_PTYPE_L4_SCTP,
3723                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3724                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3725                         RTE_PTYPE_L4_ICMP,
3726
3727                 /* PPPoE --> IPv6 */
3728                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3729                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3730                         RTE_PTYPE_L4_FRAG,
3731                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3732                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3733                         RTE_PTYPE_L4_NONFRAG,
3734                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3735                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3736                         RTE_PTYPE_L4_UDP,
3737                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3738                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3739                         RTE_PTYPE_L4_TCP,
3740                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3741                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3742                         RTE_PTYPE_L4_SCTP,
3743                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3744                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3745                         RTE_PTYPE_L4_ICMP,
3746                 /* [314] - [324] reserved */
3747
3748                 /* IPv4/IPv6 --> GTPC/GTPU */
3749                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3750                         RTE_PTYPE_TUNNEL_GTPC,
3751                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3752                         RTE_PTYPE_TUNNEL_GTPC,
3753                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3754                         RTE_PTYPE_TUNNEL_GTPC,
3755                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3756                         RTE_PTYPE_TUNNEL_GTPC,
3757                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3758                         RTE_PTYPE_TUNNEL_GTPU,
3759                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3760                         RTE_PTYPE_TUNNEL_GTPU,
3761
3762                 /* IPv4 --> GTPU --> IPv4 */
3763                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3764                         RTE_PTYPE_TUNNEL_GTPU |
3765                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3766                         RTE_PTYPE_INNER_L4_FRAG,
3767                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3768                         RTE_PTYPE_TUNNEL_GTPU |
3769                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3770                         RTE_PTYPE_INNER_L4_NONFRAG,
3771                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3772                         RTE_PTYPE_TUNNEL_GTPU |
3773                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3774                         RTE_PTYPE_INNER_L4_UDP,
3775                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3776                         RTE_PTYPE_TUNNEL_GTPU |
3777                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3778                         RTE_PTYPE_INNER_L4_TCP,
3779                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3780                         RTE_PTYPE_TUNNEL_GTPU |
3781                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3782                         RTE_PTYPE_INNER_L4_ICMP,
3783
3784                 /* IPv6 --> GTPU --> IPv4 */
3785                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3786                         RTE_PTYPE_TUNNEL_GTPU |
3787                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3788                         RTE_PTYPE_INNER_L4_FRAG,
3789                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3790                         RTE_PTYPE_TUNNEL_GTPU |
3791                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3792                         RTE_PTYPE_INNER_L4_NONFRAG,
3793                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3794                         RTE_PTYPE_TUNNEL_GTPU |
3795                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3796                         RTE_PTYPE_INNER_L4_UDP,
3797                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3798                         RTE_PTYPE_TUNNEL_GTPU |
3799                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3800                         RTE_PTYPE_INNER_L4_TCP,
3801                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3802                         RTE_PTYPE_TUNNEL_GTPU |
3803                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3804                         RTE_PTYPE_INNER_L4_ICMP,
3805
3806                 /* IPv4 --> GTPU --> IPv6 */
3807                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3808                         RTE_PTYPE_TUNNEL_GTPU |
3809                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3810                         RTE_PTYPE_INNER_L4_FRAG,
3811                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3812                         RTE_PTYPE_TUNNEL_GTPU |
3813                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3814                         RTE_PTYPE_INNER_L4_NONFRAG,
3815                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3816                         RTE_PTYPE_TUNNEL_GTPU |
3817                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3818                         RTE_PTYPE_INNER_L4_UDP,
3819                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3820                         RTE_PTYPE_TUNNEL_GTPU |
3821                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3822                         RTE_PTYPE_INNER_L4_TCP,
3823                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3824                         RTE_PTYPE_TUNNEL_GTPU |
3825                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3826                         RTE_PTYPE_INNER_L4_ICMP,
3827
3828                 /* IPv6 --> GTPU --> IPv6 */
3829                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3830                         RTE_PTYPE_TUNNEL_GTPU |
3831                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3832                         RTE_PTYPE_INNER_L4_FRAG,
3833                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3834                         RTE_PTYPE_TUNNEL_GTPU |
3835                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3836                         RTE_PTYPE_INNER_L4_NONFRAG,
3837                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3838                         RTE_PTYPE_TUNNEL_GTPU |
3839                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3840                         RTE_PTYPE_INNER_L4_UDP,
3841                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3842                         RTE_PTYPE_TUNNEL_GTPU |
3843                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3844                         RTE_PTYPE_INNER_L4_TCP,
3845                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3846                         RTE_PTYPE_TUNNEL_GTPU |
3847                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3848                         RTE_PTYPE_INNER_L4_ICMP,
3849                 /* All others reserved */
3850         };
3851
3852         return type_table[ptype];
3853 }
3854
3855 void __rte_cold
3856 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3857 {
3858         struct ice_adapter *ad =
3859                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3860         int i;
3861
3862         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3863                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3864 }
3865
3866 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
3867 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
3868                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
3869 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
3870 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
3871
3872 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
3873 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
3874         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
3875 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
3876 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
3877         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
3878
3879 /*
3880  * check the programming status descriptor in rx queue.
3881  * done after Programming Flow Director is programmed on
3882  * tx queue
3883  */
3884 static inline int
3885 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
3886 {
3887         volatile union ice_32byte_rx_desc *rxdp;
3888         uint64_t qword1;
3889         uint32_t rx_status;
3890         uint32_t error;
3891         uint32_t id;
3892         int ret = -EAGAIN;
3893
3894         rxdp = (volatile union ice_32byte_rx_desc *)
3895                 (&rxq->rx_ring[rxq->rx_tail]);
3896         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
3897         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
3898                         >> ICE_RXD_QW1_STATUS_S;
3899
3900         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
3901                 ret = 0;
3902                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
3903                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
3904                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
3905                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
3906                 if (error) {
3907                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
3908                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
3909                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
3910                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
3911                         ret = -EINVAL;
3912                         goto err;
3913                 }
3914                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
3915                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
3916                 if (error) {
3917                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
3918                         ret = -EINVAL;
3919                 }
3920 err:
3921                 rxdp->wb.qword1.status_error_len = 0;
3922                 rxq->rx_tail++;
3923                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
3924                         rxq->rx_tail = 0;
3925                 if (rxq->rx_tail == 0)
3926                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3927                 else
3928                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
3929         }
3930
3931         return ret;
3932 }
3933
3934 #define ICE_FDIR_MAX_WAIT_US 10000
3935
3936 int
3937 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
3938 {
3939         struct ice_tx_queue *txq = pf->fdir.txq;
3940         struct ice_rx_queue *rxq = pf->fdir.rxq;
3941         volatile struct ice_fltr_desc *fdirdp;
3942         volatile struct ice_tx_desc *txdp;
3943         uint32_t td_cmd;
3944         uint16_t i;
3945
3946         fdirdp = (volatile struct ice_fltr_desc *)
3947                 (&txq->tx_ring[txq->tx_tail]);
3948         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
3949         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
3950
3951         txdp = &txq->tx_ring[txq->tx_tail + 1];
3952         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
3953         td_cmd = ICE_TX_DESC_CMD_EOP |
3954                 ICE_TX_DESC_CMD_RS  |
3955                 ICE_TX_DESC_CMD_DUMMY;
3956
3957         txdp->cmd_type_offset_bsz =
3958                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
3959
3960         txq->tx_tail += 2;
3961         if (txq->tx_tail >= txq->nb_tx_desc)
3962                 txq->tx_tail = 0;
3963         /* Update the tx tail register */
3964         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
3965         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
3966                 if ((txdp->cmd_type_offset_bsz &
3967                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
3968                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
3969                         break;
3970                 rte_delay_us(1);
3971         }
3972         if (i >= ICE_FDIR_MAX_WAIT_US) {
3973                 PMD_DRV_LOG(ERR,
3974                             "Failed to program FDIR filter: time out to get DD on tx queue.");
3975                 return -ETIMEDOUT;
3976         }
3977
3978         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
3979                 int ret;
3980
3981                 ret = ice_check_fdir_programming_status(rxq);
3982                 if (ret == -EAGAIN)
3983                         rte_delay_us(1);
3984                 else
3985                         return ret;
3986         }
3987
3988         PMD_DRV_LOG(ERR,
3989                     "Failed to program FDIR filter: programming status reported.");
3990         return -ETIMEDOUT;
3991
3992
3993 }