drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <ethdev_driver.h>
   6 #include <rte_net.h>
   7 #include <rte_vect.h>
   8
   9 #include "rte_pmd_ice.h"
  10 #include "ice_rxtx.h"
  11 #include "ice_rxtx_vec_common.h"
  12
  13 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  14                 PKT_TX_IP_CKSUM |                \
  15                 PKT_TX_L4_MASK |                 \
  16                 PKT_TX_TCP_SEG |                 \
  17                 PKT_TX_OUTER_IP_CKSUM)
  18
  19 /* Offset of mbuf dynamic field for protocol extraction data */
  20 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  21
  22 /* Mask of mbuf dynamic flags for protocol extraction type */
  23 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  27 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  28 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  29
  30 static int
  31 ice_monitor_callback(const uint64_t value,
  32                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  33 {
  34         const uint64_t m = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
  35         /*
  36          * we expect the DD bit to be set to 1 if this descriptor was already
  37          * written to.
  38          */
  39         return (value & m) == m ? -1 : 0;
  40 }
  41
  42 int
  43 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  44 {
  45         volatile union ice_rx_flex_desc *rxdp;
  46         struct ice_rx_queue *rxq = rx_queue;
  47         uint16_t desc;
  48
  49         desc = rxq->rx_tail;
  50         rxdp = &rxq->rx_ring[desc];
  51         /* watch for changes in status bit */
  52         pmc->addr = &rxdp->wb.status_error0;
  53
  54         /* comparison callback */
  55         pmc->fn = ice_monitor_callback;
  56
  57         /* register is 16-bit */
  58         pmc->size = sizeof(uint16_t);
  59
  60         return 0;
  61 }
  62
  63
  64 static inline uint8_t
  65 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  66 {
  67         static uint8_t rxdid_map[] = {
  68                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_OVS,
  69                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  70                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  71                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  72                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  73                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  74                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  75         };
  76
  77         return xtr_type < RTE_DIM(rxdid_map) ?
  78                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
  79 }
  80
  81 static inline void
  82 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
  83                                        struct rte_mbuf *mb,
  84                                        volatile union ice_rx_flex_desc *rxdp)
  85 {
  86         volatile struct ice_32b_rx_flex_desc_comms *desc =
  87                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
  88         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
  89
  90         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  91                 mb->ol_flags |= PKT_RX_RSS_HASH;
  92                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  93         }
  94
  95 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  96         if (desc->flow_id != 0xFFFFFFFF) {
  97                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
  98                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  99         }
 100 #endif
 101 }
 102
 103 static inline void
 104 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
 105                                    struct rte_mbuf *mb,
 106                                    volatile union ice_rx_flex_desc *rxdp)
 107 {
 108         volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
 109                         (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
 110 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 111         uint16_t stat_err;
 112 #endif
 113
 114         if (desc->flow_id != 0xFFFFFFFF) {
 115                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 116                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 117         }
 118
 119 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 120         stat_err = rte_le_to_cpu_16(desc->status_error0);
 121         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 122                 mb->ol_flags |= PKT_RX_RSS_HASH;
 123                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 124         }
 125 #endif
 126 }
 127
 128 static inline void
 129 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
 130                                       struct rte_mbuf *mb,
 131                                       volatile union ice_rx_flex_desc *rxdp)
 132 {
 133         volatile struct ice_32b_rx_flex_desc_comms *desc =
 134                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 135         uint16_t stat_err;
 136
 137         stat_err = rte_le_to_cpu_16(desc->status_error0);
 138         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 139                 mb->ol_flags |= PKT_RX_RSS_HASH;
 140                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 141         }
 142
 143 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 144         if (desc->flow_id != 0xFFFFFFFF) {
 145                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 146                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 147         }
 148
 149         if (rxq->xtr_ol_flag) {
 150                 uint32_t metadata = 0;
 151
 152                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 153
 154                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 155                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 156
 157                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 158                         metadata |=
 159                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 160
 161                 if (metadata) {
 162                         mb->ol_flags |= rxq->xtr_ol_flag;
 163
 164                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 165                 }
 166         }
 167 #endif
 168 }
 169
 170 static inline void
 171 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
 172                                       struct rte_mbuf *mb,
 173                                       volatile union ice_rx_flex_desc *rxdp)
 174 {
 175         volatile struct ice_32b_rx_flex_desc_comms *desc =
 176                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 177         uint16_t stat_err;
 178
 179         stat_err = rte_le_to_cpu_16(desc->status_error0);
 180         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 181                 mb->ol_flags |= PKT_RX_RSS_HASH;
 182                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 183         }
 184
 185 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 186         if (desc->flow_id != 0xFFFFFFFF) {
 187                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 188                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 189         }
 190
 191         if (rxq->xtr_ol_flag) {
 192                 uint32_t metadata = 0;
 193
 194                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 195                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 196                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 197                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 198
 199                 if (metadata) {
 200                         mb->ol_flags |= rxq->xtr_ol_flag;
 201
 202                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 203                 }
 204         }
 205 #endif
 206 }
 207
 208 void
 209 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
 210 {
 211         switch (rxdid) {
 212         case ICE_RXDID_COMMS_AUX_VLAN:
 213                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
 214                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 215                 break;
 216
 217         case ICE_RXDID_COMMS_AUX_IPV4:
 218                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
 219                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 220                 break;
 221
 222         case ICE_RXDID_COMMS_AUX_IPV6:
 223                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
 224                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 225                 break;
 226
 227         case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
 228                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
 229                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 230                 break;
 231
 232         case ICE_RXDID_COMMS_AUX_TCP:
 233                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
 234                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 235                 break;
 236
 237         case ICE_RXDID_COMMS_AUX_IP_OFFSET:
 238                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
 239                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v2;
 240                 break;
 241
 242         case ICE_RXDID_COMMS_GENERIC:
 243                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_generic;
 244                 break;
 245
 246         case ICE_RXDID_COMMS_OVS:
 247                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 248                 break;
 249
 250         default:
 251                 /* update this according to the RXDID for PROTO_XTR_NONE */
 252                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 253                 break;
 254         }
 255
 256         if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
 257                 rxq->xtr_ol_flag = 0;
 258 }
 259
 260 static enum ice_status
 261 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
 262 {
 263         struct ice_vsi *vsi = rxq->vsi;
 264         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 265         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
 266         struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
 267         struct ice_rlan_ctx rx_ctx;
 268         enum ice_status err;
 269         uint16_t buf_size;
 270         struct rte_eth_rxmode *rxmode = &dev_data->dev_conf.rxmode;
 271         uint32_t rxdid = ICE_RXDID_COMMS_OVS;
 272         uint32_t regval;
 273         struct ice_adapter *ad = rxq->vsi->adapter;
 274         uint32_t frame_size = dev_data->mtu + ICE_ETH_OVERHEAD;
 275
 276         /* Set buffer size as the head split is disabled. */
 277         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 278                               RTE_PKTMBUF_HEADROOM);
 279         rxq->rx_hdr_len = 0;
 280         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
 281         rxq->max_pkt_len =
 282                 RTE_MIN((uint32_t)ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
 283                         frame_size);
 284
 285         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 286                 if (rxq->max_pkt_len <= ICE_ETH_MAX_LEN ||
 287                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 288                         PMD_DRV_LOG(ERR, "maximum packet length must "
 289                                     "be larger than %u and smaller than %u,"
 290                                     "as jumbo frame is enabled",
 291                                     (uint32_t)ICE_ETH_MAX_LEN,
 292                                     (uint32_t)ICE_FRAME_SIZE_MAX);
 293                         return -EINVAL;
 294                 }
 295         } else {
 296                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
 297                     rxq->max_pkt_len > ICE_ETH_MAX_LEN) {
 298                         PMD_DRV_LOG(ERR, "maximum packet length must be "
 299                                     "larger than %u and smaller than %u, "
 300                                     "as jumbo frame is disabled",
 301                                     (uint32_t)RTE_ETHER_MIN_LEN,
 302                                     (uint32_t)ICE_ETH_MAX_LEN);
 303                         return -EINVAL;
 304                 }
 305         }
 306
 307         if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
 308                 /* Register mbuf field and flag for Rx timestamp */
 309                 err = rte_mbuf_dyn_rx_timestamp_register(
 310                                 &ice_timestamp_dynfield_offset,
 311                                 &ice_timestamp_dynflag);
 312                 if (err) {
 313                         PMD_DRV_LOG(ERR,
 314                                 "Cannot register mbuf field/flag for timestamp");
 315                         return -EINVAL;
 316                 }
 317         }
 318
 319         memset(&rx_ctx, 0, sizeof(rx_ctx));
 320
 321         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 322         rx_ctx.qlen = rxq->nb_rx_desc;
 323         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 324         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 325         rx_ctx.dtype = 0; /* No Header Split mode */
 326 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 327         rx_ctx.dsize = 1; /* 32B descriptors */
 328 #endif
 329         rx_ctx.rxmax = rxq->max_pkt_len;
 330         /* TPH: Transaction Layer Packet (TLP) processing hints */
 331         rx_ctx.tphrdesc_ena = 1;
 332         rx_ctx.tphwdesc_ena = 1;
 333         rx_ctx.tphdata_ena = 1;
 334         rx_ctx.tphhead_ena = 1;
 335         /* Low Receive Queue Threshold defined in 64 descriptors units.
 336          * When the number of free descriptors goes below the lrxqthresh,
 337          * an immediate interrupt is triggered.
 338          */
 339         rx_ctx.lrxqthresh = 2;
 340         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 341         rx_ctx.l2tsel = 1;
 342         rx_ctx.showiv = 0;
 343         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 344
 345         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 346
 347         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 348                     rxq->port_id, rxq->queue_id, rxdid);
 349
 350         if (!(pf->supported_rxdid & BIT(rxdid))) {
 351                 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
 352                             rxdid);
 353                 return -EINVAL;
 354         }
 355
 356         ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
 357
 358         /* Enable Flexible Descriptors in the queue context which
 359          * allows this driver to select a specific receive descriptor format
 360          */
 361         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 362                 QRXFLXP_CNTXT_RXDID_IDX_M;
 363
 364         /* increasing context priority to pick up profile ID;
 365          * default is 0x01; setting to 0x03 to ensure profile
 366          * is programming if prev context is of same priority
 367          */
 368         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 369                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 370
 371         if (ad->ptp_ena || rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP)
 372                 regval |= QRXFLXP_CNTXT_TS_M;
 373
 374         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 375
 376         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 377         if (err) {
 378                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 379                             rxq->queue_id);
 380                 return -EINVAL;
 381         }
 382         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 383         if (err) {
 384                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 385                             rxq->queue_id);
 386                 return -EINVAL;
 387         }
 388
 389         /* Check if scattered RX needs to be used. */
 390         if (frame_size > buf_size)
 391                 dev_data->scattered_rx = 1;
 392
 393         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 394
 395         /* Init the Rx tail register*/
 396         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 397
 398         return 0;
 399 }
 400
 401 /* Allocate mbufs for all descriptors in rx queue */
 402 static int
 403 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 404 {
 405         struct ice_rx_entry *rxe = rxq->sw_ring;
 406         uint64_t dma_addr;
 407         uint16_t i;
 408
 409         for (i = 0; i < rxq->nb_rx_desc; i++) {
 410                 volatile union ice_rx_flex_desc *rxd;
 411                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 412
 413                 if (unlikely(!mbuf)) {
 414                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 415                         return -ENOMEM;
 416                 }
 417
 418                 rte_mbuf_refcnt_set(mbuf, 1);
 419                 mbuf->next = NULL;
 420                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 421                 mbuf->nb_segs = 1;
 422                 mbuf->port = rxq->port_id;
 423
 424                 dma_addr =
 425                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 426
 427                 rxd = &rxq->rx_ring[i];
 428                 rxd->read.pkt_addr = dma_addr;
 429                 rxd->read.hdr_addr = 0;
 430 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 431                 rxd->read.rsvd1 = 0;
 432                 rxd->read.rsvd2 = 0;
 433 #endif
 434                 rxe[i].mbuf = mbuf;
 435         }
 436
 437         return 0;
 438 }
 439
 440 /* Free all mbufs for descriptors in rx queue */
 441 static void
 442 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 443 {
 444         uint16_t i;
 445
 446         if (!rxq || !rxq->sw_ring) {
 447                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 448                 return;
 449         }
 450
 451         for (i = 0; i < rxq->nb_rx_desc; i++) {
 452                 if (rxq->sw_ring[i].mbuf) {
 453                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 454                         rxq->sw_ring[i].mbuf = NULL;
 455                 }
 456         }
 457         if (rxq->rx_nb_avail == 0)
 458                 return;
 459         for (i = 0; i < rxq->rx_nb_avail; i++)
 460                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 461
 462         rxq->rx_nb_avail = 0;
 463 }
 464
 465 /* turn on or off rx queue
 466  * @q_idx: queue index in pf scope
 467  * @on: turn on or off the queue
 468  */
 469 static int
 470 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 471 {
 472         uint32_t reg;
 473         uint16_t j;
 474
 475         /* QRX_CTRL = QRX_ENA */
 476         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 477
 478         if (on) {
 479                 if (reg & QRX_CTRL_QENA_STAT_M)
 480                         return 0; /* Already on, skip */
 481                 reg |= QRX_CTRL_QENA_REQ_M;
 482         } else {
 483                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 484                         return 0; /* Already off, skip */
 485                 reg &= ~QRX_CTRL_QENA_REQ_M;
 486         }
 487
 488         /* Write the register */
 489         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 490         /* Check the result. It is said that QENA_STAT
 491          * follows the QENA_REQ not more than 10 use.
 492          * TODO: need to change the wait counter later
 493          */
 494         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 495                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 496                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 497                 if (on) {
 498                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 499                             (reg & QRX_CTRL_QENA_STAT_M))
 500                                 break;
 501                 } else {
 502                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 503                             !(reg & QRX_CTRL_QENA_STAT_M))
 504                                 break;
 505                 }
 506         }
 507
 508         /* Check if it is timeout */
 509         if (j >= ICE_CHK_Q_ENA_COUNT) {
 510                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 511                             (on ? "enable" : "disable"), q_idx);
 512                 return -ETIMEDOUT;
 513         }
 514
 515         return 0;
 516 }
 517
 518 static inline int
 519 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 520 {
 521         int ret = 0;
 522
 523         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 524                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 525                              "rxq->rx_free_thresh=%d, "
 526                              "ICE_RX_MAX_BURST=%d",
 527                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 528                 ret = -EINVAL;
 529         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 530                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 531                              "rxq->rx_free_thresh=%d, "
 532                              "rxq->nb_rx_desc=%d",
 533                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 534                 ret = -EINVAL;
 535         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 536                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 537                              "rxq->nb_rx_desc=%d, "
 538                              "rxq->rx_free_thresh=%d",
 539                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 540                 ret = -EINVAL;
 541         }
 542
 543         return ret;
 544 }
 545
 546 /* reset fields in ice_rx_queue back to default */
 547 static void
 548 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 549 {
 550         unsigned int i;
 551         uint16_t len;
 552
 553         if (!rxq) {
 554                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 555                 return;
 556         }
 557
 558         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 559
 560         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 561                 ((volatile char *)rxq->rx_ring)[i] = 0;
 562
 563         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 564         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 565                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 566
 567         rxq->rx_nb_avail = 0;
 568         rxq->rx_next_avail = 0;
 569         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 570
 571         rxq->rx_tail = 0;
 572         rxq->nb_rx_hold = 0;
 573         rxq->pkt_first_seg = NULL;
 574         rxq->pkt_last_seg = NULL;
 575
 576         rxq->rxrearm_start = 0;
 577         rxq->rxrearm_nb = 0;
 578 }
 579
 580 int
 581 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 582 {
 583         struct ice_rx_queue *rxq;
 584         int err;
 585         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 586
 587         PMD_INIT_FUNC_TRACE();
 588
 589         if (rx_queue_id >= dev->data->nb_rx_queues) {
 590                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 591                             rx_queue_id, dev->data->nb_rx_queues);
 592                 return -EINVAL;
 593         }
 594
 595         rxq = dev->data->rx_queues[rx_queue_id];
 596         if (!rxq || !rxq->q_set) {
 597                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 598                             rx_queue_id);
 599                 return -EINVAL;
 600         }
 601
 602         err = ice_program_hw_rx_queue(rxq);
 603         if (err) {
 604                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 605                             rx_queue_id);
 606                 return -EIO;
 607         }
 608
 609         err = ice_alloc_rx_queue_mbufs(rxq);
 610         if (err) {
 611                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 612                 return -ENOMEM;
 613         }
 614
 615         /* Init the RX tail register. */
 616         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 617
 618         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 619         if (err) {
 620                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 621                             rx_queue_id);
 622
 623                 rxq->rx_rel_mbufs(rxq);
 624                 ice_reset_rx_queue(rxq);
 625                 return -EINVAL;
 626         }
 627
 628         dev->data->rx_queue_state[rx_queue_id] =
 629                 RTE_ETH_QUEUE_STATE_STARTED;
 630
 631         return 0;
 632 }
 633
 634 int
 635 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 636 {
 637         struct ice_rx_queue *rxq;
 638         int err;
 639         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 640
 641         if (rx_queue_id < dev->data->nb_rx_queues) {
 642                 rxq = dev->data->rx_queues[rx_queue_id];
 643
 644                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 645                 if (err) {
 646                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 647                                     rx_queue_id);
 648                         return -EINVAL;
 649                 }
 650                 rxq->rx_rel_mbufs(rxq);
 651                 ice_reset_rx_queue(rxq);
 652                 dev->data->rx_queue_state[rx_queue_id] =
 653                         RTE_ETH_QUEUE_STATE_STOPPED;
 654         }
 655
 656         return 0;
 657 }
 658
 659 int
 660 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 661 {
 662         struct ice_tx_queue *txq;
 663         int err;
 664         struct ice_vsi *vsi;
 665         struct ice_hw *hw;
 666         struct ice_aqc_add_tx_qgrp *txq_elem;
 667         struct ice_tlan_ctx tx_ctx;
 668         int buf_len;
 669
 670         PMD_INIT_FUNC_TRACE();
 671
 672         if (tx_queue_id >= dev->data->nb_tx_queues) {
 673                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 674                             tx_queue_id, dev->data->nb_tx_queues);
 675                 return -EINVAL;
 676         }
 677
 678         txq = dev->data->tx_queues[tx_queue_id];
 679         if (!txq || !txq->q_set) {
 680                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 681                             tx_queue_id);
 682                 return -EINVAL;
 683         }
 684
 685         buf_len = ice_struct_size(txq_elem, txqs, 1);
 686         txq_elem = ice_malloc(hw, buf_len);
 687         if (!txq_elem)
 688                 return -ENOMEM;
 689
 690         vsi = txq->vsi;
 691         hw = ICE_VSI_TO_HW(vsi);
 692
 693         memset(&tx_ctx, 0, sizeof(tx_ctx));
 694         txq_elem->num_txqs = 1;
 695         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 696
 697         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 698         tx_ctx.qlen = txq->nb_tx_desc;
 699         tx_ctx.pf_num = hw->pf_id;
 700         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 701         tx_ctx.src_vsi = vsi->vsi_id;
 702         tx_ctx.port_num = hw->port_info->lport;
 703         tx_ctx.tso_ena = 1; /* tso enable */
 704         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 705         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 706         tx_ctx.tsyn_ena = 1;
 707
 708         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 709                     ice_tlan_ctx_info);
 710
 711         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 712
 713         /* Init the Tx tail register*/
 714         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 715
 716         /* Fix me, we assume TC always 0 here */
 717         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 718                         txq_elem, buf_len, NULL);
 719         if (err) {
 720                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 721                 rte_free(txq_elem);
 722                 return -EIO;
 723         }
 724         /* store the schedule node id */
 725         txq->q_teid = txq_elem->txqs[0].q_teid;
 726
 727         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 728
 729         rte_free(txq_elem);
 730         return 0;
 731 }
 732
 733 static enum ice_status
 734 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 735 {
 736         struct ice_vsi *vsi = rxq->vsi;
 737         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 738         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 739         struct ice_rlan_ctx rx_ctx;
 740         enum ice_status err;
 741         uint32_t regval;
 742
 743         rxq->rx_hdr_len = 0;
 744         rxq->rx_buf_len = 1024;
 745
 746         memset(&rx_ctx, 0, sizeof(rx_ctx));
 747
 748         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 749         rx_ctx.qlen = rxq->nb_rx_desc;
 750         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 751         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 752         rx_ctx.dtype = 0; /* No Header Split mode */
 753         rx_ctx.dsize = 1; /* 32B descriptors */
 754         rx_ctx.rxmax = ICE_ETH_MAX_LEN;
 755         /* TPH: Transaction Layer Packet (TLP) processing hints */
 756         rx_ctx.tphrdesc_ena = 1;
 757         rx_ctx.tphwdesc_ena = 1;
 758         rx_ctx.tphdata_ena = 1;
 759         rx_ctx.tphhead_ena = 1;
 760         /* Low Receive Queue Threshold defined in 64 descriptors units.
 761          * When the number of free descriptors goes below the lrxqthresh,
 762          * an immediate interrupt is triggered.
 763          */
 764         rx_ctx.lrxqthresh = 2;
 765         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 766         rx_ctx.l2tsel = 1;
 767         rx_ctx.showiv = 0;
 768         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 769
 770         /* Enable Flexible Descriptors in the queue context which
 771          * allows this driver to select a specific receive descriptor format
 772          */
 773         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 774                 QRXFLXP_CNTXT_RXDID_IDX_M;
 775
 776         /* increasing context priority to pick up profile ID;
 777          * default is 0x01; setting to 0x03 to ensure profile
 778          * is programming if prev context is of same priority
 779          */
 780         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 781                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 782
 783         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 784
 785         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 786         if (err) {
 787                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 788                             rxq->queue_id);
 789                 return -EINVAL;
 790         }
 791         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 792         if (err) {
 793                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 794                             rxq->queue_id);
 795                 return -EINVAL;
 796         }
 797
 798         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 799
 800         /* Init the Rx tail register*/
 801         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 802
 803         return 0;
 804 }
 805
 806 int
 807 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 808 {
 809         struct ice_rx_queue *rxq;
 810         int err;
 811         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 812         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 813
 814         PMD_INIT_FUNC_TRACE();
 815
 816         rxq = pf->fdir.rxq;
 817         if (!rxq || !rxq->q_set) {
 818                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 819                             rx_queue_id);
 820                 return -EINVAL;
 821         }
 822
 823         err = ice_fdir_program_hw_rx_queue(rxq);
 824         if (err) {
 825                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 826                             rx_queue_id);
 827                 return -EIO;
 828         }
 829
 830         /* Init the RX tail register. */
 831         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 832
 833         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 834         if (err) {
 835                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 836                             rx_queue_id);
 837
 838                 ice_reset_rx_queue(rxq);
 839                 return -EINVAL;
 840         }
 841
 842         return 0;
 843 }
 844
 845 int
 846 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 847 {
 848         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 849         struct ice_tx_queue *txq;
 850         int err;
 851         struct ice_vsi *vsi;
 852         struct ice_hw *hw;
 853         struct ice_aqc_add_tx_qgrp *txq_elem;
 854         struct ice_tlan_ctx tx_ctx;
 855         int buf_len;
 856
 857         PMD_INIT_FUNC_TRACE();
 858
 859         txq = pf->fdir.txq;
 860         if (!txq || !txq->q_set) {
 861                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 862                             tx_queue_id);
 863                 return -EINVAL;
 864         }
 865
 866         buf_len = ice_struct_size(txq_elem, txqs, 1);
 867         txq_elem = ice_malloc(hw, buf_len);
 868         if (!txq_elem)
 869                 return -ENOMEM;
 870
 871         vsi = txq->vsi;
 872         hw = ICE_VSI_TO_HW(vsi);
 873
 874         memset(&tx_ctx, 0, sizeof(tx_ctx));
 875         txq_elem->num_txqs = 1;
 876         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 877
 878         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 879         tx_ctx.qlen = txq->nb_tx_desc;
 880         tx_ctx.pf_num = hw->pf_id;
 881         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 882         tx_ctx.src_vsi = vsi->vsi_id;
 883         tx_ctx.port_num = hw->port_info->lport;
 884         tx_ctx.tso_ena = 1; /* tso enable */
 885         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 886         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 887
 888         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 889                     ice_tlan_ctx_info);
 890
 891         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 892
 893         /* Init the Tx tail register*/
 894         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 895
 896         /* Fix me, we assume TC always 0 here */
 897         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 898                               txq_elem, buf_len, NULL);
 899         if (err) {
 900                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 901                 rte_free(txq_elem);
 902                 return -EIO;
 903         }
 904         /* store the schedule node id */
 905         txq->q_teid = txq_elem->txqs[0].q_teid;
 906
 907         rte_free(txq_elem);
 908         return 0;
 909 }
 910
 911 /* Free all mbufs for descriptors in tx queue */
 912 static void
 913 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 914 {
 915         uint16_t i;
 916
 917         if (!txq || !txq->sw_ring) {
 918                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 919                 return;
 920         }
 921
 922         for (i = 0; i < txq->nb_tx_desc; i++) {
 923                 if (txq->sw_ring[i].mbuf) {
 924                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 925                         txq->sw_ring[i].mbuf = NULL;
 926                 }
 927         }
 928 }
 929
 930 static void
 931 ice_reset_tx_queue(struct ice_tx_queue *txq)
 932 {
 933         struct ice_tx_entry *txe;
 934         uint16_t i, prev, size;
 935
 936         if (!txq) {
 937                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 938                 return;
 939         }
 940
 941         txe = txq->sw_ring;
 942         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 943         for (i = 0; i < size; i++)
 944                 ((volatile char *)txq->tx_ring)[i] = 0;
 945
 946         prev = (uint16_t)(txq->nb_tx_desc - 1);
 947         for (i = 0; i < txq->nb_tx_desc; i++) {
 948                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 949
 950                 txd->cmd_type_offset_bsz =
 951                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 952                 txe[i].mbuf =  NULL;
 953                 txe[i].last_id = i;
 954                 txe[prev].next_id = i;
 955                 prev = i;
 956         }
 957
 958         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 959         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 960
 961         txq->tx_tail = 0;
 962         txq->nb_tx_used = 0;
 963
 964         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 965         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 966 }
 967
 968 int
 969 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 970 {
 971         struct ice_tx_queue *txq;
 972         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 973         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 974         struct ice_vsi *vsi = pf->main_vsi;
 975         enum ice_status status;
 976         uint16_t q_ids[1];
 977         uint32_t q_teids[1];
 978         uint16_t q_handle = tx_queue_id;
 979
 980         if (tx_queue_id >= dev->data->nb_tx_queues) {
 981                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 982                             tx_queue_id, dev->data->nb_tx_queues);
 983                 return -EINVAL;
 984         }
 985
 986         txq = dev->data->tx_queues[tx_queue_id];
 987         if (!txq) {
 988                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 989                             tx_queue_id);
 990                 return -EINVAL;
 991         }
 992
 993         q_ids[0] = txq->reg_idx;
 994         q_teids[0] = txq->q_teid;
 995
 996         /* Fix me, we assume TC always 0 here */
 997         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 998                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 999         if (status != ICE_SUCCESS) {
1000                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1001                 return -EINVAL;
1002         }
1003
1004         txq->tx_rel_mbufs(txq);
1005         ice_reset_tx_queue(txq);
1006         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1007
1008         return 0;
1009 }
1010
1011 int
1012 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1013 {
1014         struct ice_rx_queue *rxq;
1015         int err;
1016         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1018
1019         rxq = pf->fdir.rxq;
1020
1021         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1022         if (err) {
1023                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1024                             rx_queue_id);
1025                 return -EINVAL;
1026         }
1027         rxq->rx_rel_mbufs(rxq);
1028
1029         return 0;
1030 }
1031
1032 int
1033 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1034 {
1035         struct ice_tx_queue *txq;
1036         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1038         struct ice_vsi *vsi = pf->main_vsi;
1039         enum ice_status status;
1040         uint16_t q_ids[1];
1041         uint32_t q_teids[1];
1042         uint16_t q_handle = tx_queue_id;
1043
1044         txq = pf->fdir.txq;
1045         if (!txq) {
1046                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1047                             tx_queue_id);
1048                 return -EINVAL;
1049         }
1050         vsi = txq->vsi;
1051
1052         q_ids[0] = txq->reg_idx;
1053         q_teids[0] = txq->q_teid;
1054
1055         /* Fix me, we assume TC always 0 here */
1056         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1057                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1058         if (status != ICE_SUCCESS) {
1059                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1060                 return -EINVAL;
1061         }
1062
1063         txq->tx_rel_mbufs(txq);
1064
1065         return 0;
1066 }
1067
1068 int
1069 ice_rx_queue_setup(struct rte_eth_dev *dev,
1070                    uint16_t queue_idx,
1071                    uint16_t nb_desc,
1072                    unsigned int socket_id,
1073                    const struct rte_eth_rxconf *rx_conf,
1074                    struct rte_mempool *mp)
1075 {
1076         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1077         struct ice_adapter *ad =
1078                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1079         struct ice_vsi *vsi = pf->main_vsi;
1080         struct ice_rx_queue *rxq;
1081         const struct rte_memzone *rz;
1082         uint32_t ring_size;
1083         uint16_t len;
1084         int use_def_burst_func = 1;
1085         uint64_t offloads;
1086
1087         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1088             nb_desc > ICE_MAX_RING_DESC ||
1089             nb_desc < ICE_MIN_RING_DESC) {
1090                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1091                              "invalid", nb_desc);
1092                 return -EINVAL;
1093         }
1094
1095         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1096
1097         /* Free memory if needed */
1098         if (dev->data->rx_queues[queue_idx]) {
1099                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1100                 dev->data->rx_queues[queue_idx] = NULL;
1101         }
1102
1103         /* Allocate the rx queue data structure */
1104         rxq = rte_zmalloc_socket(NULL,
1105                                  sizeof(struct ice_rx_queue),
1106                                  RTE_CACHE_LINE_SIZE,
1107                                  socket_id);
1108         if (!rxq) {
1109                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1110                              "rx queue data structure");
1111                 return -ENOMEM;
1112         }
1113         rxq->mp = mp;
1114         rxq->nb_rx_desc = nb_desc;
1115         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1116         rxq->queue_id = queue_idx;
1117         rxq->offloads = offloads;
1118
1119         rxq->reg_idx = vsi->base_queue + queue_idx;
1120         rxq->port_id = dev->data->port_id;
1121         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1122                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1123         else
1124                 rxq->crc_len = 0;
1125
1126         rxq->drop_en = rx_conf->rx_drop_en;
1127         rxq->vsi = vsi;
1128         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1129         rxq->proto_xtr = pf->proto_xtr != NULL ?
1130                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1131
1132         /* Allocate the maximun number of RX ring hardware descriptor. */
1133         len = ICE_MAX_RING_DESC;
1134
1135         /**
1136          * Allocating a little more memory because vectorized/bulk_alloc Rx
1137          * functions doesn't check boundaries each time.
1138          */
1139         len += ICE_RX_MAX_BURST;
1140
1141         /* Allocate the maximum number of RX ring hardware descriptor. */
1142         ring_size = sizeof(union ice_rx_flex_desc) * len;
1143         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1144         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1145                                       ring_size, ICE_RING_BASE_ALIGN,
1146                                       socket_id);
1147         if (!rz) {
1148                 ice_rx_queue_release(rxq);
1149                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1150                 return -ENOMEM;
1151         }
1152
1153         rxq->mz = rz;
1154         /* Zero all the descriptors in the ring. */
1155         memset(rz->addr, 0, ring_size);
1156
1157         rxq->rx_ring_dma = rz->iova;
1158         rxq->rx_ring = rz->addr;
1159
1160         /* always reserve more for bulk alloc */
1161         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1162
1163         /* Allocate the software ring. */
1164         rxq->sw_ring = rte_zmalloc_socket(NULL,
1165                                           sizeof(struct ice_rx_entry) * len,
1166                                           RTE_CACHE_LINE_SIZE,
1167                                           socket_id);
1168         if (!rxq->sw_ring) {
1169                 ice_rx_queue_release(rxq);
1170                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1171                 return -ENOMEM;
1172         }
1173
1174         ice_reset_rx_queue(rxq);
1175         rxq->q_set = true;
1176         dev->data->rx_queues[queue_idx] = rxq;
1177         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1178
1179         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1180
1181         if (!use_def_burst_func) {
1182                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1183                              "satisfied. Rx Burst Bulk Alloc function will be "
1184                              "used on port=%d, queue=%d.",
1185                              rxq->port_id, rxq->queue_id);
1186         } else {
1187                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1188                              "not satisfied, Scattered Rx is requested. "
1189                              "on port=%d, queue=%d.",
1190                              rxq->port_id, rxq->queue_id);
1191                 ad->rx_bulk_alloc_allowed = false;
1192         }
1193
1194         return 0;
1195 }
1196
1197 void
1198 ice_rx_queue_release(void *rxq)
1199 {
1200         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1201
1202         if (!q) {
1203                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1204                 return;
1205         }
1206
1207         q->rx_rel_mbufs(q);
1208         rte_free(q->sw_ring);
1209         rte_memzone_free(q->mz);
1210         rte_free(q);
1211 }
1212
1213 int
1214 ice_tx_queue_setup(struct rte_eth_dev *dev,
1215                    uint16_t queue_idx,
1216                    uint16_t nb_desc,
1217                    unsigned int socket_id,
1218                    const struct rte_eth_txconf *tx_conf)
1219 {
1220         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1221         struct ice_vsi *vsi = pf->main_vsi;
1222         struct ice_tx_queue *txq;
1223         const struct rte_memzone *tz;
1224         uint32_t ring_size;
1225         uint16_t tx_rs_thresh, tx_free_thresh;
1226         uint64_t offloads;
1227
1228         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1229
1230         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1231             nb_desc > ICE_MAX_RING_DESC ||
1232             nb_desc < ICE_MIN_RING_DESC) {
1233                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1234                              "invalid", nb_desc);
1235                 return -EINVAL;
1236         }
1237
1238         /**
1239          * The following two parameters control the setting of the RS bit on
1240          * transmit descriptors. TX descriptors will have their RS bit set
1241          * after txq->tx_rs_thresh descriptors have been used. The TX
1242          * descriptor ring will be cleaned after txq->tx_free_thresh
1243          * descriptors are used or if the number of descriptors required to
1244          * transmit a packet is greater than the number of free TX descriptors.
1245          *
1246          * The following constraints must be satisfied:
1247          *  - tx_rs_thresh must be greater than 0.
1248          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1249          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1250          *  - tx_rs_thresh must be a divisor of the ring size.
1251          *  - tx_free_thresh must be greater than 0.
1252          *  - tx_free_thresh must be less than the size of the ring minus 3.
1253          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1254          *
1255          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1256          * race condition, hence the maximum threshold constraints. When set
1257          * to zero use default values.
1258          */
1259         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1260                                     tx_conf->tx_free_thresh :
1261                                     ICE_DEFAULT_TX_FREE_THRESH);
1262         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1263         tx_rs_thresh =
1264                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1265                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1266         if (tx_conf->tx_rs_thresh)
1267                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1268         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1269                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1270                                 "exceed nb_desc. (tx_rs_thresh=%u "
1271                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1272                                 (unsigned int)tx_rs_thresh,
1273                                 (unsigned int)tx_free_thresh,
1274                                 (unsigned int)nb_desc,
1275                                 (int)dev->data->port_id,
1276                                 (int)queue_idx);
1277                 return -EINVAL;
1278         }
1279         if (tx_rs_thresh >= (nb_desc - 2)) {
1280                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1281                              "number of TX descriptors minus 2. "
1282                              "(tx_rs_thresh=%u port=%d queue=%d)",
1283                              (unsigned int)tx_rs_thresh,
1284                              (int)dev->data->port_id,
1285                              (int)queue_idx);
1286                 return -EINVAL;
1287         }
1288         if (tx_free_thresh >= (nb_desc - 3)) {
1289                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1290                              "tx_free_thresh must be less than the "
1291                              "number of TX descriptors minus 3. "
1292                              "(tx_free_thresh=%u port=%d queue=%d)",
1293                              (unsigned int)tx_free_thresh,
1294                              (int)dev->data->port_id,
1295                              (int)queue_idx);
1296                 return -EINVAL;
1297         }
1298         if (tx_rs_thresh > tx_free_thresh) {
1299                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1300                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1301                              " tx_rs_thresh=%u port=%d queue=%d)",
1302                              (unsigned int)tx_free_thresh,
1303                              (unsigned int)tx_rs_thresh,
1304                              (int)dev->data->port_id,
1305                              (int)queue_idx);
1306                 return -EINVAL;
1307         }
1308         if ((nb_desc % tx_rs_thresh) != 0) {
1309                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1310                              "number of TX descriptors. (tx_rs_thresh=%u"
1311                              " port=%d queue=%d)",
1312                              (unsigned int)tx_rs_thresh,
1313                              (int)dev->data->port_id,
1314                              (int)queue_idx);
1315                 return -EINVAL;
1316         }
1317         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1318                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1319                              "tx_rs_thresh is greater than 1. "
1320                              "(tx_rs_thresh=%u port=%d queue=%d)",
1321                              (unsigned int)tx_rs_thresh,
1322                              (int)dev->data->port_id,
1323                              (int)queue_idx);
1324                 return -EINVAL;
1325         }
1326
1327         /* Free memory if needed. */
1328         if (dev->data->tx_queues[queue_idx]) {
1329                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1330                 dev->data->tx_queues[queue_idx] = NULL;
1331         }
1332
1333         /* Allocate the TX queue data structure. */
1334         txq = rte_zmalloc_socket(NULL,
1335                                  sizeof(struct ice_tx_queue),
1336                                  RTE_CACHE_LINE_SIZE,
1337                                  socket_id);
1338         if (!txq) {
1339                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1340                              "tx queue structure");
1341                 return -ENOMEM;
1342         }
1343
1344         /* Allocate TX hardware ring descriptors. */
1345         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1346         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1347         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1348                                       ring_size, ICE_RING_BASE_ALIGN,
1349                                       socket_id);
1350         if (!tz) {
1351                 ice_tx_queue_release(txq);
1352                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1353                 return -ENOMEM;
1354         }
1355
1356         txq->mz = tz;
1357         txq->nb_tx_desc = nb_desc;
1358         txq->tx_rs_thresh = tx_rs_thresh;
1359         txq->tx_free_thresh = tx_free_thresh;
1360         txq->pthresh = tx_conf->tx_thresh.pthresh;
1361         txq->hthresh = tx_conf->tx_thresh.hthresh;
1362         txq->wthresh = tx_conf->tx_thresh.wthresh;
1363         txq->queue_id = queue_idx;
1364
1365         txq->reg_idx = vsi->base_queue + queue_idx;
1366         txq->port_id = dev->data->port_id;
1367         txq->offloads = offloads;
1368         txq->vsi = vsi;
1369         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1370
1371         txq->tx_ring_dma = tz->iova;
1372         txq->tx_ring = tz->addr;
1373
1374         /* Allocate software ring */
1375         txq->sw_ring =
1376                 rte_zmalloc_socket(NULL,
1377                                    sizeof(struct ice_tx_entry) * nb_desc,
1378                                    RTE_CACHE_LINE_SIZE,
1379                                    socket_id);
1380         if (!txq->sw_ring) {
1381                 ice_tx_queue_release(txq);
1382                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1383                 return -ENOMEM;
1384         }
1385
1386         ice_reset_tx_queue(txq);
1387         txq->q_set = true;
1388         dev->data->tx_queues[queue_idx] = txq;
1389         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1390         ice_set_tx_function_flag(dev, txq);
1391
1392         return 0;
1393 }
1394
1395 void
1396 ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1397 {
1398         ice_rx_queue_release(dev->data->rx_queues[qid]);
1399 }
1400
1401 void
1402 ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1403 {
1404         ice_tx_queue_release(dev->data->tx_queues[qid]);
1405 }
1406
1407 void
1408 ice_tx_queue_release(void *txq)
1409 {
1410         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1411
1412         if (!q) {
1413                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1414                 return;
1415         }
1416
1417         q->tx_rel_mbufs(q);
1418         rte_free(q->sw_ring);
1419         rte_memzone_free(q->mz);
1420         rte_free(q);
1421 }
1422
1423 void
1424 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1425                  struct rte_eth_rxq_info *qinfo)
1426 {
1427         struct ice_rx_queue *rxq;
1428
1429         rxq = dev->data->rx_queues[queue_id];
1430
1431         qinfo->mp = rxq->mp;
1432         qinfo->scattered_rx = dev->data->scattered_rx;
1433         qinfo->nb_desc = rxq->nb_rx_desc;
1434
1435         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1436         qinfo->conf.rx_drop_en = rxq->drop_en;
1437         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1438 }
1439
1440 void
1441 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1442                  struct rte_eth_txq_info *qinfo)
1443 {
1444         struct ice_tx_queue *txq;
1445
1446         txq = dev->data->tx_queues[queue_id];
1447
1448         qinfo->nb_desc = txq->nb_tx_desc;
1449
1450         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1451         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1452         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1453
1454         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1455         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1456         qinfo->conf.offloads = txq->offloads;
1457         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1458 }
1459
1460 uint32_t
1461 ice_rx_queue_count(void *rx_queue)
1462 {
1463 #define ICE_RXQ_SCAN_INTERVAL 4
1464         volatile union ice_rx_flex_desc *rxdp;
1465         struct ice_rx_queue *rxq;
1466         uint16_t desc = 0;
1467
1468         rxq = rx_queue;
1469         rxdp = &rxq->rx_ring[rxq->rx_tail];
1470         while ((desc < rxq->nb_rx_desc) &&
1471                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1472                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1473                 /**
1474                  * Check the DD bit of a rx descriptor of each 4 in a group,
1475                  * to avoid checking too frequently and downgrading performance
1476                  * too much.
1477                  */
1478                 desc += ICE_RXQ_SCAN_INTERVAL;
1479                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1480                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1481                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1482                                  desc - rxq->nb_rx_desc]);
1483         }
1484
1485         return desc;
1486 }
1487
1488 #define ICE_RX_FLEX_ERR0_BITS   \
1489         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1490          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1491          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1492          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1493          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1494          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1495
1496 /* Rx L3/L4 checksum */
1497 static inline uint64_t
1498 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1499 {
1500         uint64_t flags = 0;
1501
1502         /* check if HW has decoded the packet and checksum */
1503         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1504                 return 0;
1505
1506         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1507                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1508                 return flags;
1509         }
1510
1511         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1512                 flags |= PKT_RX_IP_CKSUM_BAD;
1513         else
1514                 flags |= PKT_RX_IP_CKSUM_GOOD;
1515
1516         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1517                 flags |= PKT_RX_L4_CKSUM_BAD;
1518         else
1519                 flags |= PKT_RX_L4_CKSUM_GOOD;
1520
1521         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1522                 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1523
1524         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1525                 flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
1526         else
1527                 flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
1528
1529         return flags;
1530 }
1531
1532 static inline void
1533 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1534 {
1535         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1536             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1537                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1538                 mb->vlan_tci =
1539                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1540                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1541                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1542         } else {
1543                 mb->vlan_tci = 0;
1544         }
1545
1546 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1547         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1548             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1549                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1550                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1551                 mb->vlan_tci_outer = mb->vlan_tci;
1552                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1553                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1554                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1555                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1556         } else {
1557                 mb->vlan_tci_outer = 0;
1558         }
1559 #endif
1560         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1561                    mb->vlan_tci, mb->vlan_tci_outer);
1562 }
1563
1564 #define ICE_LOOK_AHEAD 8
1565 #if (ICE_LOOK_AHEAD != 8)
1566 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1567 #endif
1568 static inline int
1569 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1570 {
1571         volatile union ice_rx_flex_desc *rxdp;
1572         struct ice_rx_entry *rxep;
1573         struct rte_mbuf *mb;
1574         uint16_t stat_err0;
1575         uint16_t pkt_len;
1576         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1577         int32_t i, j, nb_rx = 0;
1578         uint64_t pkt_flags = 0;
1579         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1580 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1581         struct ice_vsi *vsi = rxq->vsi;
1582         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1583         uint64_t ts_ns;
1584         struct ice_adapter *ad = rxq->vsi->adapter;
1585 #endif
1586         rxdp = &rxq->rx_ring[rxq->rx_tail];
1587         rxep = &rxq->sw_ring[rxq->rx_tail];
1588
1589         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1590
1591         /* Make sure there is at least 1 packet to receive */
1592         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1593                 return 0;
1594
1595         /**
1596          * Scan LOOK_AHEAD descriptors at a time to determine which
1597          * descriptors reference packets that are ready to be received.
1598          */
1599         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1600              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1601                 /* Read desc statuses backwards to avoid race condition */
1602                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1603                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1604
1605                 rte_smp_rmb();
1606
1607                 /* Compute how many status bits were set */
1608                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1609                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1610
1611                 nb_rx += nb_dd;
1612
1613                 /* Translate descriptor info to mbuf parameters */
1614                 for (j = 0; j < nb_dd; j++) {
1615                         mb = rxep[j].mbuf;
1616                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1617                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1618                         mb->data_len = pkt_len;
1619                         mb->pkt_len = pkt_len;
1620                         mb->ol_flags = 0;
1621                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1622                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1623                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1624                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1625                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1626                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1627 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1628                         if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
1629                                 ts_ns = ice_tstamp_convert_32b_64b(hw,
1630                                         rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high));
1631                                 if (ice_timestamp_dynflag > 0) {
1632                                         *RTE_MBUF_DYNFIELD(mb,
1633                                                 ice_timestamp_dynfield_offset,
1634                                                 rte_mbuf_timestamp_t *) = ts_ns;
1635                                         mb->ol_flags |= ice_timestamp_dynflag;
1636                                 }
1637                         }
1638
1639                         if (ad->ptp_ena && ((mb->packet_type &
1640                             RTE_PTYPE_L2_MASK) == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1641                                 rxq->time_high =
1642                                    rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high);
1643                                 mb->timesync = rxq->queue_id;
1644                                 pkt_flags |= PKT_RX_IEEE1588_PTP;
1645                         }
1646 #endif
1647                         mb->ol_flags |= pkt_flags;
1648                 }
1649
1650                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1651                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1652
1653                 if (nb_dd != ICE_LOOK_AHEAD)
1654                         break;
1655         }
1656
1657         /* Clear software ring entries */
1658         for (i = 0; i < nb_rx; i++)
1659                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1660
1661         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1662                    "port_id=%u, queue_id=%u, nb_rx=%d",
1663                    rxq->port_id, rxq->queue_id, nb_rx);
1664
1665         return nb_rx;
1666 }
1667
1668 static inline uint16_t
1669 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1670                        struct rte_mbuf **rx_pkts,
1671                        uint16_t nb_pkts)
1672 {
1673         uint16_t i;
1674         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1675
1676         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1677
1678         for (i = 0; i < nb_pkts; i++)
1679                 rx_pkts[i] = stage[i];
1680
1681         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1682         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1683
1684         return nb_pkts;
1685 }
1686
1687 static inline int
1688 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1689 {
1690         volatile union ice_rx_flex_desc *rxdp;
1691         struct ice_rx_entry *rxep;
1692         struct rte_mbuf *mb;
1693         uint16_t alloc_idx, i;
1694         uint64_t dma_addr;
1695         int diag;
1696
1697         /* Allocate buffers in bulk */
1698         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1699                                (rxq->rx_free_thresh - 1));
1700         rxep = &rxq->sw_ring[alloc_idx];
1701         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1702                                     rxq->rx_free_thresh);
1703         if (unlikely(diag != 0)) {
1704                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1705                 return -ENOMEM;
1706         }
1707
1708         rxdp = &rxq->rx_ring[alloc_idx];
1709         for (i = 0; i < rxq->rx_free_thresh; i++) {
1710                 if (likely(i < (rxq->rx_free_thresh - 1)))
1711                         /* Prefetch next mbuf */
1712                         rte_prefetch0(rxep[i + 1].mbuf);
1713
1714                 mb = rxep[i].mbuf;
1715                 rte_mbuf_refcnt_set(mb, 1);
1716                 mb->next = NULL;
1717                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1718                 mb->nb_segs = 1;
1719                 mb->port = rxq->port_id;
1720                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1721                 rxdp[i].read.hdr_addr = 0;
1722                 rxdp[i].read.pkt_addr = dma_addr;
1723         }
1724
1725         /* Update rx tail regsiter */
1726         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1727
1728         rxq->rx_free_trigger =
1729                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1730         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1731                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1732
1733         return 0;
1734 }
1735
1736 static inline uint16_t
1737 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1738 {
1739         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1740         uint16_t nb_rx = 0;
1741
1742         if (!nb_pkts)
1743                 return 0;
1744
1745         if (rxq->rx_nb_avail)
1746                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1747
1748         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1749         rxq->rx_next_avail = 0;
1750         rxq->rx_nb_avail = nb_rx;
1751         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1752
1753         if (rxq->rx_tail > rxq->rx_free_trigger) {
1754                 if (ice_rx_alloc_bufs(rxq) != 0) {
1755                         uint16_t i, j;
1756
1757                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1758                                 rxq->rx_free_thresh;
1759                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1760                                    "port_id=%u, queue_id=%u",
1761                                    rxq->port_id, rxq->queue_id);
1762                         rxq->rx_nb_avail = 0;
1763                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1764                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1765                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1766
1767                         return 0;
1768                 }
1769         }
1770
1771         if (rxq->rx_tail >= rxq->nb_rx_desc)
1772                 rxq->rx_tail = 0;
1773
1774         if (rxq->rx_nb_avail)
1775                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1776
1777         return 0;
1778 }
1779
1780 static uint16_t
1781 ice_recv_pkts_bulk_alloc(void *rx_queue,
1782                          struct rte_mbuf **rx_pkts,
1783                          uint16_t nb_pkts)
1784 {
1785         uint16_t nb_rx = 0;
1786         uint16_t n;
1787         uint16_t count;
1788
1789         if (unlikely(nb_pkts == 0))
1790                 return nb_rx;
1791
1792         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1793                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1794
1795         while (nb_pkts) {
1796                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1797                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1798                 nb_rx = (uint16_t)(nb_rx + count);
1799                 nb_pkts = (uint16_t)(nb_pkts - count);
1800                 if (count < n)
1801                         break;
1802         }
1803
1804         return nb_rx;
1805 }
1806
1807 static uint16_t
1808 ice_recv_scattered_pkts(void *rx_queue,
1809                         struct rte_mbuf **rx_pkts,
1810                         uint16_t nb_pkts)
1811 {
1812         struct ice_rx_queue *rxq = rx_queue;
1813         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1814         volatile union ice_rx_flex_desc *rxdp;
1815         union ice_rx_flex_desc rxd;
1816         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1817         struct ice_rx_entry *rxe;
1818         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1819         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1820         struct rte_mbuf *nmb; /* new allocated mbuf */
1821         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1822         uint16_t rx_id = rxq->rx_tail;
1823         uint16_t nb_rx = 0;
1824         uint16_t nb_hold = 0;
1825         uint16_t rx_packet_len;
1826         uint16_t rx_stat_err0;
1827         uint64_t dma_addr;
1828         uint64_t pkt_flags;
1829         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1830 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1831         struct ice_vsi *vsi = rxq->vsi;
1832         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1833         uint64_t ts_ns;
1834         struct ice_adapter *ad = rxq->vsi->adapter;
1835 #endif
1836         while (nb_rx < nb_pkts) {
1837                 rxdp = &rx_ring[rx_id];
1838                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1839
1840                 /* Check the DD bit first */
1841                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1842                         break;
1843
1844                 /* allocate mbuf */
1845                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1846                 if (unlikely(!nmb)) {
1847                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1848                         break;
1849                 }
1850                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1851
1852                 nb_hold++;
1853                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1854                 rx_id++;
1855                 if (unlikely(rx_id == rxq->nb_rx_desc))
1856                         rx_id = 0;
1857
1858                 /* Prefetch next mbuf */
1859                 rte_prefetch0(sw_ring[rx_id].mbuf);
1860
1861                 /**
1862                  * When next RX descriptor is on a cache line boundary,
1863                  * prefetch the next 4 RX descriptors and next 8 pointers
1864                  * to mbufs.
1865                  */
1866                 if ((rx_id & 0x3) == 0) {
1867                         rte_prefetch0(&rx_ring[rx_id]);
1868                         rte_prefetch0(&sw_ring[rx_id]);
1869                 }
1870
1871                 rxm = rxe->mbuf;
1872                 rxe->mbuf = nmb;
1873                 dma_addr =
1874                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1875
1876                 /* Set data buffer address and data length of the mbuf */
1877                 rxdp->read.hdr_addr = 0;
1878                 rxdp->read.pkt_addr = dma_addr;
1879                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1880                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1881                 rxm->data_len = rx_packet_len;
1882                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1883
1884                 /**
1885                  * If this is the first buffer of the received packet, set the
1886                  * pointer to the first mbuf of the packet and initialize its
1887                  * context. Otherwise, update the total length and the number
1888                  * of segments of the current scattered packet, and update the
1889                  * pointer to the last mbuf of the current packet.
1890                  */
1891                 if (!first_seg) {
1892                         first_seg = rxm;
1893                         first_seg->nb_segs = 1;
1894                         first_seg->pkt_len = rx_packet_len;
1895                 } else {
1896                         first_seg->pkt_len =
1897                                 (uint16_t)(first_seg->pkt_len +
1898                                            rx_packet_len);
1899                         first_seg->nb_segs++;
1900                         last_seg->next = rxm;
1901                 }
1902
1903                 /**
1904                  * If this is not the last buffer of the received packet,
1905                  * update the pointer to the last mbuf of the current scattered
1906                  * packet and continue to parse the RX ring.
1907                  */
1908                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1909                         last_seg = rxm;
1910                         continue;
1911                 }
1912
1913                 /**
1914                  * This is the last buffer of the received packet. If the CRC
1915                  * is not stripped by the hardware:
1916                  *  - Subtract the CRC length from the total packet length.
1917                  *  - If the last buffer only contains the whole CRC or a part
1918                  *  of it, free the mbuf associated to the last buffer. If part
1919                  *  of the CRC is also contained in the previous mbuf, subtract
1920                  *  the length of that CRC part from the data length of the
1921                  *  previous mbuf.
1922                  */
1923                 rxm->next = NULL;
1924                 if (unlikely(rxq->crc_len > 0)) {
1925                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1926                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1927                                 rte_pktmbuf_free_seg(rxm);
1928                                 first_seg->nb_segs--;
1929                                 last_seg->data_len =
1930                                         (uint16_t)(last_seg->data_len -
1931                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1932                                 last_seg->next = NULL;
1933                         } else
1934                                 rxm->data_len = (uint16_t)(rx_packet_len -
1935                                                            RTE_ETHER_CRC_LEN);
1936                 }
1937
1938                 first_seg->port = rxq->port_id;
1939                 first_seg->ol_flags = 0;
1940                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1941                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1942                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1943                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1944                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1945 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1946                 if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
1947                         ts_ns = ice_tstamp_convert_32b_64b(hw,
1948                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1949                         if (ice_timestamp_dynflag > 0) {
1950                                 *RTE_MBUF_DYNFIELD(first_seg,
1951                                         ice_timestamp_dynfield_offset,
1952                                         rte_mbuf_timestamp_t *) = ts_ns;
1953                                 first_seg->ol_flags |= ice_timestamp_dynflag;
1954                         }
1955                 }
1956
1957                 if (ad->ptp_ena && ((first_seg->packet_type & RTE_PTYPE_L2_MASK)
1958                     == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1959                         rxq->time_high =
1960                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
1961                         first_seg->timesync = rxq->queue_id;
1962                         pkt_flags |= PKT_RX_IEEE1588_PTP;
1963                 }
1964 #endif
1965                 first_seg->ol_flags |= pkt_flags;
1966                 /* Prefetch data of first segment, if configured to do so. */
1967                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1968                                           first_seg->data_off));
1969                 rx_pkts[nb_rx++] = first_seg;
1970                 first_seg = NULL;
1971         }
1972
1973         /* Record index of the next RX descriptor to probe. */
1974         rxq->rx_tail = rx_id;
1975         rxq->pkt_first_seg = first_seg;
1976         rxq->pkt_last_seg = last_seg;
1977
1978         /**
1979          * If the number of free RX descriptors is greater than the RX free
1980          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1981          * register. Update the RDT with the value of the last processed RX
1982          * descriptor minus 1, to guarantee that the RDT register is never
1983          * equal to the RDH register, which creates a "full" ring situtation
1984          * from the hardware point of view.
1985          */
1986         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1987         if (nb_hold > rxq->rx_free_thresh) {
1988                 rx_id = (uint16_t)(rx_id == 0 ?
1989                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1990                 /* write TAIL register */
1991                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1992                 nb_hold = 0;
1993         }
1994         rxq->nb_rx_hold = nb_hold;
1995
1996         /* return received packet in the burst */
1997         return nb_rx;
1998 }
1999
2000 const uint32_t *
2001 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2002 {
2003         struct ice_adapter *ad =
2004                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2005         const uint32_t *ptypes;
2006
2007         static const uint32_t ptypes_os[] = {
2008                 /* refers to ice_get_default_pkt_type() */
2009                 RTE_PTYPE_L2_ETHER,
2010                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2011                 RTE_PTYPE_L2_ETHER_LLDP,
2012                 RTE_PTYPE_L2_ETHER_ARP,
2013                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2014                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2015                 RTE_PTYPE_L4_FRAG,
2016                 RTE_PTYPE_L4_ICMP,
2017                 RTE_PTYPE_L4_NONFRAG,
2018                 RTE_PTYPE_L4_SCTP,
2019                 RTE_PTYPE_L4_TCP,
2020                 RTE_PTYPE_L4_UDP,
2021                 RTE_PTYPE_TUNNEL_GRENAT,
2022                 RTE_PTYPE_TUNNEL_IP,
2023                 RTE_PTYPE_INNER_L2_ETHER,
2024                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2025                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2026                 RTE_PTYPE_INNER_L4_FRAG,
2027                 RTE_PTYPE_INNER_L4_ICMP,
2028                 RTE_PTYPE_INNER_L4_NONFRAG,
2029                 RTE_PTYPE_INNER_L4_SCTP,
2030                 RTE_PTYPE_INNER_L4_TCP,
2031                 RTE_PTYPE_INNER_L4_UDP,
2032                 RTE_PTYPE_UNKNOWN
2033         };
2034
2035         static const uint32_t ptypes_comms[] = {
2036                 /* refers to ice_get_default_pkt_type() */
2037                 RTE_PTYPE_L2_ETHER,
2038                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2039                 RTE_PTYPE_L2_ETHER_LLDP,
2040                 RTE_PTYPE_L2_ETHER_ARP,
2041                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2042                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2043                 RTE_PTYPE_L4_FRAG,
2044                 RTE_PTYPE_L4_ICMP,
2045                 RTE_PTYPE_L4_NONFRAG,
2046                 RTE_PTYPE_L4_SCTP,
2047                 RTE_PTYPE_L4_TCP,
2048                 RTE_PTYPE_L4_UDP,
2049                 RTE_PTYPE_TUNNEL_GRENAT,
2050                 RTE_PTYPE_TUNNEL_IP,
2051                 RTE_PTYPE_INNER_L2_ETHER,
2052                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2053                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2054                 RTE_PTYPE_INNER_L4_FRAG,
2055                 RTE_PTYPE_INNER_L4_ICMP,
2056                 RTE_PTYPE_INNER_L4_NONFRAG,
2057                 RTE_PTYPE_INNER_L4_SCTP,
2058                 RTE_PTYPE_INNER_L4_TCP,
2059                 RTE_PTYPE_INNER_L4_UDP,
2060                 RTE_PTYPE_TUNNEL_GTPC,
2061                 RTE_PTYPE_TUNNEL_GTPU,
2062                 RTE_PTYPE_L2_ETHER_PPPOE,
2063                 RTE_PTYPE_UNKNOWN
2064         };
2065
2066         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
2067                 ptypes = ptypes_comms;
2068         else
2069                 ptypes = ptypes_os;
2070
2071         if (dev->rx_pkt_burst == ice_recv_pkts ||
2072             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
2073             dev->rx_pkt_burst == ice_recv_scattered_pkts)
2074                 return ptypes;
2075
2076 #ifdef RTE_ARCH_X86
2077         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
2078             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
2079 #ifdef CC_AVX512_SUPPORT
2080             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
2081             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
2082             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
2083             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
2084 #endif
2085             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
2086             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
2087             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2088             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2089                 return ptypes;
2090 #endif
2091
2092         return NULL;
2093 }
2094
2095 int
2096 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2097 {
2098         volatile union ice_rx_flex_desc *rxdp;
2099         struct ice_rx_queue *rxq = rx_queue;
2100         uint32_t desc;
2101
2102         if (unlikely(offset >= rxq->nb_rx_desc))
2103                 return -EINVAL;
2104
2105         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2106                 return RTE_ETH_RX_DESC_UNAVAIL;
2107
2108         desc = rxq->rx_tail + offset;
2109         if (desc >= rxq->nb_rx_desc)
2110                 desc -= rxq->nb_rx_desc;
2111
2112         rxdp = &rxq->rx_ring[desc];
2113         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2114             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2115                 return RTE_ETH_RX_DESC_DONE;
2116
2117         return RTE_ETH_RX_DESC_AVAIL;
2118 }
2119
2120 int
2121 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2122 {
2123         struct ice_tx_queue *txq = tx_queue;
2124         volatile uint64_t *status;
2125         uint64_t mask, expect;
2126         uint32_t desc;
2127
2128         if (unlikely(offset >= txq->nb_tx_desc))
2129                 return -EINVAL;
2130
2131         desc = txq->tx_tail + offset;
2132         /* go to next desc that has the RS bit */
2133         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2134                 txq->tx_rs_thresh;
2135         if (desc >= txq->nb_tx_desc) {
2136                 desc -= txq->nb_tx_desc;
2137                 if (desc >= txq->nb_tx_desc)
2138                         desc -= txq->nb_tx_desc;
2139         }
2140
2141         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2142         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2143         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2144                                   ICE_TXD_QW1_DTYPE_S);
2145         if ((*status & mask) == expect)
2146                 return RTE_ETH_TX_DESC_DONE;
2147
2148         return RTE_ETH_TX_DESC_FULL;
2149 }
2150
2151 void
2152 ice_free_queues(struct rte_eth_dev *dev)
2153 {
2154         uint16_t i;
2155
2156         PMD_INIT_FUNC_TRACE();
2157
2158         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2159                 if (!dev->data->rx_queues[i])
2160                         continue;
2161                 ice_rx_queue_release(dev->data->rx_queues[i]);
2162                 dev->data->rx_queues[i] = NULL;
2163         }
2164         dev->data->nb_rx_queues = 0;
2165
2166         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2167                 if (!dev->data->tx_queues[i])
2168                         continue;
2169                 ice_tx_queue_release(dev->data->tx_queues[i]);
2170                 dev->data->tx_queues[i] = NULL;
2171         }
2172         dev->data->nb_tx_queues = 0;
2173 }
2174
2175 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
2176 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
2177
2178 int
2179 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2180 {
2181         struct ice_tx_queue *txq;
2182         const struct rte_memzone *tz = NULL;
2183         uint32_t ring_size;
2184         struct rte_eth_dev *dev;
2185
2186         if (!pf) {
2187                 PMD_DRV_LOG(ERR, "PF is not available");
2188                 return -EINVAL;
2189         }
2190
2191         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2192
2193         /* Allocate the TX queue data structure. */
2194         txq = rte_zmalloc_socket("ice fdir tx queue",
2195                                  sizeof(struct ice_tx_queue),
2196                                  RTE_CACHE_LINE_SIZE,
2197                                  SOCKET_ID_ANY);
2198         if (!txq) {
2199                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2200                             "tx queue structure.");
2201                 return -ENOMEM;
2202         }
2203
2204         /* Allocate TX hardware ring descriptors. */
2205         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2206         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2207
2208         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2209                                       ICE_FDIR_QUEUE_ID, ring_size,
2210                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2211         if (!tz) {
2212                 ice_tx_queue_release(txq);
2213                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2214                 return -ENOMEM;
2215         }
2216
2217         txq->mz = tz;
2218         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2219         txq->queue_id = ICE_FDIR_QUEUE_ID;
2220         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2221         txq->vsi = pf->fdir.fdir_vsi;
2222
2223         txq->tx_ring_dma = tz->iova;
2224         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2225         /*
2226          * don't need to allocate software ring and reset for the fdir
2227          * program queue just set the queue has been configured.
2228          */
2229         txq->q_set = true;
2230         pf->fdir.txq = txq;
2231
2232         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2233
2234         return ICE_SUCCESS;
2235 }
2236
2237 int
2238 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2239 {
2240         struct ice_rx_queue *rxq;
2241         const struct rte_memzone *rz = NULL;
2242         uint32_t ring_size;
2243         struct rte_eth_dev *dev;
2244
2245         if (!pf) {
2246                 PMD_DRV_LOG(ERR, "PF is not available");
2247                 return -EINVAL;
2248         }
2249
2250         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2251
2252         /* Allocate the RX queue data structure. */
2253         rxq = rte_zmalloc_socket("ice fdir rx queue",
2254                                  sizeof(struct ice_rx_queue),
2255                                  RTE_CACHE_LINE_SIZE,
2256                                  SOCKET_ID_ANY);
2257         if (!rxq) {
2258                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2259                             "rx queue structure.");
2260                 return -ENOMEM;
2261         }
2262
2263         /* Allocate RX hardware ring descriptors. */
2264         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2265         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2266
2267         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2268                                       ICE_FDIR_QUEUE_ID, ring_size,
2269                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2270         if (!rz) {
2271                 ice_rx_queue_release(rxq);
2272                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2273                 return -ENOMEM;
2274         }
2275
2276         rxq->mz = rz;
2277         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2278         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2279         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2280         rxq->vsi = pf->fdir.fdir_vsi;
2281
2282         rxq->rx_ring_dma = rz->iova;
2283         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2284                sizeof(union ice_32byte_rx_desc));
2285         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2286
2287         /*
2288          * Don't need to allocate software ring and reset for the fdir
2289          * rx queue, just set the queue has been configured.
2290          */
2291         rxq->q_set = true;
2292         pf->fdir.rxq = rxq;
2293
2294         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2295
2296         return ICE_SUCCESS;
2297 }
2298
2299 uint16_t
2300 ice_recv_pkts(void *rx_queue,
2301               struct rte_mbuf **rx_pkts,
2302               uint16_t nb_pkts)
2303 {
2304         struct ice_rx_queue *rxq = rx_queue;
2305         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2306         volatile union ice_rx_flex_desc *rxdp;
2307         union ice_rx_flex_desc rxd;
2308         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2309         struct ice_rx_entry *rxe;
2310         struct rte_mbuf *nmb; /* new allocated mbuf */
2311         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2312         uint16_t rx_id = rxq->rx_tail;
2313         uint16_t nb_rx = 0;
2314         uint16_t nb_hold = 0;
2315         uint16_t rx_packet_len;
2316         uint16_t rx_stat_err0;
2317         uint64_t dma_addr;
2318         uint64_t pkt_flags;
2319         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2320 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2321         struct ice_vsi *vsi = rxq->vsi;
2322         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2323         uint64_t ts_ns;
2324         struct ice_adapter *ad = rxq->vsi->adapter;
2325 #endif
2326         while (nb_rx < nb_pkts) {
2327                 rxdp = &rx_ring[rx_id];
2328                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2329
2330                 /* Check the DD bit first */
2331                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2332                         break;
2333
2334                 /* allocate mbuf */
2335                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2336                 if (unlikely(!nmb)) {
2337                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2338                         break;
2339                 }
2340                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2341
2342                 nb_hold++;
2343                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2344                 rx_id++;
2345                 if (unlikely(rx_id == rxq->nb_rx_desc))
2346                         rx_id = 0;
2347                 rxm = rxe->mbuf;
2348                 rxe->mbuf = nmb;
2349                 dma_addr =
2350                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2351
2352                 /**
2353                  * fill the read format of descriptor with physic address in
2354                  * new allocated mbuf: nmb
2355                  */
2356                 rxdp->read.hdr_addr = 0;
2357                 rxdp->read.pkt_addr = dma_addr;
2358
2359                 /* calculate rx_packet_len of the received pkt */
2360                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2361                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2362
2363                 /* fill old mbuf with received descriptor: rxd */
2364                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2365                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2366                 rxm->nb_segs = 1;
2367                 rxm->next = NULL;
2368                 rxm->pkt_len = rx_packet_len;
2369                 rxm->data_len = rx_packet_len;
2370                 rxm->port = rxq->port_id;
2371                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2372                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2373                 ice_rxd_to_vlan_tci(rxm, &rxd);
2374                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
2375                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2376 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2377                 if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
2378                         ts_ns = ice_tstamp_convert_32b_64b(hw,
2379                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
2380                         if (ice_timestamp_dynflag > 0) {
2381                                 *RTE_MBUF_DYNFIELD(rxm,
2382                                         ice_timestamp_dynfield_offset,
2383                                         rte_mbuf_timestamp_t *) = ts_ns;
2384                                 rxm->ol_flags |= ice_timestamp_dynflag;
2385                         }
2386                 }
2387
2388                 if (ad->ptp_ena && ((rxm->packet_type & RTE_PTYPE_L2_MASK) ==
2389                     RTE_PTYPE_L2_ETHER_TIMESYNC)) {
2390                         rxq->time_high =
2391                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2392                         rxm->timesync = rxq->queue_id;
2393                         pkt_flags |= PKT_RX_IEEE1588_PTP;
2394                 }
2395 #endif
2396                 rxm->ol_flags |= pkt_flags;
2397                 /* copy old mbuf to rx_pkts */
2398                 rx_pkts[nb_rx++] = rxm;
2399         }
2400         rxq->rx_tail = rx_id;
2401         /**
2402          * If the number of free RX descriptors is greater than the RX free
2403          * threshold of the queue, advance the receive tail register of queue.
2404          * Update that register with the value of the last processed RX
2405          * descriptor minus 1.
2406          */
2407         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2408         if (nb_hold > rxq->rx_free_thresh) {
2409                 rx_id = (uint16_t)(rx_id == 0 ?
2410                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2411                 /* write TAIL register */
2412                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2413                 nb_hold = 0;
2414         }
2415         rxq->nb_rx_hold = nb_hold;
2416
2417         /* return received packet in the burst */
2418         return nb_rx;
2419 }
2420
2421 static inline void
2422 ice_parse_tunneling_params(uint64_t ol_flags,
2423                             union ice_tx_offload tx_offload,
2424                             uint32_t *cd_tunneling)
2425 {
2426         /* EIPT: External (outer) IP header type */
2427         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2428                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2429         else if (ol_flags & PKT_TX_OUTER_IPV4)
2430                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2431         else if (ol_flags & PKT_TX_OUTER_IPV6)
2432                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2433
2434         /* EIPLEN: External (outer) IP header length, in DWords */
2435         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2436                 ICE_TXD_CTX_QW0_EIPLEN_S;
2437
2438         /* L4TUNT: L4 Tunneling Type */
2439         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2440         case PKT_TX_TUNNEL_IPIP:
2441                 /* for non UDP / GRE tunneling, set to 00b */
2442                 break;
2443         case PKT_TX_TUNNEL_VXLAN:
2444         case PKT_TX_TUNNEL_GTP:
2445         case PKT_TX_TUNNEL_GENEVE:
2446                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2447                 break;
2448         case PKT_TX_TUNNEL_GRE:
2449                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2450                 break;
2451         default:
2452                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2453                 return;
2454         }
2455
2456         /* L4TUNLEN: L4 Tunneling Length, in Words
2457          *
2458          * We depend on app to set rte_mbuf.l2_len correctly.
2459          * For IP in GRE it should be set to the length of the GRE
2460          * header;
2461          * For MAC in GRE or MAC in UDP it should be set to the length
2462          * of the GRE or UDP headers plus the inner MAC up to including
2463          * its last Ethertype.
2464          * If MPLS labels exists, it should include them as well.
2465          */
2466         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2467                 ICE_TXD_CTX_QW0_NATLEN_S;
2468
2469         /**
2470          * Calculate the tunneling UDP checksum.
2471          * Shall be set only if L4TUNT = 01b and EIPT is not zero
2472          */
2473         if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2474             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2475                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2476 }
2477
2478 static inline void
2479 ice_txd_enable_checksum(uint64_t ol_flags,
2480                         uint32_t *td_cmd,
2481                         uint32_t *td_offset,
2482                         union ice_tx_offload tx_offload)
2483 {
2484         /* Set MACLEN */
2485         if (ol_flags & PKT_TX_TUNNEL_MASK)
2486                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2487                         << ICE_TX_DESC_LEN_MACLEN_S;
2488         else
2489                 *td_offset |= (tx_offload.l2_len >> 1)
2490                         << ICE_TX_DESC_LEN_MACLEN_S;
2491
2492         /* Enable L3 checksum offloads */
2493         if (ol_flags & PKT_TX_IP_CKSUM) {
2494                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2495                 *td_offset |= (tx_offload.l3_len >> 2) <<
2496                               ICE_TX_DESC_LEN_IPLEN_S;
2497         } else if (ol_flags & PKT_TX_IPV4) {
2498                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2499                 *td_offset |= (tx_offload.l3_len >> 2) <<
2500                               ICE_TX_DESC_LEN_IPLEN_S;
2501         } else if (ol_flags & PKT_TX_IPV6) {
2502                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2503                 *td_offset |= (tx_offload.l3_len >> 2) <<
2504                               ICE_TX_DESC_LEN_IPLEN_S;
2505         }
2506
2507         if (ol_flags & PKT_TX_TCP_SEG) {
2508                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2509                 *td_offset |= (tx_offload.l4_len >> 2) <<
2510                               ICE_TX_DESC_LEN_L4_LEN_S;
2511                 return;
2512         }
2513
2514         /* Enable L4 checksum offloads */
2515         switch (ol_flags & PKT_TX_L4_MASK) {
2516         case PKT_TX_TCP_CKSUM:
2517                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2518                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2519                               ICE_TX_DESC_LEN_L4_LEN_S;
2520                 break;
2521         case PKT_TX_SCTP_CKSUM:
2522                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2523                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2524                               ICE_TX_DESC_LEN_L4_LEN_S;
2525                 break;
2526         case PKT_TX_UDP_CKSUM:
2527                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2528                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2529                               ICE_TX_DESC_LEN_L4_LEN_S;
2530                 break;
2531         default:
2532                 break;
2533         }
2534 }
2535
2536 static inline int
2537 ice_xmit_cleanup(struct ice_tx_queue *txq)
2538 {
2539         struct ice_tx_entry *sw_ring = txq->sw_ring;
2540         volatile struct ice_tx_desc *txd = txq->tx_ring;
2541         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2542         uint16_t nb_tx_desc = txq->nb_tx_desc;
2543         uint16_t desc_to_clean_to;
2544         uint16_t nb_tx_to_clean;
2545
2546         /* Determine the last descriptor needing to be cleaned */
2547         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2548         if (desc_to_clean_to >= nb_tx_desc)
2549                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2550
2551         /* Check to make sure the last descriptor to clean is done */
2552         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2553         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2554             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2555                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2556                            "(port=%d queue=%d) value=0x%"PRIx64"\n",
2557                            desc_to_clean_to,
2558                            txq->port_id, txq->queue_id,
2559                            txd[desc_to_clean_to].cmd_type_offset_bsz);
2560                 /* Failed to clean any descriptors */
2561                 return -1;
2562         }
2563
2564         /* Figure out how many descriptors will be cleaned */
2565         if (last_desc_cleaned > desc_to_clean_to)
2566                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2567                                             desc_to_clean_to);
2568         else
2569                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2570                                             last_desc_cleaned);
2571
2572         /* The last descriptor to clean is done, so that means all the
2573          * descriptors from the last descriptor that was cleaned
2574          * up to the last descriptor with the RS bit set
2575          * are done. Only reset the threshold descriptor.
2576          */
2577         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2578
2579         /* Update the txq to reflect the last descriptor that was cleaned */
2580         txq->last_desc_cleaned = desc_to_clean_to;
2581         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2582
2583         return 0;
2584 }
2585
2586 /* Construct the tx flags */
2587 static inline uint64_t
2588 ice_build_ctob(uint32_t td_cmd,
2589                uint32_t td_offset,
2590                uint16_t size,
2591                uint32_t td_tag)
2592 {
2593         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2594                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2595                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2596                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2597                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2598 }
2599
2600 /* Check if the context descriptor is needed for TX offloading */
2601 static inline uint16_t
2602 ice_calc_context_desc(uint64_t flags)
2603 {
2604         static uint64_t mask = PKT_TX_TCP_SEG |
2605                 PKT_TX_QINQ |
2606                 PKT_TX_OUTER_IP_CKSUM |
2607                 PKT_TX_TUNNEL_MASK |
2608                 PKT_TX_IEEE1588_TMST;
2609
2610         return (flags & mask) ? 1 : 0;
2611 }
2612
2613 /* set ice TSO context descriptor */
2614 static inline uint64_t
2615 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2616 {
2617         uint64_t ctx_desc = 0;
2618         uint32_t cd_cmd, hdr_len, cd_tso_len;
2619
2620         if (!tx_offload.l4_len) {
2621                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2622                 return ctx_desc;
2623         }
2624
2625         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2626         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2627                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2628
2629         cd_cmd = ICE_TX_CTX_DESC_TSO;
2630         cd_tso_len = mbuf->pkt_len - hdr_len;
2631         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2632                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2633                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2634
2635         return ctx_desc;
2636 }
2637
2638 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2639 #define ICE_MAX_DATA_PER_TXD \
2640         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2641 /* Calculate the number of TX descriptors needed for each pkt */
2642 static inline uint16_t
2643 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2644 {
2645         struct rte_mbuf *txd = tx_pkt;
2646         uint16_t count = 0;
2647
2648         while (txd != NULL) {
2649                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2650                 txd = txd->next;
2651         }
2652
2653         return count;
2654 }
2655
2656 uint16_t
2657 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2658 {
2659         struct ice_tx_queue *txq;
2660         volatile struct ice_tx_desc *tx_ring;
2661         volatile struct ice_tx_desc *txd;
2662         struct ice_tx_entry *sw_ring;
2663         struct ice_tx_entry *txe, *txn;
2664         struct rte_mbuf *tx_pkt;
2665         struct rte_mbuf *m_seg;
2666         uint32_t cd_tunneling_params;
2667         uint16_t tx_id;
2668         uint16_t nb_tx;
2669         uint16_t nb_used;
2670         uint16_t nb_ctx;
2671         uint32_t td_cmd = 0;
2672         uint32_t td_offset = 0;
2673         uint32_t td_tag = 0;
2674         uint16_t tx_last;
2675         uint16_t slen;
2676         uint64_t buf_dma_addr;
2677         uint64_t ol_flags;
2678         union ice_tx_offload tx_offload = {0};
2679
2680         txq = tx_queue;
2681         sw_ring = txq->sw_ring;
2682         tx_ring = txq->tx_ring;
2683         tx_id = txq->tx_tail;
2684         txe = &sw_ring[tx_id];
2685
2686         /* Check if the descriptor ring needs to be cleaned. */
2687         if (txq->nb_tx_free < txq->tx_free_thresh)
2688                 (void)ice_xmit_cleanup(txq);
2689
2690         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2691                 tx_pkt = *tx_pkts++;
2692
2693                 td_cmd = 0;
2694                 td_tag = 0;
2695                 td_offset = 0;
2696                 ol_flags = tx_pkt->ol_flags;
2697                 tx_offload.l2_len = tx_pkt->l2_len;
2698                 tx_offload.l3_len = tx_pkt->l3_len;
2699                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2700                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2701                 tx_offload.l4_len = tx_pkt->l4_len;
2702                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2703                 /* Calculate the number of context descriptors needed. */
2704                 nb_ctx = ice_calc_context_desc(ol_flags);
2705
2706                 /* The number of descriptors that must be allocated for
2707                  * a packet equals to the number of the segments of that
2708                  * packet plus the number of context descriptor if needed.
2709                  * Recalculate the needed tx descs when TSO enabled in case
2710                  * the mbuf data size exceeds max data size that hw allows
2711                  * per tx desc.
2712                  */
2713                 if (ol_flags & PKT_TX_TCP_SEG)
2714                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2715                                              nb_ctx);
2716                 else
2717                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2718                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2719
2720                 /* Circular ring */
2721                 if (tx_last >= txq->nb_tx_desc)
2722                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2723
2724                 if (nb_used > txq->nb_tx_free) {
2725                         if (ice_xmit_cleanup(txq) != 0) {
2726                                 if (nb_tx == 0)
2727                                         return 0;
2728                                 goto end_of_tx;
2729                         }
2730                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2731                                 while (nb_used > txq->nb_tx_free) {
2732                                         if (ice_xmit_cleanup(txq) != 0) {
2733                                                 if (nb_tx == 0)
2734                                                         return 0;
2735                                                 goto end_of_tx;
2736                                         }
2737                                 }
2738                         }
2739                 }
2740
2741                 /* Descriptor based VLAN insertion */
2742                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2743                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2744                         td_tag = tx_pkt->vlan_tci;
2745                 }
2746
2747                 /* Fill in tunneling parameters if necessary */
2748                 cd_tunneling_params = 0;
2749                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2750                         ice_parse_tunneling_params(ol_flags, tx_offload,
2751                                                    &cd_tunneling_params);
2752
2753                 /* Enable checksum offloading */
2754                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2755                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2756                                                 &td_offset, tx_offload);
2757
2758                 if (nb_ctx) {
2759                         /* Setup TX context descriptor if required */
2760                         volatile struct ice_tx_ctx_desc *ctx_txd =
2761                                 (volatile struct ice_tx_ctx_desc *)
2762                                         &tx_ring[tx_id];
2763                         uint16_t cd_l2tag2 = 0;
2764                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2765
2766                         txn = &sw_ring[txe->next_id];
2767                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2768                         if (txe->mbuf) {
2769                                 rte_pktmbuf_free_seg(txe->mbuf);
2770                                 txe->mbuf = NULL;
2771                         }
2772
2773                         if (ol_flags & PKT_TX_TCP_SEG)
2774                                 cd_type_cmd_tso_mss |=
2775                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2776                         else if (ol_flags & PKT_TX_IEEE1588_TMST)
2777                                 cd_type_cmd_tso_mss |=
2778                                         ((uint64_t)ICE_TX_CTX_DESC_TSYN <<
2779                                         ICE_TXD_CTX_QW1_CMD_S);
2780
2781                         ctx_txd->tunneling_params =
2782                                 rte_cpu_to_le_32(cd_tunneling_params);
2783
2784                         /* TX context descriptor based double VLAN insert */
2785                         if (ol_flags & PKT_TX_QINQ) {
2786                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2787                                 cd_type_cmd_tso_mss |=
2788                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2789                                          ICE_TXD_CTX_QW1_CMD_S);
2790                         }
2791                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2792                         ctx_txd->qw1 =
2793                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2794
2795                         txe->last_id = tx_last;
2796                         tx_id = txe->next_id;
2797                         txe = txn;
2798                 }
2799                 m_seg = tx_pkt;
2800
2801                 do {
2802                         txd = &tx_ring[tx_id];
2803                         txn = &sw_ring[txe->next_id];
2804
2805                         if (txe->mbuf)
2806                                 rte_pktmbuf_free_seg(txe->mbuf);
2807                         txe->mbuf = m_seg;
2808
2809                         /* Setup TX Descriptor */
2810                         slen = m_seg->data_len;
2811                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2812
2813                         while ((ol_flags & PKT_TX_TCP_SEG) &&
2814                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2815                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2816                                 txd->cmd_type_offset_bsz =
2817                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2818                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2819                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2820                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2821                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2822                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2823
2824                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2825                                 slen -= ICE_MAX_DATA_PER_TXD;
2826
2827                                 txe->last_id = tx_last;
2828                                 tx_id = txe->next_id;
2829                                 txe = txn;
2830                                 txd = &tx_ring[tx_id];
2831                                 txn = &sw_ring[txe->next_id];
2832                         }
2833
2834                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2835                         txd->cmd_type_offset_bsz =
2836                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2837                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2838                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2839                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2840                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2841
2842                         txe->last_id = tx_last;
2843                         tx_id = txe->next_id;
2844                         txe = txn;
2845                         m_seg = m_seg->next;
2846                 } while (m_seg);
2847
2848                 /* fill the last descriptor with End of Packet (EOP) bit */
2849                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2850                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2851                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2852
2853                 /* set RS bit on the last descriptor of one packet */
2854                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2855                         PMD_TX_LOG(DEBUG,
2856                                    "Setting RS bit on TXD id="
2857                                    "%4u (port=%d queue=%d)",
2858                                    tx_last, txq->port_id, txq->queue_id);
2859
2860                         td_cmd |= ICE_TX_DESC_CMD_RS;
2861
2862                         /* Update txq RS bit counters */
2863                         txq->nb_tx_used = 0;
2864                 }
2865                 txd->cmd_type_offset_bsz |=
2866                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2867                                          ICE_TXD_QW1_CMD_S);
2868         }
2869 end_of_tx:
2870         /* update Tail register */
2871         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2872         txq->tx_tail = tx_id;
2873
2874         return nb_tx;
2875 }
2876
2877 static __rte_always_inline int
2878 ice_tx_free_bufs(struct ice_tx_queue *txq)
2879 {
2880         struct ice_tx_entry *txep;
2881         uint16_t i;
2882
2883         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2884              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2885             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2886                 return 0;
2887
2888         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2889
2890         for (i = 0; i < txq->tx_rs_thresh; i++)
2891                 rte_prefetch0((txep + i)->mbuf);
2892
2893         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2894                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2895                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2896                         txep->mbuf = NULL;
2897                 }
2898         } else {
2899                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2900                         rte_pktmbuf_free_seg(txep->mbuf);
2901                         txep->mbuf = NULL;
2902                 }
2903         }
2904
2905         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2906         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2907         if (txq->tx_next_dd >= txq->nb_tx_desc)
2908                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2909
2910         return txq->tx_rs_thresh;
2911 }
2912
2913 static int
2914 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2915                         uint32_t free_cnt)
2916 {
2917         struct ice_tx_entry *swr_ring = txq->sw_ring;
2918         uint16_t i, tx_last, tx_id;
2919         uint16_t nb_tx_free_last;
2920         uint16_t nb_tx_to_clean;
2921         uint32_t pkt_cnt;
2922
2923         /* Start free mbuf from the next of tx_tail */
2924         tx_last = txq->tx_tail;
2925         tx_id  = swr_ring[tx_last].next_id;
2926
2927         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2928                 return 0;
2929
2930         nb_tx_to_clean = txq->nb_tx_free;
2931         nb_tx_free_last = txq->nb_tx_free;
2932         if (!free_cnt)
2933                 free_cnt = txq->nb_tx_desc;
2934
2935         /* Loop through swr_ring to count the amount of
2936          * freeable mubfs and packets.
2937          */
2938         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2939                 for (i = 0; i < nb_tx_to_clean &&
2940                         pkt_cnt < free_cnt &&
2941                         tx_id != tx_last; i++) {
2942                         if (swr_ring[tx_id].mbuf != NULL) {
2943                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2944                                 swr_ring[tx_id].mbuf = NULL;
2945
2946                                 /*
2947                                  * last segment in the packet,
2948                                  * increment packet count
2949                                  */
2950                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2951                         }
2952
2953                         tx_id = swr_ring[tx_id].next_id;
2954                 }
2955
2956                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2957                         txq->nb_tx_free || tx_id == tx_last)
2958                         break;
2959
2960                 if (pkt_cnt < free_cnt) {
2961                         if (ice_xmit_cleanup(txq))
2962                                 break;
2963
2964                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2965                         nb_tx_free_last = txq->nb_tx_free;
2966                 }
2967         }
2968
2969         return (int)pkt_cnt;
2970 }
2971
2972 #ifdef RTE_ARCH_X86
2973 static int
2974 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2975                         uint32_t free_cnt __rte_unused)
2976 {
2977         return -ENOTSUP;
2978 }
2979 #endif
2980
2981 static int
2982 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2983                         uint32_t free_cnt)
2984 {
2985         int i, n, cnt;
2986
2987         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2988                 free_cnt = txq->nb_tx_desc;
2989
2990         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2991
2992         for (i = 0; i < cnt; i += n) {
2993                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2994                         break;
2995
2996                 n = ice_tx_free_bufs(txq);
2997
2998                 if (n == 0)
2999                         break;
3000         }
3001
3002         return i;
3003 }
3004
3005 int
3006 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
3007 {
3008         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
3009         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
3010         struct ice_adapter *ad =
3011                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3012
3013 #ifdef RTE_ARCH_X86
3014         if (ad->tx_vec_allowed)
3015                 return ice_tx_done_cleanup_vec(q, free_cnt);
3016 #endif
3017         if (ad->tx_simple_allowed)
3018                 return ice_tx_done_cleanup_simple(q, free_cnt);
3019         else
3020                 return ice_tx_done_cleanup_full(q, free_cnt);
3021 }
3022
3023 /* Populate 4 descriptors with data from 4 mbufs */
3024 static inline void
3025 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3026 {
3027         uint64_t dma_addr;
3028         uint32_t i;
3029
3030         for (i = 0; i < 4; i++, txdp++, pkts++) {
3031                 dma_addr = rte_mbuf_data_iova(*pkts);
3032                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3033                 txdp->cmd_type_offset_bsz =
3034                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3035                                        (*pkts)->data_len, 0);
3036         }
3037 }
3038
3039 /* Populate 1 descriptor with data from 1 mbuf */
3040 static inline void
3041 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3042 {
3043         uint64_t dma_addr;
3044
3045         dma_addr = rte_mbuf_data_iova(*pkts);
3046         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3047         txdp->cmd_type_offset_bsz =
3048                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3049                                (*pkts)->data_len, 0);
3050 }
3051
3052 static inline void
3053 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
3054                     uint16_t nb_pkts)
3055 {
3056         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
3057         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
3058         const int N_PER_LOOP = 4;
3059         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
3060         int mainpart, leftover;
3061         int i, j;
3062
3063         /**
3064          * Process most of the packets in chunks of N pkts.  Any
3065          * leftover packets will get processed one at a time.
3066          */
3067         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
3068         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
3069         for (i = 0; i < mainpart; i += N_PER_LOOP) {
3070                 /* Copy N mbuf pointers to the S/W ring */
3071                 for (j = 0; j < N_PER_LOOP; ++j)
3072                         (txep + i + j)->mbuf = *(pkts + i + j);
3073                 tx4(txdp + i, pkts + i);
3074         }
3075
3076         if (unlikely(leftover > 0)) {
3077                 for (i = 0; i < leftover; ++i) {
3078                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
3079                         tx1(txdp + mainpart + i, pkts + mainpart + i);
3080                 }
3081         }
3082 }
3083
3084 static inline uint16_t
3085 tx_xmit_pkts(struct ice_tx_queue *txq,
3086              struct rte_mbuf **tx_pkts,
3087              uint16_t nb_pkts)
3088 {
3089         volatile struct ice_tx_desc *txr = txq->tx_ring;
3090         uint16_t n = 0;
3091
3092         /**
3093          * Begin scanning the H/W ring for done descriptors when the number
3094          * of available descriptors drops below tx_free_thresh. For each done
3095          * descriptor, free the associated buffer.
3096          */
3097         if (txq->nb_tx_free < txq->tx_free_thresh)
3098                 ice_tx_free_bufs(txq);
3099
3100         /* Use available descriptor only */
3101         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
3102         if (unlikely(!nb_pkts))
3103                 return 0;
3104
3105         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
3106         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
3107                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
3108                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
3109                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3110                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3111                                          ICE_TXD_QW1_CMD_S);
3112                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3113                 txq->tx_tail = 0;
3114         }
3115
3116         /* Fill hardware descriptor ring with mbuf data */
3117         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3118         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3119
3120         /* Determin if RS bit needs to be set */
3121         if (txq->tx_tail > txq->tx_next_rs) {
3122                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3123                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3124                                          ICE_TXD_QW1_CMD_S);
3125                 txq->tx_next_rs =
3126                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3127                 if (txq->tx_next_rs >= txq->nb_tx_desc)
3128                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3129         }
3130
3131         if (txq->tx_tail >= txq->nb_tx_desc)
3132                 txq->tx_tail = 0;
3133
3134         /* Update the tx tail register */
3135         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3136
3137         return nb_pkts;
3138 }
3139
3140 static uint16_t
3141 ice_xmit_pkts_simple(void *tx_queue,
3142                      struct rte_mbuf **tx_pkts,
3143                      uint16_t nb_pkts)
3144 {
3145         uint16_t nb_tx = 0;
3146
3147         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3148                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3149                                     tx_pkts, nb_pkts);
3150
3151         while (nb_pkts) {
3152                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3153                                                       ICE_TX_MAX_BURST);
3154
3155                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3156                                    &tx_pkts[nb_tx], num);
3157                 nb_tx = (uint16_t)(nb_tx + ret);
3158                 nb_pkts = (uint16_t)(nb_pkts - ret);
3159                 if (ret < num)
3160                         break;
3161         }
3162
3163         return nb_tx;
3164 }
3165
3166 void __rte_cold
3167 ice_set_rx_function(struct rte_eth_dev *dev)
3168 {
3169         PMD_INIT_FUNC_TRACE();
3170         struct ice_adapter *ad =
3171                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3172 #ifdef RTE_ARCH_X86
3173         struct ice_rx_queue *rxq;
3174         int i;
3175         int rx_check_ret = -1;
3176
3177         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3178                 ad->rx_use_avx512 = false;
3179                 ad->rx_use_avx2 = false;
3180                 rx_check_ret = ice_rx_vec_dev_check(dev);
3181                 if (ad->ptp_ena)
3182                         rx_check_ret = -1;
3183                 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3184                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3185                         ad->rx_vec_allowed = true;
3186                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3187                                 rxq = dev->data->rx_queues[i];
3188                                 if (rxq && ice_rxq_vec_setup(rxq)) {
3189                                         ad->rx_vec_allowed = false;
3190                                         break;
3191                                 }
3192                         }
3193
3194                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3195                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3196                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3197 #ifdef CC_AVX512_SUPPORT
3198                                 ad->rx_use_avx512 = true;
3199 #else
3200                         PMD_DRV_LOG(NOTICE,
3201                                 "AVX512 is not supported in build env");
3202 #endif
3203                         if (!ad->rx_use_avx512 &&
3204                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3205                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3206                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3207                                 ad->rx_use_avx2 = true;
3208
3209                 } else {
3210                         ad->rx_vec_allowed = false;
3211                 }
3212         }
3213
3214         if (ad->rx_vec_allowed) {
3215                 if (dev->data->scattered_rx) {
3216                         if (ad->rx_use_avx512) {
3217 #ifdef CC_AVX512_SUPPORT
3218                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3219                                         PMD_DRV_LOG(NOTICE,
3220                                                 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3221                                                 dev->data->port_id);
3222                                         dev->rx_pkt_burst =
3223                                                 ice_recv_scattered_pkts_vec_avx512_offload;
3224                                 } else {
3225                                         PMD_DRV_LOG(NOTICE,
3226                                                 "Using AVX512 Vector Scattered Rx (port %d).",
3227                                                 dev->data->port_id);
3228                                         dev->rx_pkt_burst =
3229                                                 ice_recv_scattered_pkts_vec_avx512;
3230                                 }
3231 #endif
3232                         } else if (ad->rx_use_avx2) {
3233                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3234                                         PMD_DRV_LOG(NOTICE,
3235                                                     "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3236                                                     dev->data->port_id);
3237                                         dev->rx_pkt_burst =
3238                                                 ice_recv_scattered_pkts_vec_avx2_offload;
3239                                 } else {
3240                                         PMD_DRV_LOG(NOTICE,
3241                                                     "Using AVX2 Vector Scattered Rx (port %d).",
3242                                                     dev->data->port_id);
3243                                         dev->rx_pkt_burst =
3244                                                 ice_recv_scattered_pkts_vec_avx2;
3245                                 }
3246                         } else {
3247                                 PMD_DRV_LOG(DEBUG,
3248                                         "Using Vector Scattered Rx (port %d).",
3249                                         dev->data->port_id);
3250                                 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3251                         }
3252                 } else {
3253                         if (ad->rx_use_avx512) {
3254 #ifdef CC_AVX512_SUPPORT
3255                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3256                                         PMD_DRV_LOG(NOTICE,
3257                                                 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3258                                                 dev->data->port_id);
3259                                         dev->rx_pkt_burst =
3260                                                 ice_recv_pkts_vec_avx512_offload;
3261                                 } else {
3262                                         PMD_DRV_LOG(NOTICE,
3263                                                 "Using AVX512 Vector Rx (port %d).",
3264                                                 dev->data->port_id);
3265                                         dev->rx_pkt_burst =
3266                                                 ice_recv_pkts_vec_avx512;
3267                                 }
3268 #endif
3269                         } else if (ad->rx_use_avx2) {
3270                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3271                                         PMD_DRV_LOG(NOTICE,
3272                                                     "Using AVX2 OFFLOAD Vector Rx (port %d).",
3273                                                     dev->data->port_id);
3274                                         dev->rx_pkt_burst =
3275                                                 ice_recv_pkts_vec_avx2_offload;
3276                                 } else {
3277                                         PMD_DRV_LOG(NOTICE,
3278                                                     "Using AVX2 Vector Rx (port %d).",
3279                                                     dev->data->port_id);
3280                                         dev->rx_pkt_burst =
3281                                                 ice_recv_pkts_vec_avx2;
3282                                 }
3283                         } else {
3284                                 PMD_DRV_LOG(DEBUG,
3285                                         "Using Vector Rx (port %d).",
3286                                         dev->data->port_id);
3287                                 dev->rx_pkt_burst = ice_recv_pkts_vec;
3288                         }
3289                 }
3290                 return;
3291         }
3292
3293 #endif
3294
3295         if (dev->data->scattered_rx) {
3296                 /* Set the non-LRO scattered function */
3297                 PMD_INIT_LOG(DEBUG,
3298                              "Using a Scattered function on port %d.",
3299                              dev->data->port_id);
3300                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3301         } else if (ad->rx_bulk_alloc_allowed) {
3302                 PMD_INIT_LOG(DEBUG,
3303                              "Rx Burst Bulk Alloc Preconditions are "
3304                              "satisfied. Rx Burst Bulk Alloc function "
3305                              "will be used on port %d.",
3306                              dev->data->port_id);
3307                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3308         } else {
3309                 PMD_INIT_LOG(DEBUG,
3310                              "Rx Burst Bulk Alloc Preconditions are not "
3311                              "satisfied, Normal Rx will be used on port %d.",
3312                              dev->data->port_id);
3313                 dev->rx_pkt_burst = ice_recv_pkts;
3314         }
3315 }
3316
3317 static const struct {
3318         eth_rx_burst_t pkt_burst;
3319         const char *info;
3320 } ice_rx_burst_infos[] = {
3321         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3322         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3323         { ice_recv_pkts,                    "Scalar" },
3324 #ifdef RTE_ARCH_X86
3325 #ifdef CC_AVX512_SUPPORT
3326         { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3327         { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3328         { ice_recv_pkts_vec_avx512,           "Vector AVX512" },
3329         { ice_recv_pkts_vec_avx512_offload,   "Offload Vector AVX512" },
3330 #endif
3331         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3332         { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3333         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3334         { ice_recv_pkts_vec_avx2_offload,   "Offload Vector AVX2" },
3335         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3336         { ice_recv_pkts_vec,                "Vector SSE" },
3337 #endif
3338 };
3339
3340 int
3341 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3342                       struct rte_eth_burst_mode *mode)
3343 {
3344         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3345         int ret = -EINVAL;
3346         unsigned int i;
3347
3348         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3349                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3350                         snprintf(mode->info, sizeof(mode->info), "%s",
3351                                  ice_rx_burst_infos[i].info);
3352                         ret = 0;
3353                         break;
3354                 }
3355         }
3356
3357         return ret;
3358 }
3359
3360 void __rte_cold
3361 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3362 {
3363         struct ice_adapter *ad =
3364                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3365
3366         /* Use a simple Tx queue if possible (only fast free is allowed) */
3367         ad->tx_simple_allowed =
3368                 (txq->offloads ==
3369                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3370                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3371
3372         if (ad->tx_simple_allowed)
3373                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3374                              txq->queue_id);
3375         else
3376                 PMD_INIT_LOG(DEBUG,
3377                              "Simple Tx can NOT be enabled on Tx queue %u.",
3378                              txq->queue_id);
3379 }
3380
3381 /*********************************************************************
3382  *
3383  *  TX prep functions
3384  *
3385  **********************************************************************/
3386 /* The default values of TSO MSS */
3387 #define ICE_MIN_TSO_MSS            64
3388 #define ICE_MAX_TSO_MSS            9728
3389 #define ICE_MAX_TSO_FRAME_SIZE     262144
3390 uint16_t
3391 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3392               uint16_t nb_pkts)
3393 {
3394         int i, ret;
3395         uint64_t ol_flags;
3396         struct rte_mbuf *m;
3397
3398         for (i = 0; i < nb_pkts; i++) {
3399                 m = tx_pkts[i];
3400                 ol_flags = m->ol_flags;
3401
3402                 if (ol_flags & PKT_TX_TCP_SEG &&
3403                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3404                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3405                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3406                         /**
3407                          * MSS outside the range are considered malicious
3408                          */
3409                         rte_errno = EINVAL;
3410                         return i;
3411                 }
3412
3413 #ifdef RTE_ETHDEV_DEBUG_TX
3414                 ret = rte_validate_tx_offload(m);
3415                 if (ret != 0) {
3416                         rte_errno = -ret;
3417                         return i;
3418                 }
3419 #endif
3420                 ret = rte_net_intel_cksum_prepare(m);
3421                 if (ret != 0) {
3422                         rte_errno = -ret;
3423                         return i;
3424                 }
3425         }
3426         return i;
3427 }
3428
3429 void __rte_cold
3430 ice_set_tx_function(struct rte_eth_dev *dev)
3431 {
3432         struct ice_adapter *ad =
3433                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3434 #ifdef RTE_ARCH_X86
3435         struct ice_tx_queue *txq;
3436         int i;
3437         int tx_check_ret = -1;
3438
3439         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3440                 ad->tx_use_avx2 = false;
3441                 ad->tx_use_avx512 = false;
3442                 tx_check_ret = ice_tx_vec_dev_check(dev);
3443                 if (tx_check_ret >= 0 &&
3444                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3445                         ad->tx_vec_allowed = true;
3446
3447                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3448                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3449                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3450 #ifdef CC_AVX512_SUPPORT
3451                                 ad->tx_use_avx512 = true;
3452 #else
3453                         PMD_DRV_LOG(NOTICE,
3454                                 "AVX512 is not supported in build env");
3455 #endif
3456                         if (!ad->tx_use_avx512 &&
3457                                 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3458                                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3459                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3460                                 ad->tx_use_avx2 = true;
3461
3462                         if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3463                                 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3464                                 ad->tx_vec_allowed = false;
3465
3466                         if (ad->tx_vec_allowed) {
3467                                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3468                                         txq = dev->data->tx_queues[i];
3469                                         if (txq && ice_txq_vec_setup(txq)) {
3470                                                 ad->tx_vec_allowed = false;
3471                                                 break;
3472                                         }
3473                                 }
3474                         }
3475                 } else {
3476                         ad->tx_vec_allowed = false;
3477                 }
3478         }
3479
3480         if (ad->tx_vec_allowed) {
3481                 dev->tx_pkt_prepare = NULL;
3482                 if (ad->tx_use_avx512) {
3483 #ifdef CC_AVX512_SUPPORT
3484                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3485                                 PMD_DRV_LOG(NOTICE,
3486                                             "Using AVX512 OFFLOAD Vector Tx (port %d).",
3487                                             dev->data->port_id);
3488                                 dev->tx_pkt_burst =
3489                                         ice_xmit_pkts_vec_avx512_offload;
3490                                 dev->tx_pkt_prepare = ice_prep_pkts;
3491                         } else {
3492                                 PMD_DRV_LOG(NOTICE,
3493                                             "Using AVX512 Vector Tx (port %d).",
3494                                             dev->data->port_id);
3495                                 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3496                         }
3497 #endif
3498                 } else {
3499                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3500                                 PMD_DRV_LOG(NOTICE,
3501                                             "Using AVX2 OFFLOAD Vector Tx (port %d).",
3502                                             dev->data->port_id);
3503                                 dev->tx_pkt_burst =
3504                                         ice_xmit_pkts_vec_avx2_offload;
3505                                 dev->tx_pkt_prepare = ice_prep_pkts;
3506                         } else {
3507                                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3508                                             ad->tx_use_avx2 ? "avx2 " : "",
3509                                             dev->data->port_id);
3510                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3511                                                     ice_xmit_pkts_vec_avx2 :
3512                                                     ice_xmit_pkts_vec;
3513                         }
3514                 }
3515
3516                 return;
3517         }
3518 #endif
3519
3520         if (ad->tx_simple_allowed) {
3521                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3522                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3523                 dev->tx_pkt_prepare = NULL;
3524         } else {
3525                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3526                 dev->tx_pkt_burst = ice_xmit_pkts;
3527                 dev->tx_pkt_prepare = ice_prep_pkts;
3528         }
3529 }
3530
3531 static const struct {
3532         eth_tx_burst_t pkt_burst;
3533         const char *info;
3534 } ice_tx_burst_infos[] = {
3535         { ice_xmit_pkts_simple,   "Scalar Simple" },
3536         { ice_xmit_pkts,          "Scalar" },
3537 #ifdef RTE_ARCH_X86
3538 #ifdef CC_AVX512_SUPPORT
3539         { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3540         { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3541 #endif
3542         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3543         { ice_xmit_pkts_vec,      "Vector SSE" },
3544 #endif
3545 };
3546
3547 int
3548 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3549                       struct rte_eth_burst_mode *mode)
3550 {
3551         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3552         int ret = -EINVAL;
3553         unsigned int i;
3554
3555         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3556                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3557                         snprintf(mode->info, sizeof(mode->info), "%s",
3558                                  ice_tx_burst_infos[i].info);
3559                         ret = 0;
3560                         break;
3561                 }
3562         }
3563
3564         return ret;
3565 }
3566
3567 /* For each value it means, datasheet of hardware can tell more details
3568  *
3569  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3570  */
3571 static inline uint32_t
3572 ice_get_default_pkt_type(uint16_t ptype)
3573 {
3574         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3575                 __rte_cache_aligned = {
3576                 /* L2 types */
3577                 /* [0] reserved */
3578                 [1] = RTE_PTYPE_L2_ETHER,
3579                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3580                 /* [3] - [5] reserved */
3581                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3582                 /* [7] - [10] reserved */
3583                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3584                 /* [12] - [21] reserved */
3585
3586                 /* Non tunneled IPv4 */
3587                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3588                        RTE_PTYPE_L4_FRAG,
3589                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3590                        RTE_PTYPE_L4_NONFRAG,
3591                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3592                        RTE_PTYPE_L4_UDP,
3593                 /* [25] reserved */
3594                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3595                        RTE_PTYPE_L4_TCP,
3596                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3597                        RTE_PTYPE_L4_SCTP,
3598                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3599                        RTE_PTYPE_L4_ICMP,
3600
3601                 /* IPv4 --> IPv4 */
3602                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3603                        RTE_PTYPE_TUNNEL_IP |
3604                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3605                        RTE_PTYPE_INNER_L4_FRAG,
3606                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3607                        RTE_PTYPE_TUNNEL_IP |
3608                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3609                        RTE_PTYPE_INNER_L4_NONFRAG,
3610                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3611                        RTE_PTYPE_TUNNEL_IP |
3612                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3613                        RTE_PTYPE_INNER_L4_UDP,
3614                 /* [32] reserved */
3615                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3616                        RTE_PTYPE_TUNNEL_IP |
3617                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3618                        RTE_PTYPE_INNER_L4_TCP,
3619                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3620                        RTE_PTYPE_TUNNEL_IP |
3621                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3622                        RTE_PTYPE_INNER_L4_SCTP,
3623                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3624                        RTE_PTYPE_TUNNEL_IP |
3625                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3626                        RTE_PTYPE_INNER_L4_ICMP,
3627
3628                 /* IPv4 --> IPv6 */
3629                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3630                        RTE_PTYPE_TUNNEL_IP |
3631                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3632                        RTE_PTYPE_INNER_L4_FRAG,
3633                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3634                        RTE_PTYPE_TUNNEL_IP |
3635                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3636                        RTE_PTYPE_INNER_L4_NONFRAG,
3637                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3638                        RTE_PTYPE_TUNNEL_IP |
3639                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3640                        RTE_PTYPE_INNER_L4_UDP,
3641                 /* [39] reserved */
3642                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3643                        RTE_PTYPE_TUNNEL_IP |
3644                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3645                        RTE_PTYPE_INNER_L4_TCP,
3646                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3647                        RTE_PTYPE_TUNNEL_IP |
3648                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3649                        RTE_PTYPE_INNER_L4_SCTP,
3650                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3651                        RTE_PTYPE_TUNNEL_IP |
3652                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3653                        RTE_PTYPE_INNER_L4_ICMP,
3654
3655                 /* IPv4 --> GRE/Teredo/VXLAN */
3656                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3657                        RTE_PTYPE_TUNNEL_GRENAT,
3658
3659                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3660                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3661                        RTE_PTYPE_TUNNEL_GRENAT |
3662                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3663                        RTE_PTYPE_INNER_L4_FRAG,
3664                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3665                        RTE_PTYPE_TUNNEL_GRENAT |
3666                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3667                        RTE_PTYPE_INNER_L4_NONFRAG,
3668                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3669                        RTE_PTYPE_TUNNEL_GRENAT |
3670                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3671                        RTE_PTYPE_INNER_L4_UDP,
3672                 /* [47] reserved */
3673                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3674                        RTE_PTYPE_TUNNEL_GRENAT |
3675                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3676                        RTE_PTYPE_INNER_L4_TCP,
3677                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3678                        RTE_PTYPE_TUNNEL_GRENAT |
3679                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3680                        RTE_PTYPE_INNER_L4_SCTP,
3681                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3682                        RTE_PTYPE_TUNNEL_GRENAT |
3683                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3684                        RTE_PTYPE_INNER_L4_ICMP,
3685
3686                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3687                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3688                        RTE_PTYPE_TUNNEL_GRENAT |
3689                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3690                        RTE_PTYPE_INNER_L4_FRAG,
3691                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3692                        RTE_PTYPE_TUNNEL_GRENAT |
3693                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3694                        RTE_PTYPE_INNER_L4_NONFRAG,
3695                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3696                        RTE_PTYPE_TUNNEL_GRENAT |
3697                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3698                        RTE_PTYPE_INNER_L4_UDP,
3699                 /* [54] reserved */
3700                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3701                        RTE_PTYPE_TUNNEL_GRENAT |
3702                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3703                        RTE_PTYPE_INNER_L4_TCP,
3704                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3705                        RTE_PTYPE_TUNNEL_GRENAT |
3706                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3707                        RTE_PTYPE_INNER_L4_SCTP,
3708                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3709                        RTE_PTYPE_TUNNEL_GRENAT |
3710                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3711                        RTE_PTYPE_INNER_L4_ICMP,
3712
3713                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3714                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3715                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3716
3717                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3718                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3719                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3720                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3721                        RTE_PTYPE_INNER_L4_FRAG,
3722                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3723                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3724                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3725                        RTE_PTYPE_INNER_L4_NONFRAG,
3726                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3727                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3728                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3729                        RTE_PTYPE_INNER_L4_UDP,
3730                 /* [62] reserved */
3731                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3732                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3733                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3734                        RTE_PTYPE_INNER_L4_TCP,
3735                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3736                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3737                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3738                        RTE_PTYPE_INNER_L4_SCTP,
3739                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3740                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3741                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3742                        RTE_PTYPE_INNER_L4_ICMP,
3743
3744                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3745                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3746                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3747                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3748                        RTE_PTYPE_INNER_L4_FRAG,
3749                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3750                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3751                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3752                        RTE_PTYPE_INNER_L4_NONFRAG,
3753                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3754                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3755                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3756                        RTE_PTYPE_INNER_L4_UDP,
3757                 /* [69] reserved */
3758                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3759                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3760                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3761                        RTE_PTYPE_INNER_L4_TCP,
3762                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3763                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3764                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3765                        RTE_PTYPE_INNER_L4_SCTP,
3766                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3767                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3768                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3769                        RTE_PTYPE_INNER_L4_ICMP,
3770                 /* [73] - [87] reserved */
3771
3772                 /* Non tunneled IPv6 */
3773                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3774                        RTE_PTYPE_L4_FRAG,
3775                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3776                        RTE_PTYPE_L4_NONFRAG,
3777                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3778                        RTE_PTYPE_L4_UDP,
3779                 /* [91] reserved */
3780                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3781                        RTE_PTYPE_L4_TCP,
3782                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3783                        RTE_PTYPE_L4_SCTP,
3784                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3785                        RTE_PTYPE_L4_ICMP,
3786
3787                 /* IPv6 --> IPv4 */
3788                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3789                        RTE_PTYPE_TUNNEL_IP |
3790                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3791                        RTE_PTYPE_INNER_L4_FRAG,
3792                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3793                        RTE_PTYPE_TUNNEL_IP |
3794                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3795                        RTE_PTYPE_INNER_L4_NONFRAG,
3796                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3797                        RTE_PTYPE_TUNNEL_IP |
3798                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3799                        RTE_PTYPE_INNER_L4_UDP,
3800                 /* [98] reserved */
3801                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3802                        RTE_PTYPE_TUNNEL_IP |
3803                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3804                        RTE_PTYPE_INNER_L4_TCP,
3805                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3806                         RTE_PTYPE_TUNNEL_IP |
3807                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3808                         RTE_PTYPE_INNER_L4_SCTP,
3809                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3810                         RTE_PTYPE_TUNNEL_IP |
3811                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3812                         RTE_PTYPE_INNER_L4_ICMP,
3813
3814                 /* IPv6 --> IPv6 */
3815                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3816                         RTE_PTYPE_TUNNEL_IP |
3817                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3818                         RTE_PTYPE_INNER_L4_FRAG,
3819                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3820                         RTE_PTYPE_TUNNEL_IP |
3821                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3822                         RTE_PTYPE_INNER_L4_NONFRAG,
3823                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3824                         RTE_PTYPE_TUNNEL_IP |
3825                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3826                         RTE_PTYPE_INNER_L4_UDP,
3827                 /* [105] reserved */
3828                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3829                         RTE_PTYPE_TUNNEL_IP |
3830                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3831                         RTE_PTYPE_INNER_L4_TCP,
3832                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3833                         RTE_PTYPE_TUNNEL_IP |
3834                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3835                         RTE_PTYPE_INNER_L4_SCTP,
3836                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3837                         RTE_PTYPE_TUNNEL_IP |
3838                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3839                         RTE_PTYPE_INNER_L4_ICMP,
3840
3841                 /* IPv6 --> GRE/Teredo/VXLAN */
3842                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3843                         RTE_PTYPE_TUNNEL_GRENAT,
3844
3845                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3846                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3847                         RTE_PTYPE_TUNNEL_GRENAT |
3848                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3849                         RTE_PTYPE_INNER_L4_FRAG,
3850                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3851                         RTE_PTYPE_TUNNEL_GRENAT |
3852                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3853                         RTE_PTYPE_INNER_L4_NONFRAG,
3854                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3855                         RTE_PTYPE_TUNNEL_GRENAT |
3856                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3857                         RTE_PTYPE_INNER_L4_UDP,
3858                 /* [113] reserved */
3859                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3860                         RTE_PTYPE_TUNNEL_GRENAT |
3861                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3862                         RTE_PTYPE_INNER_L4_TCP,
3863                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3864                         RTE_PTYPE_TUNNEL_GRENAT |
3865                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3866                         RTE_PTYPE_INNER_L4_SCTP,
3867                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3868                         RTE_PTYPE_TUNNEL_GRENAT |
3869                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3870                         RTE_PTYPE_INNER_L4_ICMP,
3871
3872                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3873                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3874                         RTE_PTYPE_TUNNEL_GRENAT |
3875                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3876                         RTE_PTYPE_INNER_L4_FRAG,
3877                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3878                         RTE_PTYPE_TUNNEL_GRENAT |
3879                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3880                         RTE_PTYPE_INNER_L4_NONFRAG,
3881                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3882                         RTE_PTYPE_TUNNEL_GRENAT |
3883                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3884                         RTE_PTYPE_INNER_L4_UDP,
3885                 /* [120] reserved */
3886                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3887                         RTE_PTYPE_TUNNEL_GRENAT |
3888                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3889                         RTE_PTYPE_INNER_L4_TCP,
3890                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3891                         RTE_PTYPE_TUNNEL_GRENAT |
3892                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3893                         RTE_PTYPE_INNER_L4_SCTP,
3894                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3895                         RTE_PTYPE_TUNNEL_GRENAT |
3896                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3897                         RTE_PTYPE_INNER_L4_ICMP,
3898
3899                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3900                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3901                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3902
3903                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3904                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3905                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3906                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3907                         RTE_PTYPE_INNER_L4_FRAG,
3908                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3909                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3910                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3911                         RTE_PTYPE_INNER_L4_NONFRAG,
3912                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3913                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3914                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3915                         RTE_PTYPE_INNER_L4_UDP,
3916                 /* [128] reserved */
3917                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3918                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3919                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3920                         RTE_PTYPE_INNER_L4_TCP,
3921                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3922                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3923                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3924                         RTE_PTYPE_INNER_L4_SCTP,
3925                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3926                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3927                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3928                         RTE_PTYPE_INNER_L4_ICMP,
3929
3930                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3931                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3932                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3933                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3934                         RTE_PTYPE_INNER_L4_FRAG,
3935                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3936                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3937                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3938                         RTE_PTYPE_INNER_L4_NONFRAG,
3939                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3940                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3941                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3942                         RTE_PTYPE_INNER_L4_UDP,
3943                 /* [135] reserved */
3944                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3945                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3946                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3947                         RTE_PTYPE_INNER_L4_TCP,
3948                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3949                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3950                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3951                         RTE_PTYPE_INNER_L4_SCTP,
3952                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3953                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3954                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3955                         RTE_PTYPE_INNER_L4_ICMP,
3956                 /* [139] - [299] reserved */
3957
3958                 /* PPPoE */
3959                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3960                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3961
3962                 /* PPPoE --> IPv4 */
3963                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3964                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3965                         RTE_PTYPE_L4_FRAG,
3966                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3967                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3968                         RTE_PTYPE_L4_NONFRAG,
3969                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3970                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3971                         RTE_PTYPE_L4_UDP,
3972                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3973                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3974                         RTE_PTYPE_L4_TCP,
3975                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3976                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3977                         RTE_PTYPE_L4_SCTP,
3978                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3979                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3980                         RTE_PTYPE_L4_ICMP,
3981
3982                 /* PPPoE --> IPv6 */
3983                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3984                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3985                         RTE_PTYPE_L4_FRAG,
3986                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3987                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3988                         RTE_PTYPE_L4_NONFRAG,
3989                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3990                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3991                         RTE_PTYPE_L4_UDP,
3992                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3993                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3994                         RTE_PTYPE_L4_TCP,
3995                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3996                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3997                         RTE_PTYPE_L4_SCTP,
3998                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3999                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4000                         RTE_PTYPE_L4_ICMP,
4001                 /* [314] - [324] reserved */
4002
4003                 /* IPv4/IPv6 --> GTPC/GTPU */
4004                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4005                         RTE_PTYPE_TUNNEL_GTPC,
4006                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4007                         RTE_PTYPE_TUNNEL_GTPC,
4008                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4009                         RTE_PTYPE_TUNNEL_GTPC,
4010                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4011                         RTE_PTYPE_TUNNEL_GTPC,
4012                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4013                         RTE_PTYPE_TUNNEL_GTPU,
4014                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4015                         RTE_PTYPE_TUNNEL_GTPU,
4016
4017                 /* IPv4 --> GTPU --> IPv4 */
4018                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4019                         RTE_PTYPE_TUNNEL_GTPU |
4020                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4021                         RTE_PTYPE_INNER_L4_FRAG,
4022                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4023                         RTE_PTYPE_TUNNEL_GTPU |
4024                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4025                         RTE_PTYPE_INNER_L4_NONFRAG,
4026                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4027                         RTE_PTYPE_TUNNEL_GTPU |
4028                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4029                         RTE_PTYPE_INNER_L4_UDP,
4030                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4031                         RTE_PTYPE_TUNNEL_GTPU |
4032                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4033                         RTE_PTYPE_INNER_L4_TCP,
4034                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4035                         RTE_PTYPE_TUNNEL_GTPU |
4036                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4037                         RTE_PTYPE_INNER_L4_ICMP,
4038
4039                 /* IPv6 --> GTPU --> IPv4 */
4040                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4041                         RTE_PTYPE_TUNNEL_GTPU |
4042                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4043                         RTE_PTYPE_INNER_L4_FRAG,
4044                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4045                         RTE_PTYPE_TUNNEL_GTPU |
4046                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4047                         RTE_PTYPE_INNER_L4_NONFRAG,
4048                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4049                         RTE_PTYPE_TUNNEL_GTPU |
4050                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4051                         RTE_PTYPE_INNER_L4_UDP,
4052                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4053                         RTE_PTYPE_TUNNEL_GTPU |
4054                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4055                         RTE_PTYPE_INNER_L4_TCP,
4056                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4057                         RTE_PTYPE_TUNNEL_GTPU |
4058                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4059                         RTE_PTYPE_INNER_L4_ICMP,
4060
4061                 /* IPv4 --> GTPU --> IPv6 */
4062                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4063                         RTE_PTYPE_TUNNEL_GTPU |
4064                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4065                         RTE_PTYPE_INNER_L4_FRAG,
4066                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4067                         RTE_PTYPE_TUNNEL_GTPU |
4068                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4069                         RTE_PTYPE_INNER_L4_NONFRAG,
4070                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4071                         RTE_PTYPE_TUNNEL_GTPU |
4072                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4073                         RTE_PTYPE_INNER_L4_UDP,
4074                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4075                         RTE_PTYPE_TUNNEL_GTPU |
4076                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4077                         RTE_PTYPE_INNER_L4_TCP,
4078                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4079                         RTE_PTYPE_TUNNEL_GTPU |
4080                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4081                         RTE_PTYPE_INNER_L4_ICMP,
4082
4083                 /* IPv6 --> GTPU --> IPv6 */
4084                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4085                         RTE_PTYPE_TUNNEL_GTPU |
4086                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4087                         RTE_PTYPE_INNER_L4_FRAG,
4088                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4089                         RTE_PTYPE_TUNNEL_GTPU |
4090                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4091                         RTE_PTYPE_INNER_L4_NONFRAG,
4092                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4093                         RTE_PTYPE_TUNNEL_GTPU |
4094                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4095                         RTE_PTYPE_INNER_L4_UDP,
4096                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4097                         RTE_PTYPE_TUNNEL_GTPU |
4098                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4099                         RTE_PTYPE_INNER_L4_TCP,
4100                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4101                         RTE_PTYPE_TUNNEL_GTPU |
4102                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4103                         RTE_PTYPE_INNER_L4_ICMP,
4104
4105                 /* IPv4 --> UDP ECPRI */
4106                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4107                         RTE_PTYPE_L4_UDP,
4108                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4109                         RTE_PTYPE_L4_UDP,
4110                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4111                         RTE_PTYPE_L4_UDP,
4112                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4113                         RTE_PTYPE_L4_UDP,
4114                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4115                         RTE_PTYPE_L4_UDP,
4116                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4117                         RTE_PTYPE_L4_UDP,
4118                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4119                         RTE_PTYPE_L4_UDP,
4120                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4121                         RTE_PTYPE_L4_UDP,
4122                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4123                         RTE_PTYPE_L4_UDP,
4124                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4125                         RTE_PTYPE_L4_UDP,
4126
4127                 /* IPV6 --> UDP ECPRI */
4128                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4129                         RTE_PTYPE_L4_UDP,
4130                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4131                         RTE_PTYPE_L4_UDP,
4132                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4133                         RTE_PTYPE_L4_UDP,
4134                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4135                         RTE_PTYPE_L4_UDP,
4136                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4137                         RTE_PTYPE_L4_UDP,
4138                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4139                         RTE_PTYPE_L4_UDP,
4140                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4141                         RTE_PTYPE_L4_UDP,
4142                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4143                         RTE_PTYPE_L4_UDP,
4144                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4145                         RTE_PTYPE_L4_UDP,
4146                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4147                         RTE_PTYPE_L4_UDP,
4148                 /* All others reserved */
4149         };
4150
4151         return type_table[ptype];
4152 }
4153
4154 void __rte_cold
4155 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4156 {
4157         struct ice_adapter *ad =
4158                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4159         int i;
4160
4161         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4162                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4163 }
4164
4165 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4166 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4167                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4168 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4169 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4170
4171 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
4172 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
4173         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4174 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
4175 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
4176         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4177
4178 /*
4179  * check the programming status descriptor in rx queue.
4180  * done after Programming Flow Director is programmed on
4181  * tx queue
4182  */
4183 static inline int
4184 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4185 {
4186         volatile union ice_32byte_rx_desc *rxdp;
4187         uint64_t qword1;
4188         uint32_t rx_status;
4189         uint32_t error;
4190         uint32_t id;
4191         int ret = -EAGAIN;
4192
4193         rxdp = (volatile union ice_32byte_rx_desc *)
4194                 (&rxq->rx_ring[rxq->rx_tail]);
4195         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4196         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4197                         >> ICE_RXD_QW1_STATUS_S;
4198
4199         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4200                 ret = 0;
4201                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4202                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4203                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4204                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4205                 if (error) {
4206                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4207                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4208                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4209                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4210                         ret = -EINVAL;
4211                         goto err;
4212                 }
4213                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4214                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4215                 if (error) {
4216                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4217                         ret = -EINVAL;
4218                 }
4219 err:
4220                 rxdp->wb.qword1.status_error_len = 0;
4221                 rxq->rx_tail++;
4222                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4223                         rxq->rx_tail = 0;
4224                 if (rxq->rx_tail == 0)
4225                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4226                 else
4227                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4228         }
4229
4230         return ret;
4231 }
4232
4233 #define ICE_FDIR_MAX_WAIT_US 10000
4234
4235 int
4236 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4237 {
4238         struct ice_tx_queue *txq = pf->fdir.txq;
4239         struct ice_rx_queue *rxq = pf->fdir.rxq;
4240         volatile struct ice_fltr_desc *fdirdp;
4241         volatile struct ice_tx_desc *txdp;
4242         uint32_t td_cmd;
4243         uint16_t i;
4244
4245         fdirdp = (volatile struct ice_fltr_desc *)
4246                 (&txq->tx_ring[txq->tx_tail]);
4247         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4248         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4249
4250         txdp = &txq->tx_ring[txq->tx_tail + 1];
4251         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4252         td_cmd = ICE_TX_DESC_CMD_EOP |
4253                 ICE_TX_DESC_CMD_RS  |
4254                 ICE_TX_DESC_CMD_DUMMY;
4255
4256         txdp->cmd_type_offset_bsz =
4257                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4258
4259         txq->tx_tail += 2;
4260         if (txq->tx_tail >= txq->nb_tx_desc)
4261                 txq->tx_tail = 0;
4262         /* Update the tx tail register */
4263         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4264         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4265                 if ((txdp->cmd_type_offset_bsz &
4266                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4267                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4268                         break;
4269                 rte_delay_us(1);
4270         }
4271         if (i >= ICE_FDIR_MAX_WAIT_US) {
4272                 PMD_DRV_LOG(ERR,
4273                             "Failed to program FDIR filter: time out to get DD on tx queue.");
4274                 return -ETIMEDOUT;
4275         }
4276
4277         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4278                 int ret;
4279
4280                 ret = ice_check_fdir_programming_status(rxq);
4281                 if (ret == -EAGAIN)
4282                         rte_delay_us(1);
4283                 else
4284                         return ret;
4285         }
4286
4287         PMD_DRV_LOG(ERR,
4288                     "Failed to program FDIR filter: programming status reported.");
4289         return -ETIMEDOUT;
4290
4291
4292 }