1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <ethdev_driver.h>
9 #include "rte_pmd_ice.h"
11 #include "ice_rxtx_vec_common.h"
13 #define ICE_TX_CKSUM_OFFLOAD_MASK ( \
17 PKT_TX_OUTER_IP_CKSUM)
19 /* Offset of mbuf dynamic field for protocol extraction data */
20 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
22 /* Mask of mbuf dynamic flags for protocol extraction type */
23 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
26 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
27 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
28 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
31 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
33 volatile union ice_rx_flex_desc *rxdp;
34 struct ice_rx_queue *rxq = rx_queue;
38 rxdp = &rxq->rx_ring[desc];
39 /* watch for changes in status bit */
40 pmc->addr = &rxdp->wb.status_error0;
43 * we expect the DD bit to be set to 1 if this descriptor was already
46 pmc->val = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
47 pmc->mask = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
49 /* register is 16-bit */
50 pmc->size = sizeof(uint16_t);
57 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
59 static uint8_t rxdid_map[] = {
60 [PROTO_XTR_NONE] = ICE_RXDID_COMMS_OVS,
61 [PROTO_XTR_VLAN] = ICE_RXDID_COMMS_AUX_VLAN,
62 [PROTO_XTR_IPV4] = ICE_RXDID_COMMS_AUX_IPV4,
63 [PROTO_XTR_IPV6] = ICE_RXDID_COMMS_AUX_IPV6,
64 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
65 [PROTO_XTR_TCP] = ICE_RXDID_COMMS_AUX_TCP,
66 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
69 return xtr_type < RTE_DIM(rxdid_map) ?
70 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
74 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
76 volatile union ice_rx_flex_desc *rxdp)
78 volatile struct ice_32b_rx_flex_desc_comms *desc =
79 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
80 uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
82 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
83 mb->ol_flags |= PKT_RX_RSS_HASH;
84 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
87 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
88 if (desc->flow_id != 0xFFFFFFFF) {
89 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
90 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
96 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
98 volatile union ice_rx_flex_desc *rxdp)
100 volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
101 (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
102 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
106 if (desc->flow_id != 0xFFFFFFFF) {
107 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
108 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
111 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
112 stat_err = rte_le_to_cpu_16(desc->status_error0);
113 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
114 mb->ol_flags |= PKT_RX_RSS_HASH;
115 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
121 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
123 volatile union ice_rx_flex_desc *rxdp)
125 volatile struct ice_32b_rx_flex_desc_comms *desc =
126 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
129 stat_err = rte_le_to_cpu_16(desc->status_error0);
130 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
131 mb->ol_flags |= PKT_RX_RSS_HASH;
132 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
135 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
136 if (desc->flow_id != 0xFFFFFFFF) {
137 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
138 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
141 if (rxq->xtr_ol_flag) {
142 uint32_t metadata = 0;
144 stat_err = rte_le_to_cpu_16(desc->status_error1);
146 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
147 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
149 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
151 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
154 mb->ol_flags |= rxq->xtr_ol_flag;
156 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
163 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
165 volatile union ice_rx_flex_desc *rxdp)
167 volatile struct ice_32b_rx_flex_desc_comms *desc =
168 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
171 stat_err = rte_le_to_cpu_16(desc->status_error0);
172 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
173 mb->ol_flags |= PKT_RX_RSS_HASH;
174 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
177 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
178 if (desc->flow_id != 0xFFFFFFFF) {
179 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
180 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
183 if (rxq->xtr_ol_flag) {
184 uint32_t metadata = 0;
186 if (desc->flex_ts.flex.aux0 != 0xFFFF)
187 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
188 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
189 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
192 mb->ol_flags |= rxq->xtr_ol_flag;
194 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
201 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
204 case ICE_RXDID_COMMS_AUX_VLAN:
205 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
206 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
209 case ICE_RXDID_COMMS_AUX_IPV4:
210 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
211 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
214 case ICE_RXDID_COMMS_AUX_IPV6:
215 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
216 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
219 case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
220 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
221 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
224 case ICE_RXDID_COMMS_AUX_TCP:
225 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
226 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
229 case ICE_RXDID_COMMS_AUX_IP_OFFSET:
230 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
231 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v2;
234 case ICE_RXDID_COMMS_GENERIC:
235 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_generic;
238 case ICE_RXDID_COMMS_OVS:
239 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
243 /* update this according to the RXDID for PROTO_XTR_NONE */
244 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
248 if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
249 rxq->xtr_ol_flag = 0;
252 static enum ice_status
253 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
255 struct ice_vsi *vsi = rxq->vsi;
256 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
257 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
258 struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
259 struct ice_rlan_ctx rx_ctx;
262 struct rte_eth_rxmode *rxmode = &dev_data->dev_conf.rxmode;
263 uint32_t rxdid = ICE_RXDID_COMMS_OVS;
266 /* Set buffer size as the head split is disabled. */
267 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
268 RTE_PKTMBUF_HEADROOM);
270 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
271 rxq->max_pkt_len = RTE_MIN((uint32_t)
272 ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
273 dev_data->dev_conf.rxmode.max_rx_pkt_len);
275 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
276 if (rxq->max_pkt_len <= ICE_ETH_MAX_LEN ||
277 rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
278 PMD_DRV_LOG(ERR, "maximum packet length must "
279 "be larger than %u and smaller than %u,"
280 "as jumbo frame is enabled",
281 (uint32_t)ICE_ETH_MAX_LEN,
282 (uint32_t)ICE_FRAME_SIZE_MAX);
286 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
287 rxq->max_pkt_len > ICE_ETH_MAX_LEN) {
288 PMD_DRV_LOG(ERR, "maximum packet length must be "
289 "larger than %u and smaller than %u, "
290 "as jumbo frame is disabled",
291 (uint32_t)RTE_ETHER_MIN_LEN,
292 (uint32_t)ICE_ETH_MAX_LEN);
297 memset(&rx_ctx, 0, sizeof(rx_ctx));
299 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
300 rx_ctx.qlen = rxq->nb_rx_desc;
301 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
302 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
303 rx_ctx.dtype = 0; /* No Header Split mode */
304 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
305 rx_ctx.dsize = 1; /* 32B descriptors */
307 rx_ctx.rxmax = rxq->max_pkt_len;
308 /* TPH: Transaction Layer Packet (TLP) processing hints */
309 rx_ctx.tphrdesc_ena = 1;
310 rx_ctx.tphwdesc_ena = 1;
311 rx_ctx.tphdata_ena = 1;
312 rx_ctx.tphhead_ena = 1;
313 /* Low Receive Queue Threshold defined in 64 descriptors units.
314 * When the number of free descriptors goes below the lrxqthresh,
315 * an immediate interrupt is triggered.
317 rx_ctx.lrxqthresh = 2;
318 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
321 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
323 rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
325 PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
326 rxq->port_id, rxq->queue_id, rxdid);
328 if (!(pf->supported_rxdid & BIT(rxdid))) {
329 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
334 ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
336 /* Enable Flexible Descriptors in the queue context which
337 * allows this driver to select a specific receive descriptor format
339 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
340 QRXFLXP_CNTXT_RXDID_IDX_M;
342 /* increasing context priority to pick up profile ID;
343 * default is 0x01; setting to 0x03 to ensure profile
344 * is programming if prev context is of same priority
346 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
347 QRXFLXP_CNTXT_RXDID_PRIO_M;
349 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
351 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
353 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
357 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
359 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
364 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
365 RTE_PKTMBUF_HEADROOM);
367 /* Check if scattered RX needs to be used. */
368 if (rxq->max_pkt_len > buf_size)
369 dev_data->scattered_rx = 1;
371 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
373 /* Init the Rx tail register*/
374 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
379 /* Allocate mbufs for all descriptors in rx queue */
381 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
383 struct ice_rx_entry *rxe = rxq->sw_ring;
387 for (i = 0; i < rxq->nb_rx_desc; i++) {
388 volatile union ice_rx_flex_desc *rxd;
389 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
391 if (unlikely(!mbuf)) {
392 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
396 rte_mbuf_refcnt_set(mbuf, 1);
398 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
400 mbuf->port = rxq->port_id;
403 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
405 rxd = &rxq->rx_ring[i];
406 rxd->read.pkt_addr = dma_addr;
407 rxd->read.hdr_addr = 0;
408 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
418 /* Free all mbufs for descriptors in rx queue */
420 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
424 if (!rxq || !rxq->sw_ring) {
425 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
429 for (i = 0; i < rxq->nb_rx_desc; i++) {
430 if (rxq->sw_ring[i].mbuf) {
431 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
432 rxq->sw_ring[i].mbuf = NULL;
435 if (rxq->rx_nb_avail == 0)
437 for (i = 0; i < rxq->rx_nb_avail; i++)
438 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
440 rxq->rx_nb_avail = 0;
443 /* turn on or off rx queue
444 * @q_idx: queue index in pf scope
445 * @on: turn on or off the queue
448 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
453 /* QRX_CTRL = QRX_ENA */
454 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
457 if (reg & QRX_CTRL_QENA_STAT_M)
458 return 0; /* Already on, skip */
459 reg |= QRX_CTRL_QENA_REQ_M;
461 if (!(reg & QRX_CTRL_QENA_STAT_M))
462 return 0; /* Already off, skip */
463 reg &= ~QRX_CTRL_QENA_REQ_M;
466 /* Write the register */
467 ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
468 /* Check the result. It is said that QENA_STAT
469 * follows the QENA_REQ not more than 10 use.
470 * TODO: need to change the wait counter later
472 for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
473 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
474 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
476 if ((reg & QRX_CTRL_QENA_REQ_M) &&
477 (reg & QRX_CTRL_QENA_STAT_M))
480 if (!(reg & QRX_CTRL_QENA_REQ_M) &&
481 !(reg & QRX_CTRL_QENA_STAT_M))
486 /* Check if it is timeout */
487 if (j >= ICE_CHK_Q_ENA_COUNT) {
488 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
489 (on ? "enable" : "disable"), q_idx);
497 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
501 if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
502 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
503 "rxq->rx_free_thresh=%d, "
504 "ICE_RX_MAX_BURST=%d",
505 rxq->rx_free_thresh, ICE_RX_MAX_BURST);
507 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
508 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
509 "rxq->rx_free_thresh=%d, "
510 "rxq->nb_rx_desc=%d",
511 rxq->rx_free_thresh, rxq->nb_rx_desc);
513 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
514 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
515 "rxq->nb_rx_desc=%d, "
516 "rxq->rx_free_thresh=%d",
517 rxq->nb_rx_desc, rxq->rx_free_thresh);
524 /* reset fields in ice_rx_queue back to default */
526 ice_reset_rx_queue(struct ice_rx_queue *rxq)
532 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
536 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
538 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
539 ((volatile char *)rxq->rx_ring)[i] = 0;
541 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
542 for (i = 0; i < ICE_RX_MAX_BURST; ++i)
543 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
545 rxq->rx_nb_avail = 0;
546 rxq->rx_next_avail = 0;
547 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
551 rxq->pkt_first_seg = NULL;
552 rxq->pkt_last_seg = NULL;
554 rxq->rxrearm_start = 0;
559 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
561 struct ice_rx_queue *rxq;
563 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
565 PMD_INIT_FUNC_TRACE();
567 if (rx_queue_id >= dev->data->nb_rx_queues) {
568 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
569 rx_queue_id, dev->data->nb_rx_queues);
573 rxq = dev->data->rx_queues[rx_queue_id];
574 if (!rxq || !rxq->q_set) {
575 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
580 err = ice_program_hw_rx_queue(rxq);
582 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
587 err = ice_alloc_rx_queue_mbufs(rxq);
589 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
593 /* Init the RX tail register. */
594 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
596 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
598 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
601 rxq->rx_rel_mbufs(rxq);
602 ice_reset_rx_queue(rxq);
606 dev->data->rx_queue_state[rx_queue_id] =
607 RTE_ETH_QUEUE_STATE_STARTED;
613 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
615 struct ice_rx_queue *rxq;
617 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
619 if (rx_queue_id < dev->data->nb_rx_queues) {
620 rxq = dev->data->rx_queues[rx_queue_id];
622 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
624 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
628 rxq->rx_rel_mbufs(rxq);
629 ice_reset_rx_queue(rxq);
630 dev->data->rx_queue_state[rx_queue_id] =
631 RTE_ETH_QUEUE_STATE_STOPPED;
638 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
640 struct ice_tx_queue *txq;
644 struct ice_aqc_add_tx_qgrp *txq_elem;
645 struct ice_tlan_ctx tx_ctx;
648 PMD_INIT_FUNC_TRACE();
650 if (tx_queue_id >= dev->data->nb_tx_queues) {
651 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
652 tx_queue_id, dev->data->nb_tx_queues);
656 txq = dev->data->tx_queues[tx_queue_id];
657 if (!txq || !txq->q_set) {
658 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
663 buf_len = ice_struct_size(txq_elem, txqs, 1);
664 txq_elem = ice_malloc(hw, buf_len);
669 hw = ICE_VSI_TO_HW(vsi);
671 memset(&tx_ctx, 0, sizeof(tx_ctx));
672 txq_elem->num_txqs = 1;
673 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
675 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
676 tx_ctx.qlen = txq->nb_tx_desc;
677 tx_ctx.pf_num = hw->pf_id;
678 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
679 tx_ctx.src_vsi = vsi->vsi_id;
680 tx_ctx.port_num = hw->port_info->lport;
681 tx_ctx.tso_ena = 1; /* tso enable */
682 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
683 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
685 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
688 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
690 /* Init the Tx tail register*/
691 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
693 /* Fix me, we assume TC always 0 here */
694 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
695 txq_elem, buf_len, NULL);
697 PMD_DRV_LOG(ERR, "Failed to add lan txq");
701 /* store the schedule node id */
702 txq->q_teid = txq_elem->txqs[0].q_teid;
704 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
710 static enum ice_status
711 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
713 struct ice_vsi *vsi = rxq->vsi;
714 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
715 uint32_t rxdid = ICE_RXDID_LEGACY_1;
716 struct ice_rlan_ctx rx_ctx;
721 rxq->rx_buf_len = 1024;
723 memset(&rx_ctx, 0, sizeof(rx_ctx));
725 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
726 rx_ctx.qlen = rxq->nb_rx_desc;
727 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
728 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
729 rx_ctx.dtype = 0; /* No Header Split mode */
730 rx_ctx.dsize = 1; /* 32B descriptors */
731 rx_ctx.rxmax = ICE_ETH_MAX_LEN;
732 /* TPH: Transaction Layer Packet (TLP) processing hints */
733 rx_ctx.tphrdesc_ena = 1;
734 rx_ctx.tphwdesc_ena = 1;
735 rx_ctx.tphdata_ena = 1;
736 rx_ctx.tphhead_ena = 1;
737 /* Low Receive Queue Threshold defined in 64 descriptors units.
738 * When the number of free descriptors goes below the lrxqthresh,
739 * an immediate interrupt is triggered.
741 rx_ctx.lrxqthresh = 2;
742 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
745 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
747 /* Enable Flexible Descriptors in the queue context which
748 * allows this driver to select a specific receive descriptor format
750 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
751 QRXFLXP_CNTXT_RXDID_IDX_M;
753 /* increasing context priority to pick up profile ID;
754 * default is 0x01; setting to 0x03 to ensure profile
755 * is programming if prev context is of same priority
757 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
758 QRXFLXP_CNTXT_RXDID_PRIO_M;
760 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
762 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
764 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
768 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
770 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
775 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
777 /* Init the Rx tail register*/
778 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
784 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
786 struct ice_rx_queue *rxq;
788 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
789 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
791 PMD_INIT_FUNC_TRACE();
794 if (!rxq || !rxq->q_set) {
795 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
800 err = ice_fdir_program_hw_rx_queue(rxq);
802 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
807 /* Init the RX tail register. */
808 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
810 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
812 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
815 ice_reset_rx_queue(rxq);
823 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
825 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
826 struct ice_tx_queue *txq;
830 struct ice_aqc_add_tx_qgrp *txq_elem;
831 struct ice_tlan_ctx tx_ctx;
834 PMD_INIT_FUNC_TRACE();
837 if (!txq || !txq->q_set) {
838 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
843 buf_len = ice_struct_size(txq_elem, txqs, 1);
844 txq_elem = ice_malloc(hw, buf_len);
849 hw = ICE_VSI_TO_HW(vsi);
851 memset(&tx_ctx, 0, sizeof(tx_ctx));
852 txq_elem->num_txqs = 1;
853 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
855 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
856 tx_ctx.qlen = txq->nb_tx_desc;
857 tx_ctx.pf_num = hw->pf_id;
858 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
859 tx_ctx.src_vsi = vsi->vsi_id;
860 tx_ctx.port_num = hw->port_info->lport;
861 tx_ctx.tso_ena = 1; /* tso enable */
862 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
863 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
865 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
868 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
870 /* Init the Tx tail register*/
871 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
873 /* Fix me, we assume TC always 0 here */
874 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
875 txq_elem, buf_len, NULL);
877 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
881 /* store the schedule node id */
882 txq->q_teid = txq_elem->txqs[0].q_teid;
888 /* Free all mbufs for descriptors in tx queue */
890 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
894 if (!txq || !txq->sw_ring) {
895 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
899 for (i = 0; i < txq->nb_tx_desc; i++) {
900 if (txq->sw_ring[i].mbuf) {
901 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
902 txq->sw_ring[i].mbuf = NULL;
908 ice_reset_tx_queue(struct ice_tx_queue *txq)
910 struct ice_tx_entry *txe;
911 uint16_t i, prev, size;
914 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
919 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
920 for (i = 0; i < size; i++)
921 ((volatile char *)txq->tx_ring)[i] = 0;
923 prev = (uint16_t)(txq->nb_tx_desc - 1);
924 for (i = 0; i < txq->nb_tx_desc; i++) {
925 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
927 txd->cmd_type_offset_bsz =
928 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
931 txe[prev].next_id = i;
935 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
936 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
941 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
942 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
946 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
948 struct ice_tx_queue *txq;
949 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
950 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
951 struct ice_vsi *vsi = pf->main_vsi;
952 enum ice_status status;
955 uint16_t q_handle = tx_queue_id;
957 if (tx_queue_id >= dev->data->nb_tx_queues) {
958 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
959 tx_queue_id, dev->data->nb_tx_queues);
963 txq = dev->data->tx_queues[tx_queue_id];
965 PMD_DRV_LOG(ERR, "TX queue %u is not available",
970 q_ids[0] = txq->reg_idx;
971 q_teids[0] = txq->q_teid;
973 /* Fix me, we assume TC always 0 here */
974 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
975 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
976 if (status != ICE_SUCCESS) {
977 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
981 txq->tx_rel_mbufs(txq);
982 ice_reset_tx_queue(txq);
983 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
989 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
991 struct ice_rx_queue *rxq;
993 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
994 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
998 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1000 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1004 rxq->rx_rel_mbufs(rxq);
1010 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1012 struct ice_tx_queue *txq;
1013 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1014 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1015 struct ice_vsi *vsi = pf->main_vsi;
1016 enum ice_status status;
1018 uint32_t q_teids[1];
1019 uint16_t q_handle = tx_queue_id;
1023 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1029 q_ids[0] = txq->reg_idx;
1030 q_teids[0] = txq->q_teid;
1032 /* Fix me, we assume TC always 0 here */
1033 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1034 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1035 if (status != ICE_SUCCESS) {
1036 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1040 txq->tx_rel_mbufs(txq);
1046 ice_rx_queue_setup(struct rte_eth_dev *dev,
1049 unsigned int socket_id,
1050 const struct rte_eth_rxconf *rx_conf,
1051 struct rte_mempool *mp)
1053 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1054 struct ice_adapter *ad =
1055 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1056 struct ice_vsi *vsi = pf->main_vsi;
1057 struct ice_rx_queue *rxq;
1058 const struct rte_memzone *rz;
1061 int use_def_burst_func = 1;
1064 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1065 nb_desc > ICE_MAX_RING_DESC ||
1066 nb_desc < ICE_MIN_RING_DESC) {
1067 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1068 "invalid", nb_desc);
1072 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1074 /* Free memory if needed */
1075 if (dev->data->rx_queues[queue_idx]) {
1076 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1077 dev->data->rx_queues[queue_idx] = NULL;
1080 /* Allocate the rx queue data structure */
1081 rxq = rte_zmalloc_socket(NULL,
1082 sizeof(struct ice_rx_queue),
1083 RTE_CACHE_LINE_SIZE,
1086 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1087 "rx queue data structure");
1091 rxq->nb_rx_desc = nb_desc;
1092 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1093 rxq->queue_id = queue_idx;
1094 rxq->offloads = offloads;
1096 rxq->reg_idx = vsi->base_queue + queue_idx;
1097 rxq->port_id = dev->data->port_id;
1098 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1099 rxq->crc_len = RTE_ETHER_CRC_LEN;
1103 rxq->drop_en = rx_conf->rx_drop_en;
1105 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1106 rxq->proto_xtr = pf->proto_xtr != NULL ?
1107 pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1109 /* Allocate the maximun number of RX ring hardware descriptor. */
1110 len = ICE_MAX_RING_DESC;
1113 * Allocating a little more memory because vectorized/bulk_alloc Rx
1114 * functions doesn't check boundaries each time.
1116 len += ICE_RX_MAX_BURST;
1118 /* Allocate the maximum number of RX ring hardware descriptor. */
1119 ring_size = sizeof(union ice_rx_flex_desc) * len;
1120 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1121 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1122 ring_size, ICE_RING_BASE_ALIGN,
1125 ice_rx_queue_release(rxq);
1126 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1130 /* Zero all the descriptors in the ring. */
1131 memset(rz->addr, 0, ring_size);
1133 rxq->rx_ring_dma = rz->iova;
1134 rxq->rx_ring = rz->addr;
1136 /* always reserve more for bulk alloc */
1137 len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1139 /* Allocate the software ring. */
1140 rxq->sw_ring = rte_zmalloc_socket(NULL,
1141 sizeof(struct ice_rx_entry) * len,
1142 RTE_CACHE_LINE_SIZE,
1144 if (!rxq->sw_ring) {
1145 ice_rx_queue_release(rxq);
1146 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1150 ice_reset_rx_queue(rxq);
1152 dev->data->rx_queues[queue_idx] = rxq;
1153 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1155 use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1157 if (!use_def_burst_func) {
1158 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1159 "satisfied. Rx Burst Bulk Alloc function will be "
1160 "used on port=%d, queue=%d.",
1161 rxq->port_id, rxq->queue_id);
1163 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1164 "not satisfied, Scattered Rx is requested. "
1165 "on port=%d, queue=%d.",
1166 rxq->port_id, rxq->queue_id);
1167 ad->rx_bulk_alloc_allowed = false;
1174 ice_rx_queue_release(void *rxq)
1176 struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1179 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1184 rte_free(q->sw_ring);
1189 ice_tx_queue_setup(struct rte_eth_dev *dev,
1192 unsigned int socket_id,
1193 const struct rte_eth_txconf *tx_conf)
1195 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1196 struct ice_vsi *vsi = pf->main_vsi;
1197 struct ice_tx_queue *txq;
1198 const struct rte_memzone *tz;
1200 uint16_t tx_rs_thresh, tx_free_thresh;
1203 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1205 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1206 nb_desc > ICE_MAX_RING_DESC ||
1207 nb_desc < ICE_MIN_RING_DESC) {
1208 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1209 "invalid", nb_desc);
1214 * The following two parameters control the setting of the RS bit on
1215 * transmit descriptors. TX descriptors will have their RS bit set
1216 * after txq->tx_rs_thresh descriptors have been used. The TX
1217 * descriptor ring will be cleaned after txq->tx_free_thresh
1218 * descriptors are used or if the number of descriptors required to
1219 * transmit a packet is greater than the number of free TX descriptors.
1221 * The following constraints must be satisfied:
1222 * - tx_rs_thresh must be greater than 0.
1223 * - tx_rs_thresh must be less than the size of the ring minus 2.
1224 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1225 * - tx_rs_thresh must be a divisor of the ring size.
1226 * - tx_free_thresh must be greater than 0.
1227 * - tx_free_thresh must be less than the size of the ring minus 3.
1228 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1230 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1231 * race condition, hence the maximum threshold constraints. When set
1232 * to zero use default values.
1234 tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1235 tx_conf->tx_free_thresh :
1236 ICE_DEFAULT_TX_FREE_THRESH);
1237 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1239 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1240 nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1241 if (tx_conf->tx_rs_thresh)
1242 tx_rs_thresh = tx_conf->tx_rs_thresh;
1243 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1244 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1245 "exceed nb_desc. (tx_rs_thresh=%u "
1246 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1247 (unsigned int)tx_rs_thresh,
1248 (unsigned int)tx_free_thresh,
1249 (unsigned int)nb_desc,
1250 (int)dev->data->port_id,
1254 if (tx_rs_thresh >= (nb_desc - 2)) {
1255 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1256 "number of TX descriptors minus 2. "
1257 "(tx_rs_thresh=%u port=%d queue=%d)",
1258 (unsigned int)tx_rs_thresh,
1259 (int)dev->data->port_id,
1263 if (tx_free_thresh >= (nb_desc - 3)) {
1264 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1265 "tx_free_thresh must be less than the "
1266 "number of TX descriptors minus 3. "
1267 "(tx_free_thresh=%u port=%d queue=%d)",
1268 (unsigned int)tx_free_thresh,
1269 (int)dev->data->port_id,
1273 if (tx_rs_thresh > tx_free_thresh) {
1274 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1275 "equal to tx_free_thresh. (tx_free_thresh=%u"
1276 " tx_rs_thresh=%u port=%d queue=%d)",
1277 (unsigned int)tx_free_thresh,
1278 (unsigned int)tx_rs_thresh,
1279 (int)dev->data->port_id,
1283 if ((nb_desc % tx_rs_thresh) != 0) {
1284 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1285 "number of TX descriptors. (tx_rs_thresh=%u"
1286 " port=%d queue=%d)",
1287 (unsigned int)tx_rs_thresh,
1288 (int)dev->data->port_id,
1292 if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1293 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1294 "tx_rs_thresh is greater than 1. "
1295 "(tx_rs_thresh=%u port=%d queue=%d)",
1296 (unsigned int)tx_rs_thresh,
1297 (int)dev->data->port_id,
1302 /* Free memory if needed. */
1303 if (dev->data->tx_queues[queue_idx]) {
1304 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1305 dev->data->tx_queues[queue_idx] = NULL;
1308 /* Allocate the TX queue data structure. */
1309 txq = rte_zmalloc_socket(NULL,
1310 sizeof(struct ice_tx_queue),
1311 RTE_CACHE_LINE_SIZE,
1314 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1315 "tx queue structure");
1319 /* Allocate TX hardware ring descriptors. */
1320 ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1321 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1322 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1323 ring_size, ICE_RING_BASE_ALIGN,
1326 ice_tx_queue_release(txq);
1327 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1331 txq->nb_tx_desc = nb_desc;
1332 txq->tx_rs_thresh = tx_rs_thresh;
1333 txq->tx_free_thresh = tx_free_thresh;
1334 txq->pthresh = tx_conf->tx_thresh.pthresh;
1335 txq->hthresh = tx_conf->tx_thresh.hthresh;
1336 txq->wthresh = tx_conf->tx_thresh.wthresh;
1337 txq->queue_id = queue_idx;
1339 txq->reg_idx = vsi->base_queue + queue_idx;
1340 txq->port_id = dev->data->port_id;
1341 txq->offloads = offloads;
1343 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1345 txq->tx_ring_dma = tz->iova;
1346 txq->tx_ring = tz->addr;
1348 /* Allocate software ring */
1350 rte_zmalloc_socket(NULL,
1351 sizeof(struct ice_tx_entry) * nb_desc,
1352 RTE_CACHE_LINE_SIZE,
1354 if (!txq->sw_ring) {
1355 ice_tx_queue_release(txq);
1356 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1360 ice_reset_tx_queue(txq);
1362 dev->data->tx_queues[queue_idx] = txq;
1363 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1364 ice_set_tx_function_flag(dev, txq);
1370 ice_tx_queue_release(void *txq)
1372 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1375 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1380 rte_free(q->sw_ring);
1385 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1386 struct rte_eth_rxq_info *qinfo)
1388 struct ice_rx_queue *rxq;
1390 rxq = dev->data->rx_queues[queue_id];
1392 qinfo->mp = rxq->mp;
1393 qinfo->scattered_rx = dev->data->scattered_rx;
1394 qinfo->nb_desc = rxq->nb_rx_desc;
1396 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1397 qinfo->conf.rx_drop_en = rxq->drop_en;
1398 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1402 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1403 struct rte_eth_txq_info *qinfo)
1405 struct ice_tx_queue *txq;
1407 txq = dev->data->tx_queues[queue_id];
1409 qinfo->nb_desc = txq->nb_tx_desc;
1411 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1412 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1413 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1415 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1416 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1417 qinfo->conf.offloads = txq->offloads;
1418 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1422 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1424 #define ICE_RXQ_SCAN_INTERVAL 4
1425 volatile union ice_rx_flex_desc *rxdp;
1426 struct ice_rx_queue *rxq;
1429 rxq = dev->data->rx_queues[rx_queue_id];
1430 rxdp = &rxq->rx_ring[rxq->rx_tail];
1431 while ((desc < rxq->nb_rx_desc) &&
1432 rte_le_to_cpu_16(rxdp->wb.status_error0) &
1433 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1435 * Check the DD bit of a rx descriptor of each 4 in a group,
1436 * to avoid checking too frequently and downgrading performance
1439 desc += ICE_RXQ_SCAN_INTERVAL;
1440 rxdp += ICE_RXQ_SCAN_INTERVAL;
1441 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1442 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1443 desc - rxq->nb_rx_desc]);
1449 #define ICE_RX_FLEX_ERR0_BITS \
1450 ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) | \
1451 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1452 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1453 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1454 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1455 (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1457 /* Rx L3/L4 checksum */
1458 static inline uint64_t
1459 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1463 /* check if HW has decoded the packet and checksum */
1464 if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1467 if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1468 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1472 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1473 flags |= PKT_RX_IP_CKSUM_BAD;
1475 flags |= PKT_RX_IP_CKSUM_GOOD;
1477 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1478 flags |= PKT_RX_L4_CKSUM_BAD;
1480 flags |= PKT_RX_L4_CKSUM_GOOD;
1482 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1483 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1485 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1486 flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
1488 flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
1494 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1496 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1497 (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1498 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1500 rte_le_to_cpu_16(rxdp->wb.l2tag1);
1501 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1502 rte_le_to_cpu_16(rxdp->wb.l2tag1));
1507 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1508 if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1509 (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1510 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1511 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1512 mb->vlan_tci_outer = mb->vlan_tci;
1513 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1514 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1515 rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1516 rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1518 mb->vlan_tci_outer = 0;
1521 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1522 mb->vlan_tci, mb->vlan_tci_outer);
1525 #define ICE_LOOK_AHEAD 8
1526 #if (ICE_LOOK_AHEAD != 8)
1527 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1530 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1532 volatile union ice_rx_flex_desc *rxdp;
1533 struct ice_rx_entry *rxep;
1534 struct rte_mbuf *mb;
1537 int32_t s[ICE_LOOK_AHEAD], nb_dd;
1538 int32_t i, j, nb_rx = 0;
1539 uint64_t pkt_flags = 0;
1540 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1542 rxdp = &rxq->rx_ring[rxq->rx_tail];
1543 rxep = &rxq->sw_ring[rxq->rx_tail];
1545 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1547 /* Make sure there is at least 1 packet to receive */
1548 if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1552 * Scan LOOK_AHEAD descriptors at a time to determine which
1553 * descriptors reference packets that are ready to be received.
1555 for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1556 rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1557 /* Read desc statuses backwards to avoid race condition */
1558 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1559 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1563 /* Compute how many status bits were set */
1564 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1565 nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1569 /* Translate descriptor info to mbuf parameters */
1570 for (j = 0; j < nb_dd; j++) {
1572 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1573 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1574 mb->data_len = pkt_len;
1575 mb->pkt_len = pkt_len;
1577 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1578 pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1579 mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1580 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1581 ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1582 rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1584 mb->ol_flags |= pkt_flags;
1587 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1588 rxq->rx_stage[i + j] = rxep[j].mbuf;
1590 if (nb_dd != ICE_LOOK_AHEAD)
1594 /* Clear software ring entries */
1595 for (i = 0; i < nb_rx; i++)
1596 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1598 PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1599 "port_id=%u, queue_id=%u, nb_rx=%d",
1600 rxq->port_id, rxq->queue_id, nb_rx);
1605 static inline uint16_t
1606 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1607 struct rte_mbuf **rx_pkts,
1611 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1613 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1615 for (i = 0; i < nb_pkts; i++)
1616 rx_pkts[i] = stage[i];
1618 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1619 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1625 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1627 volatile union ice_rx_flex_desc *rxdp;
1628 struct ice_rx_entry *rxep;
1629 struct rte_mbuf *mb;
1630 uint16_t alloc_idx, i;
1634 /* Allocate buffers in bulk */
1635 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1636 (rxq->rx_free_thresh - 1));
1637 rxep = &rxq->sw_ring[alloc_idx];
1638 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1639 rxq->rx_free_thresh);
1640 if (unlikely(diag != 0)) {
1641 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1645 rxdp = &rxq->rx_ring[alloc_idx];
1646 for (i = 0; i < rxq->rx_free_thresh; i++) {
1647 if (likely(i < (rxq->rx_free_thresh - 1)))
1648 /* Prefetch next mbuf */
1649 rte_prefetch0(rxep[i + 1].mbuf);
1652 rte_mbuf_refcnt_set(mb, 1);
1654 mb->data_off = RTE_PKTMBUF_HEADROOM;
1656 mb->port = rxq->port_id;
1657 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1658 rxdp[i].read.hdr_addr = 0;
1659 rxdp[i].read.pkt_addr = dma_addr;
1662 /* Update rx tail regsiter */
1663 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1665 rxq->rx_free_trigger =
1666 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1667 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1668 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1673 static inline uint16_t
1674 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1676 struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1682 if (rxq->rx_nb_avail)
1683 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1685 nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1686 rxq->rx_next_avail = 0;
1687 rxq->rx_nb_avail = nb_rx;
1688 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1690 if (rxq->rx_tail > rxq->rx_free_trigger) {
1691 if (ice_rx_alloc_bufs(rxq) != 0) {
1694 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1695 rxq->rx_free_thresh;
1696 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1697 "port_id=%u, queue_id=%u",
1698 rxq->port_id, rxq->queue_id);
1699 rxq->rx_nb_avail = 0;
1700 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1701 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1702 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1708 if (rxq->rx_tail >= rxq->nb_rx_desc)
1711 if (rxq->rx_nb_avail)
1712 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1718 ice_recv_pkts_bulk_alloc(void *rx_queue,
1719 struct rte_mbuf **rx_pkts,
1726 if (unlikely(nb_pkts == 0))
1729 if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1730 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1733 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1734 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1735 nb_rx = (uint16_t)(nb_rx + count);
1736 nb_pkts = (uint16_t)(nb_pkts - count);
1745 ice_recv_scattered_pkts(void *rx_queue,
1746 struct rte_mbuf **rx_pkts,
1749 struct ice_rx_queue *rxq = rx_queue;
1750 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1751 volatile union ice_rx_flex_desc *rxdp;
1752 union ice_rx_flex_desc rxd;
1753 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1754 struct ice_rx_entry *rxe;
1755 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1756 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1757 struct rte_mbuf *nmb; /* new allocated mbuf */
1758 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1759 uint16_t rx_id = rxq->rx_tail;
1761 uint16_t nb_hold = 0;
1762 uint16_t rx_packet_len;
1763 uint16_t rx_stat_err0;
1766 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1768 while (nb_rx < nb_pkts) {
1769 rxdp = &rx_ring[rx_id];
1770 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1772 /* Check the DD bit first */
1773 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1777 nmb = rte_mbuf_raw_alloc(rxq->mp);
1778 if (unlikely(!nmb)) {
1779 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1782 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1785 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1787 if (unlikely(rx_id == rxq->nb_rx_desc))
1790 /* Prefetch next mbuf */
1791 rte_prefetch0(sw_ring[rx_id].mbuf);
1794 * When next RX descriptor is on a cache line boundary,
1795 * prefetch the next 4 RX descriptors and next 8 pointers
1798 if ((rx_id & 0x3) == 0) {
1799 rte_prefetch0(&rx_ring[rx_id]);
1800 rte_prefetch0(&sw_ring[rx_id]);
1806 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1808 /* Set data buffer address and data length of the mbuf */
1809 rxdp->read.hdr_addr = 0;
1810 rxdp->read.pkt_addr = dma_addr;
1811 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1812 ICE_RX_FLX_DESC_PKT_LEN_M;
1813 rxm->data_len = rx_packet_len;
1814 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1817 * If this is the first buffer of the received packet, set the
1818 * pointer to the first mbuf of the packet and initialize its
1819 * context. Otherwise, update the total length and the number
1820 * of segments of the current scattered packet, and update the
1821 * pointer to the last mbuf of the current packet.
1825 first_seg->nb_segs = 1;
1826 first_seg->pkt_len = rx_packet_len;
1828 first_seg->pkt_len =
1829 (uint16_t)(first_seg->pkt_len +
1831 first_seg->nb_segs++;
1832 last_seg->next = rxm;
1836 * If this is not the last buffer of the received packet,
1837 * update the pointer to the last mbuf of the current scattered
1838 * packet and continue to parse the RX ring.
1840 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1846 * This is the last buffer of the received packet. If the CRC
1847 * is not stripped by the hardware:
1848 * - Subtract the CRC length from the total packet length.
1849 * - If the last buffer only contains the whole CRC or a part
1850 * of it, free the mbuf associated to the last buffer. If part
1851 * of the CRC is also contained in the previous mbuf, subtract
1852 * the length of that CRC part from the data length of the
1856 if (unlikely(rxq->crc_len > 0)) {
1857 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1858 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1859 rte_pktmbuf_free_seg(rxm);
1860 first_seg->nb_segs--;
1861 last_seg->data_len =
1862 (uint16_t)(last_seg->data_len -
1863 (RTE_ETHER_CRC_LEN - rx_packet_len));
1864 last_seg->next = NULL;
1866 rxm->data_len = (uint16_t)(rx_packet_len -
1870 first_seg->port = rxq->port_id;
1871 first_seg->ol_flags = 0;
1872 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1873 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1874 ice_rxd_to_vlan_tci(first_seg, &rxd);
1875 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1876 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1877 first_seg->ol_flags |= pkt_flags;
1878 /* Prefetch data of first segment, if configured to do so. */
1879 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1880 first_seg->data_off));
1881 rx_pkts[nb_rx++] = first_seg;
1885 /* Record index of the next RX descriptor to probe. */
1886 rxq->rx_tail = rx_id;
1887 rxq->pkt_first_seg = first_seg;
1888 rxq->pkt_last_seg = last_seg;
1891 * If the number of free RX descriptors is greater than the RX free
1892 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1893 * register. Update the RDT with the value of the last processed RX
1894 * descriptor minus 1, to guarantee that the RDT register is never
1895 * equal to the RDH register, which creates a "full" ring situtation
1896 * from the hardware point of view.
1898 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1899 if (nb_hold > rxq->rx_free_thresh) {
1900 rx_id = (uint16_t)(rx_id == 0 ?
1901 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1902 /* write TAIL register */
1903 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1906 rxq->nb_rx_hold = nb_hold;
1908 /* return received packet in the burst */
1913 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1915 struct ice_adapter *ad =
1916 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1917 const uint32_t *ptypes;
1919 static const uint32_t ptypes_os[] = {
1920 /* refers to ice_get_default_pkt_type() */
1922 RTE_PTYPE_L2_ETHER_TIMESYNC,
1923 RTE_PTYPE_L2_ETHER_LLDP,
1924 RTE_PTYPE_L2_ETHER_ARP,
1925 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1926 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1929 RTE_PTYPE_L4_NONFRAG,
1933 RTE_PTYPE_TUNNEL_GRENAT,
1934 RTE_PTYPE_TUNNEL_IP,
1935 RTE_PTYPE_INNER_L2_ETHER,
1936 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1937 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1938 RTE_PTYPE_INNER_L4_FRAG,
1939 RTE_PTYPE_INNER_L4_ICMP,
1940 RTE_PTYPE_INNER_L4_NONFRAG,
1941 RTE_PTYPE_INNER_L4_SCTP,
1942 RTE_PTYPE_INNER_L4_TCP,
1943 RTE_PTYPE_INNER_L4_UDP,
1947 static const uint32_t ptypes_comms[] = {
1948 /* refers to ice_get_default_pkt_type() */
1950 RTE_PTYPE_L2_ETHER_TIMESYNC,
1951 RTE_PTYPE_L2_ETHER_LLDP,
1952 RTE_PTYPE_L2_ETHER_ARP,
1953 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1954 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1957 RTE_PTYPE_L4_NONFRAG,
1961 RTE_PTYPE_TUNNEL_GRENAT,
1962 RTE_PTYPE_TUNNEL_IP,
1963 RTE_PTYPE_INNER_L2_ETHER,
1964 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1965 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1966 RTE_PTYPE_INNER_L4_FRAG,
1967 RTE_PTYPE_INNER_L4_ICMP,
1968 RTE_PTYPE_INNER_L4_NONFRAG,
1969 RTE_PTYPE_INNER_L4_SCTP,
1970 RTE_PTYPE_INNER_L4_TCP,
1971 RTE_PTYPE_INNER_L4_UDP,
1972 RTE_PTYPE_TUNNEL_GTPC,
1973 RTE_PTYPE_TUNNEL_GTPU,
1974 RTE_PTYPE_L2_ETHER_PPPOE,
1978 if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
1979 ptypes = ptypes_comms;
1983 if (dev->rx_pkt_burst == ice_recv_pkts ||
1984 dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1985 dev->rx_pkt_burst == ice_recv_scattered_pkts)
1989 if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1990 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1991 #ifdef CC_AVX512_SUPPORT
1992 dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
1993 dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
1994 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
1995 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
1997 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1998 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
1999 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2000 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2008 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2010 volatile union ice_rx_flex_desc *rxdp;
2011 struct ice_rx_queue *rxq = rx_queue;
2014 if (unlikely(offset >= rxq->nb_rx_desc))
2017 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2018 return RTE_ETH_RX_DESC_UNAVAIL;
2020 desc = rxq->rx_tail + offset;
2021 if (desc >= rxq->nb_rx_desc)
2022 desc -= rxq->nb_rx_desc;
2024 rxdp = &rxq->rx_ring[desc];
2025 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2026 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2027 return RTE_ETH_RX_DESC_DONE;
2029 return RTE_ETH_RX_DESC_AVAIL;
2033 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2035 struct ice_tx_queue *txq = tx_queue;
2036 volatile uint64_t *status;
2037 uint64_t mask, expect;
2040 if (unlikely(offset >= txq->nb_tx_desc))
2043 desc = txq->tx_tail + offset;
2044 /* go to next desc that has the RS bit */
2045 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2047 if (desc >= txq->nb_tx_desc) {
2048 desc -= txq->nb_tx_desc;
2049 if (desc >= txq->nb_tx_desc)
2050 desc -= txq->nb_tx_desc;
2053 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2054 mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2055 expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2056 ICE_TXD_QW1_DTYPE_S);
2057 if ((*status & mask) == expect)
2058 return RTE_ETH_TX_DESC_DONE;
2060 return RTE_ETH_TX_DESC_FULL;
2064 ice_free_queues(struct rte_eth_dev *dev)
2068 PMD_INIT_FUNC_TRACE();
2070 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2071 if (!dev->data->rx_queues[i])
2073 ice_rx_queue_release(dev->data->rx_queues[i]);
2074 dev->data->rx_queues[i] = NULL;
2075 rte_eth_dma_zone_free(dev, "rx_ring", i);
2077 dev->data->nb_rx_queues = 0;
2079 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2080 if (!dev->data->tx_queues[i])
2082 ice_tx_queue_release(dev->data->tx_queues[i]);
2083 dev->data->tx_queues[i] = NULL;
2084 rte_eth_dma_zone_free(dev, "tx_ring", i);
2086 dev->data->nb_tx_queues = 0;
2089 #define ICE_FDIR_NUM_TX_DESC ICE_MIN_RING_DESC
2090 #define ICE_FDIR_NUM_RX_DESC ICE_MIN_RING_DESC
2093 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2095 struct ice_tx_queue *txq;
2096 const struct rte_memzone *tz = NULL;
2098 struct rte_eth_dev *dev;
2101 PMD_DRV_LOG(ERR, "PF is not available");
2105 dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2107 /* Allocate the TX queue data structure. */
2108 txq = rte_zmalloc_socket("ice fdir tx queue",
2109 sizeof(struct ice_tx_queue),
2110 RTE_CACHE_LINE_SIZE,
2113 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2114 "tx queue structure.");
2118 /* Allocate TX hardware ring descriptors. */
2119 ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2120 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2122 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2123 ICE_FDIR_QUEUE_ID, ring_size,
2124 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2126 ice_tx_queue_release(txq);
2127 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2131 txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2132 txq->queue_id = ICE_FDIR_QUEUE_ID;
2133 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2134 txq->vsi = pf->fdir.fdir_vsi;
2136 txq->tx_ring_dma = tz->iova;
2137 txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2139 * don't need to allocate software ring and reset for the fdir
2140 * program queue just set the queue has been configured.
2145 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2151 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2153 struct ice_rx_queue *rxq;
2154 const struct rte_memzone *rz = NULL;
2156 struct rte_eth_dev *dev;
2159 PMD_DRV_LOG(ERR, "PF is not available");
2163 dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2165 /* Allocate the RX queue data structure. */
2166 rxq = rte_zmalloc_socket("ice fdir rx queue",
2167 sizeof(struct ice_rx_queue),
2168 RTE_CACHE_LINE_SIZE,
2171 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2172 "rx queue structure.");
2176 /* Allocate RX hardware ring descriptors. */
2177 ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2178 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2180 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2181 ICE_FDIR_QUEUE_ID, ring_size,
2182 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2184 ice_rx_queue_release(rxq);
2185 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2189 rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2190 rxq->queue_id = ICE_FDIR_QUEUE_ID;
2191 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2192 rxq->vsi = pf->fdir.fdir_vsi;
2194 rxq->rx_ring_dma = rz->iova;
2195 memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2196 sizeof(union ice_32byte_rx_desc));
2197 rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2200 * Don't need to allocate software ring and reset for the fdir
2201 * rx queue, just set the queue has been configured.
2206 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2212 ice_recv_pkts(void *rx_queue,
2213 struct rte_mbuf **rx_pkts,
2216 struct ice_rx_queue *rxq = rx_queue;
2217 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2218 volatile union ice_rx_flex_desc *rxdp;
2219 union ice_rx_flex_desc rxd;
2220 struct ice_rx_entry *sw_ring = rxq->sw_ring;
2221 struct ice_rx_entry *rxe;
2222 struct rte_mbuf *nmb; /* new allocated mbuf */
2223 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2224 uint16_t rx_id = rxq->rx_tail;
2226 uint16_t nb_hold = 0;
2227 uint16_t rx_packet_len;
2228 uint16_t rx_stat_err0;
2231 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2233 while (nb_rx < nb_pkts) {
2234 rxdp = &rx_ring[rx_id];
2235 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2237 /* Check the DD bit first */
2238 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2242 nmb = rte_mbuf_raw_alloc(rxq->mp);
2243 if (unlikely(!nmb)) {
2244 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2247 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2250 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2252 if (unlikely(rx_id == rxq->nb_rx_desc))
2257 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2260 * fill the read format of descriptor with physic address in
2261 * new allocated mbuf: nmb
2263 rxdp->read.hdr_addr = 0;
2264 rxdp->read.pkt_addr = dma_addr;
2266 /* calculate rx_packet_len of the received pkt */
2267 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2268 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2270 /* fill old mbuf with received descriptor: rxd */
2271 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2272 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2275 rxm->pkt_len = rx_packet_len;
2276 rxm->data_len = rx_packet_len;
2277 rxm->port = rxq->port_id;
2278 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2279 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2280 ice_rxd_to_vlan_tci(rxm, &rxd);
2281 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
2282 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2283 rxm->ol_flags |= pkt_flags;
2284 /* copy old mbuf to rx_pkts */
2285 rx_pkts[nb_rx++] = rxm;
2287 rxq->rx_tail = rx_id;
2289 * If the number of free RX descriptors is greater than the RX free
2290 * threshold of the queue, advance the receive tail register of queue.
2291 * Update that register with the value of the last processed RX
2292 * descriptor minus 1.
2294 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2295 if (nb_hold > rxq->rx_free_thresh) {
2296 rx_id = (uint16_t)(rx_id == 0 ?
2297 (rxq->nb_rx_desc - 1) : (rx_id - 1));
2298 /* write TAIL register */
2299 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2302 rxq->nb_rx_hold = nb_hold;
2304 /* return received packet in the burst */
2309 ice_parse_tunneling_params(uint64_t ol_flags,
2310 union ice_tx_offload tx_offload,
2311 uint32_t *cd_tunneling)
2313 /* EIPT: External (outer) IP header type */
2314 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2315 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2316 else if (ol_flags & PKT_TX_OUTER_IPV4)
2317 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2318 else if (ol_flags & PKT_TX_OUTER_IPV6)
2319 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2321 /* EIPLEN: External (outer) IP header length, in DWords */
2322 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2323 ICE_TXD_CTX_QW0_EIPLEN_S;
2325 /* L4TUNT: L4 Tunneling Type */
2326 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2327 case PKT_TX_TUNNEL_IPIP:
2328 /* for non UDP / GRE tunneling, set to 00b */
2330 case PKT_TX_TUNNEL_VXLAN:
2331 case PKT_TX_TUNNEL_GTP:
2332 case PKT_TX_TUNNEL_GENEVE:
2333 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2335 case PKT_TX_TUNNEL_GRE:
2336 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2339 PMD_TX_LOG(ERR, "Tunnel type not supported");
2343 /* L4TUNLEN: L4 Tunneling Length, in Words
2345 * We depend on app to set rte_mbuf.l2_len correctly.
2346 * For IP in GRE it should be set to the length of the GRE
2348 * For MAC in GRE or MAC in UDP it should be set to the length
2349 * of the GRE or UDP headers plus the inner MAC up to including
2350 * its last Ethertype.
2351 * If MPLS labels exists, it should include them as well.
2353 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2354 ICE_TXD_CTX_QW0_NATLEN_S;
2357 * Calculate the tunneling UDP checksum.
2358 * Shall be set only if L4TUNT = 01b and EIPT is not zero
2360 if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2361 (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2362 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2366 ice_txd_enable_checksum(uint64_t ol_flags,
2368 uint32_t *td_offset,
2369 union ice_tx_offload tx_offload)
2372 if (ol_flags & PKT_TX_TUNNEL_MASK)
2373 *td_offset |= (tx_offload.outer_l2_len >> 1)
2374 << ICE_TX_DESC_LEN_MACLEN_S;
2376 *td_offset |= (tx_offload.l2_len >> 1)
2377 << ICE_TX_DESC_LEN_MACLEN_S;
2379 /* Enable L3 checksum offloads */
2380 if (ol_flags & PKT_TX_IP_CKSUM) {
2381 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2382 *td_offset |= (tx_offload.l3_len >> 2) <<
2383 ICE_TX_DESC_LEN_IPLEN_S;
2384 } else if (ol_flags & PKT_TX_IPV4) {
2385 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2386 *td_offset |= (tx_offload.l3_len >> 2) <<
2387 ICE_TX_DESC_LEN_IPLEN_S;
2388 } else if (ol_flags & PKT_TX_IPV6) {
2389 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2390 *td_offset |= (tx_offload.l3_len >> 2) <<
2391 ICE_TX_DESC_LEN_IPLEN_S;
2394 if (ol_flags & PKT_TX_TCP_SEG) {
2395 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2396 *td_offset |= (tx_offload.l4_len >> 2) <<
2397 ICE_TX_DESC_LEN_L4_LEN_S;
2401 /* Enable L4 checksum offloads */
2402 switch (ol_flags & PKT_TX_L4_MASK) {
2403 case PKT_TX_TCP_CKSUM:
2404 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2405 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2406 ICE_TX_DESC_LEN_L4_LEN_S;
2408 case PKT_TX_SCTP_CKSUM:
2409 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2410 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2411 ICE_TX_DESC_LEN_L4_LEN_S;
2413 case PKT_TX_UDP_CKSUM:
2414 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2415 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2416 ICE_TX_DESC_LEN_L4_LEN_S;
2424 ice_xmit_cleanup(struct ice_tx_queue *txq)
2426 struct ice_tx_entry *sw_ring = txq->sw_ring;
2427 volatile struct ice_tx_desc *txd = txq->tx_ring;
2428 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2429 uint16_t nb_tx_desc = txq->nb_tx_desc;
2430 uint16_t desc_to_clean_to;
2431 uint16_t nb_tx_to_clean;
2433 /* Determine the last descriptor needing to be cleaned */
2434 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2435 if (desc_to_clean_to >= nb_tx_desc)
2436 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2438 /* Check to make sure the last descriptor to clean is done */
2439 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2440 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2441 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2442 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2443 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2445 txq->port_id, txq->queue_id,
2446 txd[desc_to_clean_to].cmd_type_offset_bsz);
2447 /* Failed to clean any descriptors */
2451 /* Figure out how many descriptors will be cleaned */
2452 if (last_desc_cleaned > desc_to_clean_to)
2453 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2456 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2459 /* The last descriptor to clean is done, so that means all the
2460 * descriptors from the last descriptor that was cleaned
2461 * up to the last descriptor with the RS bit set
2462 * are done. Only reset the threshold descriptor.
2464 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2466 /* Update the txq to reflect the last descriptor that was cleaned */
2467 txq->last_desc_cleaned = desc_to_clean_to;
2468 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2473 /* Construct the tx flags */
2474 static inline uint64_t
2475 ice_build_ctob(uint32_t td_cmd,
2480 return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2481 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2482 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2483 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2484 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2487 /* Check if the context descriptor is needed for TX offloading */
2488 static inline uint16_t
2489 ice_calc_context_desc(uint64_t flags)
2491 static uint64_t mask = PKT_TX_TCP_SEG |
2493 PKT_TX_OUTER_IP_CKSUM |
2496 return (flags & mask) ? 1 : 0;
2499 /* set ice TSO context descriptor */
2500 static inline uint64_t
2501 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2503 uint64_t ctx_desc = 0;
2504 uint32_t cd_cmd, hdr_len, cd_tso_len;
2506 if (!tx_offload.l4_len) {
2507 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2511 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2512 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2513 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2515 cd_cmd = ICE_TX_CTX_DESC_TSO;
2516 cd_tso_len = mbuf->pkt_len - hdr_len;
2517 ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2518 ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2519 ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2524 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2525 #define ICE_MAX_DATA_PER_TXD \
2526 (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2527 /* Calculate the number of TX descriptors needed for each pkt */
2528 static inline uint16_t
2529 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2531 struct rte_mbuf *txd = tx_pkt;
2534 while (txd != NULL) {
2535 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2543 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2545 struct ice_tx_queue *txq;
2546 volatile struct ice_tx_desc *tx_ring;
2547 volatile struct ice_tx_desc *txd;
2548 struct ice_tx_entry *sw_ring;
2549 struct ice_tx_entry *txe, *txn;
2550 struct rte_mbuf *tx_pkt;
2551 struct rte_mbuf *m_seg;
2552 uint32_t cd_tunneling_params;
2557 uint32_t td_cmd = 0;
2558 uint32_t td_offset = 0;
2559 uint32_t td_tag = 0;
2562 uint64_t buf_dma_addr;
2564 union ice_tx_offload tx_offload = {0};
2567 sw_ring = txq->sw_ring;
2568 tx_ring = txq->tx_ring;
2569 tx_id = txq->tx_tail;
2570 txe = &sw_ring[tx_id];
2572 /* Check if the descriptor ring needs to be cleaned. */
2573 if (txq->nb_tx_free < txq->tx_free_thresh)
2574 (void)ice_xmit_cleanup(txq);
2576 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2577 tx_pkt = *tx_pkts++;
2582 ol_flags = tx_pkt->ol_flags;
2583 tx_offload.l2_len = tx_pkt->l2_len;
2584 tx_offload.l3_len = tx_pkt->l3_len;
2585 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2586 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2587 tx_offload.l4_len = tx_pkt->l4_len;
2588 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2589 /* Calculate the number of context descriptors needed. */
2590 nb_ctx = ice_calc_context_desc(ol_flags);
2592 /* The number of descriptors that must be allocated for
2593 * a packet equals to the number of the segments of that
2594 * packet plus the number of context descriptor if needed.
2595 * Recalculate the needed tx descs when TSO enabled in case
2596 * the mbuf data size exceeds max data size that hw allows
2599 if (ol_flags & PKT_TX_TCP_SEG)
2600 nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2603 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2604 tx_last = (uint16_t)(tx_id + nb_used - 1);
2607 if (tx_last >= txq->nb_tx_desc)
2608 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2610 if (nb_used > txq->nb_tx_free) {
2611 if (ice_xmit_cleanup(txq) != 0) {
2616 if (unlikely(nb_used > txq->tx_rs_thresh)) {
2617 while (nb_used > txq->nb_tx_free) {
2618 if (ice_xmit_cleanup(txq) != 0) {
2627 /* Descriptor based VLAN insertion */
2628 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2629 td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2630 td_tag = tx_pkt->vlan_tci;
2633 /* Fill in tunneling parameters if necessary */
2634 cd_tunneling_params = 0;
2635 if (ol_flags & PKT_TX_TUNNEL_MASK)
2636 ice_parse_tunneling_params(ol_flags, tx_offload,
2637 &cd_tunneling_params);
2639 /* Enable checksum offloading */
2640 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2641 ice_txd_enable_checksum(ol_flags, &td_cmd,
2642 &td_offset, tx_offload);
2645 /* Setup TX context descriptor if required */
2646 volatile struct ice_tx_ctx_desc *ctx_txd =
2647 (volatile struct ice_tx_ctx_desc *)
2649 uint16_t cd_l2tag2 = 0;
2650 uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2652 txn = &sw_ring[txe->next_id];
2653 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2655 rte_pktmbuf_free_seg(txe->mbuf);
2659 if (ol_flags & PKT_TX_TCP_SEG)
2660 cd_type_cmd_tso_mss |=
2661 ice_set_tso_ctx(tx_pkt, tx_offload);
2663 ctx_txd->tunneling_params =
2664 rte_cpu_to_le_32(cd_tunneling_params);
2666 /* TX context descriptor based double VLAN insert */
2667 if (ol_flags & PKT_TX_QINQ) {
2668 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2669 cd_type_cmd_tso_mss |=
2670 ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2671 ICE_TXD_CTX_QW1_CMD_S);
2673 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2675 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2677 txe->last_id = tx_last;
2678 tx_id = txe->next_id;
2684 txd = &tx_ring[tx_id];
2685 txn = &sw_ring[txe->next_id];
2688 rte_pktmbuf_free_seg(txe->mbuf);
2691 /* Setup TX Descriptor */
2692 slen = m_seg->data_len;
2693 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2695 while ((ol_flags & PKT_TX_TCP_SEG) &&
2696 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2697 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2698 txd->cmd_type_offset_bsz =
2699 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2700 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2701 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2702 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2703 ICE_TXD_QW1_TX_BUF_SZ_S) |
2704 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2706 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2707 slen -= ICE_MAX_DATA_PER_TXD;
2709 txe->last_id = tx_last;
2710 tx_id = txe->next_id;
2712 txd = &tx_ring[tx_id];
2713 txn = &sw_ring[txe->next_id];
2716 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2717 txd->cmd_type_offset_bsz =
2718 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2719 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2720 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2721 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2722 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2724 txe->last_id = tx_last;
2725 tx_id = txe->next_id;
2727 m_seg = m_seg->next;
2730 /* fill the last descriptor with End of Packet (EOP) bit */
2731 td_cmd |= ICE_TX_DESC_CMD_EOP;
2732 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2733 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2735 /* set RS bit on the last descriptor of one packet */
2736 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2738 "Setting RS bit on TXD id="
2739 "%4u (port=%d queue=%d)",
2740 tx_last, txq->port_id, txq->queue_id);
2742 td_cmd |= ICE_TX_DESC_CMD_RS;
2744 /* Update txq RS bit counters */
2745 txq->nb_tx_used = 0;
2747 txd->cmd_type_offset_bsz |=
2748 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2752 /* update Tail register */
2753 ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2754 txq->tx_tail = tx_id;
2759 static __rte_always_inline int
2760 ice_tx_free_bufs(struct ice_tx_queue *txq)
2762 struct ice_tx_entry *txep;
2765 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2766 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2767 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2770 txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2772 for (i = 0; i < txq->tx_rs_thresh; i++)
2773 rte_prefetch0((txep + i)->mbuf);
2775 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2776 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2777 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2781 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2782 rte_pktmbuf_free_seg(txep->mbuf);
2787 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2788 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2789 if (txq->tx_next_dd >= txq->nb_tx_desc)
2790 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2792 return txq->tx_rs_thresh;
2796 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2799 struct ice_tx_entry *swr_ring = txq->sw_ring;
2800 uint16_t i, tx_last, tx_id;
2801 uint16_t nb_tx_free_last;
2802 uint16_t nb_tx_to_clean;
2805 /* Start free mbuf from the next of tx_tail */
2806 tx_last = txq->tx_tail;
2807 tx_id = swr_ring[tx_last].next_id;
2809 if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2812 nb_tx_to_clean = txq->nb_tx_free;
2813 nb_tx_free_last = txq->nb_tx_free;
2815 free_cnt = txq->nb_tx_desc;
2817 /* Loop through swr_ring to count the amount of
2818 * freeable mubfs and packets.
2820 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2821 for (i = 0; i < nb_tx_to_clean &&
2822 pkt_cnt < free_cnt &&
2823 tx_id != tx_last; i++) {
2824 if (swr_ring[tx_id].mbuf != NULL) {
2825 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2826 swr_ring[tx_id].mbuf = NULL;
2829 * last segment in the packet,
2830 * increment packet count
2832 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2835 tx_id = swr_ring[tx_id].next_id;
2838 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2839 txq->nb_tx_free || tx_id == tx_last)
2842 if (pkt_cnt < free_cnt) {
2843 if (ice_xmit_cleanup(txq))
2846 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2847 nb_tx_free_last = txq->nb_tx_free;
2851 return (int)pkt_cnt;
2856 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2857 uint32_t free_cnt __rte_unused)
2864 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2869 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2870 free_cnt = txq->nb_tx_desc;
2872 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2874 for (i = 0; i < cnt; i += n) {
2875 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2878 n = ice_tx_free_bufs(txq);
2888 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2890 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2891 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2892 struct ice_adapter *ad =
2893 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2896 if (ad->tx_vec_allowed)
2897 return ice_tx_done_cleanup_vec(q, free_cnt);
2899 if (ad->tx_simple_allowed)
2900 return ice_tx_done_cleanup_simple(q, free_cnt);
2902 return ice_tx_done_cleanup_full(q, free_cnt);
2905 /* Populate 4 descriptors with data from 4 mbufs */
2907 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2912 for (i = 0; i < 4; i++, txdp++, pkts++) {
2913 dma_addr = rte_mbuf_data_iova(*pkts);
2914 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2915 txdp->cmd_type_offset_bsz =
2916 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2917 (*pkts)->data_len, 0);
2921 /* Populate 1 descriptor with data from 1 mbuf */
2923 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2927 dma_addr = rte_mbuf_data_iova(*pkts);
2928 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2929 txdp->cmd_type_offset_bsz =
2930 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2931 (*pkts)->data_len, 0);
2935 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2938 volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2939 struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2940 const int N_PER_LOOP = 4;
2941 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2942 int mainpart, leftover;
2946 * Process most of the packets in chunks of N pkts. Any
2947 * leftover packets will get processed one at a time.
2949 mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2950 leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2951 for (i = 0; i < mainpart; i += N_PER_LOOP) {
2952 /* Copy N mbuf pointers to the S/W ring */
2953 for (j = 0; j < N_PER_LOOP; ++j)
2954 (txep + i + j)->mbuf = *(pkts + i + j);
2955 tx4(txdp + i, pkts + i);
2958 if (unlikely(leftover > 0)) {
2959 for (i = 0; i < leftover; ++i) {
2960 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2961 tx1(txdp + mainpart + i, pkts + mainpart + i);
2966 static inline uint16_t
2967 tx_xmit_pkts(struct ice_tx_queue *txq,
2968 struct rte_mbuf **tx_pkts,
2971 volatile struct ice_tx_desc *txr = txq->tx_ring;
2975 * Begin scanning the H/W ring for done descriptors when the number
2976 * of available descriptors drops below tx_free_thresh. For each done
2977 * descriptor, free the associated buffer.
2979 if (txq->nb_tx_free < txq->tx_free_thresh)
2980 ice_tx_free_bufs(txq);
2982 /* Use available descriptor only */
2983 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2984 if (unlikely(!nb_pkts))
2987 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2988 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2989 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2990 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2991 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2992 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2994 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2998 /* Fill hardware descriptor ring with mbuf data */
2999 ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3000 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3002 /* Determin if RS bit needs to be set */
3003 if (txq->tx_tail > txq->tx_next_rs) {
3004 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3005 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3008 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3009 if (txq->tx_next_rs >= txq->nb_tx_desc)
3010 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3013 if (txq->tx_tail >= txq->nb_tx_desc)
3016 /* Update the tx tail register */
3017 ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3023 ice_xmit_pkts_simple(void *tx_queue,
3024 struct rte_mbuf **tx_pkts,
3029 if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3030 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3034 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3037 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3038 &tx_pkts[nb_tx], num);
3039 nb_tx = (uint16_t)(nb_tx + ret);
3040 nb_pkts = (uint16_t)(nb_pkts - ret);
3049 ice_set_rx_function(struct rte_eth_dev *dev)
3051 PMD_INIT_FUNC_TRACE();
3052 struct ice_adapter *ad =
3053 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3055 struct ice_rx_queue *rxq;
3057 int rx_check_ret = -1;
3059 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3060 ad->rx_use_avx512 = false;
3061 ad->rx_use_avx2 = false;
3062 rx_check_ret = ice_rx_vec_dev_check(dev);
3063 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3064 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3065 ad->rx_vec_allowed = true;
3066 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3067 rxq = dev->data->rx_queues[i];
3068 if (rxq && ice_rxq_vec_setup(rxq)) {
3069 ad->rx_vec_allowed = false;
3074 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3075 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3076 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3077 #ifdef CC_AVX512_SUPPORT
3078 ad->rx_use_avx512 = true;
3081 "AVX512 is not supported in build env");
3083 if (!ad->rx_use_avx512 &&
3084 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3085 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3086 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3087 ad->rx_use_avx2 = true;
3090 ad->rx_vec_allowed = false;
3094 if (ad->rx_vec_allowed) {
3095 if (dev->data->scattered_rx) {
3096 if (ad->rx_use_avx512) {
3097 #ifdef CC_AVX512_SUPPORT
3098 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3100 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3101 dev->data->port_id);
3103 ice_recv_scattered_pkts_vec_avx512_offload;
3106 "Using AVX512 Vector Scattered Rx (port %d).",
3107 dev->data->port_id);
3109 ice_recv_scattered_pkts_vec_avx512;
3112 } else if (ad->rx_use_avx2) {
3113 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3115 "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3116 dev->data->port_id);
3118 ice_recv_scattered_pkts_vec_avx2_offload;
3121 "Using AVX2 Vector Scattered Rx (port %d).",
3122 dev->data->port_id);
3124 ice_recv_scattered_pkts_vec_avx2;
3128 "Using Vector Scattered Rx (port %d).",
3129 dev->data->port_id);
3130 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3133 if (ad->rx_use_avx512) {
3134 #ifdef CC_AVX512_SUPPORT
3135 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3137 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3138 dev->data->port_id);
3140 ice_recv_pkts_vec_avx512_offload;
3143 "Using AVX512 Vector Rx (port %d).",
3144 dev->data->port_id);
3146 ice_recv_pkts_vec_avx512;
3149 } else if (ad->rx_use_avx2) {
3150 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3152 "Using AVX2 OFFLOAD Vector Rx (port %d).",
3153 dev->data->port_id);
3155 ice_recv_pkts_vec_avx2_offload;
3158 "Using AVX2 Vector Rx (port %d).",
3159 dev->data->port_id);
3161 ice_recv_pkts_vec_avx2;
3165 "Using Vector Rx (port %d).",
3166 dev->data->port_id);
3167 dev->rx_pkt_burst = ice_recv_pkts_vec;
3175 if (dev->data->scattered_rx) {
3176 /* Set the non-LRO scattered function */
3178 "Using a Scattered function on port %d.",
3179 dev->data->port_id);
3180 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3181 } else if (ad->rx_bulk_alloc_allowed) {
3183 "Rx Burst Bulk Alloc Preconditions are "
3184 "satisfied. Rx Burst Bulk Alloc function "
3185 "will be used on port %d.",
3186 dev->data->port_id);
3187 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3190 "Rx Burst Bulk Alloc Preconditions are not "
3191 "satisfied, Normal Rx will be used on port %d.",
3192 dev->data->port_id);
3193 dev->rx_pkt_burst = ice_recv_pkts;
3197 static const struct {
3198 eth_rx_burst_t pkt_burst;
3200 } ice_rx_burst_infos[] = {
3201 { ice_recv_scattered_pkts, "Scalar Scattered" },
3202 { ice_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3203 { ice_recv_pkts, "Scalar" },
3205 #ifdef CC_AVX512_SUPPORT
3206 { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3207 { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3208 { ice_recv_pkts_vec_avx512, "Vector AVX512" },
3209 { ice_recv_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3211 { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3212 { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3213 { ice_recv_pkts_vec_avx2, "Vector AVX2" },
3214 { ice_recv_pkts_vec_avx2_offload, "Offload Vector AVX2" },
3215 { ice_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3216 { ice_recv_pkts_vec, "Vector SSE" },
3221 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3222 struct rte_eth_burst_mode *mode)
3224 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3228 for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3229 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3230 snprintf(mode->info, sizeof(mode->info), "%s",
3231 ice_rx_burst_infos[i].info);
3241 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3243 struct ice_adapter *ad =
3244 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3246 /* Use a simple Tx queue if possible (only fast free is allowed) */
3247 ad->tx_simple_allowed =
3249 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3250 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3252 if (ad->tx_simple_allowed)
3253 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3257 "Simple Tx can NOT be enabled on Tx queue %u.",
3261 /*********************************************************************
3265 **********************************************************************/
3266 /* The default values of TSO MSS */
3267 #define ICE_MIN_TSO_MSS 64
3268 #define ICE_MAX_TSO_MSS 9728
3269 #define ICE_MAX_TSO_FRAME_SIZE 262144
3271 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3278 for (i = 0; i < nb_pkts; i++) {
3280 ol_flags = m->ol_flags;
3282 if (ol_flags & PKT_TX_TCP_SEG &&
3283 (m->tso_segsz < ICE_MIN_TSO_MSS ||
3284 m->tso_segsz > ICE_MAX_TSO_MSS ||
3285 m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3287 * MSS outside the range are considered malicious
3293 #ifdef RTE_ETHDEV_DEBUG_TX
3294 ret = rte_validate_tx_offload(m);
3300 ret = rte_net_intel_cksum_prepare(m);
3310 ice_set_tx_function(struct rte_eth_dev *dev)
3312 struct ice_adapter *ad =
3313 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3315 struct ice_tx_queue *txq;
3317 int tx_check_ret = -1;
3319 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3320 ad->tx_use_avx2 = false;
3321 ad->tx_use_avx512 = false;
3322 tx_check_ret = ice_tx_vec_dev_check(dev);
3323 if (tx_check_ret >= 0 &&
3324 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3325 ad->tx_vec_allowed = true;
3327 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3328 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3329 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3330 #ifdef CC_AVX512_SUPPORT
3331 ad->tx_use_avx512 = true;
3334 "AVX512 is not supported in build env");
3336 if (!ad->tx_use_avx512 &&
3337 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3338 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3339 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3340 ad->tx_use_avx2 = true;
3342 if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3343 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3344 ad->tx_vec_allowed = false;
3346 if (ad->tx_vec_allowed) {
3347 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3348 txq = dev->data->tx_queues[i];
3349 if (txq && ice_txq_vec_setup(txq)) {
3350 ad->tx_vec_allowed = false;
3356 ad->tx_vec_allowed = false;
3360 if (ad->tx_vec_allowed) {
3361 dev->tx_pkt_prepare = NULL;
3362 if (ad->tx_use_avx512) {
3363 #ifdef CC_AVX512_SUPPORT
3364 if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3366 "Using AVX512 OFFLOAD Vector Tx (port %d).",
3367 dev->data->port_id);
3369 ice_xmit_pkts_vec_avx512_offload;
3370 dev->tx_pkt_prepare = ice_prep_pkts;
3373 "Using AVX512 Vector Tx (port %d).",
3374 dev->data->port_id);
3375 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3379 if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3381 "Using AVX2 OFFLOAD Vector Tx (port %d).",
3382 dev->data->port_id);
3384 ice_xmit_pkts_vec_avx2_offload;
3385 dev->tx_pkt_prepare = ice_prep_pkts;
3387 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3388 ad->tx_use_avx2 ? "avx2 " : "",
3389 dev->data->port_id);
3390 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3391 ice_xmit_pkts_vec_avx2 :
3400 if (ad->tx_simple_allowed) {
3401 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3402 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3403 dev->tx_pkt_prepare = NULL;
3405 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3406 dev->tx_pkt_burst = ice_xmit_pkts;
3407 dev->tx_pkt_prepare = ice_prep_pkts;
3411 static const struct {
3412 eth_tx_burst_t pkt_burst;
3414 } ice_tx_burst_infos[] = {
3415 { ice_xmit_pkts_simple, "Scalar Simple" },
3416 { ice_xmit_pkts, "Scalar" },
3418 #ifdef CC_AVX512_SUPPORT
3419 { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3420 { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3422 { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3423 { ice_xmit_pkts_vec, "Vector SSE" },
3428 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3429 struct rte_eth_burst_mode *mode)
3431 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3435 for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3436 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3437 snprintf(mode->info, sizeof(mode->info), "%s",
3438 ice_tx_burst_infos[i].info);
3447 /* For each value it means, datasheet of hardware can tell more details
3449 * @note: fix ice_dev_supported_ptypes_get() if any change here.
3451 static inline uint32_t
3452 ice_get_default_pkt_type(uint16_t ptype)
3454 static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3455 __rte_cache_aligned = {
3458 [1] = RTE_PTYPE_L2_ETHER,
3459 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3460 /* [3] - [5] reserved */
3461 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3462 /* [7] - [10] reserved */
3463 [11] = RTE_PTYPE_L2_ETHER_ARP,
3464 /* [12] - [21] reserved */
3466 /* Non tunneled IPv4 */
3467 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3469 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3470 RTE_PTYPE_L4_NONFRAG,
3471 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3474 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3476 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3478 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3482 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3483 RTE_PTYPE_TUNNEL_IP |
3484 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3485 RTE_PTYPE_INNER_L4_FRAG,
3486 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3487 RTE_PTYPE_TUNNEL_IP |
3488 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3489 RTE_PTYPE_INNER_L4_NONFRAG,
3490 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3491 RTE_PTYPE_TUNNEL_IP |
3492 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3493 RTE_PTYPE_INNER_L4_UDP,
3495 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3496 RTE_PTYPE_TUNNEL_IP |
3497 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3498 RTE_PTYPE_INNER_L4_TCP,
3499 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3500 RTE_PTYPE_TUNNEL_IP |
3501 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3502 RTE_PTYPE_INNER_L4_SCTP,
3503 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3504 RTE_PTYPE_TUNNEL_IP |
3505 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3506 RTE_PTYPE_INNER_L4_ICMP,
3509 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3510 RTE_PTYPE_TUNNEL_IP |
3511 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3512 RTE_PTYPE_INNER_L4_FRAG,
3513 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3514 RTE_PTYPE_TUNNEL_IP |
3515 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3516 RTE_PTYPE_INNER_L4_NONFRAG,
3517 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3518 RTE_PTYPE_TUNNEL_IP |
3519 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3520 RTE_PTYPE_INNER_L4_UDP,
3522 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3523 RTE_PTYPE_TUNNEL_IP |
3524 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3525 RTE_PTYPE_INNER_L4_TCP,
3526 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3527 RTE_PTYPE_TUNNEL_IP |
3528 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3529 RTE_PTYPE_INNER_L4_SCTP,
3530 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3531 RTE_PTYPE_TUNNEL_IP |
3532 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3533 RTE_PTYPE_INNER_L4_ICMP,
3535 /* IPv4 --> GRE/Teredo/VXLAN */
3536 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3537 RTE_PTYPE_TUNNEL_GRENAT,
3539 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3540 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3541 RTE_PTYPE_TUNNEL_GRENAT |
3542 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3543 RTE_PTYPE_INNER_L4_FRAG,
3544 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3545 RTE_PTYPE_TUNNEL_GRENAT |
3546 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3547 RTE_PTYPE_INNER_L4_NONFRAG,
3548 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3549 RTE_PTYPE_TUNNEL_GRENAT |
3550 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3551 RTE_PTYPE_INNER_L4_UDP,
3553 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3554 RTE_PTYPE_TUNNEL_GRENAT |
3555 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3556 RTE_PTYPE_INNER_L4_TCP,
3557 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3558 RTE_PTYPE_TUNNEL_GRENAT |
3559 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3560 RTE_PTYPE_INNER_L4_SCTP,
3561 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3562 RTE_PTYPE_TUNNEL_GRENAT |
3563 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3564 RTE_PTYPE_INNER_L4_ICMP,
3566 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3567 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3568 RTE_PTYPE_TUNNEL_GRENAT |
3569 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3570 RTE_PTYPE_INNER_L4_FRAG,
3571 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3572 RTE_PTYPE_TUNNEL_GRENAT |
3573 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3574 RTE_PTYPE_INNER_L4_NONFRAG,
3575 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3576 RTE_PTYPE_TUNNEL_GRENAT |
3577 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3578 RTE_PTYPE_INNER_L4_UDP,
3580 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3581 RTE_PTYPE_TUNNEL_GRENAT |
3582 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3583 RTE_PTYPE_INNER_L4_TCP,
3584 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3585 RTE_PTYPE_TUNNEL_GRENAT |
3586 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3587 RTE_PTYPE_INNER_L4_SCTP,
3588 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3589 RTE_PTYPE_TUNNEL_GRENAT |
3590 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3591 RTE_PTYPE_INNER_L4_ICMP,
3593 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3594 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3595 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3597 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3598 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3599 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3600 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3601 RTE_PTYPE_INNER_L4_FRAG,
3602 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3603 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3604 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3605 RTE_PTYPE_INNER_L4_NONFRAG,
3606 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3607 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3608 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3609 RTE_PTYPE_INNER_L4_UDP,
3611 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3612 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3613 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3614 RTE_PTYPE_INNER_L4_TCP,
3615 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3616 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3617 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3618 RTE_PTYPE_INNER_L4_SCTP,
3619 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3620 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3621 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3622 RTE_PTYPE_INNER_L4_ICMP,
3624 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3625 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3626 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3627 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3628 RTE_PTYPE_INNER_L4_FRAG,
3629 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3630 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3631 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3632 RTE_PTYPE_INNER_L4_NONFRAG,
3633 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3634 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3635 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3636 RTE_PTYPE_INNER_L4_UDP,
3638 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3639 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3640 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3641 RTE_PTYPE_INNER_L4_TCP,
3642 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3643 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3644 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3645 RTE_PTYPE_INNER_L4_SCTP,
3646 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3647 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3648 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3649 RTE_PTYPE_INNER_L4_ICMP,
3650 /* [73] - [87] reserved */
3652 /* Non tunneled IPv6 */
3653 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3655 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3656 RTE_PTYPE_L4_NONFRAG,
3657 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3660 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3662 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3664 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3668 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3669 RTE_PTYPE_TUNNEL_IP |
3670 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3671 RTE_PTYPE_INNER_L4_FRAG,
3672 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3673 RTE_PTYPE_TUNNEL_IP |
3674 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3675 RTE_PTYPE_INNER_L4_NONFRAG,
3676 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3677 RTE_PTYPE_TUNNEL_IP |
3678 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3679 RTE_PTYPE_INNER_L4_UDP,
3681 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3682 RTE_PTYPE_TUNNEL_IP |
3683 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3684 RTE_PTYPE_INNER_L4_TCP,
3685 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3686 RTE_PTYPE_TUNNEL_IP |
3687 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3688 RTE_PTYPE_INNER_L4_SCTP,
3689 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3690 RTE_PTYPE_TUNNEL_IP |
3691 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3692 RTE_PTYPE_INNER_L4_ICMP,
3695 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3696 RTE_PTYPE_TUNNEL_IP |
3697 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3698 RTE_PTYPE_INNER_L4_FRAG,
3699 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3700 RTE_PTYPE_TUNNEL_IP |
3701 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3702 RTE_PTYPE_INNER_L4_NONFRAG,
3703 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3704 RTE_PTYPE_TUNNEL_IP |
3705 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3706 RTE_PTYPE_INNER_L4_UDP,
3707 /* [105] reserved */
3708 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3709 RTE_PTYPE_TUNNEL_IP |
3710 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3711 RTE_PTYPE_INNER_L4_TCP,
3712 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3713 RTE_PTYPE_TUNNEL_IP |
3714 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3715 RTE_PTYPE_INNER_L4_SCTP,
3716 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3717 RTE_PTYPE_TUNNEL_IP |
3718 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3719 RTE_PTYPE_INNER_L4_ICMP,
3721 /* IPv6 --> GRE/Teredo/VXLAN */
3722 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3723 RTE_PTYPE_TUNNEL_GRENAT,
3725 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3726 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3727 RTE_PTYPE_TUNNEL_GRENAT |
3728 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3729 RTE_PTYPE_INNER_L4_FRAG,
3730 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3731 RTE_PTYPE_TUNNEL_GRENAT |
3732 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3733 RTE_PTYPE_INNER_L4_NONFRAG,
3734 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3735 RTE_PTYPE_TUNNEL_GRENAT |
3736 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3737 RTE_PTYPE_INNER_L4_UDP,
3738 /* [113] reserved */
3739 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3740 RTE_PTYPE_TUNNEL_GRENAT |
3741 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3742 RTE_PTYPE_INNER_L4_TCP,
3743 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3744 RTE_PTYPE_TUNNEL_GRENAT |
3745 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3746 RTE_PTYPE_INNER_L4_SCTP,
3747 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3748 RTE_PTYPE_TUNNEL_GRENAT |
3749 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3750 RTE_PTYPE_INNER_L4_ICMP,
3752 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3753 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3754 RTE_PTYPE_TUNNEL_GRENAT |
3755 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3756 RTE_PTYPE_INNER_L4_FRAG,
3757 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3758 RTE_PTYPE_TUNNEL_GRENAT |
3759 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3760 RTE_PTYPE_INNER_L4_NONFRAG,
3761 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3762 RTE_PTYPE_TUNNEL_GRENAT |
3763 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3764 RTE_PTYPE_INNER_L4_UDP,
3765 /* [120] reserved */
3766 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3767 RTE_PTYPE_TUNNEL_GRENAT |
3768 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3769 RTE_PTYPE_INNER_L4_TCP,
3770 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3771 RTE_PTYPE_TUNNEL_GRENAT |
3772 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3773 RTE_PTYPE_INNER_L4_SCTP,
3774 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3775 RTE_PTYPE_TUNNEL_GRENAT |
3776 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3777 RTE_PTYPE_INNER_L4_ICMP,
3779 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3780 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3781 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3783 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3784 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3785 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3786 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3787 RTE_PTYPE_INNER_L4_FRAG,
3788 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3789 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3790 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3791 RTE_PTYPE_INNER_L4_NONFRAG,
3792 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3793 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3794 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3795 RTE_PTYPE_INNER_L4_UDP,
3796 /* [128] reserved */
3797 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3798 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3799 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3800 RTE_PTYPE_INNER_L4_TCP,
3801 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3802 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3803 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3804 RTE_PTYPE_INNER_L4_SCTP,
3805 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3806 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3807 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3808 RTE_PTYPE_INNER_L4_ICMP,
3810 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3811 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3812 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3813 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3814 RTE_PTYPE_INNER_L4_FRAG,
3815 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3816 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3817 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3818 RTE_PTYPE_INNER_L4_NONFRAG,
3819 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3820 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3821 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3822 RTE_PTYPE_INNER_L4_UDP,
3823 /* [135] reserved */
3824 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3825 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3826 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3827 RTE_PTYPE_INNER_L4_TCP,
3828 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3829 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3830 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3831 RTE_PTYPE_INNER_L4_SCTP,
3832 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3833 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3834 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3835 RTE_PTYPE_INNER_L4_ICMP,
3836 /* [139] - [299] reserved */
3839 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3840 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3842 /* PPPoE --> IPv4 */
3843 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3844 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3846 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3847 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3848 RTE_PTYPE_L4_NONFRAG,
3849 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3850 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3852 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3853 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3855 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3856 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3858 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3859 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3862 /* PPPoE --> IPv6 */
3863 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3864 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3866 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3867 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3868 RTE_PTYPE_L4_NONFRAG,
3869 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3870 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3872 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3873 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3875 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3876 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3878 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3879 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3881 /* [314] - [324] reserved */
3883 /* IPv4/IPv6 --> GTPC/GTPU */
3884 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3885 RTE_PTYPE_TUNNEL_GTPC,
3886 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3887 RTE_PTYPE_TUNNEL_GTPC,
3888 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3889 RTE_PTYPE_TUNNEL_GTPC,
3890 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3891 RTE_PTYPE_TUNNEL_GTPC,
3892 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3893 RTE_PTYPE_TUNNEL_GTPU,
3894 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3895 RTE_PTYPE_TUNNEL_GTPU,
3897 /* IPv4 --> GTPU --> IPv4 */
3898 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3899 RTE_PTYPE_TUNNEL_GTPU |
3900 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3901 RTE_PTYPE_INNER_L4_FRAG,
3902 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3903 RTE_PTYPE_TUNNEL_GTPU |
3904 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3905 RTE_PTYPE_INNER_L4_NONFRAG,
3906 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3907 RTE_PTYPE_TUNNEL_GTPU |
3908 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3909 RTE_PTYPE_INNER_L4_UDP,
3910 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3911 RTE_PTYPE_TUNNEL_GTPU |
3912 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3913 RTE_PTYPE_INNER_L4_TCP,
3914 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3915 RTE_PTYPE_TUNNEL_GTPU |
3916 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3917 RTE_PTYPE_INNER_L4_ICMP,
3919 /* IPv6 --> GTPU --> IPv4 */
3920 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3921 RTE_PTYPE_TUNNEL_GTPU |
3922 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3923 RTE_PTYPE_INNER_L4_FRAG,
3924 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3925 RTE_PTYPE_TUNNEL_GTPU |
3926 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3927 RTE_PTYPE_INNER_L4_NONFRAG,
3928 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3929 RTE_PTYPE_TUNNEL_GTPU |
3930 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3931 RTE_PTYPE_INNER_L4_UDP,
3932 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3933 RTE_PTYPE_TUNNEL_GTPU |
3934 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3935 RTE_PTYPE_INNER_L4_TCP,
3936 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3937 RTE_PTYPE_TUNNEL_GTPU |
3938 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3939 RTE_PTYPE_INNER_L4_ICMP,
3941 /* IPv4 --> GTPU --> IPv6 */
3942 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3943 RTE_PTYPE_TUNNEL_GTPU |
3944 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3945 RTE_PTYPE_INNER_L4_FRAG,
3946 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3947 RTE_PTYPE_TUNNEL_GTPU |
3948 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3949 RTE_PTYPE_INNER_L4_NONFRAG,
3950 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3951 RTE_PTYPE_TUNNEL_GTPU |
3952 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3953 RTE_PTYPE_INNER_L4_UDP,
3954 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3955 RTE_PTYPE_TUNNEL_GTPU |
3956 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3957 RTE_PTYPE_INNER_L4_TCP,
3958 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3959 RTE_PTYPE_TUNNEL_GTPU |
3960 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3961 RTE_PTYPE_INNER_L4_ICMP,
3963 /* IPv6 --> GTPU --> IPv6 */
3964 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3965 RTE_PTYPE_TUNNEL_GTPU |
3966 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3967 RTE_PTYPE_INNER_L4_FRAG,
3968 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3969 RTE_PTYPE_TUNNEL_GTPU |
3970 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3971 RTE_PTYPE_INNER_L4_NONFRAG,
3972 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3973 RTE_PTYPE_TUNNEL_GTPU |
3974 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3975 RTE_PTYPE_INNER_L4_UDP,
3976 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3977 RTE_PTYPE_TUNNEL_GTPU |
3978 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3979 RTE_PTYPE_INNER_L4_TCP,
3980 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3981 RTE_PTYPE_TUNNEL_GTPU |
3982 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3983 RTE_PTYPE_INNER_L4_ICMP,
3985 /* IPv4 --> UDP ECPRI */
3986 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3988 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3990 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3992 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3994 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3996 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3998 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4000 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4002 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4004 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4007 /* IPV6 --> UDP ECPRI */
4008 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4010 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4012 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4014 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4016 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4018 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4020 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4022 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4024 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4026 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4028 /* All others reserved */
4031 return type_table[ptype];
4035 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4037 struct ice_adapter *ad =
4038 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4041 for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4042 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4045 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4046 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4047 (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4048 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4049 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4051 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S 4
4052 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M \
4053 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4054 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S 5
4055 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M \
4056 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4059 * check the programming status descriptor in rx queue.
4060 * done after Programming Flow Director is programmed on
4064 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4066 volatile union ice_32byte_rx_desc *rxdp;
4073 rxdp = (volatile union ice_32byte_rx_desc *)
4074 (&rxq->rx_ring[rxq->rx_tail]);
4075 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4076 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4077 >> ICE_RXD_QW1_STATUS_S;
4079 if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4081 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4082 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4083 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4084 ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4086 if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4087 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4088 else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4089 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4093 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4094 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4096 PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4100 rxdp->wb.qword1.status_error_len = 0;
4102 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4104 if (rxq->rx_tail == 0)
4105 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4107 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4113 #define ICE_FDIR_MAX_WAIT_US 10000
4116 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4118 struct ice_tx_queue *txq = pf->fdir.txq;
4119 struct ice_rx_queue *rxq = pf->fdir.rxq;
4120 volatile struct ice_fltr_desc *fdirdp;
4121 volatile struct ice_tx_desc *txdp;
4125 fdirdp = (volatile struct ice_fltr_desc *)
4126 (&txq->tx_ring[txq->tx_tail]);
4127 fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4128 fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4130 txdp = &txq->tx_ring[txq->tx_tail + 1];
4131 txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4132 td_cmd = ICE_TX_DESC_CMD_EOP |
4133 ICE_TX_DESC_CMD_RS |
4134 ICE_TX_DESC_CMD_DUMMY;
4136 txdp->cmd_type_offset_bsz =
4137 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4140 if (txq->tx_tail >= txq->nb_tx_desc)
4142 /* Update the tx tail register */
4143 ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4144 for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4145 if ((txdp->cmd_type_offset_bsz &
4146 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4147 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4151 if (i >= ICE_FDIR_MAX_WAIT_US) {
4153 "Failed to program FDIR filter: time out to get DD on tx queue.");
4157 for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4160 ret = ice_check_fdir_programming_status(rxq);
4168 "Failed to program FDIR filter: programming status reported.");