1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_ethdev_driver.h>
10 #define ICE_TD_CMD ICE_TX_DESC_CMD_EOP
12 #define ICE_TX_CKSUM_OFFLOAD_MASK ( \
16 PKT_TX_OUTER_IP_CKSUM)
18 #define ICE_RX_ERR_BITS 0x3f
20 static enum ice_status
21 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
23 struct ice_vsi *vsi = rxq->vsi;
24 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
25 struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
26 struct ice_rlan_ctx rx_ctx;
28 uint16_t buf_size, len;
29 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
33 * The kernel driver uses flex descriptor. It sets the register
34 * to flex descriptor mode.
35 * DPDK uses legacy descriptor. It should set the register back
36 * to the default value, then uses legacy descriptor mode.
38 regval = (0x01 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
39 QRXFLXP_CNTXT_RXDID_PRIO_M;
40 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
42 /* Set buffer size as the head split is disabled. */
43 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
44 RTE_PKTMBUF_HEADROOM);
46 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
47 len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
48 rxq->max_pkt_len = RTE_MIN(len,
49 dev->data->dev_conf.rxmode.max_rx_pkt_len);
51 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
52 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
53 rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
54 PMD_DRV_LOG(ERR, "maximum packet length must "
55 "be larger than %u and smaller than %u,"
56 "as jumbo frame is enabled",
57 (uint32_t)ETHER_MAX_LEN,
58 (uint32_t)ICE_FRAME_SIZE_MAX);
62 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
63 rxq->max_pkt_len > ETHER_MAX_LEN) {
64 PMD_DRV_LOG(ERR, "maximum packet length must be "
65 "larger than %u and smaller than %u, "
66 "as jumbo frame is disabled",
67 (uint32_t)ETHER_MIN_LEN,
68 (uint32_t)ETHER_MAX_LEN);
73 memset(&rx_ctx, 0, sizeof(rx_ctx));
75 rx_ctx.base = rxq->rx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
76 rx_ctx.qlen = rxq->nb_rx_desc;
77 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
78 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
79 rx_ctx.dtype = 0; /* No Header Split mode */
80 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
81 rx_ctx.dsize = 1; /* 32B descriptors */
83 rx_ctx.rxmax = rxq->max_pkt_len;
84 /* TPH: Transaction Layer Packet (TLP) processing hints */
85 rx_ctx.tphrdesc_ena = 1;
86 rx_ctx.tphwdesc_ena = 1;
87 rx_ctx.tphdata_ena = 1;
88 rx_ctx.tphhead_ena = 1;
89 /* Low Receive Queue Threshold defined in 64 descriptors units.
90 * When the number of free descriptors goes below the lrxqthresh,
91 * an immediate interrupt is triggered.
93 rx_ctx.lrxqthresh = 2;
94 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
98 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
100 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
104 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
106 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
111 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
112 RTE_PKTMBUF_HEADROOM);
114 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
116 /* Init the Rx tail register*/
117 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
122 /* Allocate mbufs for all descriptors in rx queue */
124 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
126 struct ice_rx_entry *rxe = rxq->sw_ring;
130 for (i = 0; i < rxq->nb_rx_desc; i++) {
131 volatile union ice_rx_desc *rxd;
132 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
134 if (unlikely(!mbuf)) {
135 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
139 rte_mbuf_refcnt_set(mbuf, 1);
141 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
143 mbuf->port = rxq->port_id;
146 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
148 rxd = &rxq->rx_ring[i];
149 rxd->read.pkt_addr = dma_addr;
150 rxd->read.hdr_addr = 0;
151 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
161 /* Free all mbufs for descriptors in rx queue */
163 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
167 if (!rxq || !rxq->sw_ring) {
168 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
172 for (i = 0; i < rxq->nb_rx_desc; i++) {
173 if (rxq->sw_ring[i].mbuf) {
174 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
175 rxq->sw_ring[i].mbuf = NULL;
178 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
179 if (rxq->rx_nb_avail == 0)
181 for (i = 0; i < rxq->rx_nb_avail; i++) {
182 struct rte_mbuf *mbuf;
184 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
185 rte_pktmbuf_free_seg(mbuf);
187 rxq->rx_nb_avail = 0;
188 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
191 /* turn on or off rx queue
192 * @q_idx: queue index in pf scope
193 * @on: turn on or off the queue
196 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
201 /* QRX_CTRL = QRX_ENA */
202 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
205 if (reg & QRX_CTRL_QENA_STAT_M)
206 return 0; /* Already on, skip */
207 reg |= QRX_CTRL_QENA_REQ_M;
209 if (!(reg & QRX_CTRL_QENA_STAT_M))
210 return 0; /* Already off, skip */
211 reg &= ~QRX_CTRL_QENA_REQ_M;
214 /* Write the register */
215 ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
216 /* Check the result. It is said that QENA_STAT
217 * follows the QENA_REQ not more than 10 use.
218 * TODO: need to change the wait counter later
220 for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
221 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
222 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
224 if ((reg & QRX_CTRL_QENA_REQ_M) &&
225 (reg & QRX_CTRL_QENA_STAT_M))
228 if (!(reg & QRX_CTRL_QENA_REQ_M) &&
229 !(reg & QRX_CTRL_QENA_STAT_M))
234 /* Check if it is timeout */
235 if (j >= ICE_CHK_Q_ENA_COUNT) {
236 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
237 (on ? "enable" : "disable"), q_idx);
245 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
246 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
248 ice_check_rx_burst_bulk_alloc_preconditions
249 (__rte_unused struct ice_rx_queue *rxq)
254 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
255 if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
256 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
257 "rxq->rx_free_thresh=%d, "
258 "ICE_RX_MAX_BURST=%d",
259 rxq->rx_free_thresh, ICE_RX_MAX_BURST);
261 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
262 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
263 "rxq->rx_free_thresh=%d, "
264 "rxq->nb_rx_desc=%d",
265 rxq->rx_free_thresh, rxq->nb_rx_desc);
267 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
268 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
269 "rxq->nb_rx_desc=%d, "
270 "rxq->rx_free_thresh=%d",
271 rxq->nb_rx_desc, rxq->rx_free_thresh);
281 /* reset fields in ice_rx_queue back to default */
283 ice_reset_rx_queue(struct ice_rx_queue *rxq)
289 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
293 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
294 if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
295 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
297 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
298 len = rxq->nb_rx_desc;
300 for (i = 0; i < len * sizeof(union ice_rx_desc); i++)
301 ((volatile char *)rxq->rx_ring)[i] = 0;
303 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
304 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
305 for (i = 0; i < ICE_RX_MAX_BURST; ++i)
306 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
308 rxq->rx_nb_avail = 0;
309 rxq->rx_next_avail = 0;
310 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
311 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
315 rxq->pkt_first_seg = NULL;
316 rxq->pkt_last_seg = NULL;
320 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
322 struct ice_rx_queue *rxq;
324 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
326 PMD_INIT_FUNC_TRACE();
328 if (rx_queue_id >= dev->data->nb_rx_queues) {
329 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
330 rx_queue_id, dev->data->nb_rx_queues);
334 rxq = dev->data->rx_queues[rx_queue_id];
335 if (!rxq || !rxq->q_set) {
336 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
341 err = ice_program_hw_rx_queue(rxq);
343 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
348 err = ice_alloc_rx_queue_mbufs(rxq);
350 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
356 /* Init the RX tail register. */
357 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
359 err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
361 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
364 ice_rx_queue_release_mbufs(rxq);
365 ice_reset_rx_queue(rxq);
369 dev->data->rx_queue_state[rx_queue_id] =
370 RTE_ETH_QUEUE_STATE_STARTED;
376 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
378 struct ice_rx_queue *rxq;
380 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
382 if (rx_queue_id < dev->data->nb_rx_queues) {
383 rxq = dev->data->rx_queues[rx_queue_id];
385 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
387 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
391 ice_rx_queue_release_mbufs(rxq);
392 ice_reset_rx_queue(rxq);
393 dev->data->rx_queue_state[rx_queue_id] =
394 RTE_ETH_QUEUE_STATE_STOPPED;
401 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
403 struct ice_tx_queue *txq;
407 struct ice_aqc_add_tx_qgrp txq_elem;
408 struct ice_tlan_ctx tx_ctx;
410 PMD_INIT_FUNC_TRACE();
412 if (tx_queue_id >= dev->data->nb_tx_queues) {
413 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
414 tx_queue_id, dev->data->nb_tx_queues);
418 txq = dev->data->tx_queues[tx_queue_id];
419 if (!txq || !txq->q_set) {
420 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
426 hw = ICE_VSI_TO_HW(vsi);
428 memset(&txq_elem, 0, sizeof(txq_elem));
429 memset(&tx_ctx, 0, sizeof(tx_ctx));
430 txq_elem.num_txqs = 1;
431 txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
433 tx_ctx.base = txq->tx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
434 tx_ctx.qlen = txq->nb_tx_desc;
435 tx_ctx.pf_num = hw->pf_id;
436 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
437 tx_ctx.src_vsi = vsi->vsi_id;
438 tx_ctx.port_num = hw->port_info->lport;
439 tx_ctx.tso_ena = 1; /* tso enable */
440 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
441 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
443 ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
446 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
448 /* Init the Tx tail register*/
449 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
451 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, 1, &txq_elem,
452 sizeof(txq_elem), NULL);
454 PMD_DRV_LOG(ERR, "Failed to add lan txq");
457 /* store the schedule node id */
458 txq->q_teid = txq_elem.txqs[0].q_teid;
460 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
464 /* Free all mbufs for descriptors in tx queue */
466 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
470 if (!txq || !txq->sw_ring) {
471 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
475 for (i = 0; i < txq->nb_tx_desc; i++) {
476 if (txq->sw_ring[i].mbuf) {
477 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
478 txq->sw_ring[i].mbuf = NULL;
484 ice_reset_tx_queue(struct ice_tx_queue *txq)
486 struct ice_tx_entry *txe;
487 uint16_t i, prev, size;
490 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
495 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
496 for (i = 0; i < size; i++)
497 ((volatile char *)txq->tx_ring)[i] = 0;
499 prev = (uint16_t)(txq->nb_tx_desc - 1);
500 for (i = 0; i < txq->nb_tx_desc; i++) {
501 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
503 txd->cmd_type_offset_bsz =
504 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
507 txe[prev].next_id = i;
511 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
512 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
517 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
518 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
522 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
524 struct ice_tx_queue *txq;
525 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
526 enum ice_status status;
530 if (tx_queue_id >= dev->data->nb_tx_queues) {
531 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
532 tx_queue_id, dev->data->nb_tx_queues);
536 txq = dev->data->tx_queues[tx_queue_id];
538 PMD_DRV_LOG(ERR, "TX queue %u is not available",
543 q_ids[0] = txq->reg_idx;
544 q_teids[0] = txq->q_teid;
546 status = ice_dis_vsi_txq(hw->port_info, 1, q_ids, q_teids,
547 ICE_NO_RESET, 0, NULL);
548 if (status != ICE_SUCCESS) {
549 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
553 ice_tx_queue_release_mbufs(txq);
554 ice_reset_tx_queue(txq);
555 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
561 ice_rx_queue_setup(struct rte_eth_dev *dev,
564 unsigned int socket_id,
565 const struct rte_eth_rxconf *rx_conf,
566 struct rte_mempool *mp)
568 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
569 struct ice_adapter *ad =
570 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
571 struct ice_vsi *vsi = pf->main_vsi;
572 struct ice_rx_queue *rxq;
573 const struct rte_memzone *rz;
576 int use_def_burst_func = 1;
578 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
579 nb_desc > ICE_MAX_RING_DESC ||
580 nb_desc < ICE_MIN_RING_DESC) {
581 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
586 /* Free memory if needed */
587 if (dev->data->rx_queues[queue_idx]) {
588 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
589 dev->data->rx_queues[queue_idx] = NULL;
592 /* Allocate the rx queue data structure */
593 rxq = rte_zmalloc_socket(NULL,
594 sizeof(struct ice_rx_queue),
598 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
599 "rx queue data structure");
603 rxq->nb_rx_desc = nb_desc;
604 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
605 rxq->queue_id = queue_idx;
607 rxq->reg_idx = vsi->base_queue + queue_idx;
608 rxq->port_id = dev->data->port_id;
609 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
610 rxq->crc_len = ETHER_CRC_LEN;
614 rxq->drop_en = rx_conf->rx_drop_en;
616 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
618 /* Allocate the maximun number of RX ring hardware descriptor. */
619 len = ICE_MAX_RING_DESC;
621 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
623 * Allocating a little more memory because vectorized/bulk_alloc Rx
624 * functions doesn't check boundaries each time.
626 len += ICE_RX_MAX_BURST;
629 /* Allocate the maximum number of RX ring hardware descriptor. */
630 ring_size = sizeof(union ice_rx_desc) * len;
631 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
632 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
633 ring_size, ICE_RING_BASE_ALIGN,
636 ice_rx_queue_release(rxq);
637 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
641 /* Zero all the descriptors in the ring. */
642 memset(rz->addr, 0, ring_size);
644 rxq->rx_ring_phys_addr = rz->phys_addr;
645 rxq->rx_ring = (union ice_rx_desc *)rz->addr;
647 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
648 len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
653 /* Allocate the software ring. */
654 rxq->sw_ring = rte_zmalloc_socket(NULL,
655 sizeof(struct ice_rx_entry) * len,
659 ice_rx_queue_release(rxq);
660 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
664 ice_reset_rx_queue(rxq);
666 dev->data->rx_queues[queue_idx] = rxq;
668 use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
670 if (!use_def_burst_func) {
671 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
672 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
673 "satisfied. Rx Burst Bulk Alloc function will be "
674 "used on port=%d, queue=%d.",
675 rxq->port_id, rxq->queue_id);
676 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
678 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
679 "not satisfied, Scattered Rx is requested, "
680 "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
681 "not enabled on port=%d, queue=%d.",
682 rxq->port_id, rxq->queue_id);
683 ad->rx_bulk_alloc_allowed = false;
690 ice_rx_queue_release(void *rxq)
692 struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
695 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
699 ice_rx_queue_release_mbufs(q);
700 rte_free(q->sw_ring);
705 ice_tx_queue_setup(struct rte_eth_dev *dev,
708 unsigned int socket_id,
709 const struct rte_eth_txconf *tx_conf)
711 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
712 struct ice_vsi *vsi = pf->main_vsi;
713 struct ice_tx_queue *txq;
714 const struct rte_memzone *tz;
716 uint16_t tx_rs_thresh, tx_free_thresh;
719 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
721 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
722 nb_desc > ICE_MAX_RING_DESC ||
723 nb_desc < ICE_MIN_RING_DESC) {
724 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
730 * The following two parameters control the setting of the RS bit on
731 * transmit descriptors. TX descriptors will have their RS bit set
732 * after txq->tx_rs_thresh descriptors have been used. The TX
733 * descriptor ring will be cleaned after txq->tx_free_thresh
734 * descriptors are used or if the number of descriptors required to
735 * transmit a packet is greater than the number of free TX descriptors.
737 * The following constraints must be satisfied:
738 * - tx_rs_thresh must be greater than 0.
739 * - tx_rs_thresh must be less than the size of the ring minus 2.
740 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
741 * - tx_rs_thresh must be a divisor of the ring size.
742 * - tx_free_thresh must be greater than 0.
743 * - tx_free_thresh must be less than the size of the ring minus 3.
745 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
746 * race condition, hence the maximum threshold constraints. When set
747 * to zero use default values.
749 tx_rs_thresh = (uint16_t)(tx_conf->tx_rs_thresh ?
750 tx_conf->tx_rs_thresh :
751 ICE_DEFAULT_TX_RSBIT_THRESH);
752 tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
753 tx_conf->tx_free_thresh :
754 ICE_DEFAULT_TX_FREE_THRESH);
755 if (tx_rs_thresh >= (nb_desc - 2)) {
756 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
757 "number of TX descriptors minus 2. "
758 "(tx_rs_thresh=%u port=%d queue=%d)",
759 (unsigned int)tx_rs_thresh,
760 (int)dev->data->port_id,
764 if (tx_free_thresh >= (nb_desc - 3)) {
765 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
766 "tx_free_thresh must be less than the "
767 "number of TX descriptors minus 3. "
768 "(tx_free_thresh=%u port=%d queue=%d)",
769 (unsigned int)tx_free_thresh,
770 (int)dev->data->port_id,
774 if (tx_rs_thresh > tx_free_thresh) {
775 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
776 "equal to tx_free_thresh. (tx_free_thresh=%u"
777 " tx_rs_thresh=%u port=%d queue=%d)",
778 (unsigned int)tx_free_thresh,
779 (unsigned int)tx_rs_thresh,
780 (int)dev->data->port_id,
784 if ((nb_desc % tx_rs_thresh) != 0) {
785 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
786 "number of TX descriptors. (tx_rs_thresh=%u"
787 " port=%d queue=%d)",
788 (unsigned int)tx_rs_thresh,
789 (int)dev->data->port_id,
793 if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
794 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
795 "tx_rs_thresh is greater than 1. "
796 "(tx_rs_thresh=%u port=%d queue=%d)",
797 (unsigned int)tx_rs_thresh,
798 (int)dev->data->port_id,
803 /* Free memory if needed. */
804 if (dev->data->tx_queues[queue_idx]) {
805 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
806 dev->data->tx_queues[queue_idx] = NULL;
809 /* Allocate the TX queue data structure. */
810 txq = rte_zmalloc_socket(NULL,
811 sizeof(struct ice_tx_queue),
815 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
816 "tx queue structure");
820 /* Allocate TX hardware ring descriptors. */
821 ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
822 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
823 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
824 ring_size, ICE_RING_BASE_ALIGN,
827 ice_tx_queue_release(txq);
828 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
832 txq->nb_tx_desc = nb_desc;
833 txq->tx_rs_thresh = tx_rs_thresh;
834 txq->tx_free_thresh = tx_free_thresh;
835 txq->pthresh = tx_conf->tx_thresh.pthresh;
836 txq->hthresh = tx_conf->tx_thresh.hthresh;
837 txq->wthresh = tx_conf->tx_thresh.wthresh;
838 txq->queue_id = queue_idx;
840 txq->reg_idx = vsi->base_queue + queue_idx;
841 txq->port_id = dev->data->port_id;
842 txq->offloads = offloads;
844 txq->tx_deferred_start = tx_conf->tx_deferred_start;
846 txq->tx_ring_phys_addr = tz->phys_addr;
847 txq->tx_ring = (struct ice_tx_desc *)tz->addr;
849 /* Allocate software ring */
851 rte_zmalloc_socket(NULL,
852 sizeof(struct ice_tx_entry) * nb_desc,
856 ice_tx_queue_release(txq);
857 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
861 ice_reset_tx_queue(txq);
863 dev->data->tx_queues[queue_idx] = txq;
869 ice_tx_queue_release(void *txq)
871 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
874 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
878 ice_tx_queue_release_mbufs(q);
879 rte_free(q->sw_ring);
884 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
885 struct rte_eth_rxq_info *qinfo)
887 struct ice_rx_queue *rxq;
889 rxq = dev->data->rx_queues[queue_id];
892 qinfo->scattered_rx = dev->data->scattered_rx;
893 qinfo->nb_desc = rxq->nb_rx_desc;
895 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
896 qinfo->conf.rx_drop_en = rxq->drop_en;
897 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
901 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
902 struct rte_eth_txq_info *qinfo)
904 struct ice_tx_queue *txq;
906 txq = dev->data->tx_queues[queue_id];
908 qinfo->nb_desc = txq->nb_tx_desc;
910 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
911 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
912 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
914 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
915 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
916 qinfo->conf.offloads = txq->offloads;
917 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
921 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
923 #define ICE_RXQ_SCAN_INTERVAL 4
924 volatile union ice_rx_desc *rxdp;
925 struct ice_rx_queue *rxq;
928 rxq = dev->data->rx_queues[rx_queue_id];
929 rxdp = &rxq->rx_ring[rxq->rx_tail];
930 while ((desc < rxq->nb_rx_desc) &&
931 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
932 ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S) &
933 (1 << ICE_RX_DESC_STATUS_DD_S)) {
935 * Check the DD bit of a rx descriptor of each 4 in a group,
936 * to avoid checking too frequently and downgrading performance
939 desc += ICE_RXQ_SCAN_INTERVAL;
940 rxdp += ICE_RXQ_SCAN_INTERVAL;
941 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
942 rxdp = &(rxq->rx_ring[rxq->rx_tail +
943 desc - rxq->nb_rx_desc]);
950 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev __rte_unused)
952 static const uint32_t ptypes[] = {
953 /* refers to ice_get_default_pkt_type() */
955 RTE_PTYPE_L2_ETHER_LLDP,
956 RTE_PTYPE_L2_ETHER_ARP,
957 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
958 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
961 RTE_PTYPE_L4_NONFRAG,
965 RTE_PTYPE_TUNNEL_GRENAT,
967 RTE_PTYPE_INNER_L2_ETHER,
968 RTE_PTYPE_INNER_L2_ETHER_VLAN,
969 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
970 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
971 RTE_PTYPE_INNER_L4_FRAG,
972 RTE_PTYPE_INNER_L4_ICMP,
973 RTE_PTYPE_INNER_L4_NONFRAG,
974 RTE_PTYPE_INNER_L4_SCTP,
975 RTE_PTYPE_INNER_L4_TCP,
976 RTE_PTYPE_INNER_L4_UDP,
977 RTE_PTYPE_TUNNEL_GTPC,
978 RTE_PTYPE_TUNNEL_GTPU,
986 ice_clear_queues(struct rte_eth_dev *dev)
990 PMD_INIT_FUNC_TRACE();
992 for (i = 0; i < dev->data->nb_tx_queues; i++) {
993 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
994 ice_reset_tx_queue(dev->data->tx_queues[i]);
997 for (i = 0; i < dev->data->nb_rx_queues; i++) {
998 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
999 ice_reset_rx_queue(dev->data->rx_queues[i]);
1004 ice_free_queues(struct rte_eth_dev *dev)
1008 PMD_INIT_FUNC_TRACE();
1010 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1011 if (!dev->data->rx_queues[i])
1013 ice_rx_queue_release(dev->data->rx_queues[i]);
1014 dev->data->rx_queues[i] = NULL;
1016 dev->data->nb_rx_queues = 0;
1018 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1019 if (!dev->data->tx_queues[i])
1021 ice_tx_queue_release(dev->data->tx_queues[i]);
1022 dev->data->tx_queues[i] = NULL;
1024 dev->data->nb_tx_queues = 0;
1027 /* For each value it means, datasheet of hardware can tell more details
1029 * @note: fix ice_dev_supported_ptypes_get() if any change here.
1031 static inline uint32_t
1032 ice_get_default_pkt_type(uint16_t ptype)
1034 static const uint32_t type_table[ICE_MAX_PKT_TYPE]
1035 __rte_cache_aligned = {
1038 [1] = RTE_PTYPE_L2_ETHER,
1039 /* [2] - [5] reserved */
1040 [6] = RTE_PTYPE_L2_ETHER_LLDP,
1041 /* [7] - [10] reserved */
1042 [11] = RTE_PTYPE_L2_ETHER_ARP,
1043 /* [12] - [21] reserved */
1045 /* Non tunneled IPv4 */
1046 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1048 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1049 RTE_PTYPE_L4_NONFRAG,
1050 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1053 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1055 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1057 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1061 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1062 RTE_PTYPE_TUNNEL_IP |
1063 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1064 RTE_PTYPE_INNER_L4_FRAG,
1065 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1066 RTE_PTYPE_TUNNEL_IP |
1067 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1068 RTE_PTYPE_INNER_L4_NONFRAG,
1069 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1070 RTE_PTYPE_TUNNEL_IP |
1071 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1072 RTE_PTYPE_INNER_L4_UDP,
1074 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1075 RTE_PTYPE_TUNNEL_IP |
1076 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1077 RTE_PTYPE_INNER_L4_TCP,
1078 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1079 RTE_PTYPE_TUNNEL_IP |
1080 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1081 RTE_PTYPE_INNER_L4_SCTP,
1082 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1083 RTE_PTYPE_TUNNEL_IP |
1084 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1085 RTE_PTYPE_INNER_L4_ICMP,
1088 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1089 RTE_PTYPE_TUNNEL_IP |
1090 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1091 RTE_PTYPE_INNER_L4_FRAG,
1092 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1093 RTE_PTYPE_TUNNEL_IP |
1094 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1095 RTE_PTYPE_INNER_L4_NONFRAG,
1096 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1097 RTE_PTYPE_TUNNEL_IP |
1098 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1099 RTE_PTYPE_INNER_L4_UDP,
1101 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1102 RTE_PTYPE_TUNNEL_IP |
1103 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1104 RTE_PTYPE_INNER_L4_TCP,
1105 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1106 RTE_PTYPE_TUNNEL_IP |
1107 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1108 RTE_PTYPE_INNER_L4_SCTP,
1109 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1110 RTE_PTYPE_TUNNEL_IP |
1111 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1112 RTE_PTYPE_INNER_L4_ICMP,
1114 /* IPv4 --> GRE/Teredo/VXLAN */
1115 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1116 RTE_PTYPE_TUNNEL_GRENAT,
1118 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
1119 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1120 RTE_PTYPE_TUNNEL_GRENAT |
1121 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1122 RTE_PTYPE_INNER_L4_FRAG,
1123 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1124 RTE_PTYPE_TUNNEL_GRENAT |
1125 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1126 RTE_PTYPE_INNER_L4_NONFRAG,
1127 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1128 RTE_PTYPE_TUNNEL_GRENAT |
1129 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1130 RTE_PTYPE_INNER_L4_UDP,
1132 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1133 RTE_PTYPE_TUNNEL_GRENAT |
1134 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1135 RTE_PTYPE_INNER_L4_TCP,
1136 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1137 RTE_PTYPE_TUNNEL_GRENAT |
1138 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1139 RTE_PTYPE_INNER_L4_SCTP,
1140 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1141 RTE_PTYPE_TUNNEL_GRENAT |
1142 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1143 RTE_PTYPE_INNER_L4_ICMP,
1145 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
1146 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1147 RTE_PTYPE_TUNNEL_GRENAT |
1148 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1149 RTE_PTYPE_INNER_L4_FRAG,
1150 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1151 RTE_PTYPE_TUNNEL_GRENAT |
1152 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1153 RTE_PTYPE_INNER_L4_NONFRAG,
1154 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1155 RTE_PTYPE_TUNNEL_GRENAT |
1156 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1157 RTE_PTYPE_INNER_L4_UDP,
1159 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1160 RTE_PTYPE_TUNNEL_GRENAT |
1161 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1162 RTE_PTYPE_INNER_L4_TCP,
1163 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1164 RTE_PTYPE_TUNNEL_GRENAT |
1165 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1166 RTE_PTYPE_INNER_L4_SCTP,
1167 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1168 RTE_PTYPE_TUNNEL_GRENAT |
1169 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1170 RTE_PTYPE_INNER_L4_ICMP,
1172 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
1173 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1174 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
1176 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
1177 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1178 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1179 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1180 RTE_PTYPE_INNER_L4_FRAG,
1181 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1182 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1183 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1184 RTE_PTYPE_INNER_L4_NONFRAG,
1185 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1186 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1187 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1188 RTE_PTYPE_INNER_L4_UDP,
1190 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1191 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1192 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1193 RTE_PTYPE_INNER_L4_TCP,
1194 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1195 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1196 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1197 RTE_PTYPE_INNER_L4_SCTP,
1198 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1199 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1201 RTE_PTYPE_INNER_L4_ICMP,
1203 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
1204 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1205 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1206 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1207 RTE_PTYPE_INNER_L4_FRAG,
1208 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1209 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1210 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1211 RTE_PTYPE_INNER_L4_NONFRAG,
1212 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1213 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1214 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1215 RTE_PTYPE_INNER_L4_UDP,
1217 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1218 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1219 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1220 RTE_PTYPE_INNER_L4_TCP,
1221 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1222 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1223 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1224 RTE_PTYPE_INNER_L4_SCTP,
1225 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1226 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1227 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1228 RTE_PTYPE_INNER_L4_ICMP,
1230 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
1231 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1232 RTE_PTYPE_TUNNEL_GRENAT |
1233 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1235 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
1236 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1237 RTE_PTYPE_TUNNEL_GRENAT |
1238 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1239 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1240 RTE_PTYPE_INNER_L4_FRAG,
1241 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1242 RTE_PTYPE_TUNNEL_GRENAT |
1243 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1244 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1245 RTE_PTYPE_INNER_L4_NONFRAG,
1246 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1247 RTE_PTYPE_TUNNEL_GRENAT |
1248 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1249 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1250 RTE_PTYPE_INNER_L4_UDP,
1252 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1253 RTE_PTYPE_TUNNEL_GRENAT |
1254 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1255 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1256 RTE_PTYPE_INNER_L4_TCP,
1257 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1258 RTE_PTYPE_TUNNEL_GRENAT |
1259 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1260 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1261 RTE_PTYPE_INNER_L4_SCTP,
1262 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1263 RTE_PTYPE_TUNNEL_GRENAT |
1264 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1265 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1266 RTE_PTYPE_INNER_L4_ICMP,
1268 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
1269 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1270 RTE_PTYPE_TUNNEL_GRENAT |
1271 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1272 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1273 RTE_PTYPE_INNER_L4_FRAG,
1274 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1275 RTE_PTYPE_TUNNEL_GRENAT |
1276 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1277 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1278 RTE_PTYPE_INNER_L4_NONFRAG,
1279 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1280 RTE_PTYPE_TUNNEL_GRENAT |
1281 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1282 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1283 RTE_PTYPE_INNER_L4_UDP,
1285 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1286 RTE_PTYPE_TUNNEL_GRENAT |
1287 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1288 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1289 RTE_PTYPE_INNER_L4_TCP,
1290 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1291 RTE_PTYPE_TUNNEL_GRENAT |
1292 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1293 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1294 RTE_PTYPE_INNER_L4_SCTP,
1295 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1296 RTE_PTYPE_TUNNEL_GRENAT |
1297 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1298 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1299 RTE_PTYPE_INNER_L4_ICMP,
1301 /* Non tunneled IPv6 */
1302 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1304 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1305 RTE_PTYPE_L4_NONFRAG,
1306 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1309 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1311 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1313 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1317 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1318 RTE_PTYPE_TUNNEL_IP |
1319 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1320 RTE_PTYPE_INNER_L4_FRAG,
1321 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1322 RTE_PTYPE_TUNNEL_IP |
1323 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1324 RTE_PTYPE_INNER_L4_NONFRAG,
1325 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1326 RTE_PTYPE_TUNNEL_IP |
1327 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1328 RTE_PTYPE_INNER_L4_UDP,
1330 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1331 RTE_PTYPE_TUNNEL_IP |
1332 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1333 RTE_PTYPE_INNER_L4_TCP,
1334 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1335 RTE_PTYPE_TUNNEL_IP |
1336 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1337 RTE_PTYPE_INNER_L4_SCTP,
1338 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1339 RTE_PTYPE_TUNNEL_IP |
1340 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1341 RTE_PTYPE_INNER_L4_ICMP,
1344 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1345 RTE_PTYPE_TUNNEL_IP |
1346 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1347 RTE_PTYPE_INNER_L4_FRAG,
1348 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1349 RTE_PTYPE_TUNNEL_IP |
1350 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1351 RTE_PTYPE_INNER_L4_NONFRAG,
1352 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1353 RTE_PTYPE_TUNNEL_IP |
1354 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1355 RTE_PTYPE_INNER_L4_UDP,
1356 /* [105] reserved */
1357 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1358 RTE_PTYPE_TUNNEL_IP |
1359 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1360 RTE_PTYPE_INNER_L4_TCP,
1361 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1362 RTE_PTYPE_TUNNEL_IP |
1363 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1364 RTE_PTYPE_INNER_L4_SCTP,
1365 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1366 RTE_PTYPE_TUNNEL_IP |
1367 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1368 RTE_PTYPE_INNER_L4_ICMP,
1370 /* IPv6 --> GRE/Teredo/VXLAN */
1371 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1372 RTE_PTYPE_TUNNEL_GRENAT,
1374 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
1375 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1376 RTE_PTYPE_TUNNEL_GRENAT |
1377 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1378 RTE_PTYPE_INNER_L4_FRAG,
1379 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1380 RTE_PTYPE_TUNNEL_GRENAT |
1381 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1382 RTE_PTYPE_INNER_L4_NONFRAG,
1383 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1384 RTE_PTYPE_TUNNEL_GRENAT |
1385 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1386 RTE_PTYPE_INNER_L4_UDP,
1387 /* [113] reserved */
1388 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1389 RTE_PTYPE_TUNNEL_GRENAT |
1390 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1391 RTE_PTYPE_INNER_L4_TCP,
1392 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1393 RTE_PTYPE_TUNNEL_GRENAT |
1394 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1395 RTE_PTYPE_INNER_L4_SCTP,
1396 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1397 RTE_PTYPE_TUNNEL_GRENAT |
1398 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1399 RTE_PTYPE_INNER_L4_ICMP,
1401 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
1402 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1403 RTE_PTYPE_TUNNEL_GRENAT |
1404 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1405 RTE_PTYPE_INNER_L4_FRAG,
1406 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1407 RTE_PTYPE_TUNNEL_GRENAT |
1408 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1409 RTE_PTYPE_INNER_L4_NONFRAG,
1410 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1411 RTE_PTYPE_TUNNEL_GRENAT |
1412 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1413 RTE_PTYPE_INNER_L4_UDP,
1414 /* [120] reserved */
1415 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1416 RTE_PTYPE_TUNNEL_GRENAT |
1417 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1418 RTE_PTYPE_INNER_L4_TCP,
1419 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1420 RTE_PTYPE_TUNNEL_GRENAT |
1421 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1422 RTE_PTYPE_INNER_L4_SCTP,
1423 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1424 RTE_PTYPE_TUNNEL_GRENAT |
1425 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1426 RTE_PTYPE_INNER_L4_ICMP,
1428 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
1429 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1430 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
1432 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
1433 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1434 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1435 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1436 RTE_PTYPE_INNER_L4_FRAG,
1437 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1438 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1439 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1440 RTE_PTYPE_INNER_L4_NONFRAG,
1441 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1442 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1443 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1444 RTE_PTYPE_INNER_L4_UDP,
1445 /* [128] reserved */
1446 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1447 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1448 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1449 RTE_PTYPE_INNER_L4_TCP,
1450 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1451 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1452 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1453 RTE_PTYPE_INNER_L4_SCTP,
1454 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1455 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1456 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1457 RTE_PTYPE_INNER_L4_ICMP,
1459 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
1460 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1461 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1462 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1463 RTE_PTYPE_INNER_L4_FRAG,
1464 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1465 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1466 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1467 RTE_PTYPE_INNER_L4_NONFRAG,
1468 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1469 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1470 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1471 RTE_PTYPE_INNER_L4_UDP,
1472 /* [135] reserved */
1473 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1474 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1475 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1476 RTE_PTYPE_INNER_L4_TCP,
1477 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1478 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1479 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1480 RTE_PTYPE_INNER_L4_SCTP,
1481 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1482 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
1483 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1484 RTE_PTYPE_INNER_L4_ICMP,
1486 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
1487 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1488 RTE_PTYPE_TUNNEL_GRENAT |
1489 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1491 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
1492 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1493 RTE_PTYPE_TUNNEL_GRENAT |
1494 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1495 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1496 RTE_PTYPE_INNER_L4_FRAG,
1497 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1498 RTE_PTYPE_TUNNEL_GRENAT |
1499 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1500 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1501 RTE_PTYPE_INNER_L4_NONFRAG,
1502 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1503 RTE_PTYPE_TUNNEL_GRENAT |
1504 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1505 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1506 RTE_PTYPE_INNER_L4_UDP,
1507 /* [143] reserved */
1508 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1509 RTE_PTYPE_TUNNEL_GRENAT |
1510 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1511 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1512 RTE_PTYPE_INNER_L4_TCP,
1513 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1514 RTE_PTYPE_TUNNEL_GRENAT |
1515 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1516 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1517 RTE_PTYPE_INNER_L4_SCTP,
1518 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1519 RTE_PTYPE_TUNNEL_GRENAT |
1520 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1521 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
1522 RTE_PTYPE_INNER_L4_ICMP,
1524 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
1525 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1526 RTE_PTYPE_TUNNEL_GRENAT |
1527 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1528 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1529 RTE_PTYPE_INNER_L4_FRAG,
1530 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1531 RTE_PTYPE_TUNNEL_GRENAT |
1532 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1533 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1534 RTE_PTYPE_INNER_L4_NONFRAG,
1535 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1536 RTE_PTYPE_TUNNEL_GRENAT |
1537 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1538 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1539 RTE_PTYPE_INNER_L4_UDP,
1540 /* [150] reserved */
1541 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1542 RTE_PTYPE_TUNNEL_GRENAT |
1543 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1544 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1545 RTE_PTYPE_INNER_L4_TCP,
1546 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1547 RTE_PTYPE_TUNNEL_GRENAT |
1548 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1549 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1550 RTE_PTYPE_INNER_L4_SCTP,
1551 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1552 RTE_PTYPE_TUNNEL_GRENAT |
1553 RTE_PTYPE_INNER_L2_ETHER_VLAN |
1554 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
1555 RTE_PTYPE_INNER_L4_ICMP,
1556 /* [154] - [255] reserved */
1557 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1558 RTE_PTYPE_TUNNEL_GTPC,
1559 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1560 RTE_PTYPE_TUNNEL_GTPC,
1561 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1562 RTE_PTYPE_TUNNEL_GTPU,
1563 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
1564 RTE_PTYPE_TUNNEL_GTPU,
1565 /* [260] - [263] reserved */
1566 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1567 RTE_PTYPE_TUNNEL_GTPC,
1568 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1569 RTE_PTYPE_TUNNEL_GTPC,
1570 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1571 RTE_PTYPE_TUNNEL_GTPU,
1572 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
1573 RTE_PTYPE_TUNNEL_GTPU,
1575 /* All others reserved */
1578 return type_table[ptype];
1581 void __attribute__((cold))
1582 ice_set_default_ptype_table(struct rte_eth_dev *dev)
1584 struct ice_adapter *ad =
1585 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1588 for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
1589 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);