1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <ethdev_driver.h>
9 #include "rte_pmd_ice.h"
11 #include "ice_rxtx_vec_common.h"
13 #define ICE_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM | \
14 RTE_MBUF_F_TX_L4_MASK | \
15 RTE_MBUF_F_TX_TCP_SEG | \
16 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
18 /* Offset of mbuf dynamic field for protocol extraction data */
19 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
21 /* Mask of mbuf dynamic flags for protocol extraction type */
22 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
26 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
27 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
30 ice_monitor_callback(const uint64_t value,
31 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
33 const uint64_t m = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
35 * we expect the DD bit to be set to 1 if this descriptor was already
38 return (value & m) == m ? -1 : 0;
42 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
44 volatile union ice_rx_flex_desc *rxdp;
45 struct ice_rx_queue *rxq = rx_queue;
49 rxdp = &rxq->rx_ring[desc];
50 /* watch for changes in status bit */
51 pmc->addr = &rxdp->wb.status_error0;
53 /* comparison callback */
54 pmc->fn = ice_monitor_callback;
56 /* register is 16-bit */
57 pmc->size = sizeof(uint16_t);
64 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
66 static uint8_t rxdid_map[] = {
67 [PROTO_XTR_NONE] = ICE_RXDID_COMMS_OVS,
68 [PROTO_XTR_VLAN] = ICE_RXDID_COMMS_AUX_VLAN,
69 [PROTO_XTR_IPV4] = ICE_RXDID_COMMS_AUX_IPV4,
70 [PROTO_XTR_IPV6] = ICE_RXDID_COMMS_AUX_IPV6,
71 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
72 [PROTO_XTR_TCP] = ICE_RXDID_COMMS_AUX_TCP,
73 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
76 return xtr_type < RTE_DIM(rxdid_map) ?
77 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
81 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
83 volatile union ice_rx_flex_desc *rxdp)
85 volatile struct ice_32b_rx_flex_desc_comms *desc =
86 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
87 uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
89 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
90 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
91 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
94 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
95 if (desc->flow_id != 0xFFFFFFFF) {
96 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
97 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
103 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
105 volatile union ice_rx_flex_desc *rxdp)
107 volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
108 (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
109 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
113 if (desc->flow_id != 0xFFFFFFFF) {
114 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
115 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
118 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
119 stat_err = rte_le_to_cpu_16(desc->status_error0);
120 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
121 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
122 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
128 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
130 volatile union ice_rx_flex_desc *rxdp)
132 volatile struct ice_32b_rx_flex_desc_comms *desc =
133 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
136 stat_err = rte_le_to_cpu_16(desc->status_error0);
137 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
138 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
139 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
142 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
143 if (desc->flow_id != 0xFFFFFFFF) {
144 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
145 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
148 if (rxq->xtr_ol_flag) {
149 uint32_t metadata = 0;
151 stat_err = rte_le_to_cpu_16(desc->status_error1);
153 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
154 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
156 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
158 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
161 mb->ol_flags |= rxq->xtr_ol_flag;
163 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
170 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
172 volatile union ice_rx_flex_desc *rxdp)
174 volatile struct ice_32b_rx_flex_desc_comms *desc =
175 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
178 stat_err = rte_le_to_cpu_16(desc->status_error0);
179 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
180 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
181 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
184 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
185 if (desc->flow_id != 0xFFFFFFFF) {
186 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
187 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
190 if (rxq->xtr_ol_flag) {
191 uint32_t metadata = 0;
193 if (desc->flex_ts.flex.aux0 != 0xFFFF)
194 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
195 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
196 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
199 mb->ol_flags |= rxq->xtr_ol_flag;
201 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
207 static const ice_rxd_to_pkt_fields_t rxd_to_pkt_fields_ops[] = {
208 [ICE_RXDID_COMMS_AUX_VLAN] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
209 [ICE_RXDID_COMMS_AUX_IPV4] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
210 [ICE_RXDID_COMMS_AUX_IPV6] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
211 [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
212 [ICE_RXDID_COMMS_AUX_TCP] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
213 [ICE_RXDID_COMMS_AUX_IP_OFFSET] = ice_rxd_to_pkt_fields_by_comms_aux_v2,
214 [ICE_RXDID_COMMS_GENERIC] = ice_rxd_to_pkt_fields_by_comms_generic,
215 [ICE_RXDID_COMMS_OVS] = ice_rxd_to_pkt_fields_by_comms_ovs,
219 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
224 case ICE_RXDID_COMMS_AUX_VLAN:
225 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
228 case ICE_RXDID_COMMS_AUX_IPV4:
229 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
232 case ICE_RXDID_COMMS_AUX_IPV6:
233 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
236 case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
237 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
240 case ICE_RXDID_COMMS_AUX_TCP:
241 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
244 case ICE_RXDID_COMMS_AUX_IP_OFFSET:
245 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
248 case ICE_RXDID_COMMS_GENERIC:
250 case ICE_RXDID_COMMS_OVS:
254 /* update this according to the RXDID for PROTO_XTR_NONE */
255 rxq->rxdid = ICE_RXDID_COMMS_OVS;
259 if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
260 rxq->xtr_ol_flag = 0;
263 static enum ice_status
264 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
266 struct ice_vsi *vsi = rxq->vsi;
267 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
268 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
269 struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
270 struct ice_rlan_ctx rx_ctx;
273 uint32_t rxdid = ICE_RXDID_COMMS_OVS;
275 struct ice_adapter *ad = rxq->vsi->adapter;
276 uint32_t frame_size = dev_data->mtu + ICE_ETH_OVERHEAD;
278 /* Set buffer size as the head split is disabled. */
279 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
280 RTE_PKTMBUF_HEADROOM);
282 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
284 RTE_MIN((uint32_t)ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
287 if (rxq->max_pkt_len <= RTE_ETHER_MIN_LEN ||
288 rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
289 PMD_DRV_LOG(ERR, "maximum packet length must "
290 "be larger than %u and smaller than %u",
291 (uint32_t)RTE_ETHER_MIN_LEN,
292 (uint32_t)ICE_FRAME_SIZE_MAX);
296 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
297 /* Register mbuf field and flag for Rx timestamp */
298 err = rte_mbuf_dyn_rx_timestamp_register(
299 &ice_timestamp_dynfield_offset,
300 &ice_timestamp_dynflag);
303 "Cannot register mbuf field/flag for timestamp");
308 memset(&rx_ctx, 0, sizeof(rx_ctx));
310 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
311 rx_ctx.qlen = rxq->nb_rx_desc;
312 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
313 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
314 rx_ctx.dtype = 0; /* No Header Split mode */
315 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
316 rx_ctx.dsize = 1; /* 32B descriptors */
318 rx_ctx.rxmax = rxq->max_pkt_len;
319 /* TPH: Transaction Layer Packet (TLP) processing hints */
320 rx_ctx.tphrdesc_ena = 1;
321 rx_ctx.tphwdesc_ena = 1;
322 rx_ctx.tphdata_ena = 1;
323 rx_ctx.tphhead_ena = 1;
324 /* Low Receive Queue Threshold defined in 64 descriptors units.
325 * When the number of free descriptors goes below the lrxqthresh,
326 * an immediate interrupt is triggered.
328 rx_ctx.lrxqthresh = 2;
329 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
332 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
334 rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
336 PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
337 rxq->port_id, rxq->queue_id, rxdid);
339 if (!(pf->supported_rxdid & BIT(rxdid))) {
340 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
345 ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
347 /* Enable Flexible Descriptors in the queue context which
348 * allows this driver to select a specific receive descriptor format
350 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
351 QRXFLXP_CNTXT_RXDID_IDX_M;
353 /* increasing context priority to pick up profile ID;
354 * default is 0x01; setting to 0x03 to ensure profile
355 * is programming if prev context is of same priority
357 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
358 QRXFLXP_CNTXT_RXDID_PRIO_M;
360 if (ad->ptp_ena || rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
361 regval |= QRXFLXP_CNTXT_TS_M;
363 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
365 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
367 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
371 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
373 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
378 /* Check if scattered RX needs to be used. */
379 if (frame_size > buf_size)
380 dev_data->scattered_rx = 1;
382 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
384 /* Init the Rx tail register*/
385 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
390 /* Allocate mbufs for all descriptors in rx queue */
392 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
394 struct ice_rx_entry *rxe = rxq->sw_ring;
398 for (i = 0; i < rxq->nb_rx_desc; i++) {
399 volatile union ice_rx_flex_desc *rxd;
400 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
402 if (unlikely(!mbuf)) {
403 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
407 rte_mbuf_refcnt_set(mbuf, 1);
409 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
411 mbuf->port = rxq->port_id;
414 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
416 rxd = &rxq->rx_ring[i];
417 rxd->read.pkt_addr = dma_addr;
418 rxd->read.hdr_addr = 0;
419 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
429 /* Free all mbufs for descriptors in rx queue */
431 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
435 if (!rxq || !rxq->sw_ring) {
436 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
440 for (i = 0; i < rxq->nb_rx_desc; i++) {
441 if (rxq->sw_ring[i].mbuf) {
442 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
443 rxq->sw_ring[i].mbuf = NULL;
446 if (rxq->rx_nb_avail == 0)
448 for (i = 0; i < rxq->rx_nb_avail; i++)
449 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
451 rxq->rx_nb_avail = 0;
454 /* turn on or off rx queue
455 * @q_idx: queue index in pf scope
456 * @on: turn on or off the queue
459 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
464 /* QRX_CTRL = QRX_ENA */
465 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
468 if (reg & QRX_CTRL_QENA_STAT_M)
469 return 0; /* Already on, skip */
470 reg |= QRX_CTRL_QENA_REQ_M;
472 if (!(reg & QRX_CTRL_QENA_STAT_M))
473 return 0; /* Already off, skip */
474 reg &= ~QRX_CTRL_QENA_REQ_M;
477 /* Write the register */
478 ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
479 /* Check the result. It is said that QENA_STAT
480 * follows the QENA_REQ not more than 10 use.
481 * TODO: need to change the wait counter later
483 for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
484 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
485 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
487 if ((reg & QRX_CTRL_QENA_REQ_M) &&
488 (reg & QRX_CTRL_QENA_STAT_M))
491 if (!(reg & QRX_CTRL_QENA_REQ_M) &&
492 !(reg & QRX_CTRL_QENA_STAT_M))
497 /* Check if it is timeout */
498 if (j >= ICE_CHK_Q_ENA_COUNT) {
499 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
500 (on ? "enable" : "disable"), q_idx);
508 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
512 if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
513 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
514 "rxq->rx_free_thresh=%d, "
515 "ICE_RX_MAX_BURST=%d",
516 rxq->rx_free_thresh, ICE_RX_MAX_BURST);
518 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
519 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
520 "rxq->rx_free_thresh=%d, "
521 "rxq->nb_rx_desc=%d",
522 rxq->rx_free_thresh, rxq->nb_rx_desc);
524 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
525 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
526 "rxq->nb_rx_desc=%d, "
527 "rxq->rx_free_thresh=%d",
528 rxq->nb_rx_desc, rxq->rx_free_thresh);
535 /* reset fields in ice_rx_queue back to default */
537 ice_reset_rx_queue(struct ice_rx_queue *rxq)
543 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
547 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
549 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
550 ((volatile char *)rxq->rx_ring)[i] = 0;
552 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
553 for (i = 0; i < ICE_RX_MAX_BURST; ++i)
554 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
556 rxq->rx_nb_avail = 0;
557 rxq->rx_next_avail = 0;
558 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
562 rxq->pkt_first_seg = NULL;
563 rxq->pkt_last_seg = NULL;
565 rxq->rxrearm_start = 0;
570 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
572 struct ice_rx_queue *rxq;
574 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
576 PMD_INIT_FUNC_TRACE();
578 if (rx_queue_id >= dev->data->nb_rx_queues) {
579 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
580 rx_queue_id, dev->data->nb_rx_queues);
584 rxq = dev->data->rx_queues[rx_queue_id];
585 if (!rxq || !rxq->q_set) {
586 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
591 err = ice_program_hw_rx_queue(rxq);
593 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
598 err = ice_alloc_rx_queue_mbufs(rxq);
600 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
604 /* Init the RX tail register. */
605 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
607 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
609 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
612 rxq->rx_rel_mbufs(rxq);
613 ice_reset_rx_queue(rxq);
617 dev->data->rx_queue_state[rx_queue_id] =
618 RTE_ETH_QUEUE_STATE_STARTED;
624 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
626 struct ice_rx_queue *rxq;
628 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
630 if (rx_queue_id < dev->data->nb_rx_queues) {
631 rxq = dev->data->rx_queues[rx_queue_id];
633 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
635 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
639 rxq->rx_rel_mbufs(rxq);
640 ice_reset_rx_queue(rxq);
641 dev->data->rx_queue_state[rx_queue_id] =
642 RTE_ETH_QUEUE_STATE_STOPPED;
649 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
651 struct ice_tx_queue *txq;
655 struct ice_aqc_add_tx_qgrp *txq_elem;
656 struct ice_tlan_ctx tx_ctx;
659 PMD_INIT_FUNC_TRACE();
661 if (tx_queue_id >= dev->data->nb_tx_queues) {
662 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
663 tx_queue_id, dev->data->nb_tx_queues);
667 txq = dev->data->tx_queues[tx_queue_id];
668 if (!txq || !txq->q_set) {
669 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
674 buf_len = ice_struct_size(txq_elem, txqs, 1);
675 txq_elem = ice_malloc(hw, buf_len);
680 hw = ICE_VSI_TO_HW(vsi);
682 memset(&tx_ctx, 0, sizeof(tx_ctx));
683 txq_elem->num_txqs = 1;
684 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
686 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
687 tx_ctx.qlen = txq->nb_tx_desc;
688 tx_ctx.pf_num = hw->pf_id;
689 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
690 tx_ctx.src_vsi = vsi->vsi_id;
691 tx_ctx.port_num = hw->port_info->lport;
692 tx_ctx.tso_ena = 1; /* tso enable */
693 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
694 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
697 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
700 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
702 /* Init the Tx tail register*/
703 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
705 /* Fix me, we assume TC always 0 here */
706 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
707 txq_elem, buf_len, NULL);
709 PMD_DRV_LOG(ERR, "Failed to add lan txq");
713 /* store the schedule node id */
714 txq->q_teid = txq_elem->txqs[0].q_teid;
716 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
722 static enum ice_status
723 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
725 struct ice_vsi *vsi = rxq->vsi;
726 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
727 uint32_t rxdid = ICE_RXDID_LEGACY_1;
728 struct ice_rlan_ctx rx_ctx;
733 rxq->rx_buf_len = 1024;
735 memset(&rx_ctx, 0, sizeof(rx_ctx));
737 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
738 rx_ctx.qlen = rxq->nb_rx_desc;
739 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
740 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
741 rx_ctx.dtype = 0; /* No Header Split mode */
742 rx_ctx.dsize = 1; /* 32B descriptors */
743 rx_ctx.rxmax = ICE_ETH_MAX_LEN;
744 /* TPH: Transaction Layer Packet (TLP) processing hints */
745 rx_ctx.tphrdesc_ena = 1;
746 rx_ctx.tphwdesc_ena = 1;
747 rx_ctx.tphdata_ena = 1;
748 rx_ctx.tphhead_ena = 1;
749 /* Low Receive Queue Threshold defined in 64 descriptors units.
750 * When the number of free descriptors goes below the lrxqthresh,
751 * an immediate interrupt is triggered.
753 rx_ctx.lrxqthresh = 2;
754 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
757 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
759 /* Enable Flexible Descriptors in the queue context which
760 * allows this driver to select a specific receive descriptor format
762 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
763 QRXFLXP_CNTXT_RXDID_IDX_M;
765 /* increasing context priority to pick up profile ID;
766 * default is 0x01; setting to 0x03 to ensure profile
767 * is programming if prev context is of same priority
769 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
770 QRXFLXP_CNTXT_RXDID_PRIO_M;
772 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
774 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
776 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
780 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
782 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
787 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
789 /* Init the Rx tail register*/
790 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
796 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
798 struct ice_rx_queue *rxq;
800 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
801 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
803 PMD_INIT_FUNC_TRACE();
806 if (!rxq || !rxq->q_set) {
807 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
812 err = ice_fdir_program_hw_rx_queue(rxq);
814 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
819 /* Init the RX tail register. */
820 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
822 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
824 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
827 ice_reset_rx_queue(rxq);
835 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
837 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
838 struct ice_tx_queue *txq;
842 struct ice_aqc_add_tx_qgrp *txq_elem;
843 struct ice_tlan_ctx tx_ctx;
846 PMD_INIT_FUNC_TRACE();
849 if (!txq || !txq->q_set) {
850 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
855 buf_len = ice_struct_size(txq_elem, txqs, 1);
856 txq_elem = ice_malloc(hw, buf_len);
861 hw = ICE_VSI_TO_HW(vsi);
863 memset(&tx_ctx, 0, sizeof(tx_ctx));
864 txq_elem->num_txqs = 1;
865 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
867 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
868 tx_ctx.qlen = txq->nb_tx_desc;
869 tx_ctx.pf_num = hw->pf_id;
870 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
871 tx_ctx.src_vsi = vsi->vsi_id;
872 tx_ctx.port_num = hw->port_info->lport;
873 tx_ctx.tso_ena = 1; /* tso enable */
874 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
875 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
877 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
880 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
882 /* Init the Tx tail register*/
883 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
885 /* Fix me, we assume TC always 0 here */
886 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
887 txq_elem, buf_len, NULL);
889 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
893 /* store the schedule node id */
894 txq->q_teid = txq_elem->txqs[0].q_teid;
900 /* Free all mbufs for descriptors in tx queue */
902 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
906 if (!txq || !txq->sw_ring) {
907 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
911 for (i = 0; i < txq->nb_tx_desc; i++) {
912 if (txq->sw_ring[i].mbuf) {
913 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
914 txq->sw_ring[i].mbuf = NULL;
920 ice_reset_tx_queue(struct ice_tx_queue *txq)
922 struct ice_tx_entry *txe;
923 uint16_t i, prev, size;
926 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
931 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
932 for (i = 0; i < size; i++)
933 ((volatile char *)txq->tx_ring)[i] = 0;
935 prev = (uint16_t)(txq->nb_tx_desc - 1);
936 for (i = 0; i < txq->nb_tx_desc; i++) {
937 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
939 txd->cmd_type_offset_bsz =
940 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
943 txe[prev].next_id = i;
947 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
948 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
953 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
954 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
958 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
960 struct ice_tx_queue *txq;
961 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
962 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
963 struct ice_vsi *vsi = pf->main_vsi;
964 enum ice_status status;
967 uint16_t q_handle = tx_queue_id;
969 if (tx_queue_id >= dev->data->nb_tx_queues) {
970 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
971 tx_queue_id, dev->data->nb_tx_queues);
975 txq = dev->data->tx_queues[tx_queue_id];
977 PMD_DRV_LOG(ERR, "TX queue %u is not available",
982 q_ids[0] = txq->reg_idx;
983 q_teids[0] = txq->q_teid;
985 /* Fix me, we assume TC always 0 here */
986 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
987 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
988 if (status != ICE_SUCCESS) {
989 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
993 txq->tx_rel_mbufs(txq);
994 ice_reset_tx_queue(txq);
995 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1001 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1003 struct ice_rx_queue *rxq;
1005 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1010 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1012 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1016 rxq->rx_rel_mbufs(rxq);
1022 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1024 struct ice_tx_queue *txq;
1025 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1027 struct ice_vsi *vsi = pf->main_vsi;
1028 enum ice_status status;
1030 uint32_t q_teids[1];
1031 uint16_t q_handle = tx_queue_id;
1035 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1041 q_ids[0] = txq->reg_idx;
1042 q_teids[0] = txq->q_teid;
1044 /* Fix me, we assume TC always 0 here */
1045 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1046 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1047 if (status != ICE_SUCCESS) {
1048 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1052 txq->tx_rel_mbufs(txq);
1058 ice_rx_queue_setup(struct rte_eth_dev *dev,
1061 unsigned int socket_id,
1062 const struct rte_eth_rxconf *rx_conf,
1063 struct rte_mempool *mp)
1065 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1066 struct ice_adapter *ad =
1067 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1068 struct ice_vsi *vsi = pf->main_vsi;
1069 struct ice_rx_queue *rxq;
1070 const struct rte_memzone *rz;
1073 int use_def_burst_func = 1;
1076 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1077 nb_desc > ICE_MAX_RING_DESC ||
1078 nb_desc < ICE_MIN_RING_DESC) {
1079 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1080 "invalid", nb_desc);
1084 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1086 /* Free memory if needed */
1087 if (dev->data->rx_queues[queue_idx]) {
1088 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1089 dev->data->rx_queues[queue_idx] = NULL;
1092 /* Allocate the rx queue data structure */
1093 rxq = rte_zmalloc_socket(NULL,
1094 sizeof(struct ice_rx_queue),
1095 RTE_CACHE_LINE_SIZE,
1098 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1099 "rx queue data structure");
1103 rxq->nb_rx_desc = nb_desc;
1104 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1105 rxq->queue_id = queue_idx;
1106 rxq->offloads = offloads;
1108 rxq->reg_idx = vsi->base_queue + queue_idx;
1109 rxq->port_id = dev->data->port_id;
1110 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1111 rxq->crc_len = RTE_ETHER_CRC_LEN;
1115 rxq->drop_en = rx_conf->rx_drop_en;
1117 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1118 rxq->proto_xtr = pf->proto_xtr != NULL ?
1119 pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1121 /* Allocate the maximum number of RX ring hardware descriptor. */
1122 len = ICE_MAX_RING_DESC;
1125 * Allocating a little more memory because vectorized/bulk_alloc Rx
1126 * functions doesn't check boundaries each time.
1128 len += ICE_RX_MAX_BURST;
1130 /* Allocate the maximum number of RX ring hardware descriptor. */
1131 ring_size = sizeof(union ice_rx_flex_desc) * len;
1132 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1133 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1134 ring_size, ICE_RING_BASE_ALIGN,
1137 ice_rx_queue_release(rxq);
1138 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1143 /* Zero all the descriptors in the ring. */
1144 memset(rz->addr, 0, ring_size);
1146 rxq->rx_ring_dma = rz->iova;
1147 rxq->rx_ring = rz->addr;
1149 /* always reserve more for bulk alloc */
1150 len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1152 /* Allocate the software ring. */
1153 rxq->sw_ring = rte_zmalloc_socket(NULL,
1154 sizeof(struct ice_rx_entry) * len,
1155 RTE_CACHE_LINE_SIZE,
1157 if (!rxq->sw_ring) {
1158 ice_rx_queue_release(rxq);
1159 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1163 ice_reset_rx_queue(rxq);
1165 dev->data->rx_queues[queue_idx] = rxq;
1166 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1168 use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1170 if (!use_def_burst_func) {
1171 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1172 "satisfied. Rx Burst Bulk Alloc function will be "
1173 "used on port=%d, queue=%d.",
1174 rxq->port_id, rxq->queue_id);
1176 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1177 "not satisfied, Scattered Rx is requested. "
1178 "on port=%d, queue=%d.",
1179 rxq->port_id, rxq->queue_id);
1180 ad->rx_bulk_alloc_allowed = false;
1187 ice_rx_queue_release(void *rxq)
1189 struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1192 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1197 rte_free(q->sw_ring);
1198 rte_memzone_free(q->mz);
1203 ice_tx_queue_setup(struct rte_eth_dev *dev,
1206 unsigned int socket_id,
1207 const struct rte_eth_txconf *tx_conf)
1209 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1210 struct ice_vsi *vsi = pf->main_vsi;
1211 struct ice_tx_queue *txq;
1212 const struct rte_memzone *tz;
1214 uint16_t tx_rs_thresh, tx_free_thresh;
1217 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1219 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1220 nb_desc > ICE_MAX_RING_DESC ||
1221 nb_desc < ICE_MIN_RING_DESC) {
1222 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1223 "invalid", nb_desc);
1228 * The following two parameters control the setting of the RS bit on
1229 * transmit descriptors. TX descriptors will have their RS bit set
1230 * after txq->tx_rs_thresh descriptors have been used. The TX
1231 * descriptor ring will be cleaned after txq->tx_free_thresh
1232 * descriptors are used or if the number of descriptors required to
1233 * transmit a packet is greater than the number of free TX descriptors.
1235 * The following constraints must be satisfied:
1236 * - tx_rs_thresh must be greater than 0.
1237 * - tx_rs_thresh must be less than the size of the ring minus 2.
1238 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1239 * - tx_rs_thresh must be a divisor of the ring size.
1240 * - tx_free_thresh must be greater than 0.
1241 * - tx_free_thresh must be less than the size of the ring minus 3.
1242 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1244 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1245 * race condition, hence the maximum threshold constraints. When set
1246 * to zero use default values.
1248 tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1249 tx_conf->tx_free_thresh :
1250 ICE_DEFAULT_TX_FREE_THRESH);
1251 /* force tx_rs_thresh to adapt an aggressive tx_free_thresh */
1253 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1254 nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1255 if (tx_conf->tx_rs_thresh)
1256 tx_rs_thresh = tx_conf->tx_rs_thresh;
1257 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1258 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1259 "exceed nb_desc. (tx_rs_thresh=%u "
1260 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1261 (unsigned int)tx_rs_thresh,
1262 (unsigned int)tx_free_thresh,
1263 (unsigned int)nb_desc,
1264 (int)dev->data->port_id,
1268 if (tx_rs_thresh >= (nb_desc - 2)) {
1269 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1270 "number of TX descriptors minus 2. "
1271 "(tx_rs_thresh=%u port=%d queue=%d)",
1272 (unsigned int)tx_rs_thresh,
1273 (int)dev->data->port_id,
1277 if (tx_free_thresh >= (nb_desc - 3)) {
1278 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1279 "tx_free_thresh must be less than the "
1280 "number of TX descriptors minus 3. "
1281 "(tx_free_thresh=%u port=%d queue=%d)",
1282 (unsigned int)tx_free_thresh,
1283 (int)dev->data->port_id,
1287 if (tx_rs_thresh > tx_free_thresh) {
1288 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1289 "equal to tx_free_thresh. (tx_free_thresh=%u"
1290 " tx_rs_thresh=%u port=%d queue=%d)",
1291 (unsigned int)tx_free_thresh,
1292 (unsigned int)tx_rs_thresh,
1293 (int)dev->data->port_id,
1297 if ((nb_desc % tx_rs_thresh) != 0) {
1298 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1299 "number of TX descriptors. (tx_rs_thresh=%u"
1300 " port=%d queue=%d)",
1301 (unsigned int)tx_rs_thresh,
1302 (int)dev->data->port_id,
1306 if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1307 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1308 "tx_rs_thresh is greater than 1. "
1309 "(tx_rs_thresh=%u port=%d queue=%d)",
1310 (unsigned int)tx_rs_thresh,
1311 (int)dev->data->port_id,
1316 /* Free memory if needed. */
1317 if (dev->data->tx_queues[queue_idx]) {
1318 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1319 dev->data->tx_queues[queue_idx] = NULL;
1322 /* Allocate the TX queue data structure. */
1323 txq = rte_zmalloc_socket(NULL,
1324 sizeof(struct ice_tx_queue),
1325 RTE_CACHE_LINE_SIZE,
1328 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1329 "tx queue structure");
1333 /* Allocate TX hardware ring descriptors. */
1334 ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1335 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1336 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1337 ring_size, ICE_RING_BASE_ALIGN,
1340 ice_tx_queue_release(txq);
1341 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1346 txq->nb_tx_desc = nb_desc;
1347 txq->tx_rs_thresh = tx_rs_thresh;
1348 txq->tx_free_thresh = tx_free_thresh;
1349 txq->pthresh = tx_conf->tx_thresh.pthresh;
1350 txq->hthresh = tx_conf->tx_thresh.hthresh;
1351 txq->wthresh = tx_conf->tx_thresh.wthresh;
1352 txq->queue_id = queue_idx;
1354 txq->reg_idx = vsi->base_queue + queue_idx;
1355 txq->port_id = dev->data->port_id;
1356 txq->offloads = offloads;
1358 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1360 txq->tx_ring_dma = tz->iova;
1361 txq->tx_ring = tz->addr;
1363 /* Allocate software ring */
1365 rte_zmalloc_socket(NULL,
1366 sizeof(struct ice_tx_entry) * nb_desc,
1367 RTE_CACHE_LINE_SIZE,
1369 if (!txq->sw_ring) {
1370 ice_tx_queue_release(txq);
1371 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1375 ice_reset_tx_queue(txq);
1377 dev->data->tx_queues[queue_idx] = txq;
1378 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1379 ice_set_tx_function_flag(dev, txq);
1385 ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1387 ice_rx_queue_release(dev->data->rx_queues[qid]);
1391 ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1393 ice_tx_queue_release(dev->data->tx_queues[qid]);
1397 ice_tx_queue_release(void *txq)
1399 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1402 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1407 rte_free(q->sw_ring);
1408 rte_memzone_free(q->mz);
1413 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1414 struct rte_eth_rxq_info *qinfo)
1416 struct ice_rx_queue *rxq;
1418 rxq = dev->data->rx_queues[queue_id];
1420 qinfo->mp = rxq->mp;
1421 qinfo->scattered_rx = dev->data->scattered_rx;
1422 qinfo->nb_desc = rxq->nb_rx_desc;
1424 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1425 qinfo->conf.rx_drop_en = rxq->drop_en;
1426 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1430 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1431 struct rte_eth_txq_info *qinfo)
1433 struct ice_tx_queue *txq;
1435 txq = dev->data->tx_queues[queue_id];
1437 qinfo->nb_desc = txq->nb_tx_desc;
1439 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1440 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1441 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1443 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1444 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1445 qinfo->conf.offloads = txq->offloads;
1446 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1450 ice_rx_queue_count(void *rx_queue)
1452 #define ICE_RXQ_SCAN_INTERVAL 4
1453 volatile union ice_rx_flex_desc *rxdp;
1454 struct ice_rx_queue *rxq;
1458 rxdp = &rxq->rx_ring[rxq->rx_tail];
1459 while ((desc < rxq->nb_rx_desc) &&
1460 rte_le_to_cpu_16(rxdp->wb.status_error0) &
1461 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1463 * Check the DD bit of a rx descriptor of each 4 in a group,
1464 * to avoid checking too frequently and downgrading performance
1467 desc += ICE_RXQ_SCAN_INTERVAL;
1468 rxdp += ICE_RXQ_SCAN_INTERVAL;
1469 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1470 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1471 desc - rxq->nb_rx_desc]);
1477 #define ICE_RX_FLEX_ERR0_BITS \
1478 ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) | \
1479 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1480 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1481 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1482 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1483 (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1485 /* Rx L3/L4 checksum */
1486 static inline uint64_t
1487 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1491 /* check if HW has decoded the packet and checksum */
1492 if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1495 if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1496 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1500 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1501 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1503 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1505 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1506 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1508 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1510 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1511 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1513 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1514 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;
1516 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD;
1522 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1524 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1525 (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1526 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1528 rte_le_to_cpu_16(rxdp->wb.l2tag1);
1529 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1530 rte_le_to_cpu_16(rxdp->wb.l2tag1));
1535 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1536 if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1537 (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1538 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
1539 RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
1540 mb->vlan_tci_outer = mb->vlan_tci;
1541 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1542 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1543 rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1544 rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1546 mb->vlan_tci_outer = 0;
1549 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1550 mb->vlan_tci, mb->vlan_tci_outer);
1553 #define ICE_LOOK_AHEAD 8
1554 #if (ICE_LOOK_AHEAD != 8)
1555 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1558 #define ICE_PTP_TS_VALID 0x1
1561 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1563 volatile union ice_rx_flex_desc *rxdp;
1564 struct ice_rx_entry *rxep;
1565 struct rte_mbuf *mb;
1568 int32_t s[ICE_LOOK_AHEAD], nb_dd;
1569 int32_t i, j, nb_rx = 0;
1570 uint64_t pkt_flags = 0;
1571 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1572 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1573 struct ice_vsi *vsi = rxq->vsi;
1574 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1576 struct ice_adapter *ad = rxq->vsi->adapter;
1578 rxdp = &rxq->rx_ring[rxq->rx_tail];
1579 rxep = &rxq->sw_ring[rxq->rx_tail];
1581 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1583 /* Make sure there is at least 1 packet to receive */
1584 if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1587 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
1588 rxq->hw_register_set = 1;
1591 * Scan LOOK_AHEAD descriptors at a time to determine which
1592 * descriptors reference packets that are ready to be received.
1594 for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1595 rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1596 /* Read desc statuses backwards to avoid race condition */
1597 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1598 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1602 /* Compute how many status bits were set */
1603 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1604 nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1608 /* Translate descriptor info to mbuf parameters */
1609 for (j = 0; j < nb_dd; j++) {
1611 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1612 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1613 mb->data_len = pkt_len;
1614 mb->pkt_len = pkt_len;
1616 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1617 pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1618 mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1619 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1620 ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1621 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, mb, &rxdp[j]);
1622 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1623 if (ice_timestamp_dynflag > 0) {
1624 ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
1625 rxq->hw_register_set,
1626 rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high));
1627 rxq->hw_register_set = 0;
1628 *RTE_MBUF_DYNFIELD(mb,
1629 ice_timestamp_dynfield_offset,
1630 rte_mbuf_timestamp_t *) = ts_ns;
1631 mb->ol_flags |= ice_timestamp_dynflag;
1634 if (ad->ptp_ena && ((mb->packet_type &
1635 RTE_PTYPE_L2_MASK) == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1637 rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high);
1638 mb->timesync = rxq->queue_id;
1639 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1640 if (rxdp[j].wb.time_stamp_low &
1643 RTE_MBUF_F_RX_IEEE1588_TMST;
1646 mb->ol_flags |= pkt_flags;
1649 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1650 rxq->rx_stage[i + j] = rxep[j].mbuf;
1652 if (nb_dd != ICE_LOOK_AHEAD)
1656 /* Clear software ring entries */
1657 for (i = 0; i < nb_rx; i++)
1658 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1660 PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1661 "port_id=%u, queue_id=%u, nb_rx=%d",
1662 rxq->port_id, rxq->queue_id, nb_rx);
1667 static inline uint16_t
1668 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1669 struct rte_mbuf **rx_pkts,
1673 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1675 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1677 for (i = 0; i < nb_pkts; i++)
1678 rx_pkts[i] = stage[i];
1680 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1681 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1687 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1689 volatile union ice_rx_flex_desc *rxdp;
1690 struct ice_rx_entry *rxep;
1691 struct rte_mbuf *mb;
1692 uint16_t alloc_idx, i;
1696 /* Allocate buffers in bulk */
1697 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1698 (rxq->rx_free_thresh - 1));
1699 rxep = &rxq->sw_ring[alloc_idx];
1700 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1701 rxq->rx_free_thresh);
1702 if (unlikely(diag != 0)) {
1703 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1707 rxdp = &rxq->rx_ring[alloc_idx];
1708 for (i = 0; i < rxq->rx_free_thresh; i++) {
1709 if (likely(i < (rxq->rx_free_thresh - 1)))
1710 /* Prefetch next mbuf */
1711 rte_prefetch0(rxep[i + 1].mbuf);
1714 rte_mbuf_refcnt_set(mb, 1);
1716 mb->data_off = RTE_PKTMBUF_HEADROOM;
1718 mb->port = rxq->port_id;
1719 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1720 rxdp[i].read.hdr_addr = 0;
1721 rxdp[i].read.pkt_addr = dma_addr;
1724 /* Update Rx tail register */
1725 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1727 rxq->rx_free_trigger =
1728 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1729 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1730 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1735 static inline uint16_t
1736 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1738 struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1744 if (rxq->rx_nb_avail)
1745 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1747 nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1748 rxq->rx_next_avail = 0;
1749 rxq->rx_nb_avail = nb_rx;
1750 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1752 if (rxq->rx_tail > rxq->rx_free_trigger) {
1753 if (ice_rx_alloc_bufs(rxq) != 0) {
1756 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1757 rxq->rx_free_thresh;
1758 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1759 "port_id=%u, queue_id=%u",
1760 rxq->port_id, rxq->queue_id);
1761 rxq->rx_nb_avail = 0;
1762 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1763 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1764 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1770 if (rxq->rx_tail >= rxq->nb_rx_desc)
1773 if (rxq->rx_nb_avail)
1774 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1780 ice_recv_pkts_bulk_alloc(void *rx_queue,
1781 struct rte_mbuf **rx_pkts,
1788 if (unlikely(nb_pkts == 0))
1791 if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1792 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1795 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1796 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1797 nb_rx = (uint16_t)(nb_rx + count);
1798 nb_pkts = (uint16_t)(nb_pkts - count);
1807 ice_recv_scattered_pkts(void *rx_queue,
1808 struct rte_mbuf **rx_pkts,
1811 struct ice_rx_queue *rxq = rx_queue;
1812 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1813 volatile union ice_rx_flex_desc *rxdp;
1814 union ice_rx_flex_desc rxd;
1815 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1816 struct ice_rx_entry *rxe;
1817 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1818 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1819 struct rte_mbuf *nmb; /* new allocated mbuf */
1820 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1821 uint16_t rx_id = rxq->rx_tail;
1823 uint16_t nb_hold = 0;
1824 uint16_t rx_packet_len;
1825 uint16_t rx_stat_err0;
1828 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1829 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1830 struct ice_vsi *vsi = rxq->vsi;
1831 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1833 struct ice_adapter *ad = rxq->vsi->adapter;
1836 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
1837 rxq->hw_register_set = 1;
1839 while (nb_rx < nb_pkts) {
1840 rxdp = &rx_ring[rx_id];
1841 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1843 /* Check the DD bit first */
1844 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1848 nmb = rte_mbuf_raw_alloc(rxq->mp);
1849 if (unlikely(!nmb)) {
1850 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1853 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1856 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1858 if (unlikely(rx_id == rxq->nb_rx_desc))
1861 /* Prefetch next mbuf */
1862 rte_prefetch0(sw_ring[rx_id].mbuf);
1865 * When next RX descriptor is on a cache line boundary,
1866 * prefetch the next 4 RX descriptors and next 8 pointers
1869 if ((rx_id & 0x3) == 0) {
1870 rte_prefetch0(&rx_ring[rx_id]);
1871 rte_prefetch0(&sw_ring[rx_id]);
1877 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1879 /* Set data buffer address and data length of the mbuf */
1880 rxdp->read.hdr_addr = 0;
1881 rxdp->read.pkt_addr = dma_addr;
1882 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1883 ICE_RX_FLX_DESC_PKT_LEN_M;
1884 rxm->data_len = rx_packet_len;
1885 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1888 * If this is the first buffer of the received packet, set the
1889 * pointer to the first mbuf of the packet and initialize its
1890 * context. Otherwise, update the total length and the number
1891 * of segments of the current scattered packet, and update the
1892 * pointer to the last mbuf of the current packet.
1896 first_seg->nb_segs = 1;
1897 first_seg->pkt_len = rx_packet_len;
1899 first_seg->pkt_len =
1900 (uint16_t)(first_seg->pkt_len +
1902 first_seg->nb_segs++;
1903 last_seg->next = rxm;
1907 * If this is not the last buffer of the received packet,
1908 * update the pointer to the last mbuf of the current scattered
1909 * packet and continue to parse the RX ring.
1911 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1917 * This is the last buffer of the received packet. If the CRC
1918 * is not stripped by the hardware:
1919 * - Subtract the CRC length from the total packet length.
1920 * - If the last buffer only contains the whole CRC or a part
1921 * of it, free the mbuf associated to the last buffer. If part
1922 * of the CRC is also contained in the previous mbuf, subtract
1923 * the length of that CRC part from the data length of the
1927 if (unlikely(rxq->crc_len > 0)) {
1928 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1929 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1930 rte_pktmbuf_free_seg(rxm);
1931 first_seg->nb_segs--;
1932 last_seg->data_len =
1933 (uint16_t)(last_seg->data_len -
1934 (RTE_ETHER_CRC_LEN - rx_packet_len));
1935 last_seg->next = NULL;
1937 rxm->data_len = (uint16_t)(rx_packet_len -
1941 first_seg->port = rxq->port_id;
1942 first_seg->ol_flags = 0;
1943 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1944 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1945 ice_rxd_to_vlan_tci(first_seg, &rxd);
1946 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, first_seg, &rxd);
1947 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1948 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1949 if (ice_timestamp_dynflag > 0) {
1950 ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
1951 rxq->hw_register_set,
1952 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1953 rxq->hw_register_set = 0;
1954 *RTE_MBUF_DYNFIELD(first_seg,
1955 ice_timestamp_dynfield_offset,
1956 rte_mbuf_timestamp_t *) = ts_ns;
1957 first_seg->ol_flags |= ice_timestamp_dynflag;
1960 if (ad->ptp_ena && ((first_seg->packet_type & RTE_PTYPE_L2_MASK)
1961 == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1963 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
1964 first_seg->timesync = rxq->queue_id;
1965 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1968 first_seg->ol_flags |= pkt_flags;
1969 /* Prefetch data of first segment, if configured to do so. */
1970 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1971 first_seg->data_off));
1972 rx_pkts[nb_rx++] = first_seg;
1976 /* Record index of the next RX descriptor to probe. */
1977 rxq->rx_tail = rx_id;
1978 rxq->pkt_first_seg = first_seg;
1979 rxq->pkt_last_seg = last_seg;
1982 * If the number of free RX descriptors is greater than the RX free
1983 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1984 * register. Update the RDT with the value of the last processed RX
1985 * descriptor minus 1, to guarantee that the RDT register is never
1986 * equal to the RDH register, which creates a "full" ring situation
1987 * from the hardware point of view.
1989 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1990 if (nb_hold > rxq->rx_free_thresh) {
1991 rx_id = (uint16_t)(rx_id == 0 ?
1992 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1993 /* write TAIL register */
1994 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1997 rxq->nb_rx_hold = nb_hold;
1999 /* return received packet in the burst */
2004 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2006 struct ice_adapter *ad =
2007 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2008 const uint32_t *ptypes;
2010 static const uint32_t ptypes_os[] = {
2011 /* refers to ice_get_default_pkt_type() */
2013 RTE_PTYPE_L2_ETHER_TIMESYNC,
2014 RTE_PTYPE_L2_ETHER_LLDP,
2015 RTE_PTYPE_L2_ETHER_ARP,
2016 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2017 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2020 RTE_PTYPE_L4_NONFRAG,
2024 RTE_PTYPE_TUNNEL_GRENAT,
2025 RTE_PTYPE_TUNNEL_IP,
2026 RTE_PTYPE_INNER_L2_ETHER,
2027 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2028 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2029 RTE_PTYPE_INNER_L4_FRAG,
2030 RTE_PTYPE_INNER_L4_ICMP,
2031 RTE_PTYPE_INNER_L4_NONFRAG,
2032 RTE_PTYPE_INNER_L4_SCTP,
2033 RTE_PTYPE_INNER_L4_TCP,
2034 RTE_PTYPE_INNER_L4_UDP,
2038 static const uint32_t ptypes_comms[] = {
2039 /* refers to ice_get_default_pkt_type() */
2041 RTE_PTYPE_L2_ETHER_TIMESYNC,
2042 RTE_PTYPE_L2_ETHER_LLDP,
2043 RTE_PTYPE_L2_ETHER_ARP,
2044 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2045 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2048 RTE_PTYPE_L4_NONFRAG,
2052 RTE_PTYPE_TUNNEL_GRENAT,
2053 RTE_PTYPE_TUNNEL_IP,
2054 RTE_PTYPE_INNER_L2_ETHER,
2055 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2056 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2057 RTE_PTYPE_INNER_L4_FRAG,
2058 RTE_PTYPE_INNER_L4_ICMP,
2059 RTE_PTYPE_INNER_L4_NONFRAG,
2060 RTE_PTYPE_INNER_L4_SCTP,
2061 RTE_PTYPE_INNER_L4_TCP,
2062 RTE_PTYPE_INNER_L4_UDP,
2063 RTE_PTYPE_TUNNEL_GTPC,
2064 RTE_PTYPE_TUNNEL_GTPU,
2065 RTE_PTYPE_L2_ETHER_PPPOE,
2069 if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
2070 ptypes = ptypes_comms;
2074 if (dev->rx_pkt_burst == ice_recv_pkts ||
2075 dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
2076 dev->rx_pkt_burst == ice_recv_scattered_pkts)
2080 if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
2081 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
2082 #ifdef CC_AVX512_SUPPORT
2083 dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
2084 dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
2085 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
2086 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
2088 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
2089 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
2090 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2091 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2099 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2101 volatile union ice_rx_flex_desc *rxdp;
2102 struct ice_rx_queue *rxq = rx_queue;
2105 if (unlikely(offset >= rxq->nb_rx_desc))
2108 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2109 return RTE_ETH_RX_DESC_UNAVAIL;
2111 desc = rxq->rx_tail + offset;
2112 if (desc >= rxq->nb_rx_desc)
2113 desc -= rxq->nb_rx_desc;
2115 rxdp = &rxq->rx_ring[desc];
2116 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2117 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2118 return RTE_ETH_RX_DESC_DONE;
2120 return RTE_ETH_RX_DESC_AVAIL;
2124 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2126 struct ice_tx_queue *txq = tx_queue;
2127 volatile uint64_t *status;
2128 uint64_t mask, expect;
2131 if (unlikely(offset >= txq->nb_tx_desc))
2134 desc = txq->tx_tail + offset;
2135 /* go to next desc that has the RS bit */
2136 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2138 if (desc >= txq->nb_tx_desc) {
2139 desc -= txq->nb_tx_desc;
2140 if (desc >= txq->nb_tx_desc)
2141 desc -= txq->nb_tx_desc;
2144 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2145 mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2146 expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2147 ICE_TXD_QW1_DTYPE_S);
2148 if ((*status & mask) == expect)
2149 return RTE_ETH_TX_DESC_DONE;
2151 return RTE_ETH_TX_DESC_FULL;
2155 ice_free_queues(struct rte_eth_dev *dev)
2159 PMD_INIT_FUNC_TRACE();
2161 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2162 if (!dev->data->rx_queues[i])
2164 ice_rx_queue_release(dev->data->rx_queues[i]);
2165 dev->data->rx_queues[i] = NULL;
2167 dev->data->nb_rx_queues = 0;
2169 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2170 if (!dev->data->tx_queues[i])
2172 ice_tx_queue_release(dev->data->tx_queues[i]);
2173 dev->data->tx_queues[i] = NULL;
2175 dev->data->nb_tx_queues = 0;
2178 #define ICE_FDIR_NUM_TX_DESC ICE_MIN_RING_DESC
2179 #define ICE_FDIR_NUM_RX_DESC ICE_MIN_RING_DESC
2182 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2184 struct ice_tx_queue *txq;
2185 const struct rte_memzone *tz = NULL;
2187 struct rte_eth_dev *dev;
2190 PMD_DRV_LOG(ERR, "PF is not available");
2194 dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2196 /* Allocate the TX queue data structure. */
2197 txq = rte_zmalloc_socket("ice fdir tx queue",
2198 sizeof(struct ice_tx_queue),
2199 RTE_CACHE_LINE_SIZE,
2202 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2203 "tx queue structure.");
2207 /* Allocate TX hardware ring descriptors. */
2208 ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2209 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2211 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2212 ICE_FDIR_QUEUE_ID, ring_size,
2213 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2215 ice_tx_queue_release(txq);
2216 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2221 txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2222 txq->queue_id = ICE_FDIR_QUEUE_ID;
2223 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2224 txq->vsi = pf->fdir.fdir_vsi;
2226 txq->tx_ring_dma = tz->iova;
2227 txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2229 * don't need to allocate software ring and reset for the fdir
2230 * program queue just set the queue has been configured.
2235 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2241 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2243 struct ice_rx_queue *rxq;
2244 const struct rte_memzone *rz = NULL;
2246 struct rte_eth_dev *dev;
2249 PMD_DRV_LOG(ERR, "PF is not available");
2253 dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2255 /* Allocate the RX queue data structure. */
2256 rxq = rte_zmalloc_socket("ice fdir rx queue",
2257 sizeof(struct ice_rx_queue),
2258 RTE_CACHE_LINE_SIZE,
2261 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2262 "rx queue structure.");
2266 /* Allocate RX hardware ring descriptors. */
2267 ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2268 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2270 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2271 ICE_FDIR_QUEUE_ID, ring_size,
2272 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2274 ice_rx_queue_release(rxq);
2275 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2280 rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2281 rxq->queue_id = ICE_FDIR_QUEUE_ID;
2282 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2283 rxq->vsi = pf->fdir.fdir_vsi;
2285 rxq->rx_ring_dma = rz->iova;
2286 memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2287 sizeof(union ice_32byte_rx_desc));
2288 rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2291 * Don't need to allocate software ring and reset for the fdir
2292 * rx queue, just set the queue has been configured.
2297 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2303 ice_recv_pkts(void *rx_queue,
2304 struct rte_mbuf **rx_pkts,
2307 struct ice_rx_queue *rxq = rx_queue;
2308 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2309 volatile union ice_rx_flex_desc *rxdp;
2310 union ice_rx_flex_desc rxd;
2311 struct ice_rx_entry *sw_ring = rxq->sw_ring;
2312 struct ice_rx_entry *rxe;
2313 struct rte_mbuf *nmb; /* new allocated mbuf */
2314 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2315 uint16_t rx_id = rxq->rx_tail;
2317 uint16_t nb_hold = 0;
2318 uint16_t rx_packet_len;
2319 uint16_t rx_stat_err0;
2322 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2323 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2324 struct ice_vsi *vsi = rxq->vsi;
2325 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2327 struct ice_adapter *ad = rxq->vsi->adapter;
2330 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
2331 rxq->hw_register_set = 1;
2333 while (nb_rx < nb_pkts) {
2334 rxdp = &rx_ring[rx_id];
2335 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2337 /* Check the DD bit first */
2338 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2342 nmb = rte_mbuf_raw_alloc(rxq->mp);
2343 if (unlikely(!nmb)) {
2344 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2347 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2350 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2352 if (unlikely(rx_id == rxq->nb_rx_desc))
2357 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2360 * fill the read format of descriptor with physic address in
2361 * new allocated mbuf: nmb
2363 rxdp->read.hdr_addr = 0;
2364 rxdp->read.pkt_addr = dma_addr;
2366 /* calculate rx_packet_len of the received pkt */
2367 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2368 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2370 /* fill old mbuf with received descriptor: rxd */
2371 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2372 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2375 rxm->pkt_len = rx_packet_len;
2376 rxm->data_len = rx_packet_len;
2377 rxm->port = rxq->port_id;
2378 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2379 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2380 ice_rxd_to_vlan_tci(rxm, &rxd);
2381 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, rxm, &rxd);
2382 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2383 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2384 if (ice_timestamp_dynflag > 0) {
2385 ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
2386 rxq->hw_register_set,
2387 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
2388 rxq->hw_register_set = 0;
2389 *RTE_MBUF_DYNFIELD(rxm,
2390 ice_timestamp_dynfield_offset,
2391 rte_mbuf_timestamp_t *) = ts_ns;
2392 rxm->ol_flags |= ice_timestamp_dynflag;
2395 if (ad->ptp_ena && ((rxm->packet_type & RTE_PTYPE_L2_MASK) ==
2396 RTE_PTYPE_L2_ETHER_TIMESYNC)) {
2398 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2399 rxm->timesync = rxq->queue_id;
2400 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
2403 rxm->ol_flags |= pkt_flags;
2404 /* copy old mbuf to rx_pkts */
2405 rx_pkts[nb_rx++] = rxm;
2407 rxq->rx_tail = rx_id;
2409 * If the number of free RX descriptors is greater than the RX free
2410 * threshold of the queue, advance the receive tail register of queue.
2411 * Update that register with the value of the last processed RX
2412 * descriptor minus 1.
2414 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2415 if (nb_hold > rxq->rx_free_thresh) {
2416 rx_id = (uint16_t)(rx_id == 0 ?
2417 (rxq->nb_rx_desc - 1) : (rx_id - 1));
2418 /* write TAIL register */
2419 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2422 rxq->nb_rx_hold = nb_hold;
2424 /* return received packet in the burst */
2429 ice_parse_tunneling_params(uint64_t ol_flags,
2430 union ice_tx_offload tx_offload,
2431 uint32_t *cd_tunneling)
2433 /* EIPT: External (outer) IP header type */
2434 if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
2435 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2436 else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
2437 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2438 else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
2439 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2441 /* EIPLEN: External (outer) IP header length, in DWords */
2442 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2443 ICE_TXD_CTX_QW0_EIPLEN_S;
2445 /* L4TUNT: L4 Tunneling Type */
2446 switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
2447 case RTE_MBUF_F_TX_TUNNEL_IPIP:
2448 /* for non UDP / GRE tunneling, set to 00b */
2450 case RTE_MBUF_F_TX_TUNNEL_VXLAN:
2451 case RTE_MBUF_F_TX_TUNNEL_GTP:
2452 case RTE_MBUF_F_TX_TUNNEL_GENEVE:
2453 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2455 case RTE_MBUF_F_TX_TUNNEL_GRE:
2456 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2459 PMD_TX_LOG(ERR, "Tunnel type not supported");
2463 /* L4TUNLEN: L4 Tunneling Length, in Words
2465 * We depend on app to set rte_mbuf.l2_len correctly.
2466 * For IP in GRE it should be set to the length of the GRE
2468 * For MAC in GRE or MAC in UDP it should be set to the length
2469 * of the GRE or UDP headers plus the inner MAC up to including
2470 * its last Ethertype.
2471 * If MPLS labels exists, it should include them as well.
2473 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2474 ICE_TXD_CTX_QW0_NATLEN_S;
2477 * Calculate the tunneling UDP checksum.
2478 * Shall be set only if L4TUNT = 01b and EIPT is not zero
2480 if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2481 (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2482 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2486 ice_txd_enable_checksum(uint64_t ol_flags,
2488 uint32_t *td_offset,
2489 union ice_tx_offload tx_offload)
2492 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2493 *td_offset |= (tx_offload.outer_l2_len >> 1)
2494 << ICE_TX_DESC_LEN_MACLEN_S;
2496 *td_offset |= (tx_offload.l2_len >> 1)
2497 << ICE_TX_DESC_LEN_MACLEN_S;
2499 /* Enable L3 checksum offloads */
2500 /*Tunnel package usage outer len enable L3 checksum offload*/
2501 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
2502 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
2503 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2504 *td_offset |= (tx_offload.outer_l3_len >> 2) <<
2505 ICE_TX_DESC_LEN_IPLEN_S;
2506 } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2507 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2508 *td_offset |= (tx_offload.outer_l3_len >> 2) <<
2509 ICE_TX_DESC_LEN_IPLEN_S;
2510 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2511 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2512 *td_offset |= (tx_offload.outer_l3_len >> 2) <<
2513 ICE_TX_DESC_LEN_IPLEN_S;
2516 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
2517 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2518 *td_offset |= (tx_offload.l3_len >> 2) <<
2519 ICE_TX_DESC_LEN_IPLEN_S;
2520 } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2521 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2522 *td_offset |= (tx_offload.l3_len >> 2) <<
2523 ICE_TX_DESC_LEN_IPLEN_S;
2524 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2525 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2526 *td_offset |= (tx_offload.l3_len >> 2) <<
2527 ICE_TX_DESC_LEN_IPLEN_S;
2531 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2532 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2533 *td_offset |= (tx_offload.l4_len >> 2) <<
2534 ICE_TX_DESC_LEN_L4_LEN_S;
2538 /* Enable L4 checksum offloads */
2539 switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2540 case RTE_MBUF_F_TX_TCP_CKSUM:
2541 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2542 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2543 ICE_TX_DESC_LEN_L4_LEN_S;
2545 case RTE_MBUF_F_TX_SCTP_CKSUM:
2546 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2547 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2548 ICE_TX_DESC_LEN_L4_LEN_S;
2550 case RTE_MBUF_F_TX_UDP_CKSUM:
2551 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2552 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2553 ICE_TX_DESC_LEN_L4_LEN_S;
2561 ice_xmit_cleanup(struct ice_tx_queue *txq)
2563 struct ice_tx_entry *sw_ring = txq->sw_ring;
2564 volatile struct ice_tx_desc *txd = txq->tx_ring;
2565 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2566 uint16_t nb_tx_desc = txq->nb_tx_desc;
2567 uint16_t desc_to_clean_to;
2568 uint16_t nb_tx_to_clean;
2570 /* Determine the last descriptor needing to be cleaned */
2571 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2572 if (desc_to_clean_to >= nb_tx_desc)
2573 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2575 /* Check to make sure the last descriptor to clean is done */
2576 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2577 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2578 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2579 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2580 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2582 txq->port_id, txq->queue_id,
2583 txd[desc_to_clean_to].cmd_type_offset_bsz);
2584 /* Failed to clean any descriptors */
2588 /* Figure out how many descriptors will be cleaned */
2589 if (last_desc_cleaned > desc_to_clean_to)
2590 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2593 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2596 /* The last descriptor to clean is done, so that means all the
2597 * descriptors from the last descriptor that was cleaned
2598 * up to the last descriptor with the RS bit set
2599 * are done. Only reset the threshold descriptor.
2601 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2603 /* Update the txq to reflect the last descriptor that was cleaned */
2604 txq->last_desc_cleaned = desc_to_clean_to;
2605 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2610 /* Construct the tx flags */
2611 static inline uint64_t
2612 ice_build_ctob(uint32_t td_cmd,
2617 return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2618 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2619 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2620 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2621 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2624 /* Check if the context descriptor is needed for TX offloading */
2625 static inline uint16_t
2626 ice_calc_context_desc(uint64_t flags)
2628 static uint64_t mask = RTE_MBUF_F_TX_TCP_SEG |
2629 RTE_MBUF_F_TX_QINQ |
2630 RTE_MBUF_F_TX_OUTER_IP_CKSUM |
2631 RTE_MBUF_F_TX_TUNNEL_MASK |
2632 RTE_MBUF_F_TX_IEEE1588_TMST;
2634 return (flags & mask) ? 1 : 0;
2637 /* set ice TSO context descriptor */
2638 static inline uint64_t
2639 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2641 uint64_t ctx_desc = 0;
2642 uint32_t cd_cmd, hdr_len, cd_tso_len;
2644 if (!tx_offload.l4_len) {
2645 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2649 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2650 hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
2651 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2653 cd_cmd = ICE_TX_CTX_DESC_TSO;
2654 cd_tso_len = mbuf->pkt_len - hdr_len;
2655 ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2656 ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2657 ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2662 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2663 #define ICE_MAX_DATA_PER_TXD \
2664 (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2665 /* Calculate the number of TX descriptors needed for each pkt */
2666 static inline uint16_t
2667 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2669 struct rte_mbuf *txd = tx_pkt;
2672 while (txd != NULL) {
2673 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2681 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2683 struct ice_tx_queue *txq;
2684 volatile struct ice_tx_desc *tx_ring;
2685 volatile struct ice_tx_desc *txd;
2686 struct ice_tx_entry *sw_ring;
2687 struct ice_tx_entry *txe, *txn;
2688 struct rte_mbuf *tx_pkt;
2689 struct rte_mbuf *m_seg;
2690 uint32_t cd_tunneling_params;
2695 uint32_t td_cmd = 0;
2696 uint32_t td_offset = 0;
2697 uint32_t td_tag = 0;
2700 uint64_t buf_dma_addr;
2702 union ice_tx_offload tx_offload = {0};
2705 sw_ring = txq->sw_ring;
2706 tx_ring = txq->tx_ring;
2707 tx_id = txq->tx_tail;
2708 txe = &sw_ring[tx_id];
2710 /* Check if the descriptor ring needs to be cleaned. */
2711 if (txq->nb_tx_free < txq->tx_free_thresh)
2712 (void)ice_xmit_cleanup(txq);
2714 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2715 tx_pkt = *tx_pkts++;
2720 ol_flags = tx_pkt->ol_flags;
2721 tx_offload.l2_len = tx_pkt->l2_len;
2722 tx_offload.l3_len = tx_pkt->l3_len;
2723 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2724 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2725 tx_offload.l4_len = tx_pkt->l4_len;
2726 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2727 /* Calculate the number of context descriptors needed. */
2728 nb_ctx = ice_calc_context_desc(ol_flags);
2730 /* The number of descriptors that must be allocated for
2731 * a packet equals to the number of the segments of that
2732 * packet plus the number of context descriptor if needed.
2733 * Recalculate the needed tx descs when TSO enabled in case
2734 * the mbuf data size exceeds max data size that hw allows
2737 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2738 nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2741 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2742 tx_last = (uint16_t)(tx_id + nb_used - 1);
2745 if (tx_last >= txq->nb_tx_desc)
2746 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2748 if (nb_used > txq->nb_tx_free) {
2749 if (ice_xmit_cleanup(txq) != 0) {
2754 if (unlikely(nb_used > txq->tx_rs_thresh)) {
2755 while (nb_used > txq->nb_tx_free) {
2756 if (ice_xmit_cleanup(txq) != 0) {
2765 /* Descriptor based VLAN insertion */
2766 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
2767 td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2768 td_tag = tx_pkt->vlan_tci;
2771 /* Fill in tunneling parameters if necessary */
2772 cd_tunneling_params = 0;
2773 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2774 ice_parse_tunneling_params(ol_flags, tx_offload,
2775 &cd_tunneling_params);
2777 /* Enable checksum offloading */
2778 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2779 ice_txd_enable_checksum(ol_flags, &td_cmd,
2780 &td_offset, tx_offload);
2783 /* Setup TX context descriptor if required */
2784 volatile struct ice_tx_ctx_desc *ctx_txd =
2785 (volatile struct ice_tx_ctx_desc *)
2787 uint16_t cd_l2tag2 = 0;
2788 uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2790 txn = &sw_ring[txe->next_id];
2791 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2793 rte_pktmbuf_free_seg(txe->mbuf);
2797 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2798 cd_type_cmd_tso_mss |=
2799 ice_set_tso_ctx(tx_pkt, tx_offload);
2800 else if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
2801 cd_type_cmd_tso_mss |=
2802 ((uint64_t)ICE_TX_CTX_DESC_TSYN <<
2803 ICE_TXD_CTX_QW1_CMD_S);
2805 ctx_txd->tunneling_params =
2806 rte_cpu_to_le_32(cd_tunneling_params);
2808 /* TX context descriptor based double VLAN insert */
2809 if (ol_flags & RTE_MBUF_F_TX_QINQ) {
2810 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2811 cd_type_cmd_tso_mss |=
2812 ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2813 ICE_TXD_CTX_QW1_CMD_S);
2815 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2817 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2819 txe->last_id = tx_last;
2820 tx_id = txe->next_id;
2826 txd = &tx_ring[tx_id];
2827 txn = &sw_ring[txe->next_id];
2830 rte_pktmbuf_free_seg(txe->mbuf);
2833 /* Setup TX Descriptor */
2834 slen = m_seg->data_len;
2835 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2837 while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
2838 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2839 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2840 txd->cmd_type_offset_bsz =
2841 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2842 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2843 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2844 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2845 ICE_TXD_QW1_TX_BUF_SZ_S) |
2846 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2848 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2849 slen -= ICE_MAX_DATA_PER_TXD;
2851 txe->last_id = tx_last;
2852 tx_id = txe->next_id;
2854 txd = &tx_ring[tx_id];
2855 txn = &sw_ring[txe->next_id];
2858 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2859 txd->cmd_type_offset_bsz =
2860 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2861 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2862 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2863 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2864 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2866 txe->last_id = tx_last;
2867 tx_id = txe->next_id;
2869 m_seg = m_seg->next;
2872 /* fill the last descriptor with End of Packet (EOP) bit */
2873 td_cmd |= ICE_TX_DESC_CMD_EOP;
2874 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2875 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2877 /* set RS bit on the last descriptor of one packet */
2878 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2880 "Setting RS bit on TXD id="
2881 "%4u (port=%d queue=%d)",
2882 tx_last, txq->port_id, txq->queue_id);
2884 td_cmd |= ICE_TX_DESC_CMD_RS;
2886 /* Update txq RS bit counters */
2887 txq->nb_tx_used = 0;
2889 txd->cmd_type_offset_bsz |=
2890 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2894 /* update Tail register */
2895 ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2896 txq->tx_tail = tx_id;
2901 static __rte_always_inline int
2902 ice_tx_free_bufs(struct ice_tx_queue *txq)
2904 struct ice_tx_entry *txep;
2907 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2908 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2909 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2912 txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2914 for (i = 0; i < txq->tx_rs_thresh; i++)
2915 rte_prefetch0((txep + i)->mbuf);
2917 if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
2918 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2919 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2923 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2924 rte_pktmbuf_free_seg(txep->mbuf);
2929 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2930 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2931 if (txq->tx_next_dd >= txq->nb_tx_desc)
2932 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2934 return txq->tx_rs_thresh;
2938 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2941 struct ice_tx_entry *swr_ring = txq->sw_ring;
2942 uint16_t i, tx_last, tx_id;
2943 uint16_t nb_tx_free_last;
2944 uint16_t nb_tx_to_clean;
2947 /* Start free mbuf from the next of tx_tail */
2948 tx_last = txq->tx_tail;
2949 tx_id = swr_ring[tx_last].next_id;
2951 if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2954 nb_tx_to_clean = txq->nb_tx_free;
2955 nb_tx_free_last = txq->nb_tx_free;
2957 free_cnt = txq->nb_tx_desc;
2959 /* Loop through swr_ring to count the amount of
2960 * freeable mubfs and packets.
2962 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2963 for (i = 0; i < nb_tx_to_clean &&
2964 pkt_cnt < free_cnt &&
2965 tx_id != tx_last; i++) {
2966 if (swr_ring[tx_id].mbuf != NULL) {
2967 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2968 swr_ring[tx_id].mbuf = NULL;
2971 * last segment in the packet,
2972 * increment packet count
2974 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2977 tx_id = swr_ring[tx_id].next_id;
2980 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2981 txq->nb_tx_free || tx_id == tx_last)
2984 if (pkt_cnt < free_cnt) {
2985 if (ice_xmit_cleanup(txq))
2988 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2989 nb_tx_free_last = txq->nb_tx_free;
2993 return (int)pkt_cnt;
2998 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2999 uint32_t free_cnt __rte_unused)
3006 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
3011 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
3012 free_cnt = txq->nb_tx_desc;
3014 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
3016 for (i = 0; i < cnt; i += n) {
3017 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
3020 n = ice_tx_free_bufs(txq);
3030 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
3032 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
3033 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
3034 struct ice_adapter *ad =
3035 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3038 if (ad->tx_vec_allowed)
3039 return ice_tx_done_cleanup_vec(q, free_cnt);
3041 if (ad->tx_simple_allowed)
3042 return ice_tx_done_cleanup_simple(q, free_cnt);
3044 return ice_tx_done_cleanup_full(q, free_cnt);
3047 /* Populate 4 descriptors with data from 4 mbufs */
3049 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3054 for (i = 0; i < 4; i++, txdp++, pkts++) {
3055 dma_addr = rte_mbuf_data_iova(*pkts);
3056 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3057 txdp->cmd_type_offset_bsz =
3058 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3059 (*pkts)->data_len, 0);
3063 /* Populate 1 descriptor with data from 1 mbuf */
3065 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3069 dma_addr = rte_mbuf_data_iova(*pkts);
3070 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3071 txdp->cmd_type_offset_bsz =
3072 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3073 (*pkts)->data_len, 0);
3077 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
3080 volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
3081 struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
3082 const int N_PER_LOOP = 4;
3083 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
3084 int mainpart, leftover;
3088 * Process most of the packets in chunks of N pkts. Any
3089 * leftover packets will get processed one at a time.
3091 mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
3092 leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
3093 for (i = 0; i < mainpart; i += N_PER_LOOP) {
3094 /* Copy N mbuf pointers to the S/W ring */
3095 for (j = 0; j < N_PER_LOOP; ++j)
3096 (txep + i + j)->mbuf = *(pkts + i + j);
3097 tx4(txdp + i, pkts + i);
3100 if (unlikely(leftover > 0)) {
3101 for (i = 0; i < leftover; ++i) {
3102 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
3103 tx1(txdp + mainpart + i, pkts + mainpart + i);
3108 static inline uint16_t
3109 tx_xmit_pkts(struct ice_tx_queue *txq,
3110 struct rte_mbuf **tx_pkts,
3113 volatile struct ice_tx_desc *txr = txq->tx_ring;
3117 * Begin scanning the H/W ring for done descriptors when the number
3118 * of available descriptors drops below tx_free_thresh. For each done
3119 * descriptor, free the associated buffer.
3121 if (txq->nb_tx_free < txq->tx_free_thresh)
3122 ice_tx_free_bufs(txq);
3124 /* Use available descriptor only */
3125 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
3126 if (unlikely(!nb_pkts))
3129 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
3130 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
3131 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
3132 ice_tx_fill_hw_ring(txq, tx_pkts, n);
3133 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3134 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3136 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3140 /* Fill hardware descriptor ring with mbuf data */
3141 ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3142 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3144 /* Determine if RS bit needs to be set */
3145 if (txq->tx_tail > txq->tx_next_rs) {
3146 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3147 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3150 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3151 if (txq->tx_next_rs >= txq->nb_tx_desc)
3152 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3155 if (txq->tx_tail >= txq->nb_tx_desc)
3158 /* Update the tx tail register */
3159 ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3165 ice_xmit_pkts_simple(void *tx_queue,
3166 struct rte_mbuf **tx_pkts,
3171 if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3172 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3176 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3179 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3180 &tx_pkts[nb_tx], num);
3181 nb_tx = (uint16_t)(nb_tx + ret);
3182 nb_pkts = (uint16_t)(nb_pkts - ret);
3191 ice_set_rx_function(struct rte_eth_dev *dev)
3193 PMD_INIT_FUNC_TRACE();
3194 struct ice_adapter *ad =
3195 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3197 struct ice_rx_queue *rxq;
3199 int rx_check_ret = -1;
3201 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3202 ad->rx_use_avx512 = false;
3203 ad->rx_use_avx2 = false;
3204 rx_check_ret = ice_rx_vec_dev_check(dev);
3207 ad->rx_vec_offload_support =
3208 (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH);
3209 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3210 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3211 ad->rx_vec_allowed = true;
3212 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3213 rxq = dev->data->rx_queues[i];
3214 if (rxq && ice_rxq_vec_setup(rxq)) {
3215 ad->rx_vec_allowed = false;
3220 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3221 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3222 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3223 #ifdef CC_AVX512_SUPPORT
3224 ad->rx_use_avx512 = true;
3227 "AVX512 is not supported in build env");
3229 if (!ad->rx_use_avx512 &&
3230 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3231 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3232 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3233 ad->rx_use_avx2 = true;
3236 ad->rx_vec_allowed = false;
3240 if (ad->rx_vec_allowed) {
3241 if (dev->data->scattered_rx) {
3242 if (ad->rx_use_avx512) {
3243 #ifdef CC_AVX512_SUPPORT
3244 if (ad->rx_vec_offload_support) {
3246 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3247 dev->data->port_id);
3249 ice_recv_scattered_pkts_vec_avx512_offload;
3252 "Using AVX512 Vector Scattered Rx (port %d).",
3253 dev->data->port_id);
3255 ice_recv_scattered_pkts_vec_avx512;
3258 } else if (ad->rx_use_avx2) {
3259 if (ad->rx_vec_offload_support) {
3261 "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3262 dev->data->port_id);
3264 ice_recv_scattered_pkts_vec_avx2_offload;
3267 "Using AVX2 Vector Scattered Rx (port %d).",
3268 dev->data->port_id);
3270 ice_recv_scattered_pkts_vec_avx2;
3274 "Using Vector Scattered Rx (port %d).",
3275 dev->data->port_id);
3276 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3279 if (ad->rx_use_avx512) {
3280 #ifdef CC_AVX512_SUPPORT
3281 if (ad->rx_vec_offload_support) {
3283 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3284 dev->data->port_id);
3286 ice_recv_pkts_vec_avx512_offload;
3289 "Using AVX512 Vector Rx (port %d).",
3290 dev->data->port_id);
3292 ice_recv_pkts_vec_avx512;
3295 } else if (ad->rx_use_avx2) {
3296 if (ad->rx_vec_offload_support) {
3298 "Using AVX2 OFFLOAD Vector Rx (port %d).",
3299 dev->data->port_id);
3301 ice_recv_pkts_vec_avx2_offload;
3304 "Using AVX2 Vector Rx (port %d).",
3305 dev->data->port_id);
3307 ice_recv_pkts_vec_avx2;
3311 "Using Vector Rx (port %d).",
3312 dev->data->port_id);
3313 dev->rx_pkt_burst = ice_recv_pkts_vec;
3321 if (dev->data->scattered_rx) {
3322 /* Set the non-LRO scattered function */
3324 "Using a Scattered function on port %d.",
3325 dev->data->port_id);
3326 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3327 } else if (ad->rx_bulk_alloc_allowed) {
3329 "Rx Burst Bulk Alloc Preconditions are "
3330 "satisfied. Rx Burst Bulk Alloc function "
3331 "will be used on port %d.",
3332 dev->data->port_id);
3333 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3336 "Rx Burst Bulk Alloc Preconditions are not "
3337 "satisfied, Normal Rx will be used on port %d.",
3338 dev->data->port_id);
3339 dev->rx_pkt_burst = ice_recv_pkts;
3343 static const struct {
3344 eth_rx_burst_t pkt_burst;
3346 } ice_rx_burst_infos[] = {
3347 { ice_recv_scattered_pkts, "Scalar Scattered" },
3348 { ice_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3349 { ice_recv_pkts, "Scalar" },
3351 #ifdef CC_AVX512_SUPPORT
3352 { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3353 { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3354 { ice_recv_pkts_vec_avx512, "Vector AVX512" },
3355 { ice_recv_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3357 { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3358 { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3359 { ice_recv_pkts_vec_avx2, "Vector AVX2" },
3360 { ice_recv_pkts_vec_avx2_offload, "Offload Vector AVX2" },
3361 { ice_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3362 { ice_recv_pkts_vec, "Vector SSE" },
3367 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3368 struct rte_eth_burst_mode *mode)
3370 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3374 for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3375 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3376 snprintf(mode->info, sizeof(mode->info), "%s",
3377 ice_rx_burst_infos[i].info);
3387 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3389 struct ice_adapter *ad =
3390 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3392 /* Use a simple Tx queue if possible (only fast free is allowed) */
3393 ad->tx_simple_allowed =
3395 (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3396 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3398 if (ad->tx_simple_allowed)
3399 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3403 "Simple Tx can NOT be enabled on Tx queue %u.",
3407 /*********************************************************************
3411 **********************************************************************/
3412 /* The default values of TSO MSS */
3413 #define ICE_MIN_TSO_MSS 64
3414 #define ICE_MAX_TSO_MSS 9728
3415 #define ICE_MAX_TSO_FRAME_SIZE 262144
3417 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3424 for (i = 0; i < nb_pkts; i++) {
3426 ol_flags = m->ol_flags;
3428 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
3429 (m->tso_segsz < ICE_MIN_TSO_MSS ||
3430 m->tso_segsz > ICE_MAX_TSO_MSS ||
3431 m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3433 * MSS outside the range are considered malicious
3439 #ifdef RTE_ETHDEV_DEBUG_TX
3440 ret = rte_validate_tx_offload(m);
3446 ret = rte_net_intel_cksum_prepare(m);
3456 ice_set_tx_function(struct rte_eth_dev *dev)
3458 struct ice_adapter *ad =
3459 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3461 struct ice_tx_queue *txq;
3463 int tx_check_ret = -1;
3465 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3466 ad->tx_use_avx2 = false;
3467 ad->tx_use_avx512 = false;
3468 tx_check_ret = ice_tx_vec_dev_check(dev);
3469 if (tx_check_ret >= 0 &&
3470 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3471 ad->tx_vec_allowed = true;
3473 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3474 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3475 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3476 #ifdef CC_AVX512_SUPPORT
3477 ad->tx_use_avx512 = true;
3480 "AVX512 is not supported in build env");
3482 if (!ad->tx_use_avx512 &&
3483 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3484 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3485 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3486 ad->tx_use_avx2 = true;
3488 if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3489 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3490 ad->tx_vec_allowed = false;
3492 if (ad->tx_vec_allowed) {
3493 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3494 txq = dev->data->tx_queues[i];
3495 if (txq && ice_txq_vec_setup(txq)) {
3496 ad->tx_vec_allowed = false;
3502 ad->tx_vec_allowed = false;
3506 if (ad->tx_vec_allowed) {
3507 dev->tx_pkt_prepare = NULL;
3508 if (ad->tx_use_avx512) {
3509 #ifdef CC_AVX512_SUPPORT
3510 if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3512 "Using AVX512 OFFLOAD Vector Tx (port %d).",
3513 dev->data->port_id);
3515 ice_xmit_pkts_vec_avx512_offload;
3516 dev->tx_pkt_prepare = ice_prep_pkts;
3519 "Using AVX512 Vector Tx (port %d).",
3520 dev->data->port_id);
3521 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3525 if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3527 "Using AVX2 OFFLOAD Vector Tx (port %d).",
3528 dev->data->port_id);
3530 ice_xmit_pkts_vec_avx2_offload;
3531 dev->tx_pkt_prepare = ice_prep_pkts;
3533 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3534 ad->tx_use_avx2 ? "avx2 " : "",
3535 dev->data->port_id);
3536 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3537 ice_xmit_pkts_vec_avx2 :
3546 if (ad->tx_simple_allowed) {
3547 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3548 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3549 dev->tx_pkt_prepare = NULL;
3551 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3552 dev->tx_pkt_burst = ice_xmit_pkts;
3553 dev->tx_pkt_prepare = ice_prep_pkts;
3557 static const struct {
3558 eth_tx_burst_t pkt_burst;
3560 } ice_tx_burst_infos[] = {
3561 { ice_xmit_pkts_simple, "Scalar Simple" },
3562 { ice_xmit_pkts, "Scalar" },
3564 #ifdef CC_AVX512_SUPPORT
3565 { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3566 { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3568 { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3569 { ice_xmit_pkts_vec, "Vector SSE" },
3574 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3575 struct rte_eth_burst_mode *mode)
3577 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3581 for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3582 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3583 snprintf(mode->info, sizeof(mode->info), "%s",
3584 ice_tx_burst_infos[i].info);
3593 /* For each value it means, datasheet of hardware can tell more details
3595 * @note: fix ice_dev_supported_ptypes_get() if any change here.
3597 static inline uint32_t
3598 ice_get_default_pkt_type(uint16_t ptype)
3600 static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3601 __rte_cache_aligned = {
3604 [1] = RTE_PTYPE_L2_ETHER,
3605 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3606 /* [3] - [5] reserved */
3607 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3608 /* [7] - [10] reserved */
3609 [11] = RTE_PTYPE_L2_ETHER_ARP,
3610 /* [12] - [21] reserved */
3612 /* Non tunneled IPv4 */
3613 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3615 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3616 RTE_PTYPE_L4_NONFRAG,
3617 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3620 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3622 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3624 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3628 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3629 RTE_PTYPE_TUNNEL_IP |
3630 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3631 RTE_PTYPE_INNER_L4_FRAG,
3632 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3633 RTE_PTYPE_TUNNEL_IP |
3634 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3635 RTE_PTYPE_INNER_L4_NONFRAG,
3636 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3637 RTE_PTYPE_TUNNEL_IP |
3638 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3639 RTE_PTYPE_INNER_L4_UDP,
3641 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3642 RTE_PTYPE_TUNNEL_IP |
3643 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3644 RTE_PTYPE_INNER_L4_TCP,
3645 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3646 RTE_PTYPE_TUNNEL_IP |
3647 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3648 RTE_PTYPE_INNER_L4_SCTP,
3649 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3650 RTE_PTYPE_TUNNEL_IP |
3651 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3652 RTE_PTYPE_INNER_L4_ICMP,
3655 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3656 RTE_PTYPE_TUNNEL_IP |
3657 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3658 RTE_PTYPE_INNER_L4_FRAG,
3659 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3660 RTE_PTYPE_TUNNEL_IP |
3661 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3662 RTE_PTYPE_INNER_L4_NONFRAG,
3663 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3664 RTE_PTYPE_TUNNEL_IP |
3665 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3666 RTE_PTYPE_INNER_L4_UDP,
3668 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3669 RTE_PTYPE_TUNNEL_IP |
3670 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3671 RTE_PTYPE_INNER_L4_TCP,
3672 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3673 RTE_PTYPE_TUNNEL_IP |
3674 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3675 RTE_PTYPE_INNER_L4_SCTP,
3676 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3677 RTE_PTYPE_TUNNEL_IP |
3678 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3679 RTE_PTYPE_INNER_L4_ICMP,
3681 /* IPv4 --> GRE/Teredo/VXLAN */
3682 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3683 RTE_PTYPE_TUNNEL_GRENAT,
3685 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3686 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3687 RTE_PTYPE_TUNNEL_GRENAT |
3688 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3689 RTE_PTYPE_INNER_L4_FRAG,
3690 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3691 RTE_PTYPE_TUNNEL_GRENAT |
3692 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3693 RTE_PTYPE_INNER_L4_NONFRAG,
3694 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3695 RTE_PTYPE_TUNNEL_GRENAT |
3696 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3697 RTE_PTYPE_INNER_L4_UDP,
3699 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3700 RTE_PTYPE_TUNNEL_GRENAT |
3701 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3702 RTE_PTYPE_INNER_L4_TCP,
3703 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3704 RTE_PTYPE_TUNNEL_GRENAT |
3705 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3706 RTE_PTYPE_INNER_L4_SCTP,
3707 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3708 RTE_PTYPE_TUNNEL_GRENAT |
3709 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3710 RTE_PTYPE_INNER_L4_ICMP,
3712 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3713 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3714 RTE_PTYPE_TUNNEL_GRENAT |
3715 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3716 RTE_PTYPE_INNER_L4_FRAG,
3717 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3718 RTE_PTYPE_TUNNEL_GRENAT |
3719 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3720 RTE_PTYPE_INNER_L4_NONFRAG,
3721 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3722 RTE_PTYPE_TUNNEL_GRENAT |
3723 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3724 RTE_PTYPE_INNER_L4_UDP,
3726 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3727 RTE_PTYPE_TUNNEL_GRENAT |
3728 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3729 RTE_PTYPE_INNER_L4_TCP,
3730 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3731 RTE_PTYPE_TUNNEL_GRENAT |
3732 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3733 RTE_PTYPE_INNER_L4_SCTP,
3734 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3735 RTE_PTYPE_TUNNEL_GRENAT |
3736 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3737 RTE_PTYPE_INNER_L4_ICMP,
3739 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3740 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3741 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3743 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3744 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3745 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3746 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3747 RTE_PTYPE_INNER_L4_FRAG,
3748 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3749 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3750 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3751 RTE_PTYPE_INNER_L4_NONFRAG,
3752 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3753 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3754 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3755 RTE_PTYPE_INNER_L4_UDP,
3757 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3758 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3759 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3760 RTE_PTYPE_INNER_L4_TCP,
3761 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3762 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3763 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3764 RTE_PTYPE_INNER_L4_SCTP,
3765 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3766 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3767 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3768 RTE_PTYPE_INNER_L4_ICMP,
3770 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3771 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3772 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3773 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3774 RTE_PTYPE_INNER_L4_FRAG,
3775 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3776 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3777 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3778 RTE_PTYPE_INNER_L4_NONFRAG,
3779 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3780 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3781 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3782 RTE_PTYPE_INNER_L4_UDP,
3784 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3785 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3786 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3787 RTE_PTYPE_INNER_L4_TCP,
3788 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3789 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3790 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3791 RTE_PTYPE_INNER_L4_SCTP,
3792 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3793 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3794 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3795 RTE_PTYPE_INNER_L4_ICMP,
3796 /* [73] - [87] reserved */
3798 /* Non tunneled IPv6 */
3799 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3801 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3802 RTE_PTYPE_L4_NONFRAG,
3803 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3806 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3808 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3810 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3814 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3815 RTE_PTYPE_TUNNEL_IP |
3816 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3817 RTE_PTYPE_INNER_L4_FRAG,
3818 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3819 RTE_PTYPE_TUNNEL_IP |
3820 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3821 RTE_PTYPE_INNER_L4_NONFRAG,
3822 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3823 RTE_PTYPE_TUNNEL_IP |
3824 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3825 RTE_PTYPE_INNER_L4_UDP,
3827 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3828 RTE_PTYPE_TUNNEL_IP |
3829 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3830 RTE_PTYPE_INNER_L4_TCP,
3831 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3832 RTE_PTYPE_TUNNEL_IP |
3833 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3834 RTE_PTYPE_INNER_L4_SCTP,
3835 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3836 RTE_PTYPE_TUNNEL_IP |
3837 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3838 RTE_PTYPE_INNER_L4_ICMP,
3841 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3842 RTE_PTYPE_TUNNEL_IP |
3843 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3844 RTE_PTYPE_INNER_L4_FRAG,
3845 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3846 RTE_PTYPE_TUNNEL_IP |
3847 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3848 RTE_PTYPE_INNER_L4_NONFRAG,
3849 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3850 RTE_PTYPE_TUNNEL_IP |
3851 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3852 RTE_PTYPE_INNER_L4_UDP,
3853 /* [105] reserved */
3854 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3855 RTE_PTYPE_TUNNEL_IP |
3856 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3857 RTE_PTYPE_INNER_L4_TCP,
3858 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3859 RTE_PTYPE_TUNNEL_IP |
3860 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3861 RTE_PTYPE_INNER_L4_SCTP,
3862 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3863 RTE_PTYPE_TUNNEL_IP |
3864 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3865 RTE_PTYPE_INNER_L4_ICMP,
3867 /* IPv6 --> GRE/Teredo/VXLAN */
3868 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3869 RTE_PTYPE_TUNNEL_GRENAT,
3871 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3872 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3873 RTE_PTYPE_TUNNEL_GRENAT |
3874 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3875 RTE_PTYPE_INNER_L4_FRAG,
3876 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3877 RTE_PTYPE_TUNNEL_GRENAT |
3878 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3879 RTE_PTYPE_INNER_L4_NONFRAG,
3880 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3881 RTE_PTYPE_TUNNEL_GRENAT |
3882 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3883 RTE_PTYPE_INNER_L4_UDP,
3884 /* [113] reserved */
3885 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3886 RTE_PTYPE_TUNNEL_GRENAT |
3887 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3888 RTE_PTYPE_INNER_L4_TCP,
3889 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3890 RTE_PTYPE_TUNNEL_GRENAT |
3891 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3892 RTE_PTYPE_INNER_L4_SCTP,
3893 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3894 RTE_PTYPE_TUNNEL_GRENAT |
3895 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3896 RTE_PTYPE_INNER_L4_ICMP,
3898 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3899 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3900 RTE_PTYPE_TUNNEL_GRENAT |
3901 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3902 RTE_PTYPE_INNER_L4_FRAG,
3903 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3904 RTE_PTYPE_TUNNEL_GRENAT |
3905 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3906 RTE_PTYPE_INNER_L4_NONFRAG,
3907 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3908 RTE_PTYPE_TUNNEL_GRENAT |
3909 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3910 RTE_PTYPE_INNER_L4_UDP,
3911 /* [120] reserved */
3912 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3913 RTE_PTYPE_TUNNEL_GRENAT |
3914 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3915 RTE_PTYPE_INNER_L4_TCP,
3916 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3917 RTE_PTYPE_TUNNEL_GRENAT |
3918 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3919 RTE_PTYPE_INNER_L4_SCTP,
3920 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3921 RTE_PTYPE_TUNNEL_GRENAT |
3922 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3923 RTE_PTYPE_INNER_L4_ICMP,
3925 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3926 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3927 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3929 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3930 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3931 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3932 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3933 RTE_PTYPE_INNER_L4_FRAG,
3934 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3935 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3936 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3937 RTE_PTYPE_INNER_L4_NONFRAG,
3938 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3939 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3940 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3941 RTE_PTYPE_INNER_L4_UDP,
3942 /* [128] reserved */
3943 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3944 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3945 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3946 RTE_PTYPE_INNER_L4_TCP,
3947 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3948 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3949 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3950 RTE_PTYPE_INNER_L4_SCTP,
3951 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3952 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3953 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3954 RTE_PTYPE_INNER_L4_ICMP,
3956 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3957 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3958 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3959 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3960 RTE_PTYPE_INNER_L4_FRAG,
3961 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3962 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3963 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3964 RTE_PTYPE_INNER_L4_NONFRAG,
3965 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3966 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3967 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3968 RTE_PTYPE_INNER_L4_UDP,
3969 /* [135] reserved */
3970 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3971 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3972 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3973 RTE_PTYPE_INNER_L4_TCP,
3974 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3975 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3976 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3977 RTE_PTYPE_INNER_L4_SCTP,
3978 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3979 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3980 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3981 RTE_PTYPE_INNER_L4_ICMP,
3982 /* [139] - [299] reserved */
3985 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3986 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3988 /* PPPoE --> IPv4 */
3989 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3990 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3992 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3993 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3994 RTE_PTYPE_L4_NONFRAG,
3995 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3996 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3998 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3999 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4001 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
4002 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4004 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
4005 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4008 /* PPPoE --> IPv6 */
4009 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
4010 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4012 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
4013 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4014 RTE_PTYPE_L4_NONFRAG,
4015 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
4016 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4018 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
4019 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4021 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
4022 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4024 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
4025 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4027 /* [314] - [324] reserved */
4029 /* IPv4/IPv6 --> GTPC/GTPU */
4030 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4031 RTE_PTYPE_TUNNEL_GTPC,
4032 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4033 RTE_PTYPE_TUNNEL_GTPC,
4034 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4035 RTE_PTYPE_TUNNEL_GTPC,
4036 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4037 RTE_PTYPE_TUNNEL_GTPC,
4038 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4039 RTE_PTYPE_TUNNEL_GTPU,
4040 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4041 RTE_PTYPE_TUNNEL_GTPU,
4043 /* IPv4 --> GTPU --> IPv4 */
4044 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4045 RTE_PTYPE_TUNNEL_GTPU |
4046 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4047 RTE_PTYPE_INNER_L4_FRAG,
4048 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4049 RTE_PTYPE_TUNNEL_GTPU |
4050 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4051 RTE_PTYPE_INNER_L4_NONFRAG,
4052 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4053 RTE_PTYPE_TUNNEL_GTPU |
4054 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4055 RTE_PTYPE_INNER_L4_UDP,
4056 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4057 RTE_PTYPE_TUNNEL_GTPU |
4058 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4059 RTE_PTYPE_INNER_L4_TCP,
4060 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4061 RTE_PTYPE_TUNNEL_GTPU |
4062 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4063 RTE_PTYPE_INNER_L4_ICMP,
4065 /* IPv6 --> GTPU --> IPv4 */
4066 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4067 RTE_PTYPE_TUNNEL_GTPU |
4068 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4069 RTE_PTYPE_INNER_L4_FRAG,
4070 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4071 RTE_PTYPE_TUNNEL_GTPU |
4072 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4073 RTE_PTYPE_INNER_L4_NONFRAG,
4074 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4075 RTE_PTYPE_TUNNEL_GTPU |
4076 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4077 RTE_PTYPE_INNER_L4_UDP,
4078 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4079 RTE_PTYPE_TUNNEL_GTPU |
4080 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4081 RTE_PTYPE_INNER_L4_TCP,
4082 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4083 RTE_PTYPE_TUNNEL_GTPU |
4084 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4085 RTE_PTYPE_INNER_L4_ICMP,
4087 /* IPv4 --> GTPU --> IPv6 */
4088 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4089 RTE_PTYPE_TUNNEL_GTPU |
4090 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4091 RTE_PTYPE_INNER_L4_FRAG,
4092 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4093 RTE_PTYPE_TUNNEL_GTPU |
4094 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4095 RTE_PTYPE_INNER_L4_NONFRAG,
4096 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4097 RTE_PTYPE_TUNNEL_GTPU |
4098 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4099 RTE_PTYPE_INNER_L4_UDP,
4100 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4101 RTE_PTYPE_TUNNEL_GTPU |
4102 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4103 RTE_PTYPE_INNER_L4_TCP,
4104 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4105 RTE_PTYPE_TUNNEL_GTPU |
4106 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4107 RTE_PTYPE_INNER_L4_ICMP,
4109 /* IPv6 --> GTPU --> IPv6 */
4110 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4111 RTE_PTYPE_TUNNEL_GTPU |
4112 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4113 RTE_PTYPE_INNER_L4_FRAG,
4114 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4115 RTE_PTYPE_TUNNEL_GTPU |
4116 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4117 RTE_PTYPE_INNER_L4_NONFRAG,
4118 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4119 RTE_PTYPE_TUNNEL_GTPU |
4120 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4121 RTE_PTYPE_INNER_L4_UDP,
4122 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4123 RTE_PTYPE_TUNNEL_GTPU |
4124 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4125 RTE_PTYPE_INNER_L4_TCP,
4126 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4127 RTE_PTYPE_TUNNEL_GTPU |
4128 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4129 RTE_PTYPE_INNER_L4_ICMP,
4131 /* IPv4 --> UDP ECPRI */
4132 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4134 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4136 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4138 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4140 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4142 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4144 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4146 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4148 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4150 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4153 /* IPV6 --> UDP ECPRI */
4154 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4156 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4158 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4160 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4162 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4164 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4166 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4168 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4170 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4172 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4174 /* All others reserved */
4177 return type_table[ptype];
4181 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4183 struct ice_adapter *ad =
4184 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4187 for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4188 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4191 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4192 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4193 (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4194 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4195 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4197 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S 4
4198 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M \
4199 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4200 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S 5
4201 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M \
4202 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4205 * check the programming status descriptor in rx queue.
4206 * done after Programming Flow Director is programmed on
4210 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4212 volatile union ice_32byte_rx_desc *rxdp;
4219 rxdp = (volatile union ice_32byte_rx_desc *)
4220 (&rxq->rx_ring[rxq->rx_tail]);
4221 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4222 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4223 >> ICE_RXD_QW1_STATUS_S;
4225 if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4227 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4228 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4229 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4230 ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4232 if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4233 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4234 else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4235 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4239 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4240 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4242 PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4246 rxdp->wb.qword1.status_error_len = 0;
4248 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4250 if (rxq->rx_tail == 0)
4251 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4253 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4259 #define ICE_FDIR_MAX_WAIT_US 10000
4262 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4264 struct ice_tx_queue *txq = pf->fdir.txq;
4265 struct ice_rx_queue *rxq = pf->fdir.rxq;
4266 volatile struct ice_fltr_desc *fdirdp;
4267 volatile struct ice_tx_desc *txdp;
4271 fdirdp = (volatile struct ice_fltr_desc *)
4272 (&txq->tx_ring[txq->tx_tail]);
4273 fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4274 fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4276 txdp = &txq->tx_ring[txq->tx_tail + 1];
4277 txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4278 td_cmd = ICE_TX_DESC_CMD_EOP |
4279 ICE_TX_DESC_CMD_RS |
4280 ICE_TX_DESC_CMD_DUMMY;
4282 txdp->cmd_type_offset_bsz =
4283 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4286 if (txq->tx_tail >= txq->nb_tx_desc)
4288 /* Update the tx tail register */
4289 ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4290 for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4291 if ((txdp->cmd_type_offset_bsz &
4292 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4293 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4297 if (i >= ICE_FDIR_MAX_WAIT_US) {
4299 "Failed to program FDIR filter: time out to get DD on tx queue.");
4303 for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4306 ret = ice_check_fdir_programming_status(rxq);
4314 "Failed to program FDIR filter: programming status reported.");