1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_ethdev_driver.h>
10 #define ICE_TX_CKSUM_OFFLOAD_MASK ( \
14 PKT_TX_OUTER_IP_CKSUM)
17 ice_rxdid_to_proto_xtr_type(uint8_t rxdid)
19 static uint8_t xtr_map[] = {
20 [ICE_RXDID_COMMS_AUX_VLAN] = PROTO_XTR_VLAN,
21 [ICE_RXDID_COMMS_AUX_IPV4] = PROTO_XTR_IPV4,
22 [ICE_RXDID_COMMS_AUX_IPV6] = PROTO_XTR_IPV6,
23 [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = PROTO_XTR_IPV6_FLOW,
24 [ICE_RXDID_COMMS_AUX_TCP] = PROTO_XTR_TCP,
27 return rxdid < RTE_DIM(xtr_map) ? xtr_map[rxdid] : PROTO_XTR_NONE;
31 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
33 static uint8_t rxdid_map[] = {
34 [PROTO_XTR_NONE] = ICE_RXDID_COMMS_GENERIC,
35 [PROTO_XTR_VLAN] = ICE_RXDID_COMMS_AUX_VLAN,
36 [PROTO_XTR_IPV4] = ICE_RXDID_COMMS_AUX_IPV4,
37 [PROTO_XTR_IPV6] = ICE_RXDID_COMMS_AUX_IPV6,
38 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
39 [PROTO_XTR_TCP] = ICE_RXDID_COMMS_AUX_TCP,
42 return xtr_type < RTE_DIM(rxdid_map) ?
43 rxdid_map[xtr_type] : ICE_RXDID_COMMS_GENERIC;
46 static enum ice_status
47 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
49 struct ice_vsi *vsi = rxq->vsi;
50 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
51 struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
52 struct ice_rlan_ctx rx_ctx;
54 uint16_t buf_size, len;
55 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
56 uint32_t rxdid = ICE_RXDID_COMMS_GENERIC;
59 /* Set buffer size as the head split is disabled. */
60 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
61 RTE_PKTMBUF_HEADROOM);
63 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
64 len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
65 rxq->max_pkt_len = RTE_MIN(len,
66 dev->data->dev_conf.rxmode.max_rx_pkt_len);
68 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
69 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
70 rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
71 PMD_DRV_LOG(ERR, "maximum packet length must "
72 "be larger than %u and smaller than %u,"
73 "as jumbo frame is enabled",
74 (uint32_t)RTE_ETHER_MAX_LEN,
75 (uint32_t)ICE_FRAME_SIZE_MAX);
79 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
80 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
81 PMD_DRV_LOG(ERR, "maximum packet length must be "
82 "larger than %u and smaller than %u, "
83 "as jumbo frame is disabled",
84 (uint32_t)RTE_ETHER_MIN_LEN,
85 (uint32_t)RTE_ETHER_MAX_LEN);
90 memset(&rx_ctx, 0, sizeof(rx_ctx));
92 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
93 rx_ctx.qlen = rxq->nb_rx_desc;
94 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
95 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
96 rx_ctx.dtype = 0; /* No Header Split mode */
97 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
98 rx_ctx.dsize = 1; /* 32B descriptors */
100 rx_ctx.rxmax = rxq->max_pkt_len;
101 /* TPH: Transaction Layer Packet (TLP) processing hints */
102 rx_ctx.tphrdesc_ena = 1;
103 rx_ctx.tphwdesc_ena = 1;
104 rx_ctx.tphdata_ena = 1;
105 rx_ctx.tphhead_ena = 1;
106 /* Low Receive Queue Threshold defined in 64 descriptors units.
107 * When the number of free descriptors goes below the lrxqthresh,
108 * an immediate interrupt is triggered.
110 rx_ctx.lrxqthresh = 2;
111 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
114 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
116 rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
118 PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
119 rxq->port_id, rxq->queue_id, rxdid);
121 /* Enable Flexible Descriptors in the queue context which
122 * allows this driver to select a specific receive descriptor format
124 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
125 QRXFLXP_CNTXT_RXDID_IDX_M;
127 /* increasing context priority to pick up profile ID;
128 * default is 0x01; setting to 0x03 to ensure profile
129 * is programming if prev context is of same priority
131 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
132 QRXFLXP_CNTXT_RXDID_PRIO_M;
134 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
136 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
138 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
142 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
144 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
149 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
150 RTE_PKTMBUF_HEADROOM);
152 /* Check if scattered RX needs to be used. */
153 if (rxq->max_pkt_len > buf_size)
154 dev->data->scattered_rx = 1;
156 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
158 /* Init the Rx tail register*/
159 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
164 /* Allocate mbufs for all descriptors in rx queue */
166 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
168 struct ice_rx_entry *rxe = rxq->sw_ring;
172 for (i = 0; i < rxq->nb_rx_desc; i++) {
173 volatile union ice_rx_desc *rxd;
174 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
176 if (unlikely(!mbuf)) {
177 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
181 rte_mbuf_refcnt_set(mbuf, 1);
183 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
185 mbuf->port = rxq->port_id;
188 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
190 rxd = &rxq->rx_ring[i];
191 rxd->read.pkt_addr = dma_addr;
192 rxd->read.hdr_addr = 0;
193 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
203 /* Free all mbufs for descriptors in rx queue */
205 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
209 if (!rxq || !rxq->sw_ring) {
210 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
214 for (i = 0; i < rxq->nb_rx_desc; i++) {
215 if (rxq->sw_ring[i].mbuf) {
216 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
217 rxq->sw_ring[i].mbuf = NULL;
220 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
221 if (rxq->rx_nb_avail == 0)
223 for (i = 0; i < rxq->rx_nb_avail; i++) {
224 struct rte_mbuf *mbuf;
226 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
227 rte_pktmbuf_free_seg(mbuf);
229 rxq->rx_nb_avail = 0;
230 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
234 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
236 rxq->rx_rel_mbufs(rxq);
239 /* turn on or off rx queue
240 * @q_idx: queue index in pf scope
241 * @on: turn on or off the queue
244 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
249 /* QRX_CTRL = QRX_ENA */
250 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
253 if (reg & QRX_CTRL_QENA_STAT_M)
254 return 0; /* Already on, skip */
255 reg |= QRX_CTRL_QENA_REQ_M;
257 if (!(reg & QRX_CTRL_QENA_STAT_M))
258 return 0; /* Already off, skip */
259 reg &= ~QRX_CTRL_QENA_REQ_M;
262 /* Write the register */
263 ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
264 /* Check the result. It is said that QENA_STAT
265 * follows the QENA_REQ not more than 10 use.
266 * TODO: need to change the wait counter later
268 for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
269 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
270 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
272 if ((reg & QRX_CTRL_QENA_REQ_M) &&
273 (reg & QRX_CTRL_QENA_STAT_M))
276 if (!(reg & QRX_CTRL_QENA_REQ_M) &&
277 !(reg & QRX_CTRL_QENA_STAT_M))
282 /* Check if it is timeout */
283 if (j >= ICE_CHK_Q_ENA_COUNT) {
284 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
285 (on ? "enable" : "disable"), q_idx);
293 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
294 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
296 ice_check_rx_burst_bulk_alloc_preconditions
297 (__rte_unused struct ice_rx_queue *rxq)
302 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
303 if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
304 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
305 "rxq->rx_free_thresh=%d, "
306 "ICE_RX_MAX_BURST=%d",
307 rxq->rx_free_thresh, ICE_RX_MAX_BURST);
309 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
310 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
311 "rxq->rx_free_thresh=%d, "
312 "rxq->nb_rx_desc=%d",
313 rxq->rx_free_thresh, rxq->nb_rx_desc);
315 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
316 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
317 "rxq->nb_rx_desc=%d, "
318 "rxq->rx_free_thresh=%d",
319 rxq->nb_rx_desc, rxq->rx_free_thresh);
329 /* reset fields in ice_rx_queue back to default */
331 ice_reset_rx_queue(struct ice_rx_queue *rxq)
337 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
341 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
342 if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
343 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
345 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
346 len = rxq->nb_rx_desc;
348 for (i = 0; i < len * sizeof(union ice_rx_desc); i++)
349 ((volatile char *)rxq->rx_ring)[i] = 0;
351 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
352 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
353 for (i = 0; i < ICE_RX_MAX_BURST; ++i)
354 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
356 rxq->rx_nb_avail = 0;
357 rxq->rx_next_avail = 0;
358 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
359 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
363 rxq->pkt_first_seg = NULL;
364 rxq->pkt_last_seg = NULL;
366 rxq->rxrearm_start = 0;
371 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
373 struct ice_rx_queue *rxq;
375 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
377 PMD_INIT_FUNC_TRACE();
379 if (rx_queue_id >= dev->data->nb_rx_queues) {
380 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
381 rx_queue_id, dev->data->nb_rx_queues);
385 rxq = dev->data->rx_queues[rx_queue_id];
386 if (!rxq || !rxq->q_set) {
387 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
392 err = ice_program_hw_rx_queue(rxq);
394 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
399 err = ice_alloc_rx_queue_mbufs(rxq);
401 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
407 /* Init the RX tail register. */
408 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
410 err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
412 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
415 ice_rx_queue_release_mbufs(rxq);
416 ice_reset_rx_queue(rxq);
420 dev->data->rx_queue_state[rx_queue_id] =
421 RTE_ETH_QUEUE_STATE_STARTED;
427 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
429 struct ice_rx_queue *rxq;
431 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
433 if (rx_queue_id < dev->data->nb_rx_queues) {
434 rxq = dev->data->rx_queues[rx_queue_id];
436 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
438 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
442 ice_rx_queue_release_mbufs(rxq);
443 ice_reset_rx_queue(rxq);
444 dev->data->rx_queue_state[rx_queue_id] =
445 RTE_ETH_QUEUE_STATE_STOPPED;
452 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
454 struct ice_tx_queue *txq;
458 struct ice_aqc_add_tx_qgrp txq_elem;
459 struct ice_tlan_ctx tx_ctx;
461 PMD_INIT_FUNC_TRACE();
463 if (tx_queue_id >= dev->data->nb_tx_queues) {
464 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
465 tx_queue_id, dev->data->nb_tx_queues);
469 txq = dev->data->tx_queues[tx_queue_id];
470 if (!txq || !txq->q_set) {
471 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
477 hw = ICE_VSI_TO_HW(vsi);
479 memset(&txq_elem, 0, sizeof(txq_elem));
480 memset(&tx_ctx, 0, sizeof(tx_ctx));
481 txq_elem.num_txqs = 1;
482 txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
484 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
485 tx_ctx.qlen = txq->nb_tx_desc;
486 tx_ctx.pf_num = hw->pf_id;
487 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
488 tx_ctx.src_vsi = vsi->vsi_id;
489 tx_ctx.port_num = hw->port_info->lport;
490 tx_ctx.tso_ena = 1; /* tso enable */
491 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
492 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
494 ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
497 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
499 /* Init the Tx tail register*/
500 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
502 /* Fix me, we assume TC always 0 here */
503 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
504 &txq_elem, sizeof(txq_elem), NULL);
506 PMD_DRV_LOG(ERR, "Failed to add lan txq");
509 /* store the schedule node id */
510 txq->q_teid = txq_elem.txqs[0].q_teid;
512 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
516 /* Free all mbufs for descriptors in tx queue */
518 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
522 if (!txq || !txq->sw_ring) {
523 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
527 for (i = 0; i < txq->nb_tx_desc; i++) {
528 if (txq->sw_ring[i].mbuf) {
529 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
530 txq->sw_ring[i].mbuf = NULL;
535 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
537 txq->tx_rel_mbufs(txq);
541 ice_reset_tx_queue(struct ice_tx_queue *txq)
543 struct ice_tx_entry *txe;
544 uint16_t i, prev, size;
547 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
552 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
553 for (i = 0; i < size; i++)
554 ((volatile char *)txq->tx_ring)[i] = 0;
556 prev = (uint16_t)(txq->nb_tx_desc - 1);
557 for (i = 0; i < txq->nb_tx_desc; i++) {
558 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
560 txd->cmd_type_offset_bsz =
561 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
564 txe[prev].next_id = i;
568 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
569 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
574 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
575 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
579 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
581 struct ice_tx_queue *txq;
582 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
583 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
584 struct ice_vsi *vsi = pf->main_vsi;
585 enum ice_status status;
588 uint16_t q_handle = tx_queue_id;
590 if (tx_queue_id >= dev->data->nb_tx_queues) {
591 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
592 tx_queue_id, dev->data->nb_tx_queues);
596 txq = dev->data->tx_queues[tx_queue_id];
598 PMD_DRV_LOG(ERR, "TX queue %u is not available",
603 q_ids[0] = txq->reg_idx;
604 q_teids[0] = txq->q_teid;
606 /* Fix me, we assume TC always 0 here */
607 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
608 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
609 if (status != ICE_SUCCESS) {
610 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
614 ice_tx_queue_release_mbufs(txq);
615 ice_reset_tx_queue(txq);
616 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
622 ice_rx_queue_setup(struct rte_eth_dev *dev,
625 unsigned int socket_id,
626 const struct rte_eth_rxconf *rx_conf,
627 struct rte_mempool *mp)
629 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
630 struct ice_adapter *ad =
631 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
632 struct ice_vsi *vsi = pf->main_vsi;
633 struct ice_rx_queue *rxq;
634 const struct rte_memzone *rz;
637 int use_def_burst_func = 1;
639 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
640 nb_desc > ICE_MAX_RING_DESC ||
641 nb_desc < ICE_MIN_RING_DESC) {
642 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
647 /* Free memory if needed */
648 if (dev->data->rx_queues[queue_idx]) {
649 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
650 dev->data->rx_queues[queue_idx] = NULL;
653 /* Allocate the rx queue data structure */
654 rxq = rte_zmalloc_socket(NULL,
655 sizeof(struct ice_rx_queue),
659 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
660 "rx queue data structure");
664 rxq->nb_rx_desc = nb_desc;
665 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
666 rxq->queue_id = queue_idx;
668 rxq->reg_idx = vsi->base_queue + queue_idx;
669 rxq->port_id = dev->data->port_id;
670 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
671 rxq->crc_len = RTE_ETHER_CRC_LEN;
675 rxq->drop_en = rx_conf->rx_drop_en;
677 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
678 rxq->proto_xtr = pf->proto_xtr != NULL ?
679 pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
681 /* Allocate the maximun number of RX ring hardware descriptor. */
682 len = ICE_MAX_RING_DESC;
684 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
686 * Allocating a little more memory because vectorized/bulk_alloc Rx
687 * functions doesn't check boundaries each time.
689 len += ICE_RX_MAX_BURST;
692 /* Allocate the maximum number of RX ring hardware descriptor. */
693 ring_size = sizeof(union ice_rx_desc) * len;
694 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
695 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
696 ring_size, ICE_RING_BASE_ALIGN,
699 ice_rx_queue_release(rxq);
700 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
704 /* Zero all the descriptors in the ring. */
705 memset(rz->addr, 0, ring_size);
707 rxq->rx_ring_dma = rz->iova;
708 rxq->rx_ring = rz->addr;
710 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
711 len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
716 /* Allocate the software ring. */
717 rxq->sw_ring = rte_zmalloc_socket(NULL,
718 sizeof(struct ice_rx_entry) * len,
722 ice_rx_queue_release(rxq);
723 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
727 ice_reset_rx_queue(rxq);
729 dev->data->rx_queues[queue_idx] = rxq;
730 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
732 use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
734 if (!use_def_burst_func) {
735 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
736 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
737 "satisfied. Rx Burst Bulk Alloc function will be "
738 "used on port=%d, queue=%d.",
739 rxq->port_id, rxq->queue_id);
740 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
742 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
743 "not satisfied, Scattered Rx is requested, "
744 "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
745 "not enabled on port=%d, queue=%d.",
746 rxq->port_id, rxq->queue_id);
747 ad->rx_bulk_alloc_allowed = false;
754 ice_rx_queue_release(void *rxq)
756 struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
759 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
763 ice_rx_queue_release_mbufs(q);
764 rte_free(q->sw_ring);
769 ice_tx_queue_setup(struct rte_eth_dev *dev,
772 unsigned int socket_id,
773 const struct rte_eth_txconf *tx_conf)
775 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
776 struct ice_vsi *vsi = pf->main_vsi;
777 struct ice_tx_queue *txq;
778 const struct rte_memzone *tz;
780 uint16_t tx_rs_thresh, tx_free_thresh;
783 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
785 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
786 nb_desc > ICE_MAX_RING_DESC ||
787 nb_desc < ICE_MIN_RING_DESC) {
788 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
794 * The following two parameters control the setting of the RS bit on
795 * transmit descriptors. TX descriptors will have their RS bit set
796 * after txq->tx_rs_thresh descriptors have been used. The TX
797 * descriptor ring will be cleaned after txq->tx_free_thresh
798 * descriptors are used or if the number of descriptors required to
799 * transmit a packet is greater than the number of free TX descriptors.
801 * The following constraints must be satisfied:
802 * - tx_rs_thresh must be greater than 0.
803 * - tx_rs_thresh must be less than the size of the ring minus 2.
804 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
805 * - tx_rs_thresh must be a divisor of the ring size.
806 * - tx_free_thresh must be greater than 0.
807 * - tx_free_thresh must be less than the size of the ring minus 3.
808 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
810 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
811 * race condition, hence the maximum threshold constraints. When set
812 * to zero use default values.
814 tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
815 tx_conf->tx_free_thresh :
816 ICE_DEFAULT_TX_FREE_THRESH);
817 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
819 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
820 nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
821 if (tx_conf->tx_rs_thresh)
822 tx_rs_thresh = tx_conf->tx_rs_thresh;
823 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
824 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
825 "exceed nb_desc. (tx_rs_thresh=%u "
826 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
827 (unsigned int)tx_rs_thresh,
828 (unsigned int)tx_free_thresh,
829 (unsigned int)nb_desc,
830 (int)dev->data->port_id,
834 if (tx_rs_thresh >= (nb_desc - 2)) {
835 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
836 "number of TX descriptors minus 2. "
837 "(tx_rs_thresh=%u port=%d queue=%d)",
838 (unsigned int)tx_rs_thresh,
839 (int)dev->data->port_id,
843 if (tx_free_thresh >= (nb_desc - 3)) {
844 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
845 "tx_free_thresh must be less than the "
846 "number of TX descriptors minus 3. "
847 "(tx_free_thresh=%u port=%d queue=%d)",
848 (unsigned int)tx_free_thresh,
849 (int)dev->data->port_id,
853 if (tx_rs_thresh > tx_free_thresh) {
854 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
855 "equal to tx_free_thresh. (tx_free_thresh=%u"
856 " tx_rs_thresh=%u port=%d queue=%d)",
857 (unsigned int)tx_free_thresh,
858 (unsigned int)tx_rs_thresh,
859 (int)dev->data->port_id,
863 if ((nb_desc % tx_rs_thresh) != 0) {
864 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
865 "number of TX descriptors. (tx_rs_thresh=%u"
866 " port=%d queue=%d)",
867 (unsigned int)tx_rs_thresh,
868 (int)dev->data->port_id,
872 if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
873 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
874 "tx_rs_thresh is greater than 1. "
875 "(tx_rs_thresh=%u port=%d queue=%d)",
876 (unsigned int)tx_rs_thresh,
877 (int)dev->data->port_id,
882 /* Free memory if needed. */
883 if (dev->data->tx_queues[queue_idx]) {
884 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
885 dev->data->tx_queues[queue_idx] = NULL;
888 /* Allocate the TX queue data structure. */
889 txq = rte_zmalloc_socket(NULL,
890 sizeof(struct ice_tx_queue),
894 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
895 "tx queue structure");
899 /* Allocate TX hardware ring descriptors. */
900 ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
901 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
902 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
903 ring_size, ICE_RING_BASE_ALIGN,
906 ice_tx_queue_release(txq);
907 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
911 txq->nb_tx_desc = nb_desc;
912 txq->tx_rs_thresh = tx_rs_thresh;
913 txq->tx_free_thresh = tx_free_thresh;
914 txq->pthresh = tx_conf->tx_thresh.pthresh;
915 txq->hthresh = tx_conf->tx_thresh.hthresh;
916 txq->wthresh = tx_conf->tx_thresh.wthresh;
917 txq->queue_id = queue_idx;
919 txq->reg_idx = vsi->base_queue + queue_idx;
920 txq->port_id = dev->data->port_id;
921 txq->offloads = offloads;
923 txq->tx_deferred_start = tx_conf->tx_deferred_start;
925 txq->tx_ring_dma = tz->iova;
926 txq->tx_ring = tz->addr;
928 /* Allocate software ring */
930 rte_zmalloc_socket(NULL,
931 sizeof(struct ice_tx_entry) * nb_desc,
935 ice_tx_queue_release(txq);
936 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
940 ice_reset_tx_queue(txq);
942 dev->data->tx_queues[queue_idx] = txq;
943 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
944 ice_set_tx_function_flag(dev, txq);
950 ice_tx_queue_release(void *txq)
952 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
955 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
959 ice_tx_queue_release_mbufs(q);
960 rte_free(q->sw_ring);
965 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
966 struct rte_eth_rxq_info *qinfo)
968 struct ice_rx_queue *rxq;
970 rxq = dev->data->rx_queues[queue_id];
973 qinfo->scattered_rx = dev->data->scattered_rx;
974 qinfo->nb_desc = rxq->nb_rx_desc;
976 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
977 qinfo->conf.rx_drop_en = rxq->drop_en;
978 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
982 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
983 struct rte_eth_txq_info *qinfo)
985 struct ice_tx_queue *txq;
987 txq = dev->data->tx_queues[queue_id];
989 qinfo->nb_desc = txq->nb_tx_desc;
991 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
992 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
993 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
995 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
996 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
997 qinfo->conf.offloads = txq->offloads;
998 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1002 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1004 #define ICE_RXQ_SCAN_INTERVAL 4
1005 volatile union ice_rx_flex_desc *rxdp;
1006 struct ice_rx_queue *rxq;
1009 rxq = dev->data->rx_queues[rx_queue_id];
1010 rxdp = (volatile union ice_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1011 while ((desc < rxq->nb_rx_desc) &&
1012 rte_le_to_cpu_16(rxdp->wb.status_error0) &
1013 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1015 * Check the DD bit of a rx descriptor of each 4 in a group,
1016 * to avoid checking too frequently and downgrading performance
1019 desc += ICE_RXQ_SCAN_INTERVAL;
1020 rxdp += ICE_RXQ_SCAN_INTERVAL;
1021 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1022 rxdp = (volatile union ice_rx_flex_desc *)
1023 &(rxq->rx_ring[rxq->rx_tail +
1024 desc - rxq->nb_rx_desc]);
1030 #define ICE_RX_FLEX_ERR0_BITS \
1031 ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) | \
1032 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1033 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1034 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1035 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1036 (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1038 /* Rx L3/L4 checksum */
1039 static inline uint64_t
1040 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1044 /* check if HW has decoded the packet and checksum */
1045 if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1048 if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1049 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1053 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1054 flags |= PKT_RX_IP_CKSUM_BAD;
1056 flags |= PKT_RX_IP_CKSUM_GOOD;
1058 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1059 flags |= PKT_RX_L4_CKSUM_BAD;
1061 flags |= PKT_RX_L4_CKSUM_GOOD;
1063 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1064 flags |= PKT_RX_EIP_CKSUM_BAD;
1070 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1072 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1073 (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1074 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1076 rte_le_to_cpu_16(rxdp->wb.l2tag1);
1077 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1078 rte_le_to_cpu_16(rxdp->wb.l2tag1));
1083 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1084 if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1085 (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1086 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1087 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1088 mb->vlan_tci_outer = mb->vlan_tci;
1089 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1090 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1091 rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1092 rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1094 mb->vlan_tci_outer = 0;
1097 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1098 mb->vlan_tci, mb->vlan_tci_outer);
1101 #define ICE_RX_PROTO_XTR_VALID \
1102 ((1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) | \
1103 (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1106 ice_rxd_to_pkt_fields(struct rte_mbuf *mb,
1107 volatile union ice_rx_flex_desc *rxdp)
1109 volatile struct ice_32b_rx_flex_desc_comms *desc =
1110 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
1113 stat_err = rte_le_to_cpu_16(desc->status_error0);
1114 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
1115 mb->ol_flags |= PKT_RX_RSS_HASH;
1116 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
1119 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1120 init_proto_xtr_flds(mb);
1122 stat_err = rte_le_to_cpu_16(desc->status_error1);
1123 if (stat_err & ICE_RX_PROTO_XTR_VALID) {
1124 struct proto_xtr_flds *xtr = get_proto_xtr_flds(mb);
1126 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
1128 rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
1130 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1132 rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
1134 xtr->type = ice_rxdid_to_proto_xtr_type(desc->rxdid);
1135 xtr->magic = PROTO_XTR_MAGIC_ID;
1140 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1141 #define ICE_LOOK_AHEAD 8
1142 #if (ICE_LOOK_AHEAD != 8)
1143 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1146 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1148 volatile union ice_rx_flex_desc *rxdp;
1149 struct ice_rx_entry *rxep;
1150 struct rte_mbuf *mb;
1153 int32_t s[ICE_LOOK_AHEAD], nb_dd;
1154 int32_t i, j, nb_rx = 0;
1155 uint64_t pkt_flags = 0;
1156 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1158 rxdp = (volatile union ice_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1159 rxep = &rxq->sw_ring[rxq->rx_tail];
1161 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1163 /* Make sure there is at least 1 packet to receive */
1164 if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1168 * Scan LOOK_AHEAD descriptors at a time to determine which
1169 * descriptors reference packets that are ready to be received.
1171 for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1172 rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1173 /* Read desc statuses backwards to avoid race condition */
1174 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1175 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1179 /* Compute how many status bits were set */
1180 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1181 nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1185 /* Translate descriptor info to mbuf parameters */
1186 for (j = 0; j < nb_dd; j++) {
1188 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1189 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1190 mb->data_len = pkt_len;
1191 mb->pkt_len = pkt_len;
1193 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1194 pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1195 mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1196 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1197 ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1198 ice_rxd_to_pkt_fields(mb, &rxdp[j]);
1200 mb->ol_flags |= pkt_flags;
1203 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1204 rxq->rx_stage[i + j] = rxep[j].mbuf;
1206 if (nb_dd != ICE_LOOK_AHEAD)
1210 /* Clear software ring entries */
1211 for (i = 0; i < nb_rx; i++)
1212 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1214 PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1215 "port_id=%u, queue_id=%u, nb_rx=%d",
1216 rxq->port_id, rxq->queue_id, nb_rx);
1221 static inline uint16_t
1222 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1223 struct rte_mbuf **rx_pkts,
1227 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1229 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1231 for (i = 0; i < nb_pkts; i++)
1232 rx_pkts[i] = stage[i];
1234 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1235 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1241 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1243 volatile union ice_rx_desc *rxdp;
1244 struct ice_rx_entry *rxep;
1245 struct rte_mbuf *mb;
1246 uint16_t alloc_idx, i;
1250 /* Allocate buffers in bulk */
1251 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1252 (rxq->rx_free_thresh - 1));
1253 rxep = &rxq->sw_ring[alloc_idx];
1254 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1255 rxq->rx_free_thresh);
1256 if (unlikely(diag != 0)) {
1257 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1261 rxdp = &rxq->rx_ring[alloc_idx];
1262 for (i = 0; i < rxq->rx_free_thresh; i++) {
1263 if (likely(i < (rxq->rx_free_thresh - 1)))
1264 /* Prefetch next mbuf */
1265 rte_prefetch0(rxep[i + 1].mbuf);
1268 rte_mbuf_refcnt_set(mb, 1);
1270 mb->data_off = RTE_PKTMBUF_HEADROOM;
1272 mb->port = rxq->port_id;
1273 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1274 rxdp[i].read.hdr_addr = 0;
1275 rxdp[i].read.pkt_addr = dma_addr;
1278 /* Update rx tail regsiter */
1280 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1282 rxq->rx_free_trigger =
1283 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1284 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1285 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1290 static inline uint16_t
1291 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1293 struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1295 struct rte_eth_dev *dev;
1300 if (rxq->rx_nb_avail)
1301 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1303 nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1304 rxq->rx_next_avail = 0;
1305 rxq->rx_nb_avail = nb_rx;
1306 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1308 if (rxq->rx_tail > rxq->rx_free_trigger) {
1309 if (ice_rx_alloc_bufs(rxq) != 0) {
1312 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1313 dev->data->rx_mbuf_alloc_failed +=
1314 rxq->rx_free_thresh;
1315 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1316 "port_id=%u, queue_id=%u",
1317 rxq->port_id, rxq->queue_id);
1318 rxq->rx_nb_avail = 0;
1319 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1320 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1321 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1327 if (rxq->rx_tail >= rxq->nb_rx_desc)
1330 if (rxq->rx_nb_avail)
1331 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1337 ice_recv_pkts_bulk_alloc(void *rx_queue,
1338 struct rte_mbuf **rx_pkts,
1345 if (unlikely(nb_pkts == 0))
1348 if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1349 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1352 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1353 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1354 nb_rx = (uint16_t)(nb_rx + count);
1355 nb_pkts = (uint16_t)(nb_pkts - count);
1364 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1365 struct rte_mbuf __rte_unused **rx_pkts,
1366 uint16_t __rte_unused nb_pkts)
1370 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1373 ice_recv_scattered_pkts(void *rx_queue,
1374 struct rte_mbuf **rx_pkts,
1377 struct ice_rx_queue *rxq = rx_queue;
1378 volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1379 volatile union ice_rx_flex_desc *rxdp;
1380 union ice_rx_flex_desc rxd;
1381 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1382 struct ice_rx_entry *rxe;
1383 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1384 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1385 struct rte_mbuf *nmb; /* new allocated mbuf */
1386 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1387 uint16_t rx_id = rxq->rx_tail;
1389 uint16_t nb_hold = 0;
1390 uint16_t rx_packet_len;
1391 uint16_t rx_stat_err0;
1394 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1395 struct rte_eth_dev *dev;
1397 while (nb_rx < nb_pkts) {
1398 rxdp = (volatile union ice_rx_flex_desc *)&rx_ring[rx_id];
1399 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1401 /* Check the DD bit first */
1402 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1406 nmb = rte_mbuf_raw_alloc(rxq->mp);
1407 if (unlikely(!nmb)) {
1408 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1409 dev->data->rx_mbuf_alloc_failed++;
1412 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1415 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1417 if (unlikely(rx_id == rxq->nb_rx_desc))
1420 /* Prefetch next mbuf */
1421 rte_prefetch0(sw_ring[rx_id].mbuf);
1424 * When next RX descriptor is on a cache line boundary,
1425 * prefetch the next 4 RX descriptors and next 8 pointers
1428 if ((rx_id & 0x3) == 0) {
1429 rte_prefetch0(&rx_ring[rx_id]);
1430 rte_prefetch0(&sw_ring[rx_id]);
1436 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1438 /* Set data buffer address and data length of the mbuf */
1439 rxdp->read.hdr_addr = 0;
1440 rxdp->read.pkt_addr = dma_addr;
1441 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1442 ICE_RX_FLX_DESC_PKT_LEN_M;
1443 rxm->data_len = rx_packet_len;
1444 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1447 * If this is the first buffer of the received packet, set the
1448 * pointer to the first mbuf of the packet and initialize its
1449 * context. Otherwise, update the total length and the number
1450 * of segments of the current scattered packet, and update the
1451 * pointer to the last mbuf of the current packet.
1455 first_seg->nb_segs = 1;
1456 first_seg->pkt_len = rx_packet_len;
1458 first_seg->pkt_len =
1459 (uint16_t)(first_seg->pkt_len +
1461 first_seg->nb_segs++;
1462 last_seg->next = rxm;
1466 * If this is not the last buffer of the received packet,
1467 * update the pointer to the last mbuf of the current scattered
1468 * packet and continue to parse the RX ring.
1470 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1476 * This is the last buffer of the received packet. If the CRC
1477 * is not stripped by the hardware:
1478 * - Subtract the CRC length from the total packet length.
1479 * - If the last buffer only contains the whole CRC or a part
1480 * of it, free the mbuf associated to the last buffer. If part
1481 * of the CRC is also contained in the previous mbuf, subtract
1482 * the length of that CRC part from the data length of the
1486 if (unlikely(rxq->crc_len > 0)) {
1487 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1488 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1489 rte_pktmbuf_free_seg(rxm);
1490 first_seg->nb_segs--;
1491 last_seg->data_len =
1492 (uint16_t)(last_seg->data_len -
1493 (RTE_ETHER_CRC_LEN - rx_packet_len));
1494 last_seg->next = NULL;
1496 rxm->data_len = (uint16_t)(rx_packet_len -
1500 first_seg->port = rxq->port_id;
1501 first_seg->ol_flags = 0;
1502 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1503 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1504 ice_rxd_to_vlan_tci(first_seg, &rxd);
1505 ice_rxd_to_pkt_fields(first_seg, &rxd);
1506 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1507 first_seg->ol_flags |= pkt_flags;
1508 /* Prefetch data of first segment, if configured to do so. */
1509 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1510 first_seg->data_off));
1511 rx_pkts[nb_rx++] = first_seg;
1515 /* Record index of the next RX descriptor to probe. */
1516 rxq->rx_tail = rx_id;
1517 rxq->pkt_first_seg = first_seg;
1518 rxq->pkt_last_seg = last_seg;
1521 * If the number of free RX descriptors is greater than the RX free
1522 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1523 * register. Update the RDT with the value of the last processed RX
1524 * descriptor minus 1, to guarantee that the RDT register is never
1525 * equal to the RDH register, which creates a "full" ring situtation
1526 * from the hardware point of view.
1528 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1529 if (nb_hold > rxq->rx_free_thresh) {
1530 rx_id = (uint16_t)(rx_id == 0 ?
1531 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1532 /* write TAIL register */
1533 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1536 rxq->nb_rx_hold = nb_hold;
1538 /* return received packet in the burst */
1543 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1545 static const uint32_t ptypes[] = {
1546 /* refers to ice_get_default_pkt_type() */
1548 RTE_PTYPE_L2_ETHER_LLDP,
1549 RTE_PTYPE_L2_ETHER_ARP,
1550 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1551 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1554 RTE_PTYPE_L4_NONFRAG,
1558 RTE_PTYPE_TUNNEL_GRENAT,
1559 RTE_PTYPE_TUNNEL_IP,
1560 RTE_PTYPE_INNER_L2_ETHER,
1561 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1562 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1563 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1564 RTE_PTYPE_INNER_L4_FRAG,
1565 RTE_PTYPE_INNER_L4_ICMP,
1566 RTE_PTYPE_INNER_L4_NONFRAG,
1567 RTE_PTYPE_INNER_L4_SCTP,
1568 RTE_PTYPE_INNER_L4_TCP,
1569 RTE_PTYPE_INNER_L4_UDP,
1570 RTE_PTYPE_TUNNEL_GTPC,
1571 RTE_PTYPE_TUNNEL_GTPU,
1575 if (dev->rx_pkt_burst == ice_recv_pkts ||
1576 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1577 dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1579 dev->rx_pkt_burst == ice_recv_scattered_pkts)
1583 if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1584 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1585 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1586 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1594 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1596 volatile union ice_rx_flex_desc *rxdp;
1597 struct ice_rx_queue *rxq = rx_queue;
1600 if (unlikely(offset >= rxq->nb_rx_desc))
1603 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1604 return RTE_ETH_RX_DESC_UNAVAIL;
1606 desc = rxq->rx_tail + offset;
1607 if (desc >= rxq->nb_rx_desc)
1608 desc -= rxq->nb_rx_desc;
1610 rxdp = (volatile union ice_rx_flex_desc *)&rxq->rx_ring[desc];
1611 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1612 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1613 return RTE_ETH_RX_DESC_DONE;
1615 return RTE_ETH_RX_DESC_AVAIL;
1619 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1621 struct ice_tx_queue *txq = tx_queue;
1622 volatile uint64_t *status;
1623 uint64_t mask, expect;
1626 if (unlikely(offset >= txq->nb_tx_desc))
1629 desc = txq->tx_tail + offset;
1630 /* go to next desc that has the RS bit */
1631 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1633 if (desc >= txq->nb_tx_desc) {
1634 desc -= txq->nb_tx_desc;
1635 if (desc >= txq->nb_tx_desc)
1636 desc -= txq->nb_tx_desc;
1639 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1640 mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1641 expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1642 ICE_TXD_QW1_DTYPE_S);
1643 if ((*status & mask) == expect)
1644 return RTE_ETH_TX_DESC_DONE;
1646 return RTE_ETH_TX_DESC_FULL;
1650 ice_clear_queues(struct rte_eth_dev *dev)
1654 PMD_INIT_FUNC_TRACE();
1656 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1657 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1658 ice_reset_tx_queue(dev->data->tx_queues[i]);
1661 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1662 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1663 ice_reset_rx_queue(dev->data->rx_queues[i]);
1668 ice_free_queues(struct rte_eth_dev *dev)
1672 PMD_INIT_FUNC_TRACE();
1674 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1675 if (!dev->data->rx_queues[i])
1677 ice_rx_queue_release(dev->data->rx_queues[i]);
1678 dev->data->rx_queues[i] = NULL;
1680 dev->data->nb_rx_queues = 0;
1682 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1683 if (!dev->data->tx_queues[i])
1685 ice_tx_queue_release(dev->data->tx_queues[i]);
1686 dev->data->tx_queues[i] = NULL;
1688 dev->data->nb_tx_queues = 0;
1692 ice_recv_pkts(void *rx_queue,
1693 struct rte_mbuf **rx_pkts,
1696 struct ice_rx_queue *rxq = rx_queue;
1697 volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1698 volatile union ice_rx_flex_desc *rxdp;
1699 union ice_rx_flex_desc rxd;
1700 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1701 struct ice_rx_entry *rxe;
1702 struct rte_mbuf *nmb; /* new allocated mbuf */
1703 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1704 uint16_t rx_id = rxq->rx_tail;
1706 uint16_t nb_hold = 0;
1707 uint16_t rx_packet_len;
1708 uint16_t rx_stat_err0;
1711 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1712 struct rte_eth_dev *dev;
1714 while (nb_rx < nb_pkts) {
1715 rxdp = (volatile union ice_rx_flex_desc *)&rx_ring[rx_id];
1716 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1718 /* Check the DD bit first */
1719 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1723 nmb = rte_mbuf_raw_alloc(rxq->mp);
1724 if (unlikely(!nmb)) {
1725 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1726 dev->data->rx_mbuf_alloc_failed++;
1729 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1732 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1734 if (unlikely(rx_id == rxq->nb_rx_desc))
1739 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1742 * fill the read format of descriptor with physic address in
1743 * new allocated mbuf: nmb
1745 rxdp->read.hdr_addr = 0;
1746 rxdp->read.pkt_addr = dma_addr;
1748 /* calculate rx_packet_len of the received pkt */
1749 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1750 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1752 /* fill old mbuf with received descriptor: rxd */
1753 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1754 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1757 rxm->pkt_len = rx_packet_len;
1758 rxm->data_len = rx_packet_len;
1759 rxm->port = rxq->port_id;
1760 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1761 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1762 ice_rxd_to_vlan_tci(rxm, &rxd);
1763 ice_rxd_to_pkt_fields(rxm, &rxd);
1764 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1765 rxm->ol_flags |= pkt_flags;
1766 /* copy old mbuf to rx_pkts */
1767 rx_pkts[nb_rx++] = rxm;
1769 rxq->rx_tail = rx_id;
1771 * If the number of free RX descriptors is greater than the RX free
1772 * threshold of the queue, advance the receive tail register of queue.
1773 * Update that register with the value of the last processed RX
1774 * descriptor minus 1.
1776 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1777 if (nb_hold > rxq->rx_free_thresh) {
1778 rx_id = (uint16_t)(rx_id == 0 ?
1779 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1780 /* write TAIL register */
1781 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1784 rxq->nb_rx_hold = nb_hold;
1786 /* return received packet in the burst */
1791 ice_parse_tunneling_params(uint64_t ol_flags,
1792 union ice_tx_offload tx_offload,
1793 uint32_t *cd_tunneling)
1795 /* EIPT: External (outer) IP header type */
1796 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
1797 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
1798 else if (ol_flags & PKT_TX_OUTER_IPV4)
1799 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
1800 else if (ol_flags & PKT_TX_OUTER_IPV6)
1801 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
1803 /* EIPLEN: External (outer) IP header length, in DWords */
1804 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
1805 ICE_TXD_CTX_QW0_EIPLEN_S;
1807 /* L4TUNT: L4 Tunneling Type */
1808 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
1809 case PKT_TX_TUNNEL_IPIP:
1810 /* for non UDP / GRE tunneling, set to 00b */
1812 case PKT_TX_TUNNEL_VXLAN:
1813 case PKT_TX_TUNNEL_GENEVE:
1814 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
1816 case PKT_TX_TUNNEL_GRE:
1817 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
1820 PMD_TX_LOG(ERR, "Tunnel type not supported");
1824 /* L4TUNLEN: L4 Tunneling Length, in Words
1826 * We depend on app to set rte_mbuf.l2_len correctly.
1827 * For IP in GRE it should be set to the length of the GRE
1829 * For MAC in GRE or MAC in UDP it should be set to the length
1830 * of the GRE or UDP headers plus the inner MAC up to including
1831 * its last Ethertype.
1832 * If MPLS labels exists, it should include them as well.
1834 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
1835 ICE_TXD_CTX_QW0_NATLEN_S;
1837 if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
1838 (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
1839 (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
1840 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
1844 ice_txd_enable_checksum(uint64_t ol_flags,
1846 uint32_t *td_offset,
1847 union ice_tx_offload tx_offload)
1850 if (ol_flags & PKT_TX_TUNNEL_MASK)
1851 *td_offset |= (tx_offload.outer_l2_len >> 1)
1852 << ICE_TX_DESC_LEN_MACLEN_S;
1854 *td_offset |= (tx_offload.l2_len >> 1)
1855 << ICE_TX_DESC_LEN_MACLEN_S;
1857 /* Enable L3 checksum offloads */
1858 if (ol_flags & PKT_TX_IP_CKSUM) {
1859 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1860 *td_offset |= (tx_offload.l3_len >> 2) <<
1861 ICE_TX_DESC_LEN_IPLEN_S;
1862 } else if (ol_flags & PKT_TX_IPV4) {
1863 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1864 *td_offset |= (tx_offload.l3_len >> 2) <<
1865 ICE_TX_DESC_LEN_IPLEN_S;
1866 } else if (ol_flags & PKT_TX_IPV6) {
1867 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1868 *td_offset |= (tx_offload.l3_len >> 2) <<
1869 ICE_TX_DESC_LEN_IPLEN_S;
1872 if (ol_flags & PKT_TX_TCP_SEG) {
1873 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1874 *td_offset |= (tx_offload.l4_len >> 2) <<
1875 ICE_TX_DESC_LEN_L4_LEN_S;
1879 /* Enable L4 checksum offloads */
1880 switch (ol_flags & PKT_TX_L4_MASK) {
1881 case PKT_TX_TCP_CKSUM:
1882 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1883 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
1884 ICE_TX_DESC_LEN_L4_LEN_S;
1886 case PKT_TX_SCTP_CKSUM:
1887 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1888 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
1889 ICE_TX_DESC_LEN_L4_LEN_S;
1891 case PKT_TX_UDP_CKSUM:
1892 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1893 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
1894 ICE_TX_DESC_LEN_L4_LEN_S;
1902 ice_xmit_cleanup(struct ice_tx_queue *txq)
1904 struct ice_tx_entry *sw_ring = txq->sw_ring;
1905 volatile struct ice_tx_desc *txd = txq->tx_ring;
1906 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1907 uint16_t nb_tx_desc = txq->nb_tx_desc;
1908 uint16_t desc_to_clean_to;
1909 uint16_t nb_tx_to_clean;
1911 /* Determine the last descriptor needing to be cleaned */
1912 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1913 if (desc_to_clean_to >= nb_tx_desc)
1914 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1916 /* Check to make sure the last descriptor to clean is done */
1917 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1918 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
1919 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
1920 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1921 "(port=%d queue=%d) value=0x%"PRIx64"\n",
1923 txq->port_id, txq->queue_id,
1924 txd[desc_to_clean_to].cmd_type_offset_bsz);
1925 /* Failed to clean any descriptors */
1929 /* Figure out how many descriptors will be cleaned */
1930 if (last_desc_cleaned > desc_to_clean_to)
1931 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1934 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1937 /* The last descriptor to clean is done, so that means all the
1938 * descriptors from the last descriptor that was cleaned
1939 * up to the last descriptor with the RS bit set
1940 * are done. Only reset the threshold descriptor.
1942 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1944 /* Update the txq to reflect the last descriptor that was cleaned */
1945 txq->last_desc_cleaned = desc_to_clean_to;
1946 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1951 /* Construct the tx flags */
1952 static inline uint64_t
1953 ice_build_ctob(uint32_t td_cmd,
1958 return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1959 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
1960 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1961 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
1962 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
1965 /* Check if the context descriptor is needed for TX offloading */
1966 static inline uint16_t
1967 ice_calc_context_desc(uint64_t flags)
1969 static uint64_t mask = PKT_TX_TCP_SEG |
1971 PKT_TX_OUTER_IP_CKSUM |
1974 return (flags & mask) ? 1 : 0;
1977 /* set ice TSO context descriptor */
1978 static inline uint64_t
1979 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
1981 uint64_t ctx_desc = 0;
1982 uint32_t cd_cmd, hdr_len, cd_tso_len;
1984 if (!tx_offload.l4_len) {
1985 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1989 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1990 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
1991 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1993 cd_cmd = ICE_TX_CTX_DESC_TSO;
1994 cd_tso_len = mbuf->pkt_len - hdr_len;
1995 ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
1996 ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1997 ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2003 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2005 struct ice_tx_queue *txq;
2006 volatile struct ice_tx_desc *tx_ring;
2007 volatile struct ice_tx_desc *txd;
2008 struct ice_tx_entry *sw_ring;
2009 struct ice_tx_entry *txe, *txn;
2010 struct rte_mbuf *tx_pkt;
2011 struct rte_mbuf *m_seg;
2012 uint32_t cd_tunneling_params;
2017 uint32_t td_cmd = 0;
2018 uint32_t td_offset = 0;
2019 uint32_t td_tag = 0;
2021 uint64_t buf_dma_addr;
2023 union ice_tx_offload tx_offload = {0};
2026 sw_ring = txq->sw_ring;
2027 tx_ring = txq->tx_ring;
2028 tx_id = txq->tx_tail;
2029 txe = &sw_ring[tx_id];
2031 /* Check if the descriptor ring needs to be cleaned. */
2032 if (txq->nb_tx_free < txq->tx_free_thresh)
2033 ice_xmit_cleanup(txq);
2035 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2036 tx_pkt = *tx_pkts++;
2039 ol_flags = tx_pkt->ol_flags;
2040 tx_offload.l2_len = tx_pkt->l2_len;
2041 tx_offload.l3_len = tx_pkt->l3_len;
2042 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2043 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2044 tx_offload.l4_len = tx_pkt->l4_len;
2045 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2046 /* Calculate the number of context descriptors needed. */
2047 nb_ctx = ice_calc_context_desc(ol_flags);
2049 /* The number of descriptors that must be allocated for
2050 * a packet equals to the number of the segments of that
2051 * packet plus the number of context descriptor if needed.
2053 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2054 tx_last = (uint16_t)(tx_id + nb_used - 1);
2057 if (tx_last >= txq->nb_tx_desc)
2058 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2060 if (nb_used > txq->nb_tx_free) {
2061 if (ice_xmit_cleanup(txq) != 0) {
2066 if (unlikely(nb_used > txq->tx_rs_thresh)) {
2067 while (nb_used > txq->nb_tx_free) {
2068 if (ice_xmit_cleanup(txq) != 0) {
2077 /* Descriptor based VLAN insertion */
2078 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2079 td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2080 td_tag = tx_pkt->vlan_tci;
2083 /* Fill in tunneling parameters if necessary */
2084 cd_tunneling_params = 0;
2085 if (ol_flags & PKT_TX_TUNNEL_MASK)
2086 ice_parse_tunneling_params(ol_flags, tx_offload,
2087 &cd_tunneling_params);
2089 /* Enable checksum offloading */
2090 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
2091 ice_txd_enable_checksum(ol_flags, &td_cmd,
2092 &td_offset, tx_offload);
2096 /* Setup TX context descriptor if required */
2097 volatile struct ice_tx_ctx_desc *ctx_txd =
2098 (volatile struct ice_tx_ctx_desc *)
2100 uint16_t cd_l2tag2 = 0;
2101 uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2103 txn = &sw_ring[txe->next_id];
2104 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2106 rte_pktmbuf_free_seg(txe->mbuf);
2110 if (ol_flags & PKT_TX_TCP_SEG)
2111 cd_type_cmd_tso_mss |=
2112 ice_set_tso_ctx(tx_pkt, tx_offload);
2114 ctx_txd->tunneling_params =
2115 rte_cpu_to_le_32(cd_tunneling_params);
2117 /* TX context descriptor based double VLAN insert */
2118 if (ol_flags & PKT_TX_QINQ) {
2119 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2120 cd_type_cmd_tso_mss |=
2121 ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2122 ICE_TXD_CTX_QW1_CMD_S);
2124 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2126 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2128 txe->last_id = tx_last;
2129 tx_id = txe->next_id;
2135 txd = &tx_ring[tx_id];
2136 txn = &sw_ring[txe->next_id];
2139 rte_pktmbuf_free_seg(txe->mbuf);
2142 /* Setup TX Descriptor */
2143 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2144 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2145 txd->cmd_type_offset_bsz =
2146 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2147 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2148 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2149 ((uint64_t)m_seg->data_len <<
2150 ICE_TXD_QW1_TX_BUF_SZ_S) |
2151 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2153 txe->last_id = tx_last;
2154 tx_id = txe->next_id;
2156 m_seg = m_seg->next;
2159 /* fill the last descriptor with End of Packet (EOP) bit */
2160 td_cmd |= ICE_TX_DESC_CMD_EOP;
2161 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2162 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2164 /* set RS bit on the last descriptor of one packet */
2165 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2166 PMD_TX_FREE_LOG(DEBUG,
2167 "Setting RS bit on TXD id="
2168 "%4u (port=%d queue=%d)",
2169 tx_last, txq->port_id, txq->queue_id);
2171 td_cmd |= ICE_TX_DESC_CMD_RS;
2173 /* Update txq RS bit counters */
2174 txq->nb_tx_used = 0;
2176 txd->cmd_type_offset_bsz |=
2177 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2183 /* update Tail register */
2184 ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2185 txq->tx_tail = tx_id;
2190 static inline int __attribute__((always_inline))
2191 ice_tx_free_bufs(struct ice_tx_queue *txq)
2193 struct ice_tx_entry *txep;
2196 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2197 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2198 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2201 txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2203 for (i = 0; i < txq->tx_rs_thresh; i++)
2204 rte_prefetch0((txep + i)->mbuf);
2206 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2207 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2208 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2212 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2213 rte_pktmbuf_free_seg(txep->mbuf);
2218 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2219 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2220 if (txq->tx_next_dd >= txq->nb_tx_desc)
2221 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2223 return txq->tx_rs_thresh;
2226 /* Populate 4 descriptors with data from 4 mbufs */
2228 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2233 for (i = 0; i < 4; i++, txdp++, pkts++) {
2234 dma_addr = rte_mbuf_data_iova(*pkts);
2235 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2236 txdp->cmd_type_offset_bsz =
2237 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2238 (*pkts)->data_len, 0);
2242 /* Populate 1 descriptor with data from 1 mbuf */
2244 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2248 dma_addr = rte_mbuf_data_iova(*pkts);
2249 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2250 txdp->cmd_type_offset_bsz =
2251 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2252 (*pkts)->data_len, 0);
2256 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2259 volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2260 struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2261 const int N_PER_LOOP = 4;
2262 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2263 int mainpart, leftover;
2267 * Process most of the packets in chunks of N pkts. Any
2268 * leftover packets will get processed one at a time.
2270 mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2271 leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2272 for (i = 0; i < mainpart; i += N_PER_LOOP) {
2273 /* Copy N mbuf pointers to the S/W ring */
2274 for (j = 0; j < N_PER_LOOP; ++j)
2275 (txep + i + j)->mbuf = *(pkts + i + j);
2276 tx4(txdp + i, pkts + i);
2279 if (unlikely(leftover > 0)) {
2280 for (i = 0; i < leftover; ++i) {
2281 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2282 tx1(txdp + mainpart + i, pkts + mainpart + i);
2287 static inline uint16_t
2288 tx_xmit_pkts(struct ice_tx_queue *txq,
2289 struct rte_mbuf **tx_pkts,
2292 volatile struct ice_tx_desc *txr = txq->tx_ring;
2296 * Begin scanning the H/W ring for done descriptors when the number
2297 * of available descriptors drops below tx_free_thresh. For each done
2298 * descriptor, free the associated buffer.
2300 if (txq->nb_tx_free < txq->tx_free_thresh)
2301 ice_tx_free_bufs(txq);
2303 /* Use available descriptor only */
2304 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2305 if (unlikely(!nb_pkts))
2308 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2309 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2310 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2311 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2312 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2313 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2315 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2319 /* Fill hardware descriptor ring with mbuf data */
2320 ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2321 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2323 /* Determin if RS bit needs to be set */
2324 if (txq->tx_tail > txq->tx_next_rs) {
2325 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2326 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2329 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2330 if (txq->tx_next_rs >= txq->nb_tx_desc)
2331 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2334 if (txq->tx_tail >= txq->nb_tx_desc)
2337 /* Update the tx tail register */
2339 ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2345 ice_xmit_pkts_simple(void *tx_queue,
2346 struct rte_mbuf **tx_pkts,
2351 if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2352 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2356 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2359 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2360 &tx_pkts[nb_tx], num);
2361 nb_tx = (uint16_t)(nb_tx + ret);
2362 nb_pkts = (uint16_t)(nb_pkts - ret);
2370 void __attribute__((cold))
2371 ice_set_rx_function(struct rte_eth_dev *dev)
2373 PMD_INIT_FUNC_TRACE();
2374 struct ice_adapter *ad =
2375 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2377 struct ice_rx_queue *rxq;
2379 bool use_avx2 = false;
2381 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2382 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
2383 ad->rx_vec_allowed = true;
2384 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2385 rxq = dev->data->rx_queues[i];
2386 if (rxq && ice_rxq_vec_setup(rxq)) {
2387 ad->rx_vec_allowed = false;
2392 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2393 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2397 ad->rx_vec_allowed = false;
2401 if (ad->rx_vec_allowed) {
2402 if (dev->data->scattered_rx) {
2404 "Using %sVector Scattered Rx (port %d).",
2405 use_avx2 ? "avx2 " : "",
2406 dev->data->port_id);
2407 dev->rx_pkt_burst = use_avx2 ?
2408 ice_recv_scattered_pkts_vec_avx2 :
2409 ice_recv_scattered_pkts_vec;
2411 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2412 use_avx2 ? "avx2 " : "",
2413 dev->data->port_id);
2414 dev->rx_pkt_burst = use_avx2 ?
2415 ice_recv_pkts_vec_avx2 :
2423 if (dev->data->scattered_rx) {
2424 /* Set the non-LRO scattered function */
2426 "Using a Scattered function on port %d.",
2427 dev->data->port_id);
2428 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2429 } else if (ad->rx_bulk_alloc_allowed) {
2431 "Rx Burst Bulk Alloc Preconditions are "
2432 "satisfied. Rx Burst Bulk Alloc function "
2433 "will be used on port %d.",
2434 dev->data->port_id);
2435 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2438 "Rx Burst Bulk Alloc Preconditions are not "
2439 "satisfied, Normal Rx will be used on port %d.",
2440 dev->data->port_id);
2441 dev->rx_pkt_burst = ice_recv_pkts;
2445 void __attribute__((cold))
2446 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
2448 struct ice_adapter *ad =
2449 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2451 /* Use a simple Tx queue if possible (only fast free is allowed) */
2452 ad->tx_simple_allowed =
2454 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
2455 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
2457 if (ad->tx_simple_allowed)
2458 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
2462 "Simple Tx can NOT be enabled on Tx queue %u.",
2466 /*********************************************************************
2470 **********************************************************************/
2471 /* The default values of TSO MSS */
2472 #define ICE_MIN_TSO_MSS 64
2473 #define ICE_MAX_TSO_MSS 9728
2474 #define ICE_MAX_TSO_FRAME_SIZE 262144
2476 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2483 for (i = 0; i < nb_pkts; i++) {
2485 ol_flags = m->ol_flags;
2487 if (ol_flags & PKT_TX_TCP_SEG &&
2488 (m->tso_segsz < ICE_MIN_TSO_MSS ||
2489 m->tso_segsz > ICE_MAX_TSO_MSS ||
2490 m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
2492 * MSS outside the range are considered malicious
2498 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2499 ret = rte_validate_tx_offload(m);
2505 ret = rte_net_intel_cksum_prepare(m);
2514 void __attribute__((cold))
2515 ice_set_tx_function(struct rte_eth_dev *dev)
2517 struct ice_adapter *ad =
2518 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2520 struct ice_tx_queue *txq;
2522 bool use_avx2 = false;
2524 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2525 if (!ice_tx_vec_dev_check(dev)) {
2526 ad->tx_vec_allowed = true;
2527 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2528 txq = dev->data->tx_queues[i];
2529 if (txq && ice_txq_vec_setup(txq)) {
2530 ad->tx_vec_allowed = false;
2535 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2536 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2540 ad->tx_vec_allowed = false;
2544 if (ad->tx_vec_allowed) {
2545 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2546 use_avx2 ? "avx2 " : "",
2547 dev->data->port_id);
2548 dev->tx_pkt_burst = use_avx2 ?
2549 ice_xmit_pkts_vec_avx2 :
2551 dev->tx_pkt_prepare = NULL;
2557 if (ad->tx_simple_allowed) {
2558 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2559 dev->tx_pkt_burst = ice_xmit_pkts_simple;
2560 dev->tx_pkt_prepare = NULL;
2562 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
2563 dev->tx_pkt_burst = ice_xmit_pkts;
2564 dev->tx_pkt_prepare = ice_prep_pkts;
2568 /* For each value it means, datasheet of hardware can tell more details
2570 * @note: fix ice_dev_supported_ptypes_get() if any change here.
2572 static inline uint32_t
2573 ice_get_default_pkt_type(uint16_t ptype)
2575 static const uint32_t type_table[ICE_MAX_PKT_TYPE]
2576 __rte_cache_aligned = {
2579 [1] = RTE_PTYPE_L2_ETHER,
2580 /* [2] - [5] reserved */
2581 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2582 /* [7] - [10] reserved */
2583 [11] = RTE_PTYPE_L2_ETHER_ARP,
2584 /* [12] - [21] reserved */
2586 /* Non tunneled IPv4 */
2587 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2589 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2590 RTE_PTYPE_L4_NONFRAG,
2591 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2594 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2596 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2598 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2602 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2603 RTE_PTYPE_TUNNEL_IP |
2604 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2605 RTE_PTYPE_INNER_L4_FRAG,
2606 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2607 RTE_PTYPE_TUNNEL_IP |
2608 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2609 RTE_PTYPE_INNER_L4_NONFRAG,
2610 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2611 RTE_PTYPE_TUNNEL_IP |
2612 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2613 RTE_PTYPE_INNER_L4_UDP,
2615 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2616 RTE_PTYPE_TUNNEL_IP |
2617 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2618 RTE_PTYPE_INNER_L4_TCP,
2619 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2620 RTE_PTYPE_TUNNEL_IP |
2621 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2622 RTE_PTYPE_INNER_L4_SCTP,
2623 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2624 RTE_PTYPE_TUNNEL_IP |
2625 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2626 RTE_PTYPE_INNER_L4_ICMP,
2629 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2630 RTE_PTYPE_TUNNEL_IP |
2631 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2632 RTE_PTYPE_INNER_L4_FRAG,
2633 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2634 RTE_PTYPE_TUNNEL_IP |
2635 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2636 RTE_PTYPE_INNER_L4_NONFRAG,
2637 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2638 RTE_PTYPE_TUNNEL_IP |
2639 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2640 RTE_PTYPE_INNER_L4_UDP,
2642 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2643 RTE_PTYPE_TUNNEL_IP |
2644 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2645 RTE_PTYPE_INNER_L4_TCP,
2646 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2647 RTE_PTYPE_TUNNEL_IP |
2648 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2649 RTE_PTYPE_INNER_L4_SCTP,
2650 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2651 RTE_PTYPE_TUNNEL_IP |
2652 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2653 RTE_PTYPE_INNER_L4_ICMP,
2655 /* IPv4 --> GRE/Teredo/VXLAN */
2656 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2657 RTE_PTYPE_TUNNEL_GRENAT,
2659 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2660 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2661 RTE_PTYPE_TUNNEL_GRENAT |
2662 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2663 RTE_PTYPE_INNER_L4_FRAG,
2664 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2665 RTE_PTYPE_TUNNEL_GRENAT |
2666 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2667 RTE_PTYPE_INNER_L4_NONFRAG,
2668 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2669 RTE_PTYPE_TUNNEL_GRENAT |
2670 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2671 RTE_PTYPE_INNER_L4_UDP,
2673 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2674 RTE_PTYPE_TUNNEL_GRENAT |
2675 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2676 RTE_PTYPE_INNER_L4_TCP,
2677 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2678 RTE_PTYPE_TUNNEL_GRENAT |
2679 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2680 RTE_PTYPE_INNER_L4_SCTP,
2681 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2682 RTE_PTYPE_TUNNEL_GRENAT |
2683 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2684 RTE_PTYPE_INNER_L4_ICMP,
2686 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2687 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2688 RTE_PTYPE_TUNNEL_GRENAT |
2689 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2690 RTE_PTYPE_INNER_L4_FRAG,
2691 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2692 RTE_PTYPE_TUNNEL_GRENAT |
2693 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2694 RTE_PTYPE_INNER_L4_NONFRAG,
2695 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2696 RTE_PTYPE_TUNNEL_GRENAT |
2697 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2698 RTE_PTYPE_INNER_L4_UDP,
2700 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2701 RTE_PTYPE_TUNNEL_GRENAT |
2702 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2703 RTE_PTYPE_INNER_L4_TCP,
2704 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2705 RTE_PTYPE_TUNNEL_GRENAT |
2706 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2707 RTE_PTYPE_INNER_L4_SCTP,
2708 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2709 RTE_PTYPE_TUNNEL_GRENAT |
2710 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2711 RTE_PTYPE_INNER_L4_ICMP,
2713 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2714 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2715 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2717 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2718 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2719 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2720 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2721 RTE_PTYPE_INNER_L4_FRAG,
2722 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2723 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2724 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2725 RTE_PTYPE_INNER_L4_NONFRAG,
2726 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2727 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2728 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2729 RTE_PTYPE_INNER_L4_UDP,
2731 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2732 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2733 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2734 RTE_PTYPE_INNER_L4_TCP,
2735 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2736 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2737 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2738 RTE_PTYPE_INNER_L4_SCTP,
2739 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2740 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2741 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2742 RTE_PTYPE_INNER_L4_ICMP,
2744 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2745 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2746 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2747 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2748 RTE_PTYPE_INNER_L4_FRAG,
2749 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2750 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2751 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2752 RTE_PTYPE_INNER_L4_NONFRAG,
2753 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2754 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2755 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2756 RTE_PTYPE_INNER_L4_UDP,
2758 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2759 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2760 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2761 RTE_PTYPE_INNER_L4_TCP,
2762 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2763 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2764 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2765 RTE_PTYPE_INNER_L4_SCTP,
2766 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2767 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2768 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2769 RTE_PTYPE_INNER_L4_ICMP,
2771 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2772 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2773 RTE_PTYPE_TUNNEL_GRENAT |
2774 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2776 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2777 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2778 RTE_PTYPE_TUNNEL_GRENAT |
2779 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2780 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2781 RTE_PTYPE_INNER_L4_FRAG,
2782 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2783 RTE_PTYPE_TUNNEL_GRENAT |
2784 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2785 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2786 RTE_PTYPE_INNER_L4_NONFRAG,
2787 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2788 RTE_PTYPE_TUNNEL_GRENAT |
2789 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2790 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2791 RTE_PTYPE_INNER_L4_UDP,
2793 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2794 RTE_PTYPE_TUNNEL_GRENAT |
2795 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2796 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2797 RTE_PTYPE_INNER_L4_TCP,
2798 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2799 RTE_PTYPE_TUNNEL_GRENAT |
2800 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2801 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2802 RTE_PTYPE_INNER_L4_SCTP,
2803 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2804 RTE_PTYPE_TUNNEL_GRENAT |
2805 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2806 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2807 RTE_PTYPE_INNER_L4_ICMP,
2809 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2810 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2811 RTE_PTYPE_TUNNEL_GRENAT |
2812 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2813 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2814 RTE_PTYPE_INNER_L4_FRAG,
2815 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2816 RTE_PTYPE_TUNNEL_GRENAT |
2817 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2818 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2819 RTE_PTYPE_INNER_L4_NONFRAG,
2820 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2821 RTE_PTYPE_TUNNEL_GRENAT |
2822 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2823 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2824 RTE_PTYPE_INNER_L4_UDP,
2826 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2827 RTE_PTYPE_TUNNEL_GRENAT |
2828 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2829 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2830 RTE_PTYPE_INNER_L4_TCP,
2831 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2832 RTE_PTYPE_TUNNEL_GRENAT |
2833 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2834 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2835 RTE_PTYPE_INNER_L4_SCTP,
2836 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2837 RTE_PTYPE_TUNNEL_GRENAT |
2838 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2839 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2840 RTE_PTYPE_INNER_L4_ICMP,
2842 /* Non tunneled IPv6 */
2843 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2845 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2846 RTE_PTYPE_L4_NONFRAG,
2847 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2850 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2852 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2854 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2858 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2859 RTE_PTYPE_TUNNEL_IP |
2860 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2861 RTE_PTYPE_INNER_L4_FRAG,
2862 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2863 RTE_PTYPE_TUNNEL_IP |
2864 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2865 RTE_PTYPE_INNER_L4_NONFRAG,
2866 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2867 RTE_PTYPE_TUNNEL_IP |
2868 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2869 RTE_PTYPE_INNER_L4_UDP,
2871 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2872 RTE_PTYPE_TUNNEL_IP |
2873 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2874 RTE_PTYPE_INNER_L4_TCP,
2875 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2876 RTE_PTYPE_TUNNEL_IP |
2877 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2878 RTE_PTYPE_INNER_L4_SCTP,
2879 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2880 RTE_PTYPE_TUNNEL_IP |
2881 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2882 RTE_PTYPE_INNER_L4_ICMP,
2885 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2886 RTE_PTYPE_TUNNEL_IP |
2887 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2888 RTE_PTYPE_INNER_L4_FRAG,
2889 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2890 RTE_PTYPE_TUNNEL_IP |
2891 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2892 RTE_PTYPE_INNER_L4_NONFRAG,
2893 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2894 RTE_PTYPE_TUNNEL_IP |
2895 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2896 RTE_PTYPE_INNER_L4_UDP,
2897 /* [105] reserved */
2898 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2899 RTE_PTYPE_TUNNEL_IP |
2900 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2901 RTE_PTYPE_INNER_L4_TCP,
2902 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2903 RTE_PTYPE_TUNNEL_IP |
2904 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2905 RTE_PTYPE_INNER_L4_SCTP,
2906 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2907 RTE_PTYPE_TUNNEL_IP |
2908 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2909 RTE_PTYPE_INNER_L4_ICMP,
2911 /* IPv6 --> GRE/Teredo/VXLAN */
2912 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2913 RTE_PTYPE_TUNNEL_GRENAT,
2915 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2916 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2917 RTE_PTYPE_TUNNEL_GRENAT |
2918 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2919 RTE_PTYPE_INNER_L4_FRAG,
2920 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2921 RTE_PTYPE_TUNNEL_GRENAT |
2922 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2923 RTE_PTYPE_INNER_L4_NONFRAG,
2924 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2925 RTE_PTYPE_TUNNEL_GRENAT |
2926 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2927 RTE_PTYPE_INNER_L4_UDP,
2928 /* [113] reserved */
2929 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2930 RTE_PTYPE_TUNNEL_GRENAT |
2931 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2932 RTE_PTYPE_INNER_L4_TCP,
2933 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2934 RTE_PTYPE_TUNNEL_GRENAT |
2935 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2936 RTE_PTYPE_INNER_L4_SCTP,
2937 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2938 RTE_PTYPE_TUNNEL_GRENAT |
2939 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2940 RTE_PTYPE_INNER_L4_ICMP,
2942 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2943 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2944 RTE_PTYPE_TUNNEL_GRENAT |
2945 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2946 RTE_PTYPE_INNER_L4_FRAG,
2947 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2948 RTE_PTYPE_TUNNEL_GRENAT |
2949 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2950 RTE_PTYPE_INNER_L4_NONFRAG,
2951 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2952 RTE_PTYPE_TUNNEL_GRENAT |
2953 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2954 RTE_PTYPE_INNER_L4_UDP,
2955 /* [120] reserved */
2956 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2957 RTE_PTYPE_TUNNEL_GRENAT |
2958 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2959 RTE_PTYPE_INNER_L4_TCP,
2960 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2961 RTE_PTYPE_TUNNEL_GRENAT |
2962 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2963 RTE_PTYPE_INNER_L4_SCTP,
2964 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2965 RTE_PTYPE_TUNNEL_GRENAT |
2966 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2967 RTE_PTYPE_INNER_L4_ICMP,
2969 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2970 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2971 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2973 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2974 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2975 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2976 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2977 RTE_PTYPE_INNER_L4_FRAG,
2978 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2979 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2980 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2981 RTE_PTYPE_INNER_L4_NONFRAG,
2982 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2983 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2984 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2985 RTE_PTYPE_INNER_L4_UDP,
2986 /* [128] reserved */
2987 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2988 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2989 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2990 RTE_PTYPE_INNER_L4_TCP,
2991 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2992 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2993 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2994 RTE_PTYPE_INNER_L4_SCTP,
2995 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2996 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2997 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2998 RTE_PTYPE_INNER_L4_ICMP,
3000 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3001 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3002 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3003 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3004 RTE_PTYPE_INNER_L4_FRAG,
3005 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3006 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3007 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3008 RTE_PTYPE_INNER_L4_NONFRAG,
3009 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3010 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3011 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3012 RTE_PTYPE_INNER_L4_UDP,
3013 /* [135] reserved */
3014 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3015 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3016 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3017 RTE_PTYPE_INNER_L4_TCP,
3018 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3019 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3020 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3021 RTE_PTYPE_INNER_L4_SCTP,
3022 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3023 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3024 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3025 RTE_PTYPE_INNER_L4_ICMP,
3027 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
3028 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3029 RTE_PTYPE_TUNNEL_GRENAT |
3030 RTE_PTYPE_INNER_L2_ETHER_VLAN,
3032 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
3033 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3034 RTE_PTYPE_TUNNEL_GRENAT |
3035 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3036 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3037 RTE_PTYPE_INNER_L4_FRAG,
3038 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3039 RTE_PTYPE_TUNNEL_GRENAT |
3040 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3041 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3042 RTE_PTYPE_INNER_L4_NONFRAG,
3043 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3044 RTE_PTYPE_TUNNEL_GRENAT |
3045 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3046 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3047 RTE_PTYPE_INNER_L4_UDP,
3048 /* [143] reserved */
3049 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3050 RTE_PTYPE_TUNNEL_GRENAT |
3051 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3052 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3053 RTE_PTYPE_INNER_L4_TCP,
3054 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3055 RTE_PTYPE_TUNNEL_GRENAT |
3056 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3057 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3058 RTE_PTYPE_INNER_L4_SCTP,
3059 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3060 RTE_PTYPE_TUNNEL_GRENAT |
3061 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3062 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3063 RTE_PTYPE_INNER_L4_ICMP,
3065 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
3066 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3067 RTE_PTYPE_TUNNEL_GRENAT |
3068 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3069 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3070 RTE_PTYPE_INNER_L4_FRAG,
3071 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3072 RTE_PTYPE_TUNNEL_GRENAT |
3073 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3074 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3075 RTE_PTYPE_INNER_L4_NONFRAG,
3076 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3077 RTE_PTYPE_TUNNEL_GRENAT |
3078 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3079 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3080 RTE_PTYPE_INNER_L4_UDP,
3081 /* [150] reserved */
3082 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3083 RTE_PTYPE_TUNNEL_GRENAT |
3084 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3085 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3086 RTE_PTYPE_INNER_L4_TCP,
3087 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3088 RTE_PTYPE_TUNNEL_GRENAT |
3089 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3090 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3091 RTE_PTYPE_INNER_L4_SCTP,
3092 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3093 RTE_PTYPE_TUNNEL_GRENAT |
3094 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3095 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3096 RTE_PTYPE_INNER_L4_ICMP,
3097 /* [154] - [255] reserved */
3098 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3099 RTE_PTYPE_TUNNEL_GTPC,
3100 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3101 RTE_PTYPE_TUNNEL_GTPC,
3102 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3103 RTE_PTYPE_TUNNEL_GTPU,
3104 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3105 RTE_PTYPE_TUNNEL_GTPU,
3106 /* [260] - [263] reserved */
3107 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3108 RTE_PTYPE_TUNNEL_GTPC,
3109 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3110 RTE_PTYPE_TUNNEL_GTPC,
3111 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3112 RTE_PTYPE_TUNNEL_GTPU,
3113 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3114 RTE_PTYPE_TUNNEL_GTPU,
3116 /* All others reserved */
3119 return type_table[ptype];
3122 void __attribute__((cold))
3123 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3125 struct ice_adapter *ad =
3126 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3129 for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3130 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);