1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <ethdev_driver.h>
9 #include "rte_pmd_ice.h"
11 #include "ice_rxtx_vec_common.h"
13 #define ICE_TX_CKSUM_OFFLOAD_MASK ( \
17 PKT_TX_OUTER_IP_CKSUM)
19 /* Offset of mbuf dynamic field for protocol extraction data */
20 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
22 /* Mask of mbuf dynamic flags for protocol extraction type */
23 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
26 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
27 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
28 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
31 ice_monitor_callback(const uint64_t value,
32 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
34 const uint64_t m = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
36 * we expect the DD bit to be set to 1 if this descriptor was already
39 return (value & m) == m ? -1 : 0;
43 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
45 volatile union ice_rx_flex_desc *rxdp;
46 struct ice_rx_queue *rxq = rx_queue;
50 rxdp = &rxq->rx_ring[desc];
51 /* watch for changes in status bit */
52 pmc->addr = &rxdp->wb.status_error0;
54 /* comparison callback */
55 pmc->fn = ice_monitor_callback;
57 /* register is 16-bit */
58 pmc->size = sizeof(uint16_t);
65 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
67 static uint8_t rxdid_map[] = {
68 [PROTO_XTR_NONE] = ICE_RXDID_COMMS_OVS,
69 [PROTO_XTR_VLAN] = ICE_RXDID_COMMS_AUX_VLAN,
70 [PROTO_XTR_IPV4] = ICE_RXDID_COMMS_AUX_IPV4,
71 [PROTO_XTR_IPV6] = ICE_RXDID_COMMS_AUX_IPV6,
72 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
73 [PROTO_XTR_TCP] = ICE_RXDID_COMMS_AUX_TCP,
74 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
77 return xtr_type < RTE_DIM(rxdid_map) ?
78 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
82 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
84 volatile union ice_rx_flex_desc *rxdp)
86 volatile struct ice_32b_rx_flex_desc_comms *desc =
87 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
88 uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
90 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
91 mb->ol_flags |= PKT_RX_RSS_HASH;
92 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
95 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
96 if (desc->flow_id != 0xFFFFFFFF) {
97 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
98 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
104 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
106 volatile union ice_rx_flex_desc *rxdp)
108 volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
109 (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
110 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
114 if (desc->flow_id != 0xFFFFFFFF) {
115 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
116 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
119 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
120 stat_err = rte_le_to_cpu_16(desc->status_error0);
121 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
122 mb->ol_flags |= PKT_RX_RSS_HASH;
123 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
129 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
131 volatile union ice_rx_flex_desc *rxdp)
133 volatile struct ice_32b_rx_flex_desc_comms *desc =
134 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
137 stat_err = rte_le_to_cpu_16(desc->status_error0);
138 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
139 mb->ol_flags |= PKT_RX_RSS_HASH;
140 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
143 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
144 if (desc->flow_id != 0xFFFFFFFF) {
145 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
146 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
149 if (rxq->xtr_ol_flag) {
150 uint32_t metadata = 0;
152 stat_err = rte_le_to_cpu_16(desc->status_error1);
154 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
155 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
157 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
159 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
162 mb->ol_flags |= rxq->xtr_ol_flag;
164 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
171 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
173 volatile union ice_rx_flex_desc *rxdp)
175 volatile struct ice_32b_rx_flex_desc_comms *desc =
176 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
179 stat_err = rte_le_to_cpu_16(desc->status_error0);
180 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
181 mb->ol_flags |= PKT_RX_RSS_HASH;
182 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
185 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
186 if (desc->flow_id != 0xFFFFFFFF) {
187 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
188 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
191 if (rxq->xtr_ol_flag) {
192 uint32_t metadata = 0;
194 if (desc->flex_ts.flex.aux0 != 0xFFFF)
195 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
196 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
197 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
200 mb->ol_flags |= rxq->xtr_ol_flag;
202 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
209 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
212 case ICE_RXDID_COMMS_AUX_VLAN:
213 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
214 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
217 case ICE_RXDID_COMMS_AUX_IPV4:
218 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
219 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
222 case ICE_RXDID_COMMS_AUX_IPV6:
223 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
224 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
227 case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
228 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
229 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
232 case ICE_RXDID_COMMS_AUX_TCP:
233 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
234 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
237 case ICE_RXDID_COMMS_AUX_IP_OFFSET:
238 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
239 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v2;
242 case ICE_RXDID_COMMS_GENERIC:
243 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_generic;
246 case ICE_RXDID_COMMS_OVS:
247 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
251 /* update this according to the RXDID for PROTO_XTR_NONE */
252 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
256 if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
257 rxq->xtr_ol_flag = 0;
260 static enum ice_status
261 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
263 struct ice_vsi *vsi = rxq->vsi;
264 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
265 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
266 struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
267 struct ice_rlan_ctx rx_ctx;
270 struct rte_eth_rxmode *rxmode = &dev_data->dev_conf.rxmode;
271 uint32_t rxdid = ICE_RXDID_COMMS_OVS;
274 /* Set buffer size as the head split is disabled. */
275 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
276 RTE_PKTMBUF_HEADROOM);
278 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
279 rxq->max_pkt_len = RTE_MIN((uint32_t)
280 ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
281 dev_data->dev_conf.rxmode.max_rx_pkt_len);
283 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
284 if (rxq->max_pkt_len <= ICE_ETH_MAX_LEN ||
285 rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
286 PMD_DRV_LOG(ERR, "maximum packet length must "
287 "be larger than %u and smaller than %u,"
288 "as jumbo frame is enabled",
289 (uint32_t)ICE_ETH_MAX_LEN,
290 (uint32_t)ICE_FRAME_SIZE_MAX);
294 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
295 rxq->max_pkt_len > ICE_ETH_MAX_LEN) {
296 PMD_DRV_LOG(ERR, "maximum packet length must be "
297 "larger than %u and smaller than %u, "
298 "as jumbo frame is disabled",
299 (uint32_t)RTE_ETHER_MIN_LEN,
300 (uint32_t)ICE_ETH_MAX_LEN);
305 memset(&rx_ctx, 0, sizeof(rx_ctx));
307 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
308 rx_ctx.qlen = rxq->nb_rx_desc;
309 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
310 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
311 rx_ctx.dtype = 0; /* No Header Split mode */
312 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
313 rx_ctx.dsize = 1; /* 32B descriptors */
315 rx_ctx.rxmax = rxq->max_pkt_len;
316 /* TPH: Transaction Layer Packet (TLP) processing hints */
317 rx_ctx.tphrdesc_ena = 1;
318 rx_ctx.tphwdesc_ena = 1;
319 rx_ctx.tphdata_ena = 1;
320 rx_ctx.tphhead_ena = 1;
321 /* Low Receive Queue Threshold defined in 64 descriptors units.
322 * When the number of free descriptors goes below the lrxqthresh,
323 * an immediate interrupt is triggered.
325 rx_ctx.lrxqthresh = 2;
326 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
329 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
331 rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
333 PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
334 rxq->port_id, rxq->queue_id, rxdid);
336 if (!(pf->supported_rxdid & BIT(rxdid))) {
337 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
342 ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
344 /* Enable Flexible Descriptors in the queue context which
345 * allows this driver to select a specific receive descriptor format
347 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
348 QRXFLXP_CNTXT_RXDID_IDX_M;
350 /* increasing context priority to pick up profile ID;
351 * default is 0x01; setting to 0x03 to ensure profile
352 * is programming if prev context is of same priority
354 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
355 QRXFLXP_CNTXT_RXDID_PRIO_M;
357 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
359 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
361 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
365 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
367 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
372 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
373 RTE_PKTMBUF_HEADROOM);
375 /* Check if scattered RX needs to be used. */
376 if (rxq->max_pkt_len > buf_size)
377 dev_data->scattered_rx = 1;
379 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
381 /* Init the Rx tail register*/
382 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
387 /* Allocate mbufs for all descriptors in rx queue */
389 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
391 struct ice_rx_entry *rxe = rxq->sw_ring;
395 for (i = 0; i < rxq->nb_rx_desc; i++) {
396 volatile union ice_rx_flex_desc *rxd;
397 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
399 if (unlikely(!mbuf)) {
400 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
404 rte_mbuf_refcnt_set(mbuf, 1);
406 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
408 mbuf->port = rxq->port_id;
411 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
413 rxd = &rxq->rx_ring[i];
414 rxd->read.pkt_addr = dma_addr;
415 rxd->read.hdr_addr = 0;
416 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
426 /* Free all mbufs for descriptors in rx queue */
428 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
432 if (!rxq || !rxq->sw_ring) {
433 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
437 for (i = 0; i < rxq->nb_rx_desc; i++) {
438 if (rxq->sw_ring[i].mbuf) {
439 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
440 rxq->sw_ring[i].mbuf = NULL;
443 if (rxq->rx_nb_avail == 0)
445 for (i = 0; i < rxq->rx_nb_avail; i++)
446 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
448 rxq->rx_nb_avail = 0;
451 /* turn on or off rx queue
452 * @q_idx: queue index in pf scope
453 * @on: turn on or off the queue
456 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
461 /* QRX_CTRL = QRX_ENA */
462 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
465 if (reg & QRX_CTRL_QENA_STAT_M)
466 return 0; /* Already on, skip */
467 reg |= QRX_CTRL_QENA_REQ_M;
469 if (!(reg & QRX_CTRL_QENA_STAT_M))
470 return 0; /* Already off, skip */
471 reg &= ~QRX_CTRL_QENA_REQ_M;
474 /* Write the register */
475 ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
476 /* Check the result. It is said that QENA_STAT
477 * follows the QENA_REQ not more than 10 use.
478 * TODO: need to change the wait counter later
480 for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
481 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
482 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
484 if ((reg & QRX_CTRL_QENA_REQ_M) &&
485 (reg & QRX_CTRL_QENA_STAT_M))
488 if (!(reg & QRX_CTRL_QENA_REQ_M) &&
489 !(reg & QRX_CTRL_QENA_STAT_M))
494 /* Check if it is timeout */
495 if (j >= ICE_CHK_Q_ENA_COUNT) {
496 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
497 (on ? "enable" : "disable"), q_idx);
505 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
509 if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
510 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
511 "rxq->rx_free_thresh=%d, "
512 "ICE_RX_MAX_BURST=%d",
513 rxq->rx_free_thresh, ICE_RX_MAX_BURST);
515 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
516 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
517 "rxq->rx_free_thresh=%d, "
518 "rxq->nb_rx_desc=%d",
519 rxq->rx_free_thresh, rxq->nb_rx_desc);
521 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
522 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
523 "rxq->nb_rx_desc=%d, "
524 "rxq->rx_free_thresh=%d",
525 rxq->nb_rx_desc, rxq->rx_free_thresh);
532 /* reset fields in ice_rx_queue back to default */
534 ice_reset_rx_queue(struct ice_rx_queue *rxq)
540 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
544 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
546 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
547 ((volatile char *)rxq->rx_ring)[i] = 0;
549 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
550 for (i = 0; i < ICE_RX_MAX_BURST; ++i)
551 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
553 rxq->rx_nb_avail = 0;
554 rxq->rx_next_avail = 0;
555 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
559 rxq->pkt_first_seg = NULL;
560 rxq->pkt_last_seg = NULL;
562 rxq->rxrearm_start = 0;
567 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
569 struct ice_rx_queue *rxq;
571 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
573 PMD_INIT_FUNC_TRACE();
575 if (rx_queue_id >= dev->data->nb_rx_queues) {
576 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
577 rx_queue_id, dev->data->nb_rx_queues);
581 rxq = dev->data->rx_queues[rx_queue_id];
582 if (!rxq || !rxq->q_set) {
583 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
588 err = ice_program_hw_rx_queue(rxq);
590 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
595 err = ice_alloc_rx_queue_mbufs(rxq);
597 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
601 /* Init the RX tail register. */
602 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
604 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
606 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
609 rxq->rx_rel_mbufs(rxq);
610 ice_reset_rx_queue(rxq);
614 dev->data->rx_queue_state[rx_queue_id] =
615 RTE_ETH_QUEUE_STATE_STARTED;
621 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
623 struct ice_rx_queue *rxq;
625 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
627 if (rx_queue_id < dev->data->nb_rx_queues) {
628 rxq = dev->data->rx_queues[rx_queue_id];
630 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
632 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
636 rxq->rx_rel_mbufs(rxq);
637 ice_reset_rx_queue(rxq);
638 dev->data->rx_queue_state[rx_queue_id] =
639 RTE_ETH_QUEUE_STATE_STOPPED;
646 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
648 struct ice_tx_queue *txq;
652 struct ice_aqc_add_tx_qgrp *txq_elem;
653 struct ice_tlan_ctx tx_ctx;
656 PMD_INIT_FUNC_TRACE();
658 if (tx_queue_id >= dev->data->nb_tx_queues) {
659 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
660 tx_queue_id, dev->data->nb_tx_queues);
664 txq = dev->data->tx_queues[tx_queue_id];
665 if (!txq || !txq->q_set) {
666 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
671 buf_len = ice_struct_size(txq_elem, txqs, 1);
672 txq_elem = ice_malloc(hw, buf_len);
677 hw = ICE_VSI_TO_HW(vsi);
679 memset(&tx_ctx, 0, sizeof(tx_ctx));
680 txq_elem->num_txqs = 1;
681 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
683 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
684 tx_ctx.qlen = txq->nb_tx_desc;
685 tx_ctx.pf_num = hw->pf_id;
686 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
687 tx_ctx.src_vsi = vsi->vsi_id;
688 tx_ctx.port_num = hw->port_info->lport;
689 tx_ctx.tso_ena = 1; /* tso enable */
690 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
691 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
693 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
696 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
698 /* Init the Tx tail register*/
699 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
701 /* Fix me, we assume TC always 0 here */
702 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
703 txq_elem, buf_len, NULL);
705 PMD_DRV_LOG(ERR, "Failed to add lan txq");
709 /* store the schedule node id */
710 txq->q_teid = txq_elem->txqs[0].q_teid;
712 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
718 static enum ice_status
719 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
721 struct ice_vsi *vsi = rxq->vsi;
722 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
723 uint32_t rxdid = ICE_RXDID_LEGACY_1;
724 struct ice_rlan_ctx rx_ctx;
729 rxq->rx_buf_len = 1024;
731 memset(&rx_ctx, 0, sizeof(rx_ctx));
733 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
734 rx_ctx.qlen = rxq->nb_rx_desc;
735 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
736 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
737 rx_ctx.dtype = 0; /* No Header Split mode */
738 rx_ctx.dsize = 1; /* 32B descriptors */
739 rx_ctx.rxmax = ICE_ETH_MAX_LEN;
740 /* TPH: Transaction Layer Packet (TLP) processing hints */
741 rx_ctx.tphrdesc_ena = 1;
742 rx_ctx.tphwdesc_ena = 1;
743 rx_ctx.tphdata_ena = 1;
744 rx_ctx.tphhead_ena = 1;
745 /* Low Receive Queue Threshold defined in 64 descriptors units.
746 * When the number of free descriptors goes below the lrxqthresh,
747 * an immediate interrupt is triggered.
749 rx_ctx.lrxqthresh = 2;
750 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
753 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
755 /* Enable Flexible Descriptors in the queue context which
756 * allows this driver to select a specific receive descriptor format
758 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
759 QRXFLXP_CNTXT_RXDID_IDX_M;
761 /* increasing context priority to pick up profile ID;
762 * default is 0x01; setting to 0x03 to ensure profile
763 * is programming if prev context is of same priority
765 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
766 QRXFLXP_CNTXT_RXDID_PRIO_M;
768 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
770 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
772 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
776 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
778 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
783 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
785 /* Init the Rx tail register*/
786 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
792 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
794 struct ice_rx_queue *rxq;
796 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
797 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
799 PMD_INIT_FUNC_TRACE();
802 if (!rxq || !rxq->q_set) {
803 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
808 err = ice_fdir_program_hw_rx_queue(rxq);
810 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
815 /* Init the RX tail register. */
816 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
818 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
820 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
823 ice_reset_rx_queue(rxq);
831 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
833 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
834 struct ice_tx_queue *txq;
838 struct ice_aqc_add_tx_qgrp *txq_elem;
839 struct ice_tlan_ctx tx_ctx;
842 PMD_INIT_FUNC_TRACE();
845 if (!txq || !txq->q_set) {
846 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
851 buf_len = ice_struct_size(txq_elem, txqs, 1);
852 txq_elem = ice_malloc(hw, buf_len);
857 hw = ICE_VSI_TO_HW(vsi);
859 memset(&tx_ctx, 0, sizeof(tx_ctx));
860 txq_elem->num_txqs = 1;
861 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
863 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
864 tx_ctx.qlen = txq->nb_tx_desc;
865 tx_ctx.pf_num = hw->pf_id;
866 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
867 tx_ctx.src_vsi = vsi->vsi_id;
868 tx_ctx.port_num = hw->port_info->lport;
869 tx_ctx.tso_ena = 1; /* tso enable */
870 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
871 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
873 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
876 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
878 /* Init the Tx tail register*/
879 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
881 /* Fix me, we assume TC always 0 here */
882 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
883 txq_elem, buf_len, NULL);
885 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
889 /* store the schedule node id */
890 txq->q_teid = txq_elem->txqs[0].q_teid;
896 /* Free all mbufs for descriptors in tx queue */
898 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
902 if (!txq || !txq->sw_ring) {
903 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
907 for (i = 0; i < txq->nb_tx_desc; i++) {
908 if (txq->sw_ring[i].mbuf) {
909 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
910 txq->sw_ring[i].mbuf = NULL;
916 ice_reset_tx_queue(struct ice_tx_queue *txq)
918 struct ice_tx_entry *txe;
919 uint16_t i, prev, size;
922 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
927 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
928 for (i = 0; i < size; i++)
929 ((volatile char *)txq->tx_ring)[i] = 0;
931 prev = (uint16_t)(txq->nb_tx_desc - 1);
932 for (i = 0; i < txq->nb_tx_desc; i++) {
933 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
935 txd->cmd_type_offset_bsz =
936 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
939 txe[prev].next_id = i;
943 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
944 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
949 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
950 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
954 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
956 struct ice_tx_queue *txq;
957 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
958 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
959 struct ice_vsi *vsi = pf->main_vsi;
960 enum ice_status status;
963 uint16_t q_handle = tx_queue_id;
965 if (tx_queue_id >= dev->data->nb_tx_queues) {
966 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
967 tx_queue_id, dev->data->nb_tx_queues);
971 txq = dev->data->tx_queues[tx_queue_id];
973 PMD_DRV_LOG(ERR, "TX queue %u is not available",
978 q_ids[0] = txq->reg_idx;
979 q_teids[0] = txq->q_teid;
981 /* Fix me, we assume TC always 0 here */
982 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
983 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
984 if (status != ICE_SUCCESS) {
985 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
989 txq->tx_rel_mbufs(txq);
990 ice_reset_tx_queue(txq);
991 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
997 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
999 struct ice_rx_queue *rxq;
1001 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1002 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1006 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1008 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1012 rxq->rx_rel_mbufs(rxq);
1018 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1020 struct ice_tx_queue *txq;
1021 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1022 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023 struct ice_vsi *vsi = pf->main_vsi;
1024 enum ice_status status;
1026 uint32_t q_teids[1];
1027 uint16_t q_handle = tx_queue_id;
1031 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1037 q_ids[0] = txq->reg_idx;
1038 q_teids[0] = txq->q_teid;
1040 /* Fix me, we assume TC always 0 here */
1041 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1042 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1043 if (status != ICE_SUCCESS) {
1044 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1048 txq->tx_rel_mbufs(txq);
1054 ice_rx_queue_setup(struct rte_eth_dev *dev,
1057 unsigned int socket_id,
1058 const struct rte_eth_rxconf *rx_conf,
1059 struct rte_mempool *mp)
1061 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1062 struct ice_adapter *ad =
1063 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1064 struct ice_vsi *vsi = pf->main_vsi;
1065 struct ice_rx_queue *rxq;
1066 const struct rte_memzone *rz;
1069 int use_def_burst_func = 1;
1072 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1073 nb_desc > ICE_MAX_RING_DESC ||
1074 nb_desc < ICE_MIN_RING_DESC) {
1075 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1076 "invalid", nb_desc);
1080 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1082 /* Free memory if needed */
1083 if (dev->data->rx_queues[queue_idx]) {
1084 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1085 dev->data->rx_queues[queue_idx] = NULL;
1088 /* Allocate the rx queue data structure */
1089 rxq = rte_zmalloc_socket(NULL,
1090 sizeof(struct ice_rx_queue),
1091 RTE_CACHE_LINE_SIZE,
1094 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1095 "rx queue data structure");
1099 rxq->nb_rx_desc = nb_desc;
1100 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1101 rxq->queue_id = queue_idx;
1102 rxq->offloads = offloads;
1104 rxq->reg_idx = vsi->base_queue + queue_idx;
1105 rxq->port_id = dev->data->port_id;
1106 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1107 rxq->crc_len = RTE_ETHER_CRC_LEN;
1111 rxq->drop_en = rx_conf->rx_drop_en;
1113 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1114 rxq->proto_xtr = pf->proto_xtr != NULL ?
1115 pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1117 /* Allocate the maximun number of RX ring hardware descriptor. */
1118 len = ICE_MAX_RING_DESC;
1121 * Allocating a little more memory because vectorized/bulk_alloc Rx
1122 * functions doesn't check boundaries each time.
1124 len += ICE_RX_MAX_BURST;
1126 /* Allocate the maximum number of RX ring hardware descriptor. */
1127 ring_size = sizeof(union ice_rx_flex_desc) * len;
1128 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1129 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1130 ring_size, ICE_RING_BASE_ALIGN,
1133 ice_rx_queue_release(rxq);
1134 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1138 /* Zero all the descriptors in the ring. */
1139 memset(rz->addr, 0, ring_size);
1141 rxq->rx_ring_dma = rz->iova;
1142 rxq->rx_ring = rz->addr;
1144 /* always reserve more for bulk alloc */
1145 len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1147 /* Allocate the software ring. */
1148 rxq->sw_ring = rte_zmalloc_socket(NULL,
1149 sizeof(struct ice_rx_entry) * len,
1150 RTE_CACHE_LINE_SIZE,
1152 if (!rxq->sw_ring) {
1153 ice_rx_queue_release(rxq);
1154 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1158 ice_reset_rx_queue(rxq);
1160 dev->data->rx_queues[queue_idx] = rxq;
1161 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1163 use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1165 if (!use_def_burst_func) {
1166 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1167 "satisfied. Rx Burst Bulk Alloc function will be "
1168 "used on port=%d, queue=%d.",
1169 rxq->port_id, rxq->queue_id);
1171 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1172 "not satisfied, Scattered Rx is requested. "
1173 "on port=%d, queue=%d.",
1174 rxq->port_id, rxq->queue_id);
1175 ad->rx_bulk_alloc_allowed = false;
1182 ice_rx_queue_release(void *rxq)
1184 struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1187 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1192 rte_free(q->sw_ring);
1197 ice_tx_queue_setup(struct rte_eth_dev *dev,
1200 unsigned int socket_id,
1201 const struct rte_eth_txconf *tx_conf)
1203 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1204 struct ice_vsi *vsi = pf->main_vsi;
1205 struct ice_tx_queue *txq;
1206 const struct rte_memzone *tz;
1208 uint16_t tx_rs_thresh, tx_free_thresh;
1211 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1213 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1214 nb_desc > ICE_MAX_RING_DESC ||
1215 nb_desc < ICE_MIN_RING_DESC) {
1216 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1217 "invalid", nb_desc);
1222 * The following two parameters control the setting of the RS bit on
1223 * transmit descriptors. TX descriptors will have their RS bit set
1224 * after txq->tx_rs_thresh descriptors have been used. The TX
1225 * descriptor ring will be cleaned after txq->tx_free_thresh
1226 * descriptors are used or if the number of descriptors required to
1227 * transmit a packet is greater than the number of free TX descriptors.
1229 * The following constraints must be satisfied:
1230 * - tx_rs_thresh must be greater than 0.
1231 * - tx_rs_thresh must be less than the size of the ring minus 2.
1232 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1233 * - tx_rs_thresh must be a divisor of the ring size.
1234 * - tx_free_thresh must be greater than 0.
1235 * - tx_free_thresh must be less than the size of the ring minus 3.
1236 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1238 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1239 * race condition, hence the maximum threshold constraints. When set
1240 * to zero use default values.
1242 tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1243 tx_conf->tx_free_thresh :
1244 ICE_DEFAULT_TX_FREE_THRESH);
1245 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1247 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1248 nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1249 if (tx_conf->tx_rs_thresh)
1250 tx_rs_thresh = tx_conf->tx_rs_thresh;
1251 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1252 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1253 "exceed nb_desc. (tx_rs_thresh=%u "
1254 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1255 (unsigned int)tx_rs_thresh,
1256 (unsigned int)tx_free_thresh,
1257 (unsigned int)nb_desc,
1258 (int)dev->data->port_id,
1262 if (tx_rs_thresh >= (nb_desc - 2)) {
1263 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1264 "number of TX descriptors minus 2. "
1265 "(tx_rs_thresh=%u port=%d queue=%d)",
1266 (unsigned int)tx_rs_thresh,
1267 (int)dev->data->port_id,
1271 if (tx_free_thresh >= (nb_desc - 3)) {
1272 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1273 "tx_free_thresh must be less than the "
1274 "number of TX descriptors minus 3. "
1275 "(tx_free_thresh=%u port=%d queue=%d)",
1276 (unsigned int)tx_free_thresh,
1277 (int)dev->data->port_id,
1281 if (tx_rs_thresh > tx_free_thresh) {
1282 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1283 "equal to tx_free_thresh. (tx_free_thresh=%u"
1284 " tx_rs_thresh=%u port=%d queue=%d)",
1285 (unsigned int)tx_free_thresh,
1286 (unsigned int)tx_rs_thresh,
1287 (int)dev->data->port_id,
1291 if ((nb_desc % tx_rs_thresh) != 0) {
1292 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1293 "number of TX descriptors. (tx_rs_thresh=%u"
1294 " port=%d queue=%d)",
1295 (unsigned int)tx_rs_thresh,
1296 (int)dev->data->port_id,
1300 if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1301 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1302 "tx_rs_thresh is greater than 1. "
1303 "(tx_rs_thresh=%u port=%d queue=%d)",
1304 (unsigned int)tx_rs_thresh,
1305 (int)dev->data->port_id,
1310 /* Free memory if needed. */
1311 if (dev->data->tx_queues[queue_idx]) {
1312 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1313 dev->data->tx_queues[queue_idx] = NULL;
1316 /* Allocate the TX queue data structure. */
1317 txq = rte_zmalloc_socket(NULL,
1318 sizeof(struct ice_tx_queue),
1319 RTE_CACHE_LINE_SIZE,
1322 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1323 "tx queue structure");
1327 /* Allocate TX hardware ring descriptors. */
1328 ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1329 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1330 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1331 ring_size, ICE_RING_BASE_ALIGN,
1334 ice_tx_queue_release(txq);
1335 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1339 txq->nb_tx_desc = nb_desc;
1340 txq->tx_rs_thresh = tx_rs_thresh;
1341 txq->tx_free_thresh = tx_free_thresh;
1342 txq->pthresh = tx_conf->tx_thresh.pthresh;
1343 txq->hthresh = tx_conf->tx_thresh.hthresh;
1344 txq->wthresh = tx_conf->tx_thresh.wthresh;
1345 txq->queue_id = queue_idx;
1347 txq->reg_idx = vsi->base_queue + queue_idx;
1348 txq->port_id = dev->data->port_id;
1349 txq->offloads = offloads;
1351 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1353 txq->tx_ring_dma = tz->iova;
1354 txq->tx_ring = tz->addr;
1356 /* Allocate software ring */
1358 rte_zmalloc_socket(NULL,
1359 sizeof(struct ice_tx_entry) * nb_desc,
1360 RTE_CACHE_LINE_SIZE,
1362 if (!txq->sw_ring) {
1363 ice_tx_queue_release(txq);
1364 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1368 ice_reset_tx_queue(txq);
1370 dev->data->tx_queues[queue_idx] = txq;
1371 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1372 ice_set_tx_function_flag(dev, txq);
1378 ice_tx_queue_release(void *txq)
1380 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1383 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1388 rte_free(q->sw_ring);
1393 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1394 struct rte_eth_rxq_info *qinfo)
1396 struct ice_rx_queue *rxq;
1398 rxq = dev->data->rx_queues[queue_id];
1400 qinfo->mp = rxq->mp;
1401 qinfo->scattered_rx = dev->data->scattered_rx;
1402 qinfo->nb_desc = rxq->nb_rx_desc;
1404 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1405 qinfo->conf.rx_drop_en = rxq->drop_en;
1406 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1410 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1411 struct rte_eth_txq_info *qinfo)
1413 struct ice_tx_queue *txq;
1415 txq = dev->data->tx_queues[queue_id];
1417 qinfo->nb_desc = txq->nb_tx_desc;
1419 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1420 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1421 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1423 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1424 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1425 qinfo->conf.offloads = txq->offloads;
1426 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1430 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1432 #define ICE_RXQ_SCAN_INTERVAL 4
1433 volatile union ice_rx_flex_desc *rxdp;
1434 struct ice_rx_queue *rxq;
1437 rxq = dev->data->rx_queues[rx_queue_id];
1438 rxdp = &rxq->rx_ring[rxq->rx_tail];
1439 while ((desc < rxq->nb_rx_desc) &&
1440 rte_le_to_cpu_16(rxdp->wb.status_error0) &
1441 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1443 * Check the DD bit of a rx descriptor of each 4 in a group,
1444 * to avoid checking too frequently and downgrading performance
1447 desc += ICE_RXQ_SCAN_INTERVAL;
1448 rxdp += ICE_RXQ_SCAN_INTERVAL;
1449 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1450 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1451 desc - rxq->nb_rx_desc]);
1457 #define ICE_RX_FLEX_ERR0_BITS \
1458 ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) | \
1459 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1460 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1461 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1462 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1463 (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1465 /* Rx L3/L4 checksum */
1466 static inline uint64_t
1467 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1471 /* check if HW has decoded the packet and checksum */
1472 if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1475 if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1476 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1480 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1481 flags |= PKT_RX_IP_CKSUM_BAD;
1483 flags |= PKT_RX_IP_CKSUM_GOOD;
1485 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1486 flags |= PKT_RX_L4_CKSUM_BAD;
1488 flags |= PKT_RX_L4_CKSUM_GOOD;
1490 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1491 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1493 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1494 flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
1496 flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
1502 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1504 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1505 (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1506 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1508 rte_le_to_cpu_16(rxdp->wb.l2tag1);
1509 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1510 rte_le_to_cpu_16(rxdp->wb.l2tag1));
1515 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1516 if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1517 (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1518 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1519 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1520 mb->vlan_tci_outer = mb->vlan_tci;
1521 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1522 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1523 rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1524 rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1526 mb->vlan_tci_outer = 0;
1529 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1530 mb->vlan_tci, mb->vlan_tci_outer);
1533 #define ICE_LOOK_AHEAD 8
1534 #if (ICE_LOOK_AHEAD != 8)
1535 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1538 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1540 volatile union ice_rx_flex_desc *rxdp;
1541 struct ice_rx_entry *rxep;
1542 struct rte_mbuf *mb;
1545 int32_t s[ICE_LOOK_AHEAD], nb_dd;
1546 int32_t i, j, nb_rx = 0;
1547 uint64_t pkt_flags = 0;
1548 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1550 rxdp = &rxq->rx_ring[rxq->rx_tail];
1551 rxep = &rxq->sw_ring[rxq->rx_tail];
1553 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1555 /* Make sure there is at least 1 packet to receive */
1556 if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1560 * Scan LOOK_AHEAD descriptors at a time to determine which
1561 * descriptors reference packets that are ready to be received.
1563 for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1564 rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1565 /* Read desc statuses backwards to avoid race condition */
1566 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1567 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1571 /* Compute how many status bits were set */
1572 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1573 nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1577 /* Translate descriptor info to mbuf parameters */
1578 for (j = 0; j < nb_dd; j++) {
1580 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1581 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1582 mb->data_len = pkt_len;
1583 mb->pkt_len = pkt_len;
1585 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1586 pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1587 mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1588 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1589 ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1590 rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1592 mb->ol_flags |= pkt_flags;
1595 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1596 rxq->rx_stage[i + j] = rxep[j].mbuf;
1598 if (nb_dd != ICE_LOOK_AHEAD)
1602 /* Clear software ring entries */
1603 for (i = 0; i < nb_rx; i++)
1604 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1606 PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1607 "port_id=%u, queue_id=%u, nb_rx=%d",
1608 rxq->port_id, rxq->queue_id, nb_rx);
1613 static inline uint16_t
1614 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1615 struct rte_mbuf **rx_pkts,
1619 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1621 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1623 for (i = 0; i < nb_pkts; i++)
1624 rx_pkts[i] = stage[i];
1626 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1627 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1633 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1635 volatile union ice_rx_flex_desc *rxdp;
1636 struct ice_rx_entry *rxep;
1637 struct rte_mbuf *mb;
1638 uint16_t alloc_idx, i;
1642 /* Allocate buffers in bulk */
1643 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1644 (rxq->rx_free_thresh - 1));
1645 rxep = &rxq->sw_ring[alloc_idx];
1646 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1647 rxq->rx_free_thresh);
1648 if (unlikely(diag != 0)) {
1649 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1653 rxdp = &rxq->rx_ring[alloc_idx];
1654 for (i = 0; i < rxq->rx_free_thresh; i++) {
1655 if (likely(i < (rxq->rx_free_thresh - 1)))
1656 /* Prefetch next mbuf */
1657 rte_prefetch0(rxep[i + 1].mbuf);
1660 rte_mbuf_refcnt_set(mb, 1);
1662 mb->data_off = RTE_PKTMBUF_HEADROOM;
1664 mb->port = rxq->port_id;
1665 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1666 rxdp[i].read.hdr_addr = 0;
1667 rxdp[i].read.pkt_addr = dma_addr;
1670 /* Update rx tail regsiter */
1671 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1673 rxq->rx_free_trigger =
1674 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1675 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1676 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1681 static inline uint16_t
1682 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1684 struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1690 if (rxq->rx_nb_avail)
1691 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1693 nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1694 rxq->rx_next_avail = 0;
1695 rxq->rx_nb_avail = nb_rx;
1696 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1698 if (rxq->rx_tail > rxq->rx_free_trigger) {
1699 if (ice_rx_alloc_bufs(rxq) != 0) {
1702 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1703 rxq->rx_free_thresh;
1704 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1705 "port_id=%u, queue_id=%u",
1706 rxq->port_id, rxq->queue_id);
1707 rxq->rx_nb_avail = 0;
1708 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1709 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1710 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1716 if (rxq->rx_tail >= rxq->nb_rx_desc)
1719 if (rxq->rx_nb_avail)
1720 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1726 ice_recv_pkts_bulk_alloc(void *rx_queue,
1727 struct rte_mbuf **rx_pkts,
1734 if (unlikely(nb_pkts == 0))
1737 if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1738 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1741 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1742 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1743 nb_rx = (uint16_t)(nb_rx + count);
1744 nb_pkts = (uint16_t)(nb_pkts - count);
1753 ice_recv_scattered_pkts(void *rx_queue,
1754 struct rte_mbuf **rx_pkts,
1757 struct ice_rx_queue *rxq = rx_queue;
1758 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1759 volatile union ice_rx_flex_desc *rxdp;
1760 union ice_rx_flex_desc rxd;
1761 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1762 struct ice_rx_entry *rxe;
1763 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1764 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1765 struct rte_mbuf *nmb; /* new allocated mbuf */
1766 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1767 uint16_t rx_id = rxq->rx_tail;
1769 uint16_t nb_hold = 0;
1770 uint16_t rx_packet_len;
1771 uint16_t rx_stat_err0;
1774 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1776 while (nb_rx < nb_pkts) {
1777 rxdp = &rx_ring[rx_id];
1778 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1780 /* Check the DD bit first */
1781 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1785 nmb = rte_mbuf_raw_alloc(rxq->mp);
1786 if (unlikely(!nmb)) {
1787 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1790 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1793 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1795 if (unlikely(rx_id == rxq->nb_rx_desc))
1798 /* Prefetch next mbuf */
1799 rte_prefetch0(sw_ring[rx_id].mbuf);
1802 * When next RX descriptor is on a cache line boundary,
1803 * prefetch the next 4 RX descriptors and next 8 pointers
1806 if ((rx_id & 0x3) == 0) {
1807 rte_prefetch0(&rx_ring[rx_id]);
1808 rte_prefetch0(&sw_ring[rx_id]);
1814 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1816 /* Set data buffer address and data length of the mbuf */
1817 rxdp->read.hdr_addr = 0;
1818 rxdp->read.pkt_addr = dma_addr;
1819 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1820 ICE_RX_FLX_DESC_PKT_LEN_M;
1821 rxm->data_len = rx_packet_len;
1822 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1825 * If this is the first buffer of the received packet, set the
1826 * pointer to the first mbuf of the packet and initialize its
1827 * context. Otherwise, update the total length and the number
1828 * of segments of the current scattered packet, and update the
1829 * pointer to the last mbuf of the current packet.
1833 first_seg->nb_segs = 1;
1834 first_seg->pkt_len = rx_packet_len;
1836 first_seg->pkt_len =
1837 (uint16_t)(first_seg->pkt_len +
1839 first_seg->nb_segs++;
1840 last_seg->next = rxm;
1844 * If this is not the last buffer of the received packet,
1845 * update the pointer to the last mbuf of the current scattered
1846 * packet and continue to parse the RX ring.
1848 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1854 * This is the last buffer of the received packet. If the CRC
1855 * is not stripped by the hardware:
1856 * - Subtract the CRC length from the total packet length.
1857 * - If the last buffer only contains the whole CRC or a part
1858 * of it, free the mbuf associated to the last buffer. If part
1859 * of the CRC is also contained in the previous mbuf, subtract
1860 * the length of that CRC part from the data length of the
1864 if (unlikely(rxq->crc_len > 0)) {
1865 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1866 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1867 rte_pktmbuf_free_seg(rxm);
1868 first_seg->nb_segs--;
1869 last_seg->data_len =
1870 (uint16_t)(last_seg->data_len -
1871 (RTE_ETHER_CRC_LEN - rx_packet_len));
1872 last_seg->next = NULL;
1874 rxm->data_len = (uint16_t)(rx_packet_len -
1878 first_seg->port = rxq->port_id;
1879 first_seg->ol_flags = 0;
1880 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1881 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1882 ice_rxd_to_vlan_tci(first_seg, &rxd);
1883 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1884 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1885 first_seg->ol_flags |= pkt_flags;
1886 /* Prefetch data of first segment, if configured to do so. */
1887 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1888 first_seg->data_off));
1889 rx_pkts[nb_rx++] = first_seg;
1893 /* Record index of the next RX descriptor to probe. */
1894 rxq->rx_tail = rx_id;
1895 rxq->pkt_first_seg = first_seg;
1896 rxq->pkt_last_seg = last_seg;
1899 * If the number of free RX descriptors is greater than the RX free
1900 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1901 * register. Update the RDT with the value of the last processed RX
1902 * descriptor minus 1, to guarantee that the RDT register is never
1903 * equal to the RDH register, which creates a "full" ring situtation
1904 * from the hardware point of view.
1906 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1907 if (nb_hold > rxq->rx_free_thresh) {
1908 rx_id = (uint16_t)(rx_id == 0 ?
1909 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1910 /* write TAIL register */
1911 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1914 rxq->nb_rx_hold = nb_hold;
1916 /* return received packet in the burst */
1921 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1923 struct ice_adapter *ad =
1924 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1925 const uint32_t *ptypes;
1927 static const uint32_t ptypes_os[] = {
1928 /* refers to ice_get_default_pkt_type() */
1930 RTE_PTYPE_L2_ETHER_TIMESYNC,
1931 RTE_PTYPE_L2_ETHER_LLDP,
1932 RTE_PTYPE_L2_ETHER_ARP,
1933 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1934 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1937 RTE_PTYPE_L4_NONFRAG,
1941 RTE_PTYPE_TUNNEL_GRENAT,
1942 RTE_PTYPE_TUNNEL_IP,
1943 RTE_PTYPE_INNER_L2_ETHER,
1944 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1945 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1946 RTE_PTYPE_INNER_L4_FRAG,
1947 RTE_PTYPE_INNER_L4_ICMP,
1948 RTE_PTYPE_INNER_L4_NONFRAG,
1949 RTE_PTYPE_INNER_L4_SCTP,
1950 RTE_PTYPE_INNER_L4_TCP,
1951 RTE_PTYPE_INNER_L4_UDP,
1955 static const uint32_t ptypes_comms[] = {
1956 /* refers to ice_get_default_pkt_type() */
1958 RTE_PTYPE_L2_ETHER_TIMESYNC,
1959 RTE_PTYPE_L2_ETHER_LLDP,
1960 RTE_PTYPE_L2_ETHER_ARP,
1961 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1962 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1965 RTE_PTYPE_L4_NONFRAG,
1969 RTE_PTYPE_TUNNEL_GRENAT,
1970 RTE_PTYPE_TUNNEL_IP,
1971 RTE_PTYPE_INNER_L2_ETHER,
1972 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1973 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1974 RTE_PTYPE_INNER_L4_FRAG,
1975 RTE_PTYPE_INNER_L4_ICMP,
1976 RTE_PTYPE_INNER_L4_NONFRAG,
1977 RTE_PTYPE_INNER_L4_SCTP,
1978 RTE_PTYPE_INNER_L4_TCP,
1979 RTE_PTYPE_INNER_L4_UDP,
1980 RTE_PTYPE_TUNNEL_GTPC,
1981 RTE_PTYPE_TUNNEL_GTPU,
1982 RTE_PTYPE_L2_ETHER_PPPOE,
1986 if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
1987 ptypes = ptypes_comms;
1991 if (dev->rx_pkt_burst == ice_recv_pkts ||
1992 dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1993 dev->rx_pkt_burst == ice_recv_scattered_pkts)
1997 if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1998 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1999 #ifdef CC_AVX512_SUPPORT
2000 dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
2001 dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
2002 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
2003 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
2005 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
2006 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
2007 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2008 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2016 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2018 volatile union ice_rx_flex_desc *rxdp;
2019 struct ice_rx_queue *rxq = rx_queue;
2022 if (unlikely(offset >= rxq->nb_rx_desc))
2025 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2026 return RTE_ETH_RX_DESC_UNAVAIL;
2028 desc = rxq->rx_tail + offset;
2029 if (desc >= rxq->nb_rx_desc)
2030 desc -= rxq->nb_rx_desc;
2032 rxdp = &rxq->rx_ring[desc];
2033 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2034 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2035 return RTE_ETH_RX_DESC_DONE;
2037 return RTE_ETH_RX_DESC_AVAIL;
2041 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2043 struct ice_tx_queue *txq = tx_queue;
2044 volatile uint64_t *status;
2045 uint64_t mask, expect;
2048 if (unlikely(offset >= txq->nb_tx_desc))
2051 desc = txq->tx_tail + offset;
2052 /* go to next desc that has the RS bit */
2053 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2055 if (desc >= txq->nb_tx_desc) {
2056 desc -= txq->nb_tx_desc;
2057 if (desc >= txq->nb_tx_desc)
2058 desc -= txq->nb_tx_desc;
2061 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2062 mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2063 expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2064 ICE_TXD_QW1_DTYPE_S);
2065 if ((*status & mask) == expect)
2066 return RTE_ETH_TX_DESC_DONE;
2068 return RTE_ETH_TX_DESC_FULL;
2072 ice_free_queues(struct rte_eth_dev *dev)
2076 PMD_INIT_FUNC_TRACE();
2078 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2079 if (!dev->data->rx_queues[i])
2081 ice_rx_queue_release(dev->data->rx_queues[i]);
2082 dev->data->rx_queues[i] = NULL;
2083 rte_eth_dma_zone_free(dev, "rx_ring", i);
2085 dev->data->nb_rx_queues = 0;
2087 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2088 if (!dev->data->tx_queues[i])
2090 ice_tx_queue_release(dev->data->tx_queues[i]);
2091 dev->data->tx_queues[i] = NULL;
2092 rte_eth_dma_zone_free(dev, "tx_ring", i);
2094 dev->data->nb_tx_queues = 0;
2097 #define ICE_FDIR_NUM_TX_DESC ICE_MIN_RING_DESC
2098 #define ICE_FDIR_NUM_RX_DESC ICE_MIN_RING_DESC
2101 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2103 struct ice_tx_queue *txq;
2104 const struct rte_memzone *tz = NULL;
2106 struct rte_eth_dev *dev;
2109 PMD_DRV_LOG(ERR, "PF is not available");
2113 dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2115 /* Allocate the TX queue data structure. */
2116 txq = rte_zmalloc_socket("ice fdir tx queue",
2117 sizeof(struct ice_tx_queue),
2118 RTE_CACHE_LINE_SIZE,
2121 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2122 "tx queue structure.");
2126 /* Allocate TX hardware ring descriptors. */
2127 ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2128 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2130 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2131 ICE_FDIR_QUEUE_ID, ring_size,
2132 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2134 ice_tx_queue_release(txq);
2135 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2139 txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2140 txq->queue_id = ICE_FDIR_QUEUE_ID;
2141 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2142 txq->vsi = pf->fdir.fdir_vsi;
2144 txq->tx_ring_dma = tz->iova;
2145 txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2147 * don't need to allocate software ring and reset for the fdir
2148 * program queue just set the queue has been configured.
2153 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2159 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2161 struct ice_rx_queue *rxq;
2162 const struct rte_memzone *rz = NULL;
2164 struct rte_eth_dev *dev;
2167 PMD_DRV_LOG(ERR, "PF is not available");
2171 dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2173 /* Allocate the RX queue data structure. */
2174 rxq = rte_zmalloc_socket("ice fdir rx queue",
2175 sizeof(struct ice_rx_queue),
2176 RTE_CACHE_LINE_SIZE,
2179 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2180 "rx queue structure.");
2184 /* Allocate RX hardware ring descriptors. */
2185 ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2186 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2188 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2189 ICE_FDIR_QUEUE_ID, ring_size,
2190 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2192 ice_rx_queue_release(rxq);
2193 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2197 rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2198 rxq->queue_id = ICE_FDIR_QUEUE_ID;
2199 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2200 rxq->vsi = pf->fdir.fdir_vsi;
2202 rxq->rx_ring_dma = rz->iova;
2203 memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2204 sizeof(union ice_32byte_rx_desc));
2205 rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2208 * Don't need to allocate software ring and reset for the fdir
2209 * rx queue, just set the queue has been configured.
2214 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2220 ice_recv_pkts(void *rx_queue,
2221 struct rte_mbuf **rx_pkts,
2224 struct ice_rx_queue *rxq = rx_queue;
2225 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2226 volatile union ice_rx_flex_desc *rxdp;
2227 union ice_rx_flex_desc rxd;
2228 struct ice_rx_entry *sw_ring = rxq->sw_ring;
2229 struct ice_rx_entry *rxe;
2230 struct rte_mbuf *nmb; /* new allocated mbuf */
2231 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2232 uint16_t rx_id = rxq->rx_tail;
2234 uint16_t nb_hold = 0;
2235 uint16_t rx_packet_len;
2236 uint16_t rx_stat_err0;
2239 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2241 while (nb_rx < nb_pkts) {
2242 rxdp = &rx_ring[rx_id];
2243 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2245 /* Check the DD bit first */
2246 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2250 nmb = rte_mbuf_raw_alloc(rxq->mp);
2251 if (unlikely(!nmb)) {
2252 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2255 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2258 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2260 if (unlikely(rx_id == rxq->nb_rx_desc))
2265 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2268 * fill the read format of descriptor with physic address in
2269 * new allocated mbuf: nmb
2271 rxdp->read.hdr_addr = 0;
2272 rxdp->read.pkt_addr = dma_addr;
2274 /* calculate rx_packet_len of the received pkt */
2275 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2276 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2278 /* fill old mbuf with received descriptor: rxd */
2279 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2280 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2283 rxm->pkt_len = rx_packet_len;
2284 rxm->data_len = rx_packet_len;
2285 rxm->port = rxq->port_id;
2286 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2287 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2288 ice_rxd_to_vlan_tci(rxm, &rxd);
2289 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
2290 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2291 rxm->ol_flags |= pkt_flags;
2292 /* copy old mbuf to rx_pkts */
2293 rx_pkts[nb_rx++] = rxm;
2295 rxq->rx_tail = rx_id;
2297 * If the number of free RX descriptors is greater than the RX free
2298 * threshold of the queue, advance the receive tail register of queue.
2299 * Update that register with the value of the last processed RX
2300 * descriptor minus 1.
2302 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2303 if (nb_hold > rxq->rx_free_thresh) {
2304 rx_id = (uint16_t)(rx_id == 0 ?
2305 (rxq->nb_rx_desc - 1) : (rx_id - 1));
2306 /* write TAIL register */
2307 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2310 rxq->nb_rx_hold = nb_hold;
2312 /* return received packet in the burst */
2317 ice_parse_tunneling_params(uint64_t ol_flags,
2318 union ice_tx_offload tx_offload,
2319 uint32_t *cd_tunneling)
2321 /* EIPT: External (outer) IP header type */
2322 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2323 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2324 else if (ol_flags & PKT_TX_OUTER_IPV4)
2325 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2326 else if (ol_flags & PKT_TX_OUTER_IPV6)
2327 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2329 /* EIPLEN: External (outer) IP header length, in DWords */
2330 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2331 ICE_TXD_CTX_QW0_EIPLEN_S;
2333 /* L4TUNT: L4 Tunneling Type */
2334 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2335 case PKT_TX_TUNNEL_IPIP:
2336 /* for non UDP / GRE tunneling, set to 00b */
2338 case PKT_TX_TUNNEL_VXLAN:
2339 case PKT_TX_TUNNEL_GTP:
2340 case PKT_TX_TUNNEL_GENEVE:
2341 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2343 case PKT_TX_TUNNEL_GRE:
2344 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2347 PMD_TX_LOG(ERR, "Tunnel type not supported");
2351 /* L4TUNLEN: L4 Tunneling Length, in Words
2353 * We depend on app to set rte_mbuf.l2_len correctly.
2354 * For IP in GRE it should be set to the length of the GRE
2356 * For MAC in GRE or MAC in UDP it should be set to the length
2357 * of the GRE or UDP headers plus the inner MAC up to including
2358 * its last Ethertype.
2359 * If MPLS labels exists, it should include them as well.
2361 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2362 ICE_TXD_CTX_QW0_NATLEN_S;
2365 * Calculate the tunneling UDP checksum.
2366 * Shall be set only if L4TUNT = 01b and EIPT is not zero
2368 if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2369 (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2370 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2374 ice_txd_enable_checksum(uint64_t ol_flags,
2376 uint32_t *td_offset,
2377 union ice_tx_offload tx_offload)
2380 if (ol_flags & PKT_TX_TUNNEL_MASK)
2381 *td_offset |= (tx_offload.outer_l2_len >> 1)
2382 << ICE_TX_DESC_LEN_MACLEN_S;
2384 *td_offset |= (tx_offload.l2_len >> 1)
2385 << ICE_TX_DESC_LEN_MACLEN_S;
2387 /* Enable L3 checksum offloads */
2388 if (ol_flags & PKT_TX_IP_CKSUM) {
2389 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2390 *td_offset |= (tx_offload.l3_len >> 2) <<
2391 ICE_TX_DESC_LEN_IPLEN_S;
2392 } else if (ol_flags & PKT_TX_IPV4) {
2393 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2394 *td_offset |= (tx_offload.l3_len >> 2) <<
2395 ICE_TX_DESC_LEN_IPLEN_S;
2396 } else if (ol_flags & PKT_TX_IPV6) {
2397 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2398 *td_offset |= (tx_offload.l3_len >> 2) <<
2399 ICE_TX_DESC_LEN_IPLEN_S;
2402 if (ol_flags & PKT_TX_TCP_SEG) {
2403 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2404 *td_offset |= (tx_offload.l4_len >> 2) <<
2405 ICE_TX_DESC_LEN_L4_LEN_S;
2409 /* Enable L4 checksum offloads */
2410 switch (ol_flags & PKT_TX_L4_MASK) {
2411 case PKT_TX_TCP_CKSUM:
2412 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2413 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2414 ICE_TX_DESC_LEN_L4_LEN_S;
2416 case PKT_TX_SCTP_CKSUM:
2417 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2418 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2419 ICE_TX_DESC_LEN_L4_LEN_S;
2421 case PKT_TX_UDP_CKSUM:
2422 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2423 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2424 ICE_TX_DESC_LEN_L4_LEN_S;
2432 ice_xmit_cleanup(struct ice_tx_queue *txq)
2434 struct ice_tx_entry *sw_ring = txq->sw_ring;
2435 volatile struct ice_tx_desc *txd = txq->tx_ring;
2436 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2437 uint16_t nb_tx_desc = txq->nb_tx_desc;
2438 uint16_t desc_to_clean_to;
2439 uint16_t nb_tx_to_clean;
2441 /* Determine the last descriptor needing to be cleaned */
2442 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2443 if (desc_to_clean_to >= nb_tx_desc)
2444 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2446 /* Check to make sure the last descriptor to clean is done */
2447 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2448 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2449 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2450 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2451 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2453 txq->port_id, txq->queue_id,
2454 txd[desc_to_clean_to].cmd_type_offset_bsz);
2455 /* Failed to clean any descriptors */
2459 /* Figure out how many descriptors will be cleaned */
2460 if (last_desc_cleaned > desc_to_clean_to)
2461 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2464 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2467 /* The last descriptor to clean is done, so that means all the
2468 * descriptors from the last descriptor that was cleaned
2469 * up to the last descriptor with the RS bit set
2470 * are done. Only reset the threshold descriptor.
2472 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2474 /* Update the txq to reflect the last descriptor that was cleaned */
2475 txq->last_desc_cleaned = desc_to_clean_to;
2476 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2481 /* Construct the tx flags */
2482 static inline uint64_t
2483 ice_build_ctob(uint32_t td_cmd,
2488 return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2489 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2490 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2491 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2492 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2495 /* Check if the context descriptor is needed for TX offloading */
2496 static inline uint16_t
2497 ice_calc_context_desc(uint64_t flags)
2499 static uint64_t mask = PKT_TX_TCP_SEG |
2501 PKT_TX_OUTER_IP_CKSUM |
2504 return (flags & mask) ? 1 : 0;
2507 /* set ice TSO context descriptor */
2508 static inline uint64_t
2509 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2511 uint64_t ctx_desc = 0;
2512 uint32_t cd_cmd, hdr_len, cd_tso_len;
2514 if (!tx_offload.l4_len) {
2515 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2519 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2520 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2521 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2523 cd_cmd = ICE_TX_CTX_DESC_TSO;
2524 cd_tso_len = mbuf->pkt_len - hdr_len;
2525 ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2526 ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2527 ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2532 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2533 #define ICE_MAX_DATA_PER_TXD \
2534 (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2535 /* Calculate the number of TX descriptors needed for each pkt */
2536 static inline uint16_t
2537 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2539 struct rte_mbuf *txd = tx_pkt;
2542 while (txd != NULL) {
2543 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2551 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2553 struct ice_tx_queue *txq;
2554 volatile struct ice_tx_desc *tx_ring;
2555 volatile struct ice_tx_desc *txd;
2556 struct ice_tx_entry *sw_ring;
2557 struct ice_tx_entry *txe, *txn;
2558 struct rte_mbuf *tx_pkt;
2559 struct rte_mbuf *m_seg;
2560 uint32_t cd_tunneling_params;
2565 uint32_t td_cmd = 0;
2566 uint32_t td_offset = 0;
2567 uint32_t td_tag = 0;
2570 uint64_t buf_dma_addr;
2572 union ice_tx_offload tx_offload = {0};
2575 sw_ring = txq->sw_ring;
2576 tx_ring = txq->tx_ring;
2577 tx_id = txq->tx_tail;
2578 txe = &sw_ring[tx_id];
2580 /* Check if the descriptor ring needs to be cleaned. */
2581 if (txq->nb_tx_free < txq->tx_free_thresh)
2582 (void)ice_xmit_cleanup(txq);
2584 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2585 tx_pkt = *tx_pkts++;
2590 ol_flags = tx_pkt->ol_flags;
2591 tx_offload.l2_len = tx_pkt->l2_len;
2592 tx_offload.l3_len = tx_pkt->l3_len;
2593 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2594 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2595 tx_offload.l4_len = tx_pkt->l4_len;
2596 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2597 /* Calculate the number of context descriptors needed. */
2598 nb_ctx = ice_calc_context_desc(ol_flags);
2600 /* The number of descriptors that must be allocated for
2601 * a packet equals to the number of the segments of that
2602 * packet plus the number of context descriptor if needed.
2603 * Recalculate the needed tx descs when TSO enabled in case
2604 * the mbuf data size exceeds max data size that hw allows
2607 if (ol_flags & PKT_TX_TCP_SEG)
2608 nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2611 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2612 tx_last = (uint16_t)(tx_id + nb_used - 1);
2615 if (tx_last >= txq->nb_tx_desc)
2616 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2618 if (nb_used > txq->nb_tx_free) {
2619 if (ice_xmit_cleanup(txq) != 0) {
2624 if (unlikely(nb_used > txq->tx_rs_thresh)) {
2625 while (nb_used > txq->nb_tx_free) {
2626 if (ice_xmit_cleanup(txq) != 0) {
2635 /* Descriptor based VLAN insertion */
2636 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2637 td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2638 td_tag = tx_pkt->vlan_tci;
2641 /* Fill in tunneling parameters if necessary */
2642 cd_tunneling_params = 0;
2643 if (ol_flags & PKT_TX_TUNNEL_MASK)
2644 ice_parse_tunneling_params(ol_flags, tx_offload,
2645 &cd_tunneling_params);
2647 /* Enable checksum offloading */
2648 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2649 ice_txd_enable_checksum(ol_flags, &td_cmd,
2650 &td_offset, tx_offload);
2653 /* Setup TX context descriptor if required */
2654 volatile struct ice_tx_ctx_desc *ctx_txd =
2655 (volatile struct ice_tx_ctx_desc *)
2657 uint16_t cd_l2tag2 = 0;
2658 uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2660 txn = &sw_ring[txe->next_id];
2661 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2663 rte_pktmbuf_free_seg(txe->mbuf);
2667 if (ol_flags & PKT_TX_TCP_SEG)
2668 cd_type_cmd_tso_mss |=
2669 ice_set_tso_ctx(tx_pkt, tx_offload);
2671 ctx_txd->tunneling_params =
2672 rte_cpu_to_le_32(cd_tunneling_params);
2674 /* TX context descriptor based double VLAN insert */
2675 if (ol_flags & PKT_TX_QINQ) {
2676 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2677 cd_type_cmd_tso_mss |=
2678 ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2679 ICE_TXD_CTX_QW1_CMD_S);
2681 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2683 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2685 txe->last_id = tx_last;
2686 tx_id = txe->next_id;
2692 txd = &tx_ring[tx_id];
2693 txn = &sw_ring[txe->next_id];
2696 rte_pktmbuf_free_seg(txe->mbuf);
2699 /* Setup TX Descriptor */
2700 slen = m_seg->data_len;
2701 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2703 while ((ol_flags & PKT_TX_TCP_SEG) &&
2704 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2705 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2706 txd->cmd_type_offset_bsz =
2707 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2708 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2709 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2710 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2711 ICE_TXD_QW1_TX_BUF_SZ_S) |
2712 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2714 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2715 slen -= ICE_MAX_DATA_PER_TXD;
2717 txe->last_id = tx_last;
2718 tx_id = txe->next_id;
2720 txd = &tx_ring[tx_id];
2721 txn = &sw_ring[txe->next_id];
2724 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2725 txd->cmd_type_offset_bsz =
2726 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2727 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2728 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2729 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2730 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2732 txe->last_id = tx_last;
2733 tx_id = txe->next_id;
2735 m_seg = m_seg->next;
2738 /* fill the last descriptor with End of Packet (EOP) bit */
2739 td_cmd |= ICE_TX_DESC_CMD_EOP;
2740 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2741 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2743 /* set RS bit on the last descriptor of one packet */
2744 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2746 "Setting RS bit on TXD id="
2747 "%4u (port=%d queue=%d)",
2748 tx_last, txq->port_id, txq->queue_id);
2750 td_cmd |= ICE_TX_DESC_CMD_RS;
2752 /* Update txq RS bit counters */
2753 txq->nb_tx_used = 0;
2755 txd->cmd_type_offset_bsz |=
2756 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2760 /* update Tail register */
2761 ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2762 txq->tx_tail = tx_id;
2767 static __rte_always_inline int
2768 ice_tx_free_bufs(struct ice_tx_queue *txq)
2770 struct ice_tx_entry *txep;
2773 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2774 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2775 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2778 txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2780 for (i = 0; i < txq->tx_rs_thresh; i++)
2781 rte_prefetch0((txep + i)->mbuf);
2783 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2784 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2785 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2789 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2790 rte_pktmbuf_free_seg(txep->mbuf);
2795 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2796 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2797 if (txq->tx_next_dd >= txq->nb_tx_desc)
2798 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2800 return txq->tx_rs_thresh;
2804 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2807 struct ice_tx_entry *swr_ring = txq->sw_ring;
2808 uint16_t i, tx_last, tx_id;
2809 uint16_t nb_tx_free_last;
2810 uint16_t nb_tx_to_clean;
2813 /* Start free mbuf from the next of tx_tail */
2814 tx_last = txq->tx_tail;
2815 tx_id = swr_ring[tx_last].next_id;
2817 if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2820 nb_tx_to_clean = txq->nb_tx_free;
2821 nb_tx_free_last = txq->nb_tx_free;
2823 free_cnt = txq->nb_tx_desc;
2825 /* Loop through swr_ring to count the amount of
2826 * freeable mubfs and packets.
2828 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2829 for (i = 0; i < nb_tx_to_clean &&
2830 pkt_cnt < free_cnt &&
2831 tx_id != tx_last; i++) {
2832 if (swr_ring[tx_id].mbuf != NULL) {
2833 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2834 swr_ring[tx_id].mbuf = NULL;
2837 * last segment in the packet,
2838 * increment packet count
2840 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2843 tx_id = swr_ring[tx_id].next_id;
2846 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2847 txq->nb_tx_free || tx_id == tx_last)
2850 if (pkt_cnt < free_cnt) {
2851 if (ice_xmit_cleanup(txq))
2854 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2855 nb_tx_free_last = txq->nb_tx_free;
2859 return (int)pkt_cnt;
2864 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2865 uint32_t free_cnt __rte_unused)
2872 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2877 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2878 free_cnt = txq->nb_tx_desc;
2880 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2882 for (i = 0; i < cnt; i += n) {
2883 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2886 n = ice_tx_free_bufs(txq);
2896 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2898 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2899 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2900 struct ice_adapter *ad =
2901 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2904 if (ad->tx_vec_allowed)
2905 return ice_tx_done_cleanup_vec(q, free_cnt);
2907 if (ad->tx_simple_allowed)
2908 return ice_tx_done_cleanup_simple(q, free_cnt);
2910 return ice_tx_done_cleanup_full(q, free_cnt);
2913 /* Populate 4 descriptors with data from 4 mbufs */
2915 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2920 for (i = 0; i < 4; i++, txdp++, pkts++) {
2921 dma_addr = rte_mbuf_data_iova(*pkts);
2922 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2923 txdp->cmd_type_offset_bsz =
2924 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2925 (*pkts)->data_len, 0);
2929 /* Populate 1 descriptor with data from 1 mbuf */
2931 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2935 dma_addr = rte_mbuf_data_iova(*pkts);
2936 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2937 txdp->cmd_type_offset_bsz =
2938 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2939 (*pkts)->data_len, 0);
2943 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2946 volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2947 struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2948 const int N_PER_LOOP = 4;
2949 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2950 int mainpart, leftover;
2954 * Process most of the packets in chunks of N pkts. Any
2955 * leftover packets will get processed one at a time.
2957 mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2958 leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2959 for (i = 0; i < mainpart; i += N_PER_LOOP) {
2960 /* Copy N mbuf pointers to the S/W ring */
2961 for (j = 0; j < N_PER_LOOP; ++j)
2962 (txep + i + j)->mbuf = *(pkts + i + j);
2963 tx4(txdp + i, pkts + i);
2966 if (unlikely(leftover > 0)) {
2967 for (i = 0; i < leftover; ++i) {
2968 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2969 tx1(txdp + mainpart + i, pkts + mainpart + i);
2974 static inline uint16_t
2975 tx_xmit_pkts(struct ice_tx_queue *txq,
2976 struct rte_mbuf **tx_pkts,
2979 volatile struct ice_tx_desc *txr = txq->tx_ring;
2983 * Begin scanning the H/W ring for done descriptors when the number
2984 * of available descriptors drops below tx_free_thresh. For each done
2985 * descriptor, free the associated buffer.
2987 if (txq->nb_tx_free < txq->tx_free_thresh)
2988 ice_tx_free_bufs(txq);
2990 /* Use available descriptor only */
2991 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2992 if (unlikely(!nb_pkts))
2995 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2996 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2997 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2998 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2999 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3000 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3002 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3006 /* Fill hardware descriptor ring with mbuf data */
3007 ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3008 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3010 /* Determin if RS bit needs to be set */
3011 if (txq->tx_tail > txq->tx_next_rs) {
3012 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3013 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3016 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3017 if (txq->tx_next_rs >= txq->nb_tx_desc)
3018 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3021 if (txq->tx_tail >= txq->nb_tx_desc)
3024 /* Update the tx tail register */
3025 ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3031 ice_xmit_pkts_simple(void *tx_queue,
3032 struct rte_mbuf **tx_pkts,
3037 if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3038 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3042 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3045 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3046 &tx_pkts[nb_tx], num);
3047 nb_tx = (uint16_t)(nb_tx + ret);
3048 nb_pkts = (uint16_t)(nb_pkts - ret);
3057 ice_set_rx_function(struct rte_eth_dev *dev)
3059 PMD_INIT_FUNC_TRACE();
3060 struct ice_adapter *ad =
3061 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3063 struct ice_rx_queue *rxq;
3065 int rx_check_ret = -1;
3067 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3068 ad->rx_use_avx512 = false;
3069 ad->rx_use_avx2 = false;
3070 rx_check_ret = ice_rx_vec_dev_check(dev);
3071 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3072 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3073 ad->rx_vec_allowed = true;
3074 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3075 rxq = dev->data->rx_queues[i];
3076 if (rxq && ice_rxq_vec_setup(rxq)) {
3077 ad->rx_vec_allowed = false;
3082 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3083 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3084 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3085 #ifdef CC_AVX512_SUPPORT
3086 ad->rx_use_avx512 = true;
3089 "AVX512 is not supported in build env");
3091 if (!ad->rx_use_avx512 &&
3092 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3093 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3094 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3095 ad->rx_use_avx2 = true;
3098 ad->rx_vec_allowed = false;
3102 if (ad->rx_vec_allowed) {
3103 if (dev->data->scattered_rx) {
3104 if (ad->rx_use_avx512) {
3105 #ifdef CC_AVX512_SUPPORT
3106 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3108 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3109 dev->data->port_id);
3111 ice_recv_scattered_pkts_vec_avx512_offload;
3114 "Using AVX512 Vector Scattered Rx (port %d).",
3115 dev->data->port_id);
3117 ice_recv_scattered_pkts_vec_avx512;
3120 } else if (ad->rx_use_avx2) {
3121 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3123 "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3124 dev->data->port_id);
3126 ice_recv_scattered_pkts_vec_avx2_offload;
3129 "Using AVX2 Vector Scattered Rx (port %d).",
3130 dev->data->port_id);
3132 ice_recv_scattered_pkts_vec_avx2;
3136 "Using Vector Scattered Rx (port %d).",
3137 dev->data->port_id);
3138 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3141 if (ad->rx_use_avx512) {
3142 #ifdef CC_AVX512_SUPPORT
3143 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3145 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3146 dev->data->port_id);
3148 ice_recv_pkts_vec_avx512_offload;
3151 "Using AVX512 Vector Rx (port %d).",
3152 dev->data->port_id);
3154 ice_recv_pkts_vec_avx512;
3157 } else if (ad->rx_use_avx2) {
3158 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3160 "Using AVX2 OFFLOAD Vector Rx (port %d).",
3161 dev->data->port_id);
3163 ice_recv_pkts_vec_avx2_offload;
3166 "Using AVX2 Vector Rx (port %d).",
3167 dev->data->port_id);
3169 ice_recv_pkts_vec_avx2;
3173 "Using Vector Rx (port %d).",
3174 dev->data->port_id);
3175 dev->rx_pkt_burst = ice_recv_pkts_vec;
3183 if (dev->data->scattered_rx) {
3184 /* Set the non-LRO scattered function */
3186 "Using a Scattered function on port %d.",
3187 dev->data->port_id);
3188 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3189 } else if (ad->rx_bulk_alloc_allowed) {
3191 "Rx Burst Bulk Alloc Preconditions are "
3192 "satisfied. Rx Burst Bulk Alloc function "
3193 "will be used on port %d.",
3194 dev->data->port_id);
3195 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3198 "Rx Burst Bulk Alloc Preconditions are not "
3199 "satisfied, Normal Rx will be used on port %d.",
3200 dev->data->port_id);
3201 dev->rx_pkt_burst = ice_recv_pkts;
3205 static const struct {
3206 eth_rx_burst_t pkt_burst;
3208 } ice_rx_burst_infos[] = {
3209 { ice_recv_scattered_pkts, "Scalar Scattered" },
3210 { ice_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3211 { ice_recv_pkts, "Scalar" },
3213 #ifdef CC_AVX512_SUPPORT
3214 { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3215 { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3216 { ice_recv_pkts_vec_avx512, "Vector AVX512" },
3217 { ice_recv_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3219 { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3220 { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3221 { ice_recv_pkts_vec_avx2, "Vector AVX2" },
3222 { ice_recv_pkts_vec_avx2_offload, "Offload Vector AVX2" },
3223 { ice_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3224 { ice_recv_pkts_vec, "Vector SSE" },
3229 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3230 struct rte_eth_burst_mode *mode)
3232 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3236 for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3237 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3238 snprintf(mode->info, sizeof(mode->info), "%s",
3239 ice_rx_burst_infos[i].info);
3249 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3251 struct ice_adapter *ad =
3252 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3254 /* Use a simple Tx queue if possible (only fast free is allowed) */
3255 ad->tx_simple_allowed =
3257 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3258 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3260 if (ad->tx_simple_allowed)
3261 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3265 "Simple Tx can NOT be enabled on Tx queue %u.",
3269 /*********************************************************************
3273 **********************************************************************/
3274 /* The default values of TSO MSS */
3275 #define ICE_MIN_TSO_MSS 64
3276 #define ICE_MAX_TSO_MSS 9728
3277 #define ICE_MAX_TSO_FRAME_SIZE 262144
3279 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3286 for (i = 0; i < nb_pkts; i++) {
3288 ol_flags = m->ol_flags;
3290 if (ol_flags & PKT_TX_TCP_SEG &&
3291 (m->tso_segsz < ICE_MIN_TSO_MSS ||
3292 m->tso_segsz > ICE_MAX_TSO_MSS ||
3293 m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3295 * MSS outside the range are considered malicious
3301 #ifdef RTE_ETHDEV_DEBUG_TX
3302 ret = rte_validate_tx_offload(m);
3308 ret = rte_net_intel_cksum_prepare(m);
3318 ice_set_tx_function(struct rte_eth_dev *dev)
3320 struct ice_adapter *ad =
3321 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3323 struct ice_tx_queue *txq;
3325 int tx_check_ret = -1;
3327 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3328 ad->tx_use_avx2 = false;
3329 ad->tx_use_avx512 = false;
3330 tx_check_ret = ice_tx_vec_dev_check(dev);
3331 if (tx_check_ret >= 0 &&
3332 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3333 ad->tx_vec_allowed = true;
3335 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3336 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3337 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3338 #ifdef CC_AVX512_SUPPORT
3339 ad->tx_use_avx512 = true;
3342 "AVX512 is not supported in build env");
3344 if (!ad->tx_use_avx512 &&
3345 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3346 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3347 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3348 ad->tx_use_avx2 = true;
3350 if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3351 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3352 ad->tx_vec_allowed = false;
3354 if (ad->tx_vec_allowed) {
3355 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3356 txq = dev->data->tx_queues[i];
3357 if (txq && ice_txq_vec_setup(txq)) {
3358 ad->tx_vec_allowed = false;
3364 ad->tx_vec_allowed = false;
3368 if (ad->tx_vec_allowed) {
3369 dev->tx_pkt_prepare = NULL;
3370 if (ad->tx_use_avx512) {
3371 #ifdef CC_AVX512_SUPPORT
3372 if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3374 "Using AVX512 OFFLOAD Vector Tx (port %d).",
3375 dev->data->port_id);
3377 ice_xmit_pkts_vec_avx512_offload;
3378 dev->tx_pkt_prepare = ice_prep_pkts;
3381 "Using AVX512 Vector Tx (port %d).",
3382 dev->data->port_id);
3383 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3387 if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3389 "Using AVX2 OFFLOAD Vector Tx (port %d).",
3390 dev->data->port_id);
3392 ice_xmit_pkts_vec_avx2_offload;
3393 dev->tx_pkt_prepare = ice_prep_pkts;
3395 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3396 ad->tx_use_avx2 ? "avx2 " : "",
3397 dev->data->port_id);
3398 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3399 ice_xmit_pkts_vec_avx2 :
3408 if (ad->tx_simple_allowed) {
3409 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3410 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3411 dev->tx_pkt_prepare = NULL;
3413 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3414 dev->tx_pkt_burst = ice_xmit_pkts;
3415 dev->tx_pkt_prepare = ice_prep_pkts;
3419 static const struct {
3420 eth_tx_burst_t pkt_burst;
3422 } ice_tx_burst_infos[] = {
3423 { ice_xmit_pkts_simple, "Scalar Simple" },
3424 { ice_xmit_pkts, "Scalar" },
3426 #ifdef CC_AVX512_SUPPORT
3427 { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3428 { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3430 { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3431 { ice_xmit_pkts_vec, "Vector SSE" },
3436 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3437 struct rte_eth_burst_mode *mode)
3439 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3443 for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3444 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3445 snprintf(mode->info, sizeof(mode->info), "%s",
3446 ice_tx_burst_infos[i].info);
3455 /* For each value it means, datasheet of hardware can tell more details
3457 * @note: fix ice_dev_supported_ptypes_get() if any change here.
3459 static inline uint32_t
3460 ice_get_default_pkt_type(uint16_t ptype)
3462 static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3463 __rte_cache_aligned = {
3466 [1] = RTE_PTYPE_L2_ETHER,
3467 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3468 /* [3] - [5] reserved */
3469 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3470 /* [7] - [10] reserved */
3471 [11] = RTE_PTYPE_L2_ETHER_ARP,
3472 /* [12] - [21] reserved */
3474 /* Non tunneled IPv4 */
3475 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3477 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3478 RTE_PTYPE_L4_NONFRAG,
3479 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3482 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3484 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3486 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3490 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3491 RTE_PTYPE_TUNNEL_IP |
3492 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3493 RTE_PTYPE_INNER_L4_FRAG,
3494 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3495 RTE_PTYPE_TUNNEL_IP |
3496 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3497 RTE_PTYPE_INNER_L4_NONFRAG,
3498 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3499 RTE_PTYPE_TUNNEL_IP |
3500 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3501 RTE_PTYPE_INNER_L4_UDP,
3503 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3504 RTE_PTYPE_TUNNEL_IP |
3505 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3506 RTE_PTYPE_INNER_L4_TCP,
3507 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3508 RTE_PTYPE_TUNNEL_IP |
3509 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3510 RTE_PTYPE_INNER_L4_SCTP,
3511 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3512 RTE_PTYPE_TUNNEL_IP |
3513 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3514 RTE_PTYPE_INNER_L4_ICMP,
3517 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3518 RTE_PTYPE_TUNNEL_IP |
3519 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3520 RTE_PTYPE_INNER_L4_FRAG,
3521 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3522 RTE_PTYPE_TUNNEL_IP |
3523 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3524 RTE_PTYPE_INNER_L4_NONFRAG,
3525 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3526 RTE_PTYPE_TUNNEL_IP |
3527 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3528 RTE_PTYPE_INNER_L4_UDP,
3530 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3531 RTE_PTYPE_TUNNEL_IP |
3532 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3533 RTE_PTYPE_INNER_L4_TCP,
3534 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3535 RTE_PTYPE_TUNNEL_IP |
3536 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3537 RTE_PTYPE_INNER_L4_SCTP,
3538 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3539 RTE_PTYPE_TUNNEL_IP |
3540 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3541 RTE_PTYPE_INNER_L4_ICMP,
3543 /* IPv4 --> GRE/Teredo/VXLAN */
3544 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3545 RTE_PTYPE_TUNNEL_GRENAT,
3547 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3548 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3549 RTE_PTYPE_TUNNEL_GRENAT |
3550 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3551 RTE_PTYPE_INNER_L4_FRAG,
3552 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3553 RTE_PTYPE_TUNNEL_GRENAT |
3554 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3555 RTE_PTYPE_INNER_L4_NONFRAG,
3556 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3557 RTE_PTYPE_TUNNEL_GRENAT |
3558 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3559 RTE_PTYPE_INNER_L4_UDP,
3561 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3562 RTE_PTYPE_TUNNEL_GRENAT |
3563 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3564 RTE_PTYPE_INNER_L4_TCP,
3565 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3566 RTE_PTYPE_TUNNEL_GRENAT |
3567 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3568 RTE_PTYPE_INNER_L4_SCTP,
3569 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3570 RTE_PTYPE_TUNNEL_GRENAT |
3571 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3572 RTE_PTYPE_INNER_L4_ICMP,
3574 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3575 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3576 RTE_PTYPE_TUNNEL_GRENAT |
3577 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3578 RTE_PTYPE_INNER_L4_FRAG,
3579 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3580 RTE_PTYPE_TUNNEL_GRENAT |
3581 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3582 RTE_PTYPE_INNER_L4_NONFRAG,
3583 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3584 RTE_PTYPE_TUNNEL_GRENAT |
3585 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3586 RTE_PTYPE_INNER_L4_UDP,
3588 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3589 RTE_PTYPE_TUNNEL_GRENAT |
3590 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3591 RTE_PTYPE_INNER_L4_TCP,
3592 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3593 RTE_PTYPE_TUNNEL_GRENAT |
3594 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3595 RTE_PTYPE_INNER_L4_SCTP,
3596 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3597 RTE_PTYPE_TUNNEL_GRENAT |
3598 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3599 RTE_PTYPE_INNER_L4_ICMP,
3601 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3602 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3603 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3605 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3606 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3607 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3608 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3609 RTE_PTYPE_INNER_L4_FRAG,
3610 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3611 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3612 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3613 RTE_PTYPE_INNER_L4_NONFRAG,
3614 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3615 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3616 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3617 RTE_PTYPE_INNER_L4_UDP,
3619 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3620 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3621 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3622 RTE_PTYPE_INNER_L4_TCP,
3623 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3624 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3625 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3626 RTE_PTYPE_INNER_L4_SCTP,
3627 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3628 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3629 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3630 RTE_PTYPE_INNER_L4_ICMP,
3632 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3633 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3634 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3635 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3636 RTE_PTYPE_INNER_L4_FRAG,
3637 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3638 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3639 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3640 RTE_PTYPE_INNER_L4_NONFRAG,
3641 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3642 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3643 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3644 RTE_PTYPE_INNER_L4_UDP,
3646 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3647 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3648 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3649 RTE_PTYPE_INNER_L4_TCP,
3650 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3651 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3652 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3653 RTE_PTYPE_INNER_L4_SCTP,
3654 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3655 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3656 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3657 RTE_PTYPE_INNER_L4_ICMP,
3658 /* [73] - [87] reserved */
3660 /* Non tunneled IPv6 */
3661 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3663 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3664 RTE_PTYPE_L4_NONFRAG,
3665 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3668 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3670 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3672 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3676 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3677 RTE_PTYPE_TUNNEL_IP |
3678 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3679 RTE_PTYPE_INNER_L4_FRAG,
3680 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3681 RTE_PTYPE_TUNNEL_IP |
3682 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3683 RTE_PTYPE_INNER_L4_NONFRAG,
3684 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3685 RTE_PTYPE_TUNNEL_IP |
3686 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3687 RTE_PTYPE_INNER_L4_UDP,
3689 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3690 RTE_PTYPE_TUNNEL_IP |
3691 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3692 RTE_PTYPE_INNER_L4_TCP,
3693 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3694 RTE_PTYPE_TUNNEL_IP |
3695 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3696 RTE_PTYPE_INNER_L4_SCTP,
3697 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3698 RTE_PTYPE_TUNNEL_IP |
3699 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3700 RTE_PTYPE_INNER_L4_ICMP,
3703 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3704 RTE_PTYPE_TUNNEL_IP |
3705 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3706 RTE_PTYPE_INNER_L4_FRAG,
3707 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3708 RTE_PTYPE_TUNNEL_IP |
3709 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3710 RTE_PTYPE_INNER_L4_NONFRAG,
3711 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3712 RTE_PTYPE_TUNNEL_IP |
3713 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3714 RTE_PTYPE_INNER_L4_UDP,
3715 /* [105] reserved */
3716 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3717 RTE_PTYPE_TUNNEL_IP |
3718 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3719 RTE_PTYPE_INNER_L4_TCP,
3720 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3721 RTE_PTYPE_TUNNEL_IP |
3722 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3723 RTE_PTYPE_INNER_L4_SCTP,
3724 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3725 RTE_PTYPE_TUNNEL_IP |
3726 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3727 RTE_PTYPE_INNER_L4_ICMP,
3729 /* IPv6 --> GRE/Teredo/VXLAN */
3730 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3731 RTE_PTYPE_TUNNEL_GRENAT,
3733 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3734 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3735 RTE_PTYPE_TUNNEL_GRENAT |
3736 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3737 RTE_PTYPE_INNER_L4_FRAG,
3738 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3739 RTE_PTYPE_TUNNEL_GRENAT |
3740 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3741 RTE_PTYPE_INNER_L4_NONFRAG,
3742 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3743 RTE_PTYPE_TUNNEL_GRENAT |
3744 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3745 RTE_PTYPE_INNER_L4_UDP,
3746 /* [113] reserved */
3747 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3748 RTE_PTYPE_TUNNEL_GRENAT |
3749 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3750 RTE_PTYPE_INNER_L4_TCP,
3751 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3752 RTE_PTYPE_TUNNEL_GRENAT |
3753 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3754 RTE_PTYPE_INNER_L4_SCTP,
3755 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3756 RTE_PTYPE_TUNNEL_GRENAT |
3757 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3758 RTE_PTYPE_INNER_L4_ICMP,
3760 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3761 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3762 RTE_PTYPE_TUNNEL_GRENAT |
3763 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3764 RTE_PTYPE_INNER_L4_FRAG,
3765 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3766 RTE_PTYPE_TUNNEL_GRENAT |
3767 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3768 RTE_PTYPE_INNER_L4_NONFRAG,
3769 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3770 RTE_PTYPE_TUNNEL_GRENAT |
3771 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3772 RTE_PTYPE_INNER_L4_UDP,
3773 /* [120] reserved */
3774 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3775 RTE_PTYPE_TUNNEL_GRENAT |
3776 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3777 RTE_PTYPE_INNER_L4_TCP,
3778 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3779 RTE_PTYPE_TUNNEL_GRENAT |
3780 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3781 RTE_PTYPE_INNER_L4_SCTP,
3782 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3783 RTE_PTYPE_TUNNEL_GRENAT |
3784 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3785 RTE_PTYPE_INNER_L4_ICMP,
3787 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3788 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3789 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3791 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3792 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3793 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3794 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3795 RTE_PTYPE_INNER_L4_FRAG,
3796 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3797 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3798 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3799 RTE_PTYPE_INNER_L4_NONFRAG,
3800 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3801 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3802 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3803 RTE_PTYPE_INNER_L4_UDP,
3804 /* [128] reserved */
3805 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3806 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3807 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3808 RTE_PTYPE_INNER_L4_TCP,
3809 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3810 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3811 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3812 RTE_PTYPE_INNER_L4_SCTP,
3813 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3814 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3815 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3816 RTE_PTYPE_INNER_L4_ICMP,
3818 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3819 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3820 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3821 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3822 RTE_PTYPE_INNER_L4_FRAG,
3823 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3824 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3825 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3826 RTE_PTYPE_INNER_L4_NONFRAG,
3827 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3828 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3829 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3830 RTE_PTYPE_INNER_L4_UDP,
3831 /* [135] reserved */
3832 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3833 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3834 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3835 RTE_PTYPE_INNER_L4_TCP,
3836 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3837 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3838 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3839 RTE_PTYPE_INNER_L4_SCTP,
3840 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3841 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3842 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3843 RTE_PTYPE_INNER_L4_ICMP,
3844 /* [139] - [299] reserved */
3847 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3848 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3850 /* PPPoE --> IPv4 */
3851 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3852 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3854 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3855 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3856 RTE_PTYPE_L4_NONFRAG,
3857 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3858 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3860 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3861 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3863 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3864 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3866 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3867 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3870 /* PPPoE --> IPv6 */
3871 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3872 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3874 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3875 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3876 RTE_PTYPE_L4_NONFRAG,
3877 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3878 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3880 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3881 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3883 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3884 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3886 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3887 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3889 /* [314] - [324] reserved */
3891 /* IPv4/IPv6 --> GTPC/GTPU */
3892 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3893 RTE_PTYPE_TUNNEL_GTPC,
3894 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3895 RTE_PTYPE_TUNNEL_GTPC,
3896 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3897 RTE_PTYPE_TUNNEL_GTPC,
3898 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3899 RTE_PTYPE_TUNNEL_GTPC,
3900 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3901 RTE_PTYPE_TUNNEL_GTPU,
3902 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3903 RTE_PTYPE_TUNNEL_GTPU,
3905 /* IPv4 --> GTPU --> IPv4 */
3906 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3907 RTE_PTYPE_TUNNEL_GTPU |
3908 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3909 RTE_PTYPE_INNER_L4_FRAG,
3910 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3911 RTE_PTYPE_TUNNEL_GTPU |
3912 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3913 RTE_PTYPE_INNER_L4_NONFRAG,
3914 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3915 RTE_PTYPE_TUNNEL_GTPU |
3916 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3917 RTE_PTYPE_INNER_L4_UDP,
3918 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3919 RTE_PTYPE_TUNNEL_GTPU |
3920 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3921 RTE_PTYPE_INNER_L4_TCP,
3922 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3923 RTE_PTYPE_TUNNEL_GTPU |
3924 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3925 RTE_PTYPE_INNER_L4_ICMP,
3927 /* IPv6 --> GTPU --> IPv4 */
3928 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3929 RTE_PTYPE_TUNNEL_GTPU |
3930 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3931 RTE_PTYPE_INNER_L4_FRAG,
3932 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3933 RTE_PTYPE_TUNNEL_GTPU |
3934 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3935 RTE_PTYPE_INNER_L4_NONFRAG,
3936 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3937 RTE_PTYPE_TUNNEL_GTPU |
3938 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3939 RTE_PTYPE_INNER_L4_UDP,
3940 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3941 RTE_PTYPE_TUNNEL_GTPU |
3942 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3943 RTE_PTYPE_INNER_L4_TCP,
3944 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3945 RTE_PTYPE_TUNNEL_GTPU |
3946 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3947 RTE_PTYPE_INNER_L4_ICMP,
3949 /* IPv4 --> GTPU --> IPv6 */
3950 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3951 RTE_PTYPE_TUNNEL_GTPU |
3952 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3953 RTE_PTYPE_INNER_L4_FRAG,
3954 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3955 RTE_PTYPE_TUNNEL_GTPU |
3956 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3957 RTE_PTYPE_INNER_L4_NONFRAG,
3958 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3959 RTE_PTYPE_TUNNEL_GTPU |
3960 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3961 RTE_PTYPE_INNER_L4_UDP,
3962 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3963 RTE_PTYPE_TUNNEL_GTPU |
3964 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3965 RTE_PTYPE_INNER_L4_TCP,
3966 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3967 RTE_PTYPE_TUNNEL_GTPU |
3968 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3969 RTE_PTYPE_INNER_L4_ICMP,
3971 /* IPv6 --> GTPU --> IPv6 */
3972 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3973 RTE_PTYPE_TUNNEL_GTPU |
3974 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3975 RTE_PTYPE_INNER_L4_FRAG,
3976 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3977 RTE_PTYPE_TUNNEL_GTPU |
3978 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3979 RTE_PTYPE_INNER_L4_NONFRAG,
3980 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3981 RTE_PTYPE_TUNNEL_GTPU |
3982 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3983 RTE_PTYPE_INNER_L4_UDP,
3984 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3985 RTE_PTYPE_TUNNEL_GTPU |
3986 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3987 RTE_PTYPE_INNER_L4_TCP,
3988 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3989 RTE_PTYPE_TUNNEL_GTPU |
3990 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3991 RTE_PTYPE_INNER_L4_ICMP,
3993 /* IPv4 --> UDP ECPRI */
3994 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3996 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3998 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4000 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4002 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4004 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4006 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4008 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4010 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4012 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4015 /* IPV6 --> UDP ECPRI */
4016 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4018 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4020 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4022 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4024 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4026 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4028 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4030 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4032 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4034 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4036 /* All others reserved */
4039 return type_table[ptype];
4043 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4045 struct ice_adapter *ad =
4046 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4049 for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4050 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4053 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4054 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4055 (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4056 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4057 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4059 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S 4
4060 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M \
4061 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4062 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S 5
4063 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M \
4064 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4067 * check the programming status descriptor in rx queue.
4068 * done after Programming Flow Director is programmed on
4072 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4074 volatile union ice_32byte_rx_desc *rxdp;
4081 rxdp = (volatile union ice_32byte_rx_desc *)
4082 (&rxq->rx_ring[rxq->rx_tail]);
4083 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4084 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4085 >> ICE_RXD_QW1_STATUS_S;
4087 if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4089 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4090 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4091 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4092 ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4094 if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4095 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4096 else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4097 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4101 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4102 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4104 PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4108 rxdp->wb.qword1.status_error_len = 0;
4110 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4112 if (rxq->rx_tail == 0)
4113 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4115 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4121 #define ICE_FDIR_MAX_WAIT_US 10000
4124 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4126 struct ice_tx_queue *txq = pf->fdir.txq;
4127 struct ice_rx_queue *rxq = pf->fdir.rxq;
4128 volatile struct ice_fltr_desc *fdirdp;
4129 volatile struct ice_tx_desc *txdp;
4133 fdirdp = (volatile struct ice_fltr_desc *)
4134 (&txq->tx_ring[txq->tx_tail]);
4135 fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4136 fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4138 txdp = &txq->tx_ring[txq->tx_tail + 1];
4139 txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4140 td_cmd = ICE_TX_DESC_CMD_EOP |
4141 ICE_TX_DESC_CMD_RS |
4142 ICE_TX_DESC_CMD_DUMMY;
4144 txdp->cmd_type_offset_bsz =
4145 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4148 if (txq->tx_tail >= txq->nb_tx_desc)
4150 /* Update the tx tail register */
4151 ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4152 for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4153 if ((txdp->cmd_type_offset_bsz &
4154 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4155 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4159 if (i >= ICE_FDIR_MAX_WAIT_US) {
4161 "Failed to program FDIR filter: time out to get DD on tx queue.");
4165 for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4168 ret = ice_check_fdir_programming_status(rxq);
4176 "Failed to program FDIR filter: programming status reported.");