1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_ethdev_driver.h>
10 #define ICE_TX_CKSUM_OFFLOAD_MASK ( \
14 PKT_TX_OUTER_IP_CKSUM)
16 #define ICE_RX_ERR_BITS 0x3f
18 static enum ice_status
19 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
21 struct ice_vsi *vsi = rxq->vsi;
22 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
23 struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
24 struct ice_rlan_ctx rx_ctx;
26 uint16_t buf_size, len;
27 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
31 * The kernel driver uses flex descriptor. It sets the register
32 * to flex descriptor mode.
33 * DPDK uses legacy descriptor. It should set the register back
34 * to the default value, then uses legacy descriptor mode.
36 regval = (0x01 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
37 QRXFLXP_CNTXT_RXDID_PRIO_M;
38 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
40 /* Set buffer size as the head split is disabled. */
41 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
42 RTE_PKTMBUF_HEADROOM);
44 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
45 len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
46 rxq->max_pkt_len = RTE_MIN(len,
47 dev->data->dev_conf.rxmode.max_rx_pkt_len);
49 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
50 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
51 rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
52 PMD_DRV_LOG(ERR, "maximum packet length must "
53 "be larger than %u and smaller than %u,"
54 "as jumbo frame is enabled",
55 (uint32_t)RTE_ETHER_MAX_LEN,
56 (uint32_t)ICE_FRAME_SIZE_MAX);
60 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
61 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
62 PMD_DRV_LOG(ERR, "maximum packet length must be "
63 "larger than %u and smaller than %u, "
64 "as jumbo frame is disabled",
65 (uint32_t)RTE_ETHER_MIN_LEN,
66 (uint32_t)RTE_ETHER_MAX_LEN);
71 memset(&rx_ctx, 0, sizeof(rx_ctx));
73 rx_ctx.base = rxq->rx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
74 rx_ctx.qlen = rxq->nb_rx_desc;
75 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
76 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
77 rx_ctx.dtype = 0; /* No Header Split mode */
78 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
79 rx_ctx.dsize = 1; /* 32B descriptors */
81 rx_ctx.rxmax = rxq->max_pkt_len;
82 /* TPH: Transaction Layer Packet (TLP) processing hints */
83 rx_ctx.tphrdesc_ena = 1;
84 rx_ctx.tphwdesc_ena = 1;
85 rx_ctx.tphdata_ena = 1;
86 rx_ctx.tphhead_ena = 1;
87 /* Low Receive Queue Threshold defined in 64 descriptors units.
88 * When the number of free descriptors goes below the lrxqthresh,
89 * an immediate interrupt is triggered.
91 rx_ctx.lrxqthresh = 2;
92 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
95 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
97 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
99 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
103 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
105 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
110 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
111 RTE_PKTMBUF_HEADROOM);
113 /* Check if scattered RX needs to be used. */
114 if (rxq->max_pkt_len > buf_size)
115 dev->data->scattered_rx = 1;
117 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
119 /* Init the Rx tail register*/
120 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
125 /* Allocate mbufs for all descriptors in rx queue */
127 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
129 struct ice_rx_entry *rxe = rxq->sw_ring;
133 for (i = 0; i < rxq->nb_rx_desc; i++) {
134 volatile union ice_rx_desc *rxd;
135 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
137 if (unlikely(!mbuf)) {
138 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
142 rte_mbuf_refcnt_set(mbuf, 1);
144 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
146 mbuf->port = rxq->port_id;
149 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
151 rxd = &rxq->rx_ring[i];
152 rxd->read.pkt_addr = dma_addr;
153 rxd->read.hdr_addr = 0;
154 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
164 /* Free all mbufs for descriptors in rx queue */
166 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
170 if (!rxq || !rxq->sw_ring) {
171 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
175 for (i = 0; i < rxq->nb_rx_desc; i++) {
176 if (rxq->sw_ring[i].mbuf) {
177 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
178 rxq->sw_ring[i].mbuf = NULL;
181 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
182 if (rxq->rx_nb_avail == 0)
184 for (i = 0; i < rxq->rx_nb_avail; i++) {
185 struct rte_mbuf *mbuf;
187 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
188 rte_pktmbuf_free_seg(mbuf);
190 rxq->rx_nb_avail = 0;
191 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
195 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
197 rxq->rx_rel_mbufs(rxq);
200 /* turn on or off rx queue
201 * @q_idx: queue index in pf scope
202 * @on: turn on or off the queue
205 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
210 /* QRX_CTRL = QRX_ENA */
211 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
214 if (reg & QRX_CTRL_QENA_STAT_M)
215 return 0; /* Already on, skip */
216 reg |= QRX_CTRL_QENA_REQ_M;
218 if (!(reg & QRX_CTRL_QENA_STAT_M))
219 return 0; /* Already off, skip */
220 reg &= ~QRX_CTRL_QENA_REQ_M;
223 /* Write the register */
224 ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
225 /* Check the result. It is said that QENA_STAT
226 * follows the QENA_REQ not more than 10 use.
227 * TODO: need to change the wait counter later
229 for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
230 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
231 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
233 if ((reg & QRX_CTRL_QENA_REQ_M) &&
234 (reg & QRX_CTRL_QENA_STAT_M))
237 if (!(reg & QRX_CTRL_QENA_REQ_M) &&
238 !(reg & QRX_CTRL_QENA_STAT_M))
243 /* Check if it is timeout */
244 if (j >= ICE_CHK_Q_ENA_COUNT) {
245 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
246 (on ? "enable" : "disable"), q_idx);
254 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
255 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
257 ice_check_rx_burst_bulk_alloc_preconditions
258 (__rte_unused struct ice_rx_queue *rxq)
263 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
264 if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
265 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
266 "rxq->rx_free_thresh=%d, "
267 "ICE_RX_MAX_BURST=%d",
268 rxq->rx_free_thresh, ICE_RX_MAX_BURST);
270 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
271 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
272 "rxq->rx_free_thresh=%d, "
273 "rxq->nb_rx_desc=%d",
274 rxq->rx_free_thresh, rxq->nb_rx_desc);
276 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
277 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
278 "rxq->nb_rx_desc=%d, "
279 "rxq->rx_free_thresh=%d",
280 rxq->nb_rx_desc, rxq->rx_free_thresh);
290 /* reset fields in ice_rx_queue back to default */
292 ice_reset_rx_queue(struct ice_rx_queue *rxq)
298 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
302 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
303 if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
304 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
306 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
307 len = rxq->nb_rx_desc;
309 for (i = 0; i < len * sizeof(union ice_rx_desc); i++)
310 ((volatile char *)rxq->rx_ring)[i] = 0;
312 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
313 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
314 for (i = 0; i < ICE_RX_MAX_BURST; ++i)
315 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
317 rxq->rx_nb_avail = 0;
318 rxq->rx_next_avail = 0;
319 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
320 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
324 rxq->pkt_first_seg = NULL;
325 rxq->pkt_last_seg = NULL;
327 rxq->rxrearm_start = 0;
332 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
334 struct ice_rx_queue *rxq;
336 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
338 PMD_INIT_FUNC_TRACE();
340 if (rx_queue_id >= dev->data->nb_rx_queues) {
341 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
342 rx_queue_id, dev->data->nb_rx_queues);
346 rxq = dev->data->rx_queues[rx_queue_id];
347 if (!rxq || !rxq->q_set) {
348 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
353 err = ice_program_hw_rx_queue(rxq);
355 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
360 err = ice_alloc_rx_queue_mbufs(rxq);
362 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
368 /* Init the RX tail register. */
369 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
371 err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
373 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
376 ice_rx_queue_release_mbufs(rxq);
377 ice_reset_rx_queue(rxq);
381 dev->data->rx_queue_state[rx_queue_id] =
382 RTE_ETH_QUEUE_STATE_STARTED;
388 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
390 struct ice_rx_queue *rxq;
392 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
394 if (rx_queue_id < dev->data->nb_rx_queues) {
395 rxq = dev->data->rx_queues[rx_queue_id];
397 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
399 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
403 ice_rx_queue_release_mbufs(rxq);
404 ice_reset_rx_queue(rxq);
405 dev->data->rx_queue_state[rx_queue_id] =
406 RTE_ETH_QUEUE_STATE_STOPPED;
413 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
415 struct ice_tx_queue *txq;
419 struct ice_aqc_add_tx_qgrp txq_elem;
420 struct ice_tlan_ctx tx_ctx;
422 PMD_INIT_FUNC_TRACE();
424 if (tx_queue_id >= dev->data->nb_tx_queues) {
425 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
426 tx_queue_id, dev->data->nb_tx_queues);
430 txq = dev->data->tx_queues[tx_queue_id];
431 if (!txq || !txq->q_set) {
432 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
438 hw = ICE_VSI_TO_HW(vsi);
440 memset(&txq_elem, 0, sizeof(txq_elem));
441 memset(&tx_ctx, 0, sizeof(tx_ctx));
442 txq_elem.num_txqs = 1;
443 txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
445 tx_ctx.base = txq->tx_ring_phys_addr / ICE_QUEUE_BASE_ADDR_UNIT;
446 tx_ctx.qlen = txq->nb_tx_desc;
447 tx_ctx.pf_num = hw->pf_id;
448 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
449 tx_ctx.src_vsi = vsi->vsi_id;
450 tx_ctx.port_num = hw->port_info->lport;
451 tx_ctx.tso_ena = 1; /* tso enable */
452 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
453 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
455 ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
458 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
460 /* Init the Tx tail register*/
461 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
463 /* Fix me, we assume TC always 0 here */
464 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
465 &txq_elem, sizeof(txq_elem), NULL);
467 PMD_DRV_LOG(ERR, "Failed to add lan txq");
470 /* store the schedule node id */
471 txq->q_teid = txq_elem.txqs[0].q_teid;
473 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
477 /* Free all mbufs for descriptors in tx queue */
479 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
483 if (!txq || !txq->sw_ring) {
484 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
488 for (i = 0; i < txq->nb_tx_desc; i++) {
489 if (txq->sw_ring[i].mbuf) {
490 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
491 txq->sw_ring[i].mbuf = NULL;
496 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
498 txq->tx_rel_mbufs(txq);
502 ice_reset_tx_queue(struct ice_tx_queue *txq)
504 struct ice_tx_entry *txe;
505 uint16_t i, prev, size;
508 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
513 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
514 for (i = 0; i < size; i++)
515 ((volatile char *)txq->tx_ring)[i] = 0;
517 prev = (uint16_t)(txq->nb_tx_desc - 1);
518 for (i = 0; i < txq->nb_tx_desc; i++) {
519 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
521 txd->cmd_type_offset_bsz =
522 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
525 txe[prev].next_id = i;
529 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
530 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
535 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
536 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
540 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
542 struct ice_tx_queue *txq;
543 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
544 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
545 struct ice_vsi *vsi = pf->main_vsi;
546 enum ice_status status;
549 uint16_t q_handle = tx_queue_id;
551 if (tx_queue_id >= dev->data->nb_tx_queues) {
552 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
553 tx_queue_id, dev->data->nb_tx_queues);
557 txq = dev->data->tx_queues[tx_queue_id];
559 PMD_DRV_LOG(ERR, "TX queue %u is not available",
564 q_ids[0] = txq->reg_idx;
565 q_teids[0] = txq->q_teid;
567 /* Fix me, we assume TC always 0 here */
568 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
569 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
570 if (status != ICE_SUCCESS) {
571 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
575 ice_tx_queue_release_mbufs(txq);
576 ice_reset_tx_queue(txq);
577 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
583 ice_rx_queue_setup(struct rte_eth_dev *dev,
586 unsigned int socket_id,
587 const struct rte_eth_rxconf *rx_conf,
588 struct rte_mempool *mp)
590 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
591 struct ice_adapter *ad =
592 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
593 struct ice_vsi *vsi = pf->main_vsi;
594 struct ice_rx_queue *rxq;
595 const struct rte_memzone *rz;
598 int use_def_burst_func = 1;
600 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
601 nb_desc > ICE_MAX_RING_DESC ||
602 nb_desc < ICE_MIN_RING_DESC) {
603 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
608 /* Free memory if needed */
609 if (dev->data->rx_queues[queue_idx]) {
610 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
611 dev->data->rx_queues[queue_idx] = NULL;
614 /* Allocate the rx queue data structure */
615 rxq = rte_zmalloc_socket(NULL,
616 sizeof(struct ice_rx_queue),
620 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
621 "rx queue data structure");
625 rxq->nb_rx_desc = nb_desc;
626 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
627 rxq->queue_id = queue_idx;
629 rxq->reg_idx = vsi->base_queue + queue_idx;
630 rxq->port_id = dev->data->port_id;
631 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
632 rxq->crc_len = RTE_ETHER_CRC_LEN;
636 rxq->drop_en = rx_conf->rx_drop_en;
638 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
640 /* Allocate the maximun number of RX ring hardware descriptor. */
641 len = ICE_MAX_RING_DESC;
643 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
645 * Allocating a little more memory because vectorized/bulk_alloc Rx
646 * functions doesn't check boundaries each time.
648 len += ICE_RX_MAX_BURST;
651 /* Allocate the maximum number of RX ring hardware descriptor. */
652 ring_size = sizeof(union ice_rx_desc) * len;
653 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
654 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
655 ring_size, ICE_RING_BASE_ALIGN,
658 ice_rx_queue_release(rxq);
659 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
663 /* Zero all the descriptors in the ring. */
664 memset(rz->addr, 0, ring_size);
666 rxq->rx_ring_phys_addr = rz->phys_addr;
667 rxq->rx_ring = (union ice_rx_desc *)rz->addr;
669 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
670 len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
675 /* Allocate the software ring. */
676 rxq->sw_ring = rte_zmalloc_socket(NULL,
677 sizeof(struct ice_rx_entry) * len,
681 ice_rx_queue_release(rxq);
682 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
686 ice_reset_rx_queue(rxq);
688 dev->data->rx_queues[queue_idx] = rxq;
689 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
691 use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
693 if (!use_def_burst_func) {
694 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
695 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
696 "satisfied. Rx Burst Bulk Alloc function will be "
697 "used on port=%d, queue=%d.",
698 rxq->port_id, rxq->queue_id);
699 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
701 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
702 "not satisfied, Scattered Rx is requested, "
703 "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
704 "not enabled on port=%d, queue=%d.",
705 rxq->port_id, rxq->queue_id);
706 ad->rx_bulk_alloc_allowed = false;
713 ice_rx_queue_release(void *rxq)
715 struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
718 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
722 ice_rx_queue_release_mbufs(q);
723 rte_free(q->sw_ring);
728 ice_tx_queue_setup(struct rte_eth_dev *dev,
731 unsigned int socket_id,
732 const struct rte_eth_txconf *tx_conf)
734 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
735 struct ice_vsi *vsi = pf->main_vsi;
736 struct ice_tx_queue *txq;
737 const struct rte_memzone *tz;
739 uint16_t tx_rs_thresh, tx_free_thresh;
742 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
744 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
745 nb_desc > ICE_MAX_RING_DESC ||
746 nb_desc < ICE_MIN_RING_DESC) {
747 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
753 * The following two parameters control the setting of the RS bit on
754 * transmit descriptors. TX descriptors will have their RS bit set
755 * after txq->tx_rs_thresh descriptors have been used. The TX
756 * descriptor ring will be cleaned after txq->tx_free_thresh
757 * descriptors are used or if the number of descriptors required to
758 * transmit a packet is greater than the number of free TX descriptors.
760 * The following constraints must be satisfied:
761 * - tx_rs_thresh must be greater than 0.
762 * - tx_rs_thresh must be less than the size of the ring minus 2.
763 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
764 * - tx_rs_thresh must be a divisor of the ring size.
765 * - tx_free_thresh must be greater than 0.
766 * - tx_free_thresh must be less than the size of the ring minus 3.
767 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
769 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
770 * race condition, hence the maximum threshold constraints. When set
771 * to zero use default values.
773 tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
774 tx_conf->tx_free_thresh :
775 ICE_DEFAULT_TX_FREE_THRESH);
776 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
778 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
779 nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
780 if (tx_conf->tx_rs_thresh)
781 tx_rs_thresh = tx_conf->tx_rs_thresh;
782 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
783 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
784 "exceed nb_desc. (tx_rs_thresh=%u "
785 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
786 (unsigned int)tx_rs_thresh,
787 (unsigned int)tx_free_thresh,
788 (unsigned int)nb_desc,
789 (int)dev->data->port_id,
793 if (tx_rs_thresh >= (nb_desc - 2)) {
794 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
795 "number of TX descriptors minus 2. "
796 "(tx_rs_thresh=%u port=%d queue=%d)",
797 (unsigned int)tx_rs_thresh,
798 (int)dev->data->port_id,
802 if (tx_free_thresh >= (nb_desc - 3)) {
803 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
804 "tx_free_thresh must be less than the "
805 "number of TX descriptors minus 3. "
806 "(tx_free_thresh=%u port=%d queue=%d)",
807 (unsigned int)tx_free_thresh,
808 (int)dev->data->port_id,
812 if (tx_rs_thresh > tx_free_thresh) {
813 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
814 "equal to tx_free_thresh. (tx_free_thresh=%u"
815 " tx_rs_thresh=%u port=%d queue=%d)",
816 (unsigned int)tx_free_thresh,
817 (unsigned int)tx_rs_thresh,
818 (int)dev->data->port_id,
822 if ((nb_desc % tx_rs_thresh) != 0) {
823 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
824 "number of TX descriptors. (tx_rs_thresh=%u"
825 " port=%d queue=%d)",
826 (unsigned int)tx_rs_thresh,
827 (int)dev->data->port_id,
831 if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
832 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
833 "tx_rs_thresh is greater than 1. "
834 "(tx_rs_thresh=%u port=%d queue=%d)",
835 (unsigned int)tx_rs_thresh,
836 (int)dev->data->port_id,
841 /* Free memory if needed. */
842 if (dev->data->tx_queues[queue_idx]) {
843 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
844 dev->data->tx_queues[queue_idx] = NULL;
847 /* Allocate the TX queue data structure. */
848 txq = rte_zmalloc_socket(NULL,
849 sizeof(struct ice_tx_queue),
853 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
854 "tx queue structure");
858 /* Allocate TX hardware ring descriptors. */
859 ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
860 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
861 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
862 ring_size, ICE_RING_BASE_ALIGN,
865 ice_tx_queue_release(txq);
866 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
870 txq->nb_tx_desc = nb_desc;
871 txq->tx_rs_thresh = tx_rs_thresh;
872 txq->tx_free_thresh = tx_free_thresh;
873 txq->pthresh = tx_conf->tx_thresh.pthresh;
874 txq->hthresh = tx_conf->tx_thresh.hthresh;
875 txq->wthresh = tx_conf->tx_thresh.wthresh;
876 txq->queue_id = queue_idx;
878 txq->reg_idx = vsi->base_queue + queue_idx;
879 txq->port_id = dev->data->port_id;
880 txq->offloads = offloads;
882 txq->tx_deferred_start = tx_conf->tx_deferred_start;
884 txq->tx_ring_phys_addr = tz->phys_addr;
885 txq->tx_ring = (struct ice_tx_desc *)tz->addr;
887 /* Allocate software ring */
889 rte_zmalloc_socket(NULL,
890 sizeof(struct ice_tx_entry) * nb_desc,
894 ice_tx_queue_release(txq);
895 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
899 ice_reset_tx_queue(txq);
901 dev->data->tx_queues[queue_idx] = txq;
902 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
903 ice_set_tx_function_flag(dev, txq);
909 ice_tx_queue_release(void *txq)
911 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
914 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
918 ice_tx_queue_release_mbufs(q);
919 rte_free(q->sw_ring);
924 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
925 struct rte_eth_rxq_info *qinfo)
927 struct ice_rx_queue *rxq;
929 rxq = dev->data->rx_queues[queue_id];
932 qinfo->scattered_rx = dev->data->scattered_rx;
933 qinfo->nb_desc = rxq->nb_rx_desc;
935 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
936 qinfo->conf.rx_drop_en = rxq->drop_en;
937 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
941 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
942 struct rte_eth_txq_info *qinfo)
944 struct ice_tx_queue *txq;
946 txq = dev->data->tx_queues[queue_id];
948 qinfo->nb_desc = txq->nb_tx_desc;
950 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
951 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
952 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
954 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
955 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
956 qinfo->conf.offloads = txq->offloads;
957 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
961 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
963 #define ICE_RXQ_SCAN_INTERVAL 4
964 volatile union ice_rx_desc *rxdp;
965 struct ice_rx_queue *rxq;
968 rxq = dev->data->rx_queues[rx_queue_id];
969 rxdp = &rxq->rx_ring[rxq->rx_tail];
970 while ((desc < rxq->nb_rx_desc) &&
971 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
972 ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S) &
973 (1 << ICE_RX_DESC_STATUS_DD_S)) {
975 * Check the DD bit of a rx descriptor of each 4 in a group,
976 * to avoid checking too frequently and downgrading performance
979 desc += ICE_RXQ_SCAN_INTERVAL;
980 rxdp += ICE_RXQ_SCAN_INTERVAL;
981 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
982 rxdp = &(rxq->rx_ring[rxq->rx_tail +
983 desc - rxq->nb_rx_desc]);
989 /* Translate the rx descriptor status to pkt flags */
990 static inline uint64_t
991 ice_rxd_status_to_pkt_flags(uint64_t qword)
995 /* Check if RSS_HASH */
996 flags = (((qword >> ICE_RX_DESC_STATUS_FLTSTAT_S) &
997 ICE_RX_DESC_FLTSTAT_RSS_HASH) ==
998 ICE_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
1003 /* Rx L3/L4 checksum */
1004 static inline uint64_t
1005 ice_rxd_error_to_pkt_flags(uint64_t qword)
1008 uint64_t error_bits = (qword >> ICE_RXD_QW1_ERROR_S);
1010 if (likely((error_bits & ICE_RX_ERR_BITS) == 0)) {
1011 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1015 if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_IPE_S)))
1016 flags |= PKT_RX_IP_CKSUM_BAD;
1018 flags |= PKT_RX_IP_CKSUM_GOOD;
1020 if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_L4E_S)))
1021 flags |= PKT_RX_L4_CKSUM_BAD;
1023 flags |= PKT_RX_L4_CKSUM_GOOD;
1025 if (unlikely(error_bits & (1 << ICE_RX_DESC_ERROR_EIPE_S)))
1026 flags |= PKT_RX_EIP_CKSUM_BAD;
1032 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_desc *rxdp)
1034 if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1035 (1 << ICE_RX_DESC_STATUS_L2TAG1P_S)) {
1036 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1038 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
1039 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1040 rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
1045 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1046 if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
1047 (1 << ICE_RX_DESC_EXT_STATUS_L2TAG2P_S)) {
1048 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1049 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1050 mb->vlan_tci_outer = mb->vlan_tci;
1051 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
1052 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1053 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
1054 rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
1056 mb->vlan_tci_outer = 0;
1059 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1060 mb->vlan_tci, mb->vlan_tci_outer);
1063 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1064 #define ICE_LOOK_AHEAD 8
1065 #if (ICE_LOOK_AHEAD != 8)
1066 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1069 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1071 volatile union ice_rx_desc *rxdp;
1072 struct ice_rx_entry *rxep;
1073 struct rte_mbuf *mb;
1077 int32_t s[ICE_LOOK_AHEAD], nb_dd;
1078 int32_t i, j, nb_rx = 0;
1079 uint64_t pkt_flags = 0;
1080 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1082 rxdp = &rxq->rx_ring[rxq->rx_tail];
1083 rxep = &rxq->sw_ring[rxq->rx_tail];
1085 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1086 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >> ICE_RXD_QW1_STATUS_S;
1088 /* Make sure there is at least 1 packet to receive */
1089 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1093 * Scan LOOK_AHEAD descriptors at a time to determine which
1094 * descriptors reference packets that are ready to be received.
1096 for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1097 rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1098 /* Read desc statuses backwards to avoid race condition */
1099 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--) {
1100 qword1 = rte_le_to_cpu_64(
1101 rxdp[j].wb.qword1.status_error_len);
1102 s[j] = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1103 ICE_RXD_QW1_STATUS_S;
1108 /* Compute how many status bits were set */
1109 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1110 nb_dd += s[j] & (1 << ICE_RX_DESC_STATUS_DD_S);
1114 /* Translate descriptor info to mbuf parameters */
1115 for (j = 0; j < nb_dd; j++) {
1117 qword1 = rte_le_to_cpu_64(
1118 rxdp[j].wb.qword1.status_error_len);
1119 pkt_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1120 ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1121 mb->data_len = pkt_len;
1122 mb->pkt_len = pkt_len;
1124 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1125 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1126 if (pkt_flags & PKT_RX_RSS_HASH)
1129 rxdp[j].wb.qword0.hi_dword.rss);
1130 mb->packet_type = ptype_tbl[(uint8_t)(
1132 ICE_RXD_QW1_PTYPE_M) >>
1133 ICE_RXD_QW1_PTYPE_S)];
1134 ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1136 mb->ol_flags |= pkt_flags;
1139 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1140 rxq->rx_stage[i + j] = rxep[j].mbuf;
1142 if (nb_dd != ICE_LOOK_AHEAD)
1146 /* Clear software ring entries */
1147 for (i = 0; i < nb_rx; i++)
1148 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1150 PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1151 "port_id=%u, queue_id=%u, nb_rx=%d",
1152 rxq->port_id, rxq->queue_id, nb_rx);
1157 static inline uint16_t
1158 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1159 struct rte_mbuf **rx_pkts,
1163 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1165 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1167 for (i = 0; i < nb_pkts; i++)
1168 rx_pkts[i] = stage[i];
1170 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1171 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1177 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1179 volatile union ice_rx_desc *rxdp;
1180 struct ice_rx_entry *rxep;
1181 struct rte_mbuf *mb;
1182 uint16_t alloc_idx, i;
1186 /* Allocate buffers in bulk */
1187 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1188 (rxq->rx_free_thresh - 1));
1189 rxep = &rxq->sw_ring[alloc_idx];
1190 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1191 rxq->rx_free_thresh);
1192 if (unlikely(diag != 0)) {
1193 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1197 rxdp = &rxq->rx_ring[alloc_idx];
1198 for (i = 0; i < rxq->rx_free_thresh; i++) {
1199 if (likely(i < (rxq->rx_free_thresh - 1)))
1200 /* Prefetch next mbuf */
1201 rte_prefetch0(rxep[i + 1].mbuf);
1204 rte_mbuf_refcnt_set(mb, 1);
1206 mb->data_off = RTE_PKTMBUF_HEADROOM;
1208 mb->port = rxq->port_id;
1209 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1210 rxdp[i].read.hdr_addr = 0;
1211 rxdp[i].read.pkt_addr = dma_addr;
1214 /* Update rx tail regsiter */
1216 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1218 rxq->rx_free_trigger =
1219 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1220 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1221 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1226 static inline uint16_t
1227 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1229 struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1231 struct rte_eth_dev *dev;
1236 if (rxq->rx_nb_avail)
1237 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1239 nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1240 rxq->rx_next_avail = 0;
1241 rxq->rx_nb_avail = nb_rx;
1242 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1244 if (rxq->rx_tail > rxq->rx_free_trigger) {
1245 if (ice_rx_alloc_bufs(rxq) != 0) {
1248 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1249 dev->data->rx_mbuf_alloc_failed +=
1250 rxq->rx_free_thresh;
1251 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1252 "port_id=%u, queue_id=%u",
1253 rxq->port_id, rxq->queue_id);
1254 rxq->rx_nb_avail = 0;
1255 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1256 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1257 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1263 if (rxq->rx_tail >= rxq->nb_rx_desc)
1266 if (rxq->rx_nb_avail)
1267 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1273 ice_recv_pkts_bulk_alloc(void *rx_queue,
1274 struct rte_mbuf **rx_pkts,
1281 if (unlikely(nb_pkts == 0))
1284 if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1285 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1288 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1289 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1290 nb_rx = (uint16_t)(nb_rx + count);
1291 nb_pkts = (uint16_t)(nb_pkts - count);
1300 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1301 struct rte_mbuf __rte_unused **rx_pkts,
1302 uint16_t __rte_unused nb_pkts)
1306 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1309 ice_recv_scattered_pkts(void *rx_queue,
1310 struct rte_mbuf **rx_pkts,
1313 struct ice_rx_queue *rxq = rx_queue;
1314 volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1315 volatile union ice_rx_desc *rxdp;
1316 union ice_rx_desc rxd;
1317 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1318 struct ice_rx_entry *rxe;
1319 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1320 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1321 struct rte_mbuf *nmb; /* new allocated mbuf */
1322 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1323 uint16_t rx_id = rxq->rx_tail;
1325 uint16_t nb_hold = 0;
1326 uint16_t rx_packet_len;
1330 uint64_t pkt_flags = 0;
1331 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1332 struct rte_eth_dev *dev;
1334 while (nb_rx < nb_pkts) {
1335 rxdp = &rx_ring[rx_id];
1336 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1337 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1338 ICE_RXD_QW1_STATUS_S;
1340 /* Check the DD bit first */
1341 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1345 nmb = rte_mbuf_raw_alloc(rxq->mp);
1346 if (unlikely(!nmb)) {
1347 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1348 dev->data->rx_mbuf_alloc_failed++;
1351 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1354 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1356 if (unlikely(rx_id == rxq->nb_rx_desc))
1359 /* Prefetch next mbuf */
1360 rte_prefetch0(sw_ring[rx_id].mbuf);
1363 * When next RX descriptor is on a cache line boundary,
1364 * prefetch the next 4 RX descriptors and next 8 pointers
1367 if ((rx_id & 0x3) == 0) {
1368 rte_prefetch0(&rx_ring[rx_id]);
1369 rte_prefetch0(&sw_ring[rx_id]);
1375 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1377 /* Set data buffer address and data length of the mbuf */
1378 rxdp->read.hdr_addr = 0;
1379 rxdp->read.pkt_addr = dma_addr;
1380 rx_packet_len = (qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1381 ICE_RXD_QW1_LEN_PBUF_S;
1382 rxm->data_len = rx_packet_len;
1383 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1384 ice_rxd_to_vlan_tci(rxm, rxdp);
1385 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1386 ICE_RXD_QW1_PTYPE_M) >>
1387 ICE_RXD_QW1_PTYPE_S)];
1390 * If this is the first buffer of the received packet, set the
1391 * pointer to the first mbuf of the packet and initialize its
1392 * context. Otherwise, update the total length and the number
1393 * of segments of the current scattered packet, and update the
1394 * pointer to the last mbuf of the current packet.
1398 first_seg->nb_segs = 1;
1399 first_seg->pkt_len = rx_packet_len;
1401 first_seg->pkt_len =
1402 (uint16_t)(first_seg->pkt_len +
1404 first_seg->nb_segs++;
1405 last_seg->next = rxm;
1409 * If this is not the last buffer of the received packet,
1410 * update the pointer to the last mbuf of the current scattered
1411 * packet and continue to parse the RX ring.
1413 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_EOF_S))) {
1419 * This is the last buffer of the received packet. If the CRC
1420 * is not stripped by the hardware:
1421 * - Subtract the CRC length from the total packet length.
1422 * - If the last buffer only contains the whole CRC or a part
1423 * of it, free the mbuf associated to the last buffer. If part
1424 * of the CRC is also contained in the previous mbuf, subtract
1425 * the length of that CRC part from the data length of the
1429 if (unlikely(rxq->crc_len > 0)) {
1430 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1431 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1432 rte_pktmbuf_free_seg(rxm);
1433 first_seg->nb_segs--;
1434 last_seg->data_len =
1435 (uint16_t)(last_seg->data_len -
1436 (RTE_ETHER_CRC_LEN - rx_packet_len));
1437 last_seg->next = NULL;
1439 rxm->data_len = (uint16_t)(rx_packet_len -
1443 first_seg->port = rxq->port_id;
1444 first_seg->ol_flags = 0;
1446 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1447 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1448 if (pkt_flags & PKT_RX_RSS_HASH)
1449 first_seg->hash.rss =
1450 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1452 first_seg->ol_flags |= pkt_flags;
1453 /* Prefetch data of first segment, if configured to do so. */
1454 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1455 first_seg->data_off));
1456 rx_pkts[nb_rx++] = first_seg;
1460 /* Record index of the next RX descriptor to probe. */
1461 rxq->rx_tail = rx_id;
1462 rxq->pkt_first_seg = first_seg;
1463 rxq->pkt_last_seg = last_seg;
1466 * If the number of free RX descriptors is greater than the RX free
1467 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1468 * register. Update the RDT with the value of the last processed RX
1469 * descriptor minus 1, to guarantee that the RDT register is never
1470 * equal to the RDH register, which creates a "full" ring situtation
1471 * from the hardware point of view.
1473 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1474 if (nb_hold > rxq->rx_free_thresh) {
1475 rx_id = (uint16_t)(rx_id == 0 ?
1476 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1477 /* write TAIL register */
1478 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1481 rxq->nb_rx_hold = nb_hold;
1483 /* return received packet in the burst */
1488 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1490 static const uint32_t ptypes[] = {
1491 /* refers to ice_get_default_pkt_type() */
1493 RTE_PTYPE_L2_ETHER_LLDP,
1494 RTE_PTYPE_L2_ETHER_ARP,
1495 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1496 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1499 RTE_PTYPE_L4_NONFRAG,
1503 RTE_PTYPE_TUNNEL_GRENAT,
1504 RTE_PTYPE_TUNNEL_IP,
1505 RTE_PTYPE_INNER_L2_ETHER,
1506 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1507 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1508 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1509 RTE_PTYPE_INNER_L4_FRAG,
1510 RTE_PTYPE_INNER_L4_ICMP,
1511 RTE_PTYPE_INNER_L4_NONFRAG,
1512 RTE_PTYPE_INNER_L4_SCTP,
1513 RTE_PTYPE_INNER_L4_TCP,
1514 RTE_PTYPE_INNER_L4_UDP,
1515 RTE_PTYPE_TUNNEL_GTPC,
1516 RTE_PTYPE_TUNNEL_GTPU,
1520 if (dev->rx_pkt_burst == ice_recv_pkts ||
1521 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1522 dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1524 dev->rx_pkt_burst == ice_recv_scattered_pkts)
1528 if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1529 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1530 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1531 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1539 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1541 struct ice_rx_queue *rxq = rx_queue;
1542 volatile uint64_t *status;
1546 if (unlikely(offset >= rxq->nb_rx_desc))
1549 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1550 return RTE_ETH_RX_DESC_UNAVAIL;
1552 desc = rxq->rx_tail + offset;
1553 if (desc >= rxq->nb_rx_desc)
1554 desc -= rxq->nb_rx_desc;
1556 status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1557 mask = rte_cpu_to_le_64((1ULL << ICE_RX_DESC_STATUS_DD_S) <<
1558 ICE_RXD_QW1_STATUS_S);
1560 return RTE_ETH_RX_DESC_DONE;
1562 return RTE_ETH_RX_DESC_AVAIL;
1566 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1568 struct ice_tx_queue *txq = tx_queue;
1569 volatile uint64_t *status;
1570 uint64_t mask, expect;
1573 if (unlikely(offset >= txq->nb_tx_desc))
1576 desc = txq->tx_tail + offset;
1577 /* go to next desc that has the RS bit */
1578 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1580 if (desc >= txq->nb_tx_desc) {
1581 desc -= txq->nb_tx_desc;
1582 if (desc >= txq->nb_tx_desc)
1583 desc -= txq->nb_tx_desc;
1586 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1587 mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1588 expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1589 ICE_TXD_QW1_DTYPE_S);
1590 if ((*status & mask) == expect)
1591 return RTE_ETH_TX_DESC_DONE;
1593 return RTE_ETH_TX_DESC_FULL;
1597 ice_clear_queues(struct rte_eth_dev *dev)
1601 PMD_INIT_FUNC_TRACE();
1603 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1604 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1605 ice_reset_tx_queue(dev->data->tx_queues[i]);
1608 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1609 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1610 ice_reset_rx_queue(dev->data->rx_queues[i]);
1615 ice_free_queues(struct rte_eth_dev *dev)
1619 PMD_INIT_FUNC_TRACE();
1621 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1622 if (!dev->data->rx_queues[i])
1624 ice_rx_queue_release(dev->data->rx_queues[i]);
1625 dev->data->rx_queues[i] = NULL;
1627 dev->data->nb_rx_queues = 0;
1629 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1630 if (!dev->data->tx_queues[i])
1632 ice_tx_queue_release(dev->data->tx_queues[i]);
1633 dev->data->tx_queues[i] = NULL;
1635 dev->data->nb_tx_queues = 0;
1639 ice_recv_pkts(void *rx_queue,
1640 struct rte_mbuf **rx_pkts,
1643 struct ice_rx_queue *rxq = rx_queue;
1644 volatile union ice_rx_desc *rx_ring = rxq->rx_ring;
1645 volatile union ice_rx_desc *rxdp;
1646 union ice_rx_desc rxd;
1647 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1648 struct ice_rx_entry *rxe;
1649 struct rte_mbuf *nmb; /* new allocated mbuf */
1650 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1651 uint16_t rx_id = rxq->rx_tail;
1653 uint16_t nb_hold = 0;
1654 uint16_t rx_packet_len;
1658 uint64_t pkt_flags = 0;
1659 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1660 struct rte_eth_dev *dev;
1662 while (nb_rx < nb_pkts) {
1663 rxdp = &rx_ring[rx_id];
1664 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1665 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M) >>
1666 ICE_RXD_QW1_STATUS_S;
1668 /* Check the DD bit first */
1669 if (!(rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)))
1673 nmb = rte_mbuf_raw_alloc(rxq->mp);
1674 if (unlikely(!nmb)) {
1675 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1676 dev->data->rx_mbuf_alloc_failed++;
1679 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1682 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1684 if (unlikely(rx_id == rxq->nb_rx_desc))
1689 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1692 * fill the read format of descriptor with physic address in
1693 * new allocated mbuf: nmb
1695 rxdp->read.hdr_addr = 0;
1696 rxdp->read.pkt_addr = dma_addr;
1698 /* calculate rx_packet_len of the received pkt */
1699 rx_packet_len = ((qword1 & ICE_RXD_QW1_LEN_PBUF_M) >>
1700 ICE_RXD_QW1_LEN_PBUF_S) - rxq->crc_len;
1702 /* fill old mbuf with received descriptor: rxd */
1703 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1704 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1707 rxm->pkt_len = rx_packet_len;
1708 rxm->data_len = rx_packet_len;
1709 rxm->port = rxq->port_id;
1710 ice_rxd_to_vlan_tci(rxm, rxdp);
1711 rxm->packet_type = ptype_tbl[(uint8_t)((qword1 &
1712 ICE_RXD_QW1_PTYPE_M) >>
1713 ICE_RXD_QW1_PTYPE_S)];
1714 pkt_flags = ice_rxd_status_to_pkt_flags(qword1);
1715 pkt_flags |= ice_rxd_error_to_pkt_flags(qword1);
1716 if (pkt_flags & PKT_RX_RSS_HASH)
1718 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1719 rxm->ol_flags |= pkt_flags;
1720 /* copy old mbuf to rx_pkts */
1721 rx_pkts[nb_rx++] = rxm;
1723 rxq->rx_tail = rx_id;
1725 * If the number of free RX descriptors is greater than the RX free
1726 * threshold of the queue, advance the receive tail register of queue.
1727 * Update that register with the value of the last processed RX
1728 * descriptor minus 1.
1730 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1731 if (nb_hold > rxq->rx_free_thresh) {
1732 rx_id = (uint16_t)(rx_id == 0 ?
1733 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1734 /* write TAIL register */
1735 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1738 rxq->nb_rx_hold = nb_hold;
1740 /* return received packet in the burst */
1745 ice_txd_enable_checksum(uint64_t ol_flags,
1747 uint32_t *td_offset,
1748 union ice_tx_offload tx_offload)
1750 /* L2 length must be set. */
1751 *td_offset |= (tx_offload.l2_len >> 1) <<
1752 ICE_TX_DESC_LEN_MACLEN_S;
1754 /* Enable L3 checksum offloads */
1755 if (ol_flags & PKT_TX_IP_CKSUM) {
1756 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1757 *td_offset |= (tx_offload.l3_len >> 2) <<
1758 ICE_TX_DESC_LEN_IPLEN_S;
1759 } else if (ol_flags & PKT_TX_IPV4) {
1760 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1761 *td_offset |= (tx_offload.l3_len >> 2) <<
1762 ICE_TX_DESC_LEN_IPLEN_S;
1763 } else if (ol_flags & PKT_TX_IPV6) {
1764 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1765 *td_offset |= (tx_offload.l3_len >> 2) <<
1766 ICE_TX_DESC_LEN_IPLEN_S;
1769 if (ol_flags & PKT_TX_TCP_SEG) {
1770 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1771 *td_offset |= (tx_offload.l4_len >> 2) <<
1772 ICE_TX_DESC_LEN_L4_LEN_S;
1776 /* Enable L4 checksum offloads */
1777 switch (ol_flags & PKT_TX_L4_MASK) {
1778 case PKT_TX_TCP_CKSUM:
1779 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1780 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
1781 ICE_TX_DESC_LEN_L4_LEN_S;
1783 case PKT_TX_SCTP_CKSUM:
1784 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1785 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
1786 ICE_TX_DESC_LEN_L4_LEN_S;
1788 case PKT_TX_UDP_CKSUM:
1789 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1790 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
1791 ICE_TX_DESC_LEN_L4_LEN_S;
1799 ice_xmit_cleanup(struct ice_tx_queue *txq)
1801 struct ice_tx_entry *sw_ring = txq->sw_ring;
1802 volatile struct ice_tx_desc *txd = txq->tx_ring;
1803 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1804 uint16_t nb_tx_desc = txq->nb_tx_desc;
1805 uint16_t desc_to_clean_to;
1806 uint16_t nb_tx_to_clean;
1808 /* Determine the last descriptor needing to be cleaned */
1809 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1810 if (desc_to_clean_to >= nb_tx_desc)
1811 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1813 /* Check to make sure the last descriptor to clean is done */
1814 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1815 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
1816 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
1817 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1818 "(port=%d queue=%d) value=0x%"PRIx64"\n",
1820 txq->port_id, txq->queue_id,
1821 txd[desc_to_clean_to].cmd_type_offset_bsz);
1822 /* Failed to clean any descriptors */
1826 /* Figure out how many descriptors will be cleaned */
1827 if (last_desc_cleaned > desc_to_clean_to)
1828 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1831 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1834 /* The last descriptor to clean is done, so that means all the
1835 * descriptors from the last descriptor that was cleaned
1836 * up to the last descriptor with the RS bit set
1837 * are done. Only reset the threshold descriptor.
1839 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1841 /* Update the txq to reflect the last descriptor that was cleaned */
1842 txq->last_desc_cleaned = desc_to_clean_to;
1843 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1848 /* Construct the tx flags */
1849 static inline uint64_t
1850 ice_build_ctob(uint32_t td_cmd,
1855 return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1856 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
1857 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1858 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
1859 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
1862 /* Check if the context descriptor is needed for TX offloading */
1863 static inline uint16_t
1864 ice_calc_context_desc(uint64_t flags)
1866 static uint64_t mask = PKT_TX_TCP_SEG | PKT_TX_QINQ;
1868 return (flags & mask) ? 1 : 0;
1871 /* set ice TSO context descriptor */
1872 static inline uint64_t
1873 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
1875 uint64_t ctx_desc = 0;
1876 uint32_t cd_cmd, hdr_len, cd_tso_len;
1878 if (!tx_offload.l4_len) {
1879 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1884 * in case of non tunneling packet, the outer_l2_len and
1885 * outer_l3_len must be 0.
1887 hdr_len = tx_offload.outer_l2_len +
1888 tx_offload.outer_l3_len +
1893 cd_cmd = ICE_TX_CTX_DESC_TSO;
1894 cd_tso_len = mbuf->pkt_len - hdr_len;
1895 ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
1896 ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1897 ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
1903 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1905 struct ice_tx_queue *txq;
1906 volatile struct ice_tx_desc *tx_ring;
1907 volatile struct ice_tx_desc *txd;
1908 struct ice_tx_entry *sw_ring;
1909 struct ice_tx_entry *txe, *txn;
1910 struct rte_mbuf *tx_pkt;
1911 struct rte_mbuf *m_seg;
1916 uint32_t td_cmd = 0;
1917 uint32_t td_offset = 0;
1918 uint32_t td_tag = 0;
1920 uint64_t buf_dma_addr;
1922 union ice_tx_offload tx_offload = {0};
1925 sw_ring = txq->sw_ring;
1926 tx_ring = txq->tx_ring;
1927 tx_id = txq->tx_tail;
1928 txe = &sw_ring[tx_id];
1930 /* Check if the descriptor ring needs to be cleaned. */
1931 if (txq->nb_tx_free < txq->tx_free_thresh)
1932 ice_xmit_cleanup(txq);
1934 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1935 tx_pkt = *tx_pkts++;
1938 ol_flags = tx_pkt->ol_flags;
1939 tx_offload.l2_len = tx_pkt->l2_len;
1940 tx_offload.l3_len = tx_pkt->l3_len;
1941 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1942 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1943 tx_offload.l4_len = tx_pkt->l4_len;
1944 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1945 /* Calculate the number of context descriptors needed. */
1946 nb_ctx = ice_calc_context_desc(ol_flags);
1948 /* The number of descriptors that must be allocated for
1949 * a packet equals to the number of the segments of that
1950 * packet plus the number of context descriptor if needed.
1952 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1953 tx_last = (uint16_t)(tx_id + nb_used - 1);
1956 if (tx_last >= txq->nb_tx_desc)
1957 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1959 if (nb_used > txq->nb_tx_free) {
1960 if (ice_xmit_cleanup(txq) != 0) {
1965 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1966 while (nb_used > txq->nb_tx_free) {
1967 if (ice_xmit_cleanup(txq) != 0) {
1976 /* Descriptor based VLAN insertion */
1977 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
1978 td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
1979 td_tag = tx_pkt->vlan_tci;
1982 /* Enable checksum offloading */
1983 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
1984 ice_txd_enable_checksum(ol_flags, &td_cmd,
1985 &td_offset, tx_offload);
1989 /* Setup TX context descriptor if required */
1990 volatile struct ice_tx_ctx_desc *ctx_txd =
1991 (volatile struct ice_tx_ctx_desc *)
1993 uint16_t cd_l2tag2 = 0;
1994 uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
1996 txn = &sw_ring[txe->next_id];
1997 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1999 rte_pktmbuf_free_seg(txe->mbuf);
2003 if (ol_flags & PKT_TX_TCP_SEG)
2004 cd_type_cmd_tso_mss |=
2005 ice_set_tso_ctx(tx_pkt, tx_offload);
2007 /* TX context descriptor based double VLAN insert */
2008 if (ol_flags & PKT_TX_QINQ) {
2009 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2010 cd_type_cmd_tso_mss |=
2011 ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2012 ICE_TXD_CTX_QW1_CMD_S);
2014 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2016 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2018 txe->last_id = tx_last;
2019 tx_id = txe->next_id;
2025 txd = &tx_ring[tx_id];
2026 txn = &sw_ring[txe->next_id];
2029 rte_pktmbuf_free_seg(txe->mbuf);
2032 /* Setup TX Descriptor */
2033 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2034 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2035 txd->cmd_type_offset_bsz =
2036 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2037 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2038 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2039 ((uint64_t)m_seg->data_len <<
2040 ICE_TXD_QW1_TX_BUF_SZ_S) |
2041 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2043 txe->last_id = tx_last;
2044 tx_id = txe->next_id;
2046 m_seg = m_seg->next;
2049 /* fill the last descriptor with End of Packet (EOP) bit */
2050 td_cmd |= ICE_TX_DESC_CMD_EOP;
2051 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2052 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2054 /* set RS bit on the last descriptor of one packet */
2055 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2056 PMD_TX_FREE_LOG(DEBUG,
2057 "Setting RS bit on TXD id="
2058 "%4u (port=%d queue=%d)",
2059 tx_last, txq->port_id, txq->queue_id);
2061 td_cmd |= ICE_TX_DESC_CMD_RS;
2063 /* Update txq RS bit counters */
2064 txq->nb_tx_used = 0;
2066 txd->cmd_type_offset_bsz |=
2067 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2073 /* update Tail register */
2074 ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2075 txq->tx_tail = tx_id;
2080 static inline int __attribute__((always_inline))
2081 ice_tx_free_bufs(struct ice_tx_queue *txq)
2083 struct ice_tx_entry *txep;
2086 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2087 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2088 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2091 txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2093 for (i = 0; i < txq->tx_rs_thresh; i++)
2094 rte_prefetch0((txep + i)->mbuf);
2096 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2097 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2098 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2102 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2103 rte_pktmbuf_free_seg(txep->mbuf);
2108 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2109 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2110 if (txq->tx_next_dd >= txq->nb_tx_desc)
2111 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2113 return txq->tx_rs_thresh;
2116 /* Populate 4 descriptors with data from 4 mbufs */
2118 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2123 for (i = 0; i < 4; i++, txdp++, pkts++) {
2124 dma_addr = rte_mbuf_data_iova(*pkts);
2125 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2126 txdp->cmd_type_offset_bsz =
2127 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2128 (*pkts)->data_len, 0);
2132 /* Populate 1 descriptor with data from 1 mbuf */
2134 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2138 dma_addr = rte_mbuf_data_iova(*pkts);
2139 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2140 txdp->cmd_type_offset_bsz =
2141 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2142 (*pkts)->data_len, 0);
2146 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2149 volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2150 struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2151 const int N_PER_LOOP = 4;
2152 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2153 int mainpart, leftover;
2157 * Process most of the packets in chunks of N pkts. Any
2158 * leftover packets will get processed one at a time.
2160 mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2161 leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2162 for (i = 0; i < mainpart; i += N_PER_LOOP) {
2163 /* Copy N mbuf pointers to the S/W ring */
2164 for (j = 0; j < N_PER_LOOP; ++j)
2165 (txep + i + j)->mbuf = *(pkts + i + j);
2166 tx4(txdp + i, pkts + i);
2169 if (unlikely(leftover > 0)) {
2170 for (i = 0; i < leftover; ++i) {
2171 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2172 tx1(txdp + mainpart + i, pkts + mainpart + i);
2177 static inline uint16_t
2178 tx_xmit_pkts(struct ice_tx_queue *txq,
2179 struct rte_mbuf **tx_pkts,
2182 volatile struct ice_tx_desc *txr = txq->tx_ring;
2186 * Begin scanning the H/W ring for done descriptors when the number
2187 * of available descriptors drops below tx_free_thresh. For each done
2188 * descriptor, free the associated buffer.
2190 if (txq->nb_tx_free < txq->tx_free_thresh)
2191 ice_tx_free_bufs(txq);
2193 /* Use available descriptor only */
2194 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2195 if (unlikely(!nb_pkts))
2198 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2199 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2200 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2201 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2202 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2203 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2205 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2209 /* Fill hardware descriptor ring with mbuf data */
2210 ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2211 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2213 /* Determin if RS bit needs to be set */
2214 if (txq->tx_tail > txq->tx_next_rs) {
2215 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2216 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2219 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2220 if (txq->tx_next_rs >= txq->nb_tx_desc)
2221 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2224 if (txq->tx_tail >= txq->nb_tx_desc)
2227 /* Update the tx tail register */
2229 ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2235 ice_xmit_pkts_simple(void *tx_queue,
2236 struct rte_mbuf **tx_pkts,
2241 if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2242 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2246 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2249 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2250 &tx_pkts[nb_tx], num);
2251 nb_tx = (uint16_t)(nb_tx + ret);
2252 nb_pkts = (uint16_t)(nb_pkts - ret);
2260 void __attribute__((cold))
2261 ice_set_rx_function(struct rte_eth_dev *dev)
2263 PMD_INIT_FUNC_TRACE();
2264 struct ice_adapter *ad =
2265 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2267 struct ice_rx_queue *rxq;
2269 bool use_avx2 = false;
2271 if (!ice_rx_vec_dev_check(dev)) {
2272 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2273 rxq = dev->data->rx_queues[i];
2274 (void)ice_rxq_vec_setup(rxq);
2277 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2278 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2281 if (dev->data->scattered_rx) {
2283 "Using %sVector Scattered Rx (port %d).",
2284 use_avx2 ? "avx2 " : "",
2285 dev->data->port_id);
2286 dev->rx_pkt_burst = use_avx2 ?
2287 ice_recv_scattered_pkts_vec_avx2 :
2288 ice_recv_scattered_pkts_vec;
2290 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2291 use_avx2 ? "avx2 " : "",
2292 dev->data->port_id);
2293 dev->rx_pkt_burst = use_avx2 ?
2294 ice_recv_pkts_vec_avx2 :
2302 if (dev->data->scattered_rx) {
2303 /* Set the non-LRO scattered function */
2305 "Using a Scattered function on port %d.",
2306 dev->data->port_id);
2307 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2308 } else if (ad->rx_bulk_alloc_allowed) {
2310 "Rx Burst Bulk Alloc Preconditions are "
2311 "satisfied. Rx Burst Bulk Alloc function "
2312 "will be used on port %d.",
2313 dev->data->port_id);
2314 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2317 "Rx Burst Bulk Alloc Preconditions are not "
2318 "satisfied, Normal Rx will be used on port %d.",
2319 dev->data->port_id);
2320 dev->rx_pkt_burst = ice_recv_pkts;
2324 void __attribute__((cold))
2325 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
2327 struct ice_adapter *ad =
2328 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2330 /* Use a simple Tx queue if possible (only fast free is allowed) */
2331 ad->tx_simple_allowed =
2333 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
2334 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
2336 if (ad->tx_simple_allowed)
2337 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
2341 "Simple Tx can NOT be enabled on Tx queue %u.",
2345 /*********************************************************************
2349 **********************************************************************/
2350 /* The default values of TSO MSS */
2351 #define ICE_MIN_TSO_MSS 64
2352 #define ICE_MAX_TSO_MSS 9728
2353 #define ICE_MAX_TSO_FRAME_SIZE 262144
2355 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2362 for (i = 0; i < nb_pkts; i++) {
2364 ol_flags = m->ol_flags;
2366 if (ol_flags & PKT_TX_TCP_SEG &&
2367 (m->tso_segsz < ICE_MIN_TSO_MSS ||
2368 m->tso_segsz > ICE_MAX_TSO_MSS ||
2369 m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
2371 * MSS outside the range are considered malicious
2377 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2378 ret = rte_validate_tx_offload(m);
2384 ret = rte_net_intel_cksum_prepare(m);
2393 void __attribute__((cold))
2394 ice_set_tx_function(struct rte_eth_dev *dev)
2396 struct ice_adapter *ad =
2397 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2399 struct ice_tx_queue *txq;
2401 bool use_avx2 = false;
2403 if (!ice_tx_vec_dev_check(dev)) {
2404 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2405 txq = dev->data->tx_queues[i];
2406 (void)ice_txq_vec_setup(txq);
2409 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2410 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2413 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2414 use_avx2 ? "avx2 " : "",
2415 dev->data->port_id);
2416 dev->tx_pkt_burst = use_avx2 ?
2417 ice_xmit_pkts_vec_avx2 :
2419 dev->tx_pkt_prepare = NULL;
2425 if (ad->tx_simple_allowed) {
2426 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2427 dev->tx_pkt_burst = ice_xmit_pkts_simple;
2428 dev->tx_pkt_prepare = NULL;
2430 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
2431 dev->tx_pkt_burst = ice_xmit_pkts;
2432 dev->tx_pkt_prepare = ice_prep_pkts;
2436 /* For each value it means, datasheet of hardware can tell more details
2438 * @note: fix ice_dev_supported_ptypes_get() if any change here.
2440 static inline uint32_t
2441 ice_get_default_pkt_type(uint16_t ptype)
2443 static const uint32_t type_table[ICE_MAX_PKT_TYPE]
2444 __rte_cache_aligned = {
2447 [1] = RTE_PTYPE_L2_ETHER,
2448 /* [2] - [5] reserved */
2449 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2450 /* [7] - [10] reserved */
2451 [11] = RTE_PTYPE_L2_ETHER_ARP,
2452 /* [12] - [21] reserved */
2454 /* Non tunneled IPv4 */
2455 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2457 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2458 RTE_PTYPE_L4_NONFRAG,
2459 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2462 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2464 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2466 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2470 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2471 RTE_PTYPE_TUNNEL_IP |
2472 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2473 RTE_PTYPE_INNER_L4_FRAG,
2474 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2475 RTE_PTYPE_TUNNEL_IP |
2476 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2477 RTE_PTYPE_INNER_L4_NONFRAG,
2478 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2479 RTE_PTYPE_TUNNEL_IP |
2480 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2481 RTE_PTYPE_INNER_L4_UDP,
2483 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2484 RTE_PTYPE_TUNNEL_IP |
2485 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2486 RTE_PTYPE_INNER_L4_TCP,
2487 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2488 RTE_PTYPE_TUNNEL_IP |
2489 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2490 RTE_PTYPE_INNER_L4_SCTP,
2491 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2492 RTE_PTYPE_TUNNEL_IP |
2493 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2494 RTE_PTYPE_INNER_L4_ICMP,
2497 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2498 RTE_PTYPE_TUNNEL_IP |
2499 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2500 RTE_PTYPE_INNER_L4_FRAG,
2501 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2502 RTE_PTYPE_TUNNEL_IP |
2503 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2504 RTE_PTYPE_INNER_L4_NONFRAG,
2505 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2506 RTE_PTYPE_TUNNEL_IP |
2507 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2508 RTE_PTYPE_INNER_L4_UDP,
2510 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2511 RTE_PTYPE_TUNNEL_IP |
2512 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2513 RTE_PTYPE_INNER_L4_TCP,
2514 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2515 RTE_PTYPE_TUNNEL_IP |
2516 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2517 RTE_PTYPE_INNER_L4_SCTP,
2518 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2519 RTE_PTYPE_TUNNEL_IP |
2520 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2521 RTE_PTYPE_INNER_L4_ICMP,
2523 /* IPv4 --> GRE/Teredo/VXLAN */
2524 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2525 RTE_PTYPE_TUNNEL_GRENAT,
2527 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2528 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2529 RTE_PTYPE_TUNNEL_GRENAT |
2530 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2531 RTE_PTYPE_INNER_L4_FRAG,
2532 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2533 RTE_PTYPE_TUNNEL_GRENAT |
2534 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2535 RTE_PTYPE_INNER_L4_NONFRAG,
2536 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2537 RTE_PTYPE_TUNNEL_GRENAT |
2538 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2539 RTE_PTYPE_INNER_L4_UDP,
2541 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2542 RTE_PTYPE_TUNNEL_GRENAT |
2543 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2544 RTE_PTYPE_INNER_L4_TCP,
2545 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2546 RTE_PTYPE_TUNNEL_GRENAT |
2547 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2548 RTE_PTYPE_INNER_L4_SCTP,
2549 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2550 RTE_PTYPE_TUNNEL_GRENAT |
2551 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2552 RTE_PTYPE_INNER_L4_ICMP,
2554 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2555 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2556 RTE_PTYPE_TUNNEL_GRENAT |
2557 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2558 RTE_PTYPE_INNER_L4_FRAG,
2559 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2560 RTE_PTYPE_TUNNEL_GRENAT |
2561 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2562 RTE_PTYPE_INNER_L4_NONFRAG,
2563 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2564 RTE_PTYPE_TUNNEL_GRENAT |
2565 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2566 RTE_PTYPE_INNER_L4_UDP,
2568 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2569 RTE_PTYPE_TUNNEL_GRENAT |
2570 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2571 RTE_PTYPE_INNER_L4_TCP,
2572 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2573 RTE_PTYPE_TUNNEL_GRENAT |
2574 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2575 RTE_PTYPE_INNER_L4_SCTP,
2576 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2577 RTE_PTYPE_TUNNEL_GRENAT |
2578 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2579 RTE_PTYPE_INNER_L4_ICMP,
2581 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2582 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2583 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2585 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2586 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2587 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2588 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2589 RTE_PTYPE_INNER_L4_FRAG,
2590 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2591 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2592 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2593 RTE_PTYPE_INNER_L4_NONFRAG,
2594 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2595 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2596 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2597 RTE_PTYPE_INNER_L4_UDP,
2599 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2600 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2601 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2602 RTE_PTYPE_INNER_L4_TCP,
2603 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2604 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2605 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2606 RTE_PTYPE_INNER_L4_SCTP,
2607 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2608 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2609 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2610 RTE_PTYPE_INNER_L4_ICMP,
2612 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2613 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2614 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2615 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2616 RTE_PTYPE_INNER_L4_FRAG,
2617 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2618 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2619 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2620 RTE_PTYPE_INNER_L4_NONFRAG,
2621 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2622 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2623 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2624 RTE_PTYPE_INNER_L4_UDP,
2626 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2627 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2628 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2629 RTE_PTYPE_INNER_L4_TCP,
2630 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2631 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2632 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2633 RTE_PTYPE_INNER_L4_SCTP,
2634 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2635 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2636 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2637 RTE_PTYPE_INNER_L4_ICMP,
2639 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2640 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2641 RTE_PTYPE_TUNNEL_GRENAT |
2642 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2644 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2645 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2646 RTE_PTYPE_TUNNEL_GRENAT |
2647 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2648 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2649 RTE_PTYPE_INNER_L4_FRAG,
2650 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2651 RTE_PTYPE_TUNNEL_GRENAT |
2652 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2653 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2654 RTE_PTYPE_INNER_L4_NONFRAG,
2655 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2656 RTE_PTYPE_TUNNEL_GRENAT |
2657 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2658 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2659 RTE_PTYPE_INNER_L4_UDP,
2661 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2662 RTE_PTYPE_TUNNEL_GRENAT |
2663 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2664 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2665 RTE_PTYPE_INNER_L4_TCP,
2666 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2667 RTE_PTYPE_TUNNEL_GRENAT |
2668 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2669 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2670 RTE_PTYPE_INNER_L4_SCTP,
2671 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2672 RTE_PTYPE_TUNNEL_GRENAT |
2673 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2674 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2675 RTE_PTYPE_INNER_L4_ICMP,
2677 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2678 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2679 RTE_PTYPE_TUNNEL_GRENAT |
2680 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2681 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2682 RTE_PTYPE_INNER_L4_FRAG,
2683 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2684 RTE_PTYPE_TUNNEL_GRENAT |
2685 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2686 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2687 RTE_PTYPE_INNER_L4_NONFRAG,
2688 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2689 RTE_PTYPE_TUNNEL_GRENAT |
2690 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2691 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2692 RTE_PTYPE_INNER_L4_UDP,
2694 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2695 RTE_PTYPE_TUNNEL_GRENAT |
2696 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2697 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2698 RTE_PTYPE_INNER_L4_TCP,
2699 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2700 RTE_PTYPE_TUNNEL_GRENAT |
2701 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2702 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2703 RTE_PTYPE_INNER_L4_SCTP,
2704 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2705 RTE_PTYPE_TUNNEL_GRENAT |
2706 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2707 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2708 RTE_PTYPE_INNER_L4_ICMP,
2710 /* Non tunneled IPv6 */
2711 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2713 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2714 RTE_PTYPE_L4_NONFRAG,
2715 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2718 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2720 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2722 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2726 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2727 RTE_PTYPE_TUNNEL_IP |
2728 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2729 RTE_PTYPE_INNER_L4_FRAG,
2730 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2731 RTE_PTYPE_TUNNEL_IP |
2732 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2733 RTE_PTYPE_INNER_L4_NONFRAG,
2734 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2735 RTE_PTYPE_TUNNEL_IP |
2736 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2737 RTE_PTYPE_INNER_L4_UDP,
2739 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2740 RTE_PTYPE_TUNNEL_IP |
2741 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2742 RTE_PTYPE_INNER_L4_TCP,
2743 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2744 RTE_PTYPE_TUNNEL_IP |
2745 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2746 RTE_PTYPE_INNER_L4_SCTP,
2747 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2748 RTE_PTYPE_TUNNEL_IP |
2749 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2750 RTE_PTYPE_INNER_L4_ICMP,
2753 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2754 RTE_PTYPE_TUNNEL_IP |
2755 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2756 RTE_PTYPE_INNER_L4_FRAG,
2757 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2758 RTE_PTYPE_TUNNEL_IP |
2759 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2760 RTE_PTYPE_INNER_L4_NONFRAG,
2761 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2762 RTE_PTYPE_TUNNEL_IP |
2763 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2764 RTE_PTYPE_INNER_L4_UDP,
2765 /* [105] reserved */
2766 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2767 RTE_PTYPE_TUNNEL_IP |
2768 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2769 RTE_PTYPE_INNER_L4_TCP,
2770 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2771 RTE_PTYPE_TUNNEL_IP |
2772 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2773 RTE_PTYPE_INNER_L4_SCTP,
2774 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2775 RTE_PTYPE_TUNNEL_IP |
2776 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2777 RTE_PTYPE_INNER_L4_ICMP,
2779 /* IPv6 --> GRE/Teredo/VXLAN */
2780 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2781 RTE_PTYPE_TUNNEL_GRENAT,
2783 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2784 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2785 RTE_PTYPE_TUNNEL_GRENAT |
2786 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2787 RTE_PTYPE_INNER_L4_FRAG,
2788 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2789 RTE_PTYPE_TUNNEL_GRENAT |
2790 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2791 RTE_PTYPE_INNER_L4_NONFRAG,
2792 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2793 RTE_PTYPE_TUNNEL_GRENAT |
2794 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2795 RTE_PTYPE_INNER_L4_UDP,
2796 /* [113] reserved */
2797 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2798 RTE_PTYPE_TUNNEL_GRENAT |
2799 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2800 RTE_PTYPE_INNER_L4_TCP,
2801 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2802 RTE_PTYPE_TUNNEL_GRENAT |
2803 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2804 RTE_PTYPE_INNER_L4_SCTP,
2805 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2806 RTE_PTYPE_TUNNEL_GRENAT |
2807 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2808 RTE_PTYPE_INNER_L4_ICMP,
2810 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2811 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2812 RTE_PTYPE_TUNNEL_GRENAT |
2813 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2814 RTE_PTYPE_INNER_L4_FRAG,
2815 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2816 RTE_PTYPE_TUNNEL_GRENAT |
2817 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2818 RTE_PTYPE_INNER_L4_NONFRAG,
2819 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2820 RTE_PTYPE_TUNNEL_GRENAT |
2821 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2822 RTE_PTYPE_INNER_L4_UDP,
2823 /* [120] reserved */
2824 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2825 RTE_PTYPE_TUNNEL_GRENAT |
2826 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2827 RTE_PTYPE_INNER_L4_TCP,
2828 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2829 RTE_PTYPE_TUNNEL_GRENAT |
2830 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2831 RTE_PTYPE_INNER_L4_SCTP,
2832 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2833 RTE_PTYPE_TUNNEL_GRENAT |
2834 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2835 RTE_PTYPE_INNER_L4_ICMP,
2837 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2838 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2839 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2841 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2842 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2843 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2844 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2845 RTE_PTYPE_INNER_L4_FRAG,
2846 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2847 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2848 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2849 RTE_PTYPE_INNER_L4_NONFRAG,
2850 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2851 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2852 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2853 RTE_PTYPE_INNER_L4_UDP,
2854 /* [128] reserved */
2855 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2856 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2857 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2858 RTE_PTYPE_INNER_L4_TCP,
2859 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2860 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2861 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2862 RTE_PTYPE_INNER_L4_SCTP,
2863 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2864 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2865 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2866 RTE_PTYPE_INNER_L4_ICMP,
2868 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2869 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2870 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2871 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2872 RTE_PTYPE_INNER_L4_FRAG,
2873 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2874 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2875 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2876 RTE_PTYPE_INNER_L4_NONFRAG,
2877 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2878 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2879 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2880 RTE_PTYPE_INNER_L4_UDP,
2881 /* [135] reserved */
2882 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2883 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2884 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2885 RTE_PTYPE_INNER_L4_TCP,
2886 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2887 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2888 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2889 RTE_PTYPE_INNER_L4_SCTP,
2890 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2891 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2892 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2893 RTE_PTYPE_INNER_L4_ICMP,
2895 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2896 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2897 RTE_PTYPE_TUNNEL_GRENAT |
2898 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2900 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2901 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2902 RTE_PTYPE_TUNNEL_GRENAT |
2903 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2904 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2905 RTE_PTYPE_INNER_L4_FRAG,
2906 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2907 RTE_PTYPE_TUNNEL_GRENAT |
2908 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2909 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2910 RTE_PTYPE_INNER_L4_NONFRAG,
2911 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2912 RTE_PTYPE_TUNNEL_GRENAT |
2913 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2914 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2915 RTE_PTYPE_INNER_L4_UDP,
2916 /* [143] reserved */
2917 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2918 RTE_PTYPE_TUNNEL_GRENAT |
2919 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2920 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2921 RTE_PTYPE_INNER_L4_TCP,
2922 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2923 RTE_PTYPE_TUNNEL_GRENAT |
2924 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2925 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2926 RTE_PTYPE_INNER_L4_SCTP,
2927 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2928 RTE_PTYPE_TUNNEL_GRENAT |
2929 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2930 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2931 RTE_PTYPE_INNER_L4_ICMP,
2933 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2934 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2935 RTE_PTYPE_TUNNEL_GRENAT |
2936 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2937 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2938 RTE_PTYPE_INNER_L4_FRAG,
2939 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2940 RTE_PTYPE_TUNNEL_GRENAT |
2941 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2942 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2943 RTE_PTYPE_INNER_L4_NONFRAG,
2944 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2945 RTE_PTYPE_TUNNEL_GRENAT |
2946 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2947 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2948 RTE_PTYPE_INNER_L4_UDP,
2949 /* [150] reserved */
2950 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2951 RTE_PTYPE_TUNNEL_GRENAT |
2952 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2953 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2954 RTE_PTYPE_INNER_L4_TCP,
2955 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2956 RTE_PTYPE_TUNNEL_GRENAT |
2957 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2958 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2959 RTE_PTYPE_INNER_L4_SCTP,
2960 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2961 RTE_PTYPE_TUNNEL_GRENAT |
2962 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2963 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2964 RTE_PTYPE_INNER_L4_ICMP,
2965 /* [154] - [255] reserved */
2966 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2967 RTE_PTYPE_TUNNEL_GTPC,
2968 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2969 RTE_PTYPE_TUNNEL_GTPC,
2970 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2971 RTE_PTYPE_TUNNEL_GTPU,
2972 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2973 RTE_PTYPE_TUNNEL_GTPU,
2974 /* [260] - [263] reserved */
2975 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2976 RTE_PTYPE_TUNNEL_GTPC,
2977 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2978 RTE_PTYPE_TUNNEL_GTPC,
2979 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2980 RTE_PTYPE_TUNNEL_GTPU,
2981 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2982 RTE_PTYPE_TUNNEL_GTPU,
2984 /* All others reserved */
2987 return type_table[ptype];
2990 void __attribute__((cold))
2991 ice_set_default_ptype_table(struct rte_eth_dev *dev)
2993 struct ice_adapter *ad =
2994 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2997 for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
2998 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);