drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "ice_rxtx.h"
   9
  10 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  11                 PKT_TX_IP_CKSUM |                \
  12                 PKT_TX_L4_MASK |                 \
  13                 PKT_TX_TCP_SEG |                 \
  14                 PKT_TX_OUTER_IP_CKSUM)
  15
  16 static inline uint8_t
  17 ice_rxdid_to_proto_xtr_type(uint8_t rxdid)
  18 {
  19         static uint8_t xtr_map[] = {
  20                 [ICE_RXDID_COMMS_AUX_VLAN]      = PROTO_XTR_VLAN,
  21                 [ICE_RXDID_COMMS_AUX_IPV4]      = PROTO_XTR_IPV4,
  22                 [ICE_RXDID_COMMS_AUX_IPV6]      = PROTO_XTR_IPV6,
  23                 [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = PROTO_XTR_IPV6_FLOW,
  24                 [ICE_RXDID_COMMS_AUX_TCP]       = PROTO_XTR_TCP,
  25         };
  26
  27         return rxdid < RTE_DIM(xtr_map) ? xtr_map[rxdid] : PROTO_XTR_NONE;
  28 }
  29
  30 static inline uint8_t
  31 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  32 {
  33         static uint8_t rxdid_map[] = {
  34                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_GENERIC,
  35                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  36                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  37                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  38                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  39                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  40         };
  41
  42         return xtr_type < RTE_DIM(rxdid_map) ?
  43                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_GENERIC;
  44 }
  45
  46 static enum ice_status
  47 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  48 {
  49         struct ice_vsi *vsi = rxq->vsi;
  50         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  51         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  52         struct ice_rlan_ctx rx_ctx;
  53         enum ice_status err;
  54         uint16_t buf_size, len;
  55         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  56         uint32_t rxdid = ICE_RXDID_COMMS_GENERIC;
  57         uint32_t regval;
  58
  59         /* Set buffer size as the head split is disabled. */
  60         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  61                               RTE_PKTMBUF_HEADROOM);
  62         rxq->rx_hdr_len = 0;
  63         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  64         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  65         rxq->max_pkt_len = RTE_MIN(len,
  66                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
  67
  68         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
  69                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
  70                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
  71                         PMD_DRV_LOG(ERR, "maximum packet length must "
  72                                     "be larger than %u and smaller than %u,"
  73                                     "as jumbo frame is enabled",
  74                                     (uint32_t)RTE_ETHER_MAX_LEN,
  75                                     (uint32_t)ICE_FRAME_SIZE_MAX);
  76                         return -EINVAL;
  77                 }
  78         } else {
  79                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
  80                     rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
  81                         PMD_DRV_LOG(ERR, "maximum packet length must be "
  82                                     "larger than %u and smaller than %u, "
  83                                     "as jumbo frame is disabled",
  84                                     (uint32_t)RTE_ETHER_MIN_LEN,
  85                                     (uint32_t)RTE_ETHER_MAX_LEN);
  86                         return -EINVAL;
  87                 }
  88         }
  89
  90         memset(&rx_ctx, 0, sizeof(rx_ctx));
  91
  92         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
  93         rx_ctx.qlen = rxq->nb_rx_desc;
  94         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
  95         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
  96         rx_ctx.dtype = 0; /* No Header Split mode */
  97 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  98         rx_ctx.dsize = 1; /* 32B descriptors */
  99 #endif
 100         rx_ctx.rxmax = rxq->max_pkt_len;
 101         /* TPH: Transaction Layer Packet (TLP) processing hints */
 102         rx_ctx.tphrdesc_ena = 1;
 103         rx_ctx.tphwdesc_ena = 1;
 104         rx_ctx.tphdata_ena = 1;
 105         rx_ctx.tphhead_ena = 1;
 106         /* Low Receive Queue Threshold defined in 64 descriptors units.
 107          * When the number of free descriptors goes below the lrxqthresh,
 108          * an immediate interrupt is triggered.
 109          */
 110         rx_ctx.lrxqthresh = 2;
 111         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 112         rx_ctx.l2tsel = 1;
 113         rx_ctx.showiv = 0;
 114         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 115
 116         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 117
 118         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 119                     rxq->port_id, rxq->queue_id, rxdid);
 120
 121         /* Enable Flexible Descriptors in the queue context which
 122          * allows this driver to select a specific receive descriptor format
 123          */
 124         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 125                 QRXFLXP_CNTXT_RXDID_IDX_M;
 126
 127         /* increasing context priority to pick up profile ID;
 128          * default is 0x01; setting to 0x03 to ensure profile
 129          * is programming if prev context is of same priority
 130          */
 131         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 132                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 133
 134         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 135
 136         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 137         if (err) {
 138                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 139                             rxq->queue_id);
 140                 return -EINVAL;
 141         }
 142         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 143         if (err) {
 144                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 145                             rxq->queue_id);
 146                 return -EINVAL;
 147         }
 148
 149         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 150                               RTE_PKTMBUF_HEADROOM);
 151
 152         /* Check if scattered RX needs to be used. */
 153         if (rxq->max_pkt_len > buf_size)
 154                 dev->data->scattered_rx = 1;
 155
 156         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 157
 158         /* Init the Rx tail register*/
 159         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 160
 161         return 0;
 162 }
 163
 164 /* Allocate mbufs for all descriptors in rx queue */
 165 static int
 166 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 167 {
 168         struct ice_rx_entry *rxe = rxq->sw_ring;
 169         uint64_t dma_addr;
 170         uint16_t i;
 171
 172         for (i = 0; i < rxq->nb_rx_desc; i++) {
 173                 volatile union ice_rx_flex_desc *rxd;
 174                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 175
 176                 if (unlikely(!mbuf)) {
 177                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 178                         return -ENOMEM;
 179                 }
 180
 181                 rte_mbuf_refcnt_set(mbuf, 1);
 182                 mbuf->next = NULL;
 183                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 184                 mbuf->nb_segs = 1;
 185                 mbuf->port = rxq->port_id;
 186
 187                 dma_addr =
 188                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 189
 190                 rxd = &rxq->rx_ring[i];
 191                 rxd->read.pkt_addr = dma_addr;
 192                 rxd->read.hdr_addr = 0;
 193 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 194                 rxd->read.rsvd1 = 0;
 195                 rxd->read.rsvd2 = 0;
 196 #endif
 197                 rxe[i].mbuf = mbuf;
 198         }
 199
 200         return 0;
 201 }
 202
 203 /* Free all mbufs for descriptors in rx queue */
 204 static void
 205 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 206 {
 207         uint16_t i;
 208
 209         if (!rxq || !rxq->sw_ring) {
 210                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 211                 return;
 212         }
 213
 214         for (i = 0; i < rxq->nb_rx_desc; i++) {
 215                 if (rxq->sw_ring[i].mbuf) {
 216                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 217                         rxq->sw_ring[i].mbuf = NULL;
 218                 }
 219         }
 220 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 221                 if (rxq->rx_nb_avail == 0)
 222                         return;
 223                 for (i = 0; i < rxq->rx_nb_avail; i++) {
 224                         struct rte_mbuf *mbuf;
 225
 226                         mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 227                         rte_pktmbuf_free_seg(mbuf);
 228                 }
 229                 rxq->rx_nb_avail = 0;
 230 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 231 }
 232
 233 static void
 234 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 235 {
 236         rxq->rx_rel_mbufs(rxq);
 237 }
 238
 239 /* turn on or off rx queue
 240  * @q_idx: queue index in pf scope
 241  * @on: turn on or off the queue
 242  */
 243 static int
 244 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 245 {
 246         uint32_t reg;
 247         uint16_t j;
 248
 249         /* QRX_CTRL = QRX_ENA */
 250         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 251
 252         if (on) {
 253                 if (reg & QRX_CTRL_QENA_STAT_M)
 254                         return 0; /* Already on, skip */
 255                 reg |= QRX_CTRL_QENA_REQ_M;
 256         } else {
 257                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 258                         return 0; /* Already off, skip */
 259                 reg &= ~QRX_CTRL_QENA_REQ_M;
 260         }
 261
 262         /* Write the register */
 263         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 264         /* Check the result. It is said that QENA_STAT
 265          * follows the QENA_REQ not more than 10 use.
 266          * TODO: need to change the wait counter later
 267          */
 268         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 269                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 270                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 271                 if (on) {
 272                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 273                             (reg & QRX_CTRL_QENA_STAT_M))
 274                                 break;
 275                 } else {
 276                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 277                             !(reg & QRX_CTRL_QENA_STAT_M))
 278                                 break;
 279                 }
 280         }
 281
 282         /* Check if it is timeout */
 283         if (j >= ICE_CHK_Q_ENA_COUNT) {
 284                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 285                             (on ? "enable" : "disable"), q_idx);
 286                 return -ETIMEDOUT;
 287         }
 288
 289         return 0;
 290 }
 291
 292 static inline int
 293 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 294 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 295 #else
 296 ice_check_rx_burst_bulk_alloc_preconditions
 297         (__rte_unused struct ice_rx_queue *rxq)
 298 #endif
 299 {
 300         int ret = 0;
 301
 302 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 303         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 304                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 305                              "rxq->rx_free_thresh=%d, "
 306                              "ICE_RX_MAX_BURST=%d",
 307                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 308                 ret = -EINVAL;
 309         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 310                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 311                              "rxq->rx_free_thresh=%d, "
 312                              "rxq->nb_rx_desc=%d",
 313                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 314                 ret = -EINVAL;
 315         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 316                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 317                              "rxq->nb_rx_desc=%d, "
 318                              "rxq->rx_free_thresh=%d",
 319                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 320                 ret = -EINVAL;
 321         }
 322 #else
 323         ret = -EINVAL;
 324 #endif
 325
 326         return ret;
 327 }
 328
 329 /* reset fields in ice_rx_queue back to default */
 330 static void
 331 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 332 {
 333         unsigned int i;
 334         uint16_t len;
 335
 336         if (!rxq) {
 337                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 338                 return;
 339         }
 340
 341 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 342         if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
 343                 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 344         else
 345 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 346                 len = rxq->nb_rx_desc;
 347
 348         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 349                 ((volatile char *)rxq->rx_ring)[i] = 0;
 350
 351 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 352         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 353         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 354                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 355
 356         rxq->rx_nb_avail = 0;
 357         rxq->rx_next_avail = 0;
 358         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 359 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 360
 361         rxq->rx_tail = 0;
 362         rxq->nb_rx_hold = 0;
 363         rxq->pkt_first_seg = NULL;
 364         rxq->pkt_last_seg = NULL;
 365
 366         rxq->rxrearm_start = 0;
 367         rxq->rxrearm_nb = 0;
 368 }
 369
 370 int
 371 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 372 {
 373         struct ice_rx_queue *rxq;
 374         int err;
 375         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 376
 377         PMD_INIT_FUNC_TRACE();
 378
 379         if (rx_queue_id >= dev->data->nb_rx_queues) {
 380                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 381                             rx_queue_id, dev->data->nb_rx_queues);
 382                 return -EINVAL;
 383         }
 384
 385         rxq = dev->data->rx_queues[rx_queue_id];
 386         if (!rxq || !rxq->q_set) {
 387                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 388                             rx_queue_id);
 389                 return -EINVAL;
 390         }
 391
 392         err = ice_program_hw_rx_queue(rxq);
 393         if (err) {
 394                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 395                             rx_queue_id);
 396                 return -EIO;
 397         }
 398
 399         err = ice_alloc_rx_queue_mbufs(rxq);
 400         if (err) {
 401                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 402                 return -ENOMEM;
 403         }
 404
 405         rte_wmb();
 406
 407         /* Init the RX tail register. */
 408         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 409
 410         err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
 411         if (err) {
 412                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 413                             rx_queue_id);
 414
 415                 ice_rx_queue_release_mbufs(rxq);
 416                 ice_reset_rx_queue(rxq);
 417                 return -EINVAL;
 418         }
 419
 420         dev->data->rx_queue_state[rx_queue_id] =
 421                 RTE_ETH_QUEUE_STATE_STARTED;
 422
 423         return 0;
 424 }
 425
 426 int
 427 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 428 {
 429         struct ice_rx_queue *rxq;
 430         int err;
 431         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 432
 433         if (rx_queue_id < dev->data->nb_rx_queues) {
 434                 rxq = dev->data->rx_queues[rx_queue_id];
 435
 436                 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
 437                 if (err) {
 438                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 439                                     rx_queue_id);
 440                         return -EINVAL;
 441                 }
 442                 ice_rx_queue_release_mbufs(rxq);
 443                 ice_reset_rx_queue(rxq);
 444                 dev->data->rx_queue_state[rx_queue_id] =
 445                         RTE_ETH_QUEUE_STATE_STOPPED;
 446         }
 447
 448         return 0;
 449 }
 450
 451 int
 452 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 453 {
 454         struct ice_tx_queue *txq;
 455         int err;
 456         struct ice_vsi *vsi;
 457         struct ice_hw *hw;
 458         struct ice_aqc_add_tx_qgrp txq_elem;
 459         struct ice_tlan_ctx tx_ctx;
 460
 461         PMD_INIT_FUNC_TRACE();
 462
 463         if (tx_queue_id >= dev->data->nb_tx_queues) {
 464                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 465                             tx_queue_id, dev->data->nb_tx_queues);
 466                 return -EINVAL;
 467         }
 468
 469         txq = dev->data->tx_queues[tx_queue_id];
 470         if (!txq || !txq->q_set) {
 471                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 472                             tx_queue_id);
 473                 return -EINVAL;
 474         }
 475
 476         vsi = txq->vsi;
 477         hw = ICE_VSI_TO_HW(vsi);
 478
 479         memset(&txq_elem, 0, sizeof(txq_elem));
 480         memset(&tx_ctx, 0, sizeof(tx_ctx));
 481         txq_elem.num_txqs = 1;
 482         txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 483
 484         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 485         tx_ctx.qlen = txq->nb_tx_desc;
 486         tx_ctx.pf_num = hw->pf_id;
 487         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 488         tx_ctx.src_vsi = vsi->vsi_id;
 489         tx_ctx.port_num = hw->port_info->lport;
 490         tx_ctx.tso_ena = 1; /* tso enable */
 491         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 492         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 493
 494         ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
 495                     ice_tlan_ctx_info);
 496
 497         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 498
 499         /* Init the Tx tail register*/
 500         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 501
 502         /* Fix me, we assume TC always 0 here */
 503         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 504                         &txq_elem, sizeof(txq_elem), NULL);
 505         if (err) {
 506                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 507                 return -EIO;
 508         }
 509         /* store the schedule node id */
 510         txq->q_teid = txq_elem.txqs[0].q_teid;
 511
 512         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 513         return 0;
 514 }
 515
 516 /* Free all mbufs for descriptors in tx queue */
 517 static void
 518 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 519 {
 520         uint16_t i;
 521
 522         if (!txq || !txq->sw_ring) {
 523                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 524                 return;
 525         }
 526
 527         for (i = 0; i < txq->nb_tx_desc; i++) {
 528                 if (txq->sw_ring[i].mbuf) {
 529                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 530                         txq->sw_ring[i].mbuf = NULL;
 531                 }
 532         }
 533 }
 534 static void
 535 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 536 {
 537         txq->tx_rel_mbufs(txq);
 538 }
 539
 540 static void
 541 ice_reset_tx_queue(struct ice_tx_queue *txq)
 542 {
 543         struct ice_tx_entry *txe;
 544         uint16_t i, prev, size;
 545
 546         if (!txq) {
 547                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 548                 return;
 549         }
 550
 551         txe = txq->sw_ring;
 552         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 553         for (i = 0; i < size; i++)
 554                 ((volatile char *)txq->tx_ring)[i] = 0;
 555
 556         prev = (uint16_t)(txq->nb_tx_desc - 1);
 557         for (i = 0; i < txq->nb_tx_desc; i++) {
 558                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 559
 560                 txd->cmd_type_offset_bsz =
 561                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 562                 txe[i].mbuf =  NULL;
 563                 txe[i].last_id = i;
 564                 txe[prev].next_id = i;
 565                 prev = i;
 566         }
 567
 568         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 569         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 570
 571         txq->tx_tail = 0;
 572         txq->nb_tx_used = 0;
 573
 574         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 575         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 576 }
 577
 578 int
 579 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 580 {
 581         struct ice_tx_queue *txq;
 582         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 583         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 584         struct ice_vsi *vsi = pf->main_vsi;
 585         enum ice_status status;
 586         uint16_t q_ids[1];
 587         uint32_t q_teids[1];
 588         uint16_t q_handle = tx_queue_id;
 589
 590         if (tx_queue_id >= dev->data->nb_tx_queues) {
 591                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 592                             tx_queue_id, dev->data->nb_tx_queues);
 593                 return -EINVAL;
 594         }
 595
 596         txq = dev->data->tx_queues[tx_queue_id];
 597         if (!txq) {
 598                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 599                             tx_queue_id);
 600                 return -EINVAL;
 601         }
 602
 603         q_ids[0] = txq->reg_idx;
 604         q_teids[0] = txq->q_teid;
 605
 606         /* Fix me, we assume TC always 0 here */
 607         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 608                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 609         if (status != ICE_SUCCESS) {
 610                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 611                 return -EINVAL;
 612         }
 613
 614         ice_tx_queue_release_mbufs(txq);
 615         ice_reset_tx_queue(txq);
 616         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 617
 618         return 0;
 619 }
 620
 621 int
 622 ice_rx_queue_setup(struct rte_eth_dev *dev,
 623                    uint16_t queue_idx,
 624                    uint16_t nb_desc,
 625                    unsigned int socket_id,
 626                    const struct rte_eth_rxconf *rx_conf,
 627                    struct rte_mempool *mp)
 628 {
 629         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 630         struct ice_adapter *ad =
 631                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 632         struct ice_vsi *vsi = pf->main_vsi;
 633         struct ice_rx_queue *rxq;
 634         const struct rte_memzone *rz;
 635         uint32_t ring_size;
 636         uint16_t len;
 637         int use_def_burst_func = 1;
 638
 639         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 640             nb_desc > ICE_MAX_RING_DESC ||
 641             nb_desc < ICE_MIN_RING_DESC) {
 642                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 643                              "invalid", nb_desc);
 644                 return -EINVAL;
 645         }
 646
 647         /* Free memory if needed */
 648         if (dev->data->rx_queues[queue_idx]) {
 649                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 650                 dev->data->rx_queues[queue_idx] = NULL;
 651         }
 652
 653         /* Allocate the rx queue data structure */
 654         rxq = rte_zmalloc_socket(NULL,
 655                                  sizeof(struct ice_rx_queue),
 656                                  RTE_CACHE_LINE_SIZE,
 657                                  socket_id);
 658         if (!rxq) {
 659                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 660                              "rx queue data structure");
 661                 return -ENOMEM;
 662         }
 663         rxq->mp = mp;
 664         rxq->nb_rx_desc = nb_desc;
 665         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 666         rxq->queue_id = queue_idx;
 667
 668         rxq->reg_idx = vsi->base_queue + queue_idx;
 669         rxq->port_id = dev->data->port_id;
 670         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 671                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 672         else
 673                 rxq->crc_len = 0;
 674
 675         rxq->drop_en = rx_conf->rx_drop_en;
 676         rxq->vsi = vsi;
 677         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 678         rxq->proto_xtr = pf->proto_xtr != NULL ?
 679                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
 680
 681         /* Allocate the maximun number of RX ring hardware descriptor. */
 682         len = ICE_MAX_RING_DESC;
 683
 684 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 685         /**
 686          * Allocating a little more memory because vectorized/bulk_alloc Rx
 687          * functions doesn't check boundaries each time.
 688          */
 689         len += ICE_RX_MAX_BURST;
 690 #endif
 691
 692         /* Allocate the maximum number of RX ring hardware descriptor. */
 693         ring_size = sizeof(union ice_rx_flex_desc) * len;
 694         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 695         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 696                                       ring_size, ICE_RING_BASE_ALIGN,
 697                                       socket_id);
 698         if (!rz) {
 699                 ice_rx_queue_release(rxq);
 700                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 701                 return -ENOMEM;
 702         }
 703
 704         /* Zero all the descriptors in the ring. */
 705         memset(rz->addr, 0, ring_size);
 706
 707         rxq->rx_ring_dma = rz->iova;
 708         rxq->rx_ring = rz->addr;
 709
 710 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 711         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 712 #else
 713         len = nb_desc;
 714 #endif
 715
 716         /* Allocate the software ring. */
 717         rxq->sw_ring = rte_zmalloc_socket(NULL,
 718                                           sizeof(struct ice_rx_entry) * len,
 719                                           RTE_CACHE_LINE_SIZE,
 720                                           socket_id);
 721         if (!rxq->sw_ring) {
 722                 ice_rx_queue_release(rxq);
 723                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 724                 return -ENOMEM;
 725         }
 726
 727         ice_reset_rx_queue(rxq);
 728         rxq->q_set = TRUE;
 729         dev->data->rx_queues[queue_idx] = rxq;
 730         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
 731
 732         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 733
 734         if (!use_def_burst_func) {
 735 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
 736                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 737                              "satisfied. Rx Burst Bulk Alloc function will be "
 738                              "used on port=%d, queue=%d.",
 739                              rxq->port_id, rxq->queue_id);
 740 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
 741         } else {
 742                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 743                              "not satisfied, Scattered Rx is requested, "
 744                              "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
 745                              "not enabled on port=%d, queue=%d.",
 746                              rxq->port_id, rxq->queue_id);
 747                 ad->rx_bulk_alloc_allowed = false;
 748         }
 749
 750         return 0;
 751 }
 752
 753 void
 754 ice_rx_queue_release(void *rxq)
 755 {
 756         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
 757
 758         if (!q) {
 759                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 760                 return;
 761         }
 762
 763         ice_rx_queue_release_mbufs(q);
 764         rte_free(q->sw_ring);
 765         rte_free(q);
 766 }
 767
 768 int
 769 ice_tx_queue_setup(struct rte_eth_dev *dev,
 770                    uint16_t queue_idx,
 771                    uint16_t nb_desc,
 772                    unsigned int socket_id,
 773                    const struct rte_eth_txconf *tx_conf)
 774 {
 775         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 776         struct ice_vsi *vsi = pf->main_vsi;
 777         struct ice_tx_queue *txq;
 778         const struct rte_memzone *tz;
 779         uint32_t ring_size;
 780         uint16_t tx_rs_thresh, tx_free_thresh;
 781         uint64_t offloads;
 782
 783         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 784
 785         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 786             nb_desc > ICE_MAX_RING_DESC ||
 787             nb_desc < ICE_MIN_RING_DESC) {
 788                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 789                              "invalid", nb_desc);
 790                 return -EINVAL;
 791         }
 792
 793         /**
 794          * The following two parameters control the setting of the RS bit on
 795          * transmit descriptors. TX descriptors will have their RS bit set
 796          * after txq->tx_rs_thresh descriptors have been used. The TX
 797          * descriptor ring will be cleaned after txq->tx_free_thresh
 798          * descriptors are used or if the number of descriptors required to
 799          * transmit a packet is greater than the number of free TX descriptors.
 800          *
 801          * The following constraints must be satisfied:
 802          *  - tx_rs_thresh must be greater than 0.
 803          *  - tx_rs_thresh must be less than the size of the ring minus 2.
 804          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
 805          *  - tx_rs_thresh must be a divisor of the ring size.
 806          *  - tx_free_thresh must be greater than 0.
 807          *  - tx_free_thresh must be less than the size of the ring minus 3.
 808          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
 809          *
 810          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
 811          * race condition, hence the maximum threshold constraints. When set
 812          * to zero use default values.
 813          */
 814         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
 815                                     tx_conf->tx_free_thresh :
 816                                     ICE_DEFAULT_TX_FREE_THRESH);
 817         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
 818         tx_rs_thresh =
 819                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
 820                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
 821         if (tx_conf->tx_rs_thresh)
 822                 tx_rs_thresh = tx_conf->tx_rs_thresh;
 823         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
 824                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
 825                                 "exceed nb_desc. (tx_rs_thresh=%u "
 826                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
 827                                 (unsigned int)tx_rs_thresh,
 828                                 (unsigned int)tx_free_thresh,
 829                                 (unsigned int)nb_desc,
 830                                 (int)dev->data->port_id,
 831                                 (int)queue_idx);
 832                 return -EINVAL;
 833         }
 834         if (tx_rs_thresh >= (nb_desc - 2)) {
 835                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 836                              "number of TX descriptors minus 2. "
 837                              "(tx_rs_thresh=%u port=%d queue=%d)",
 838                              (unsigned int)tx_rs_thresh,
 839                              (int)dev->data->port_id,
 840                              (int)queue_idx);
 841                 return -EINVAL;
 842         }
 843         if (tx_free_thresh >= (nb_desc - 3)) {
 844                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
 845                              "tx_free_thresh must be less than the "
 846                              "number of TX descriptors minus 3. "
 847                              "(tx_free_thresh=%u port=%d queue=%d)",
 848                              (unsigned int)tx_free_thresh,
 849                              (int)dev->data->port_id,
 850                              (int)queue_idx);
 851                 return -EINVAL;
 852         }
 853         if (tx_rs_thresh > tx_free_thresh) {
 854                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
 855                              "equal to tx_free_thresh. (tx_free_thresh=%u"
 856                              " tx_rs_thresh=%u port=%d queue=%d)",
 857                              (unsigned int)tx_free_thresh,
 858                              (unsigned int)tx_rs_thresh,
 859                              (int)dev->data->port_id,
 860                              (int)queue_idx);
 861                 return -EINVAL;
 862         }
 863         if ((nb_desc % tx_rs_thresh) != 0) {
 864                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
 865                              "number of TX descriptors. (tx_rs_thresh=%u"
 866                              " port=%d queue=%d)",
 867                              (unsigned int)tx_rs_thresh,
 868                              (int)dev->data->port_id,
 869                              (int)queue_idx);
 870                 return -EINVAL;
 871         }
 872         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
 873                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
 874                              "tx_rs_thresh is greater than 1. "
 875                              "(tx_rs_thresh=%u port=%d queue=%d)",
 876                              (unsigned int)tx_rs_thresh,
 877                              (int)dev->data->port_id,
 878                              (int)queue_idx);
 879                 return -EINVAL;
 880         }
 881
 882         /* Free memory if needed. */
 883         if (dev->data->tx_queues[queue_idx]) {
 884                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
 885                 dev->data->tx_queues[queue_idx] = NULL;
 886         }
 887
 888         /* Allocate the TX queue data structure. */
 889         txq = rte_zmalloc_socket(NULL,
 890                                  sizeof(struct ice_tx_queue),
 891                                  RTE_CACHE_LINE_SIZE,
 892                                  socket_id);
 893         if (!txq) {
 894                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 895                              "tx queue structure");
 896                 return -ENOMEM;
 897         }
 898
 899         /* Allocate TX hardware ring descriptors. */
 900         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
 901         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 902         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 903                                       ring_size, ICE_RING_BASE_ALIGN,
 904                                       socket_id);
 905         if (!tz) {
 906                 ice_tx_queue_release(txq);
 907                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 908                 return -ENOMEM;
 909         }
 910
 911         txq->nb_tx_desc = nb_desc;
 912         txq->tx_rs_thresh = tx_rs_thresh;
 913         txq->tx_free_thresh = tx_free_thresh;
 914         txq->pthresh = tx_conf->tx_thresh.pthresh;
 915         txq->hthresh = tx_conf->tx_thresh.hthresh;
 916         txq->wthresh = tx_conf->tx_thresh.wthresh;
 917         txq->queue_id = queue_idx;
 918
 919         txq->reg_idx = vsi->base_queue + queue_idx;
 920         txq->port_id = dev->data->port_id;
 921         txq->offloads = offloads;
 922         txq->vsi = vsi;
 923         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 924
 925         txq->tx_ring_dma = tz->iova;
 926         txq->tx_ring = tz->addr;
 927
 928         /* Allocate software ring */
 929         txq->sw_ring =
 930                 rte_zmalloc_socket(NULL,
 931                                    sizeof(struct ice_tx_entry) * nb_desc,
 932                                    RTE_CACHE_LINE_SIZE,
 933                                    socket_id);
 934         if (!txq->sw_ring) {
 935                 ice_tx_queue_release(txq);
 936                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 937                 return -ENOMEM;
 938         }
 939
 940         ice_reset_tx_queue(txq);
 941         txq->q_set = TRUE;
 942         dev->data->tx_queues[queue_idx] = txq;
 943         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
 944         ice_set_tx_function_flag(dev, txq);
 945
 946         return 0;
 947 }
 948
 949 void
 950 ice_tx_queue_release(void *txq)
 951 {
 952         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
 953
 954         if (!q) {
 955                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
 956                 return;
 957         }
 958
 959         ice_tx_queue_release_mbufs(q);
 960         rte_free(q->sw_ring);
 961         rte_free(q);
 962 }
 963
 964 void
 965 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 966                  struct rte_eth_rxq_info *qinfo)
 967 {
 968         struct ice_rx_queue *rxq;
 969
 970         rxq = dev->data->rx_queues[queue_id];
 971
 972         qinfo->mp = rxq->mp;
 973         qinfo->scattered_rx = dev->data->scattered_rx;
 974         qinfo->nb_desc = rxq->nb_rx_desc;
 975
 976         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
 977         qinfo->conf.rx_drop_en = rxq->drop_en;
 978         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
 979 }
 980
 981 void
 982 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
 983                  struct rte_eth_txq_info *qinfo)
 984 {
 985         struct ice_tx_queue *txq;
 986
 987         txq = dev->data->tx_queues[queue_id];
 988
 989         qinfo->nb_desc = txq->nb_tx_desc;
 990
 991         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
 992         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
 993         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
 994
 995         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
 996         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
 997         qinfo->conf.offloads = txq->offloads;
 998         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
 999 }
1000
1001 uint32_t
1002 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1003 {
1004 #define ICE_RXQ_SCAN_INTERVAL 4
1005         volatile union ice_rx_flex_desc *rxdp;
1006         struct ice_rx_queue *rxq;
1007         uint16_t desc = 0;
1008
1009         rxq = dev->data->rx_queues[rx_queue_id];
1010         rxdp = &rxq->rx_ring[rxq->rx_tail];
1011         while ((desc < rxq->nb_rx_desc) &&
1012                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1013                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1014                 /**
1015                  * Check the DD bit of a rx descriptor of each 4 in a group,
1016                  * to avoid checking too frequently and downgrading performance
1017                  * too much.
1018                  */
1019                 desc += ICE_RXQ_SCAN_INTERVAL;
1020                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1021                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1022                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1023                                  desc - rxq->nb_rx_desc]);
1024         }
1025
1026         return desc;
1027 }
1028
1029 #define ICE_RX_FLEX_ERR0_BITS   \
1030         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1031          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1032          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1033          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1034          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1035          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1036
1037 /* Rx L3/L4 checksum */
1038 static inline uint64_t
1039 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1040 {
1041         uint64_t flags = 0;
1042
1043         /* check if HW has decoded the packet and checksum */
1044         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1045                 return 0;
1046
1047         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1048                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1049                 return flags;
1050         }
1051
1052         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1053                 flags |= PKT_RX_IP_CKSUM_BAD;
1054         else
1055                 flags |= PKT_RX_IP_CKSUM_GOOD;
1056
1057         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1058                 flags |= PKT_RX_L4_CKSUM_BAD;
1059         else
1060                 flags |= PKT_RX_L4_CKSUM_GOOD;
1061
1062         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1063                 flags |= PKT_RX_EIP_CKSUM_BAD;
1064
1065         return flags;
1066 }
1067
1068 static inline void
1069 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1070 {
1071         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1072             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1073                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1074                 mb->vlan_tci =
1075                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1076                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1077                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1078         } else {
1079                 mb->vlan_tci = 0;
1080         }
1081
1082 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1083         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1084             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1085                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1086                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1087                 mb->vlan_tci_outer = mb->vlan_tci;
1088                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1089                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1090                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1091                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1092         } else {
1093                 mb->vlan_tci_outer = 0;
1094         }
1095 #endif
1096         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1097                    mb->vlan_tci, mb->vlan_tci_outer);
1098 }
1099
1100 #define ICE_RX_PROTO_XTR_VALID \
1101         ((1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) | \
1102          (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1103
1104 static inline void
1105 ice_rxd_to_pkt_fields(struct rte_mbuf *mb,
1106                       volatile union ice_rx_flex_desc *rxdp)
1107 {
1108         volatile struct ice_32b_rx_flex_desc_comms *desc =
1109                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
1110         uint16_t stat_err;
1111
1112         stat_err = rte_le_to_cpu_16(desc->status_error0);
1113         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
1114                 mb->ol_flags |= PKT_RX_RSS_HASH;
1115                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
1116         }
1117
1118 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1119         init_proto_xtr_flds(mb);
1120
1121         stat_err = rte_le_to_cpu_16(desc->status_error1);
1122         if (stat_err & ICE_RX_PROTO_XTR_VALID) {
1123                 struct proto_xtr_flds *xtr = get_proto_xtr_flds(mb);
1124
1125                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
1126                         xtr->u.raw.data0 =
1127                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
1128
1129                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1130                         xtr->u.raw.data1 =
1131                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
1132
1133                 xtr->type = ice_rxdid_to_proto_xtr_type(desc->rxdid);
1134                 xtr->magic = PROTO_XTR_MAGIC_ID;
1135         }
1136 #endif
1137 }
1138
1139 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1140 #define ICE_LOOK_AHEAD 8
1141 #if (ICE_LOOK_AHEAD != 8)
1142 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1143 #endif
1144 static inline int
1145 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1146 {
1147         volatile union ice_rx_flex_desc *rxdp;
1148         struct ice_rx_entry *rxep;
1149         struct rte_mbuf *mb;
1150         uint16_t stat_err0;
1151         uint16_t pkt_len;
1152         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1153         int32_t i, j, nb_rx = 0;
1154         uint64_t pkt_flags = 0;
1155         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1156
1157         rxdp = &rxq->rx_ring[rxq->rx_tail];
1158         rxep = &rxq->sw_ring[rxq->rx_tail];
1159
1160         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1161
1162         /* Make sure there is at least 1 packet to receive */
1163         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1164                 return 0;
1165
1166         /**
1167          * Scan LOOK_AHEAD descriptors at a time to determine which
1168          * descriptors reference packets that are ready to be received.
1169          */
1170         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1171              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1172                 /* Read desc statuses backwards to avoid race condition */
1173                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1174                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1175
1176                 rte_smp_rmb();
1177
1178                 /* Compute how many status bits were set */
1179                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1180                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1181
1182                 nb_rx += nb_dd;
1183
1184                 /* Translate descriptor info to mbuf parameters */
1185                 for (j = 0; j < nb_dd; j++) {
1186                         mb = rxep[j].mbuf;
1187                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1188                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1189                         mb->data_len = pkt_len;
1190                         mb->pkt_len = pkt_len;
1191                         mb->ol_flags = 0;
1192                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1193                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1194                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1195                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1196                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1197                         ice_rxd_to_pkt_fields(mb, &rxdp[j]);
1198
1199                         mb->ol_flags |= pkt_flags;
1200                 }
1201
1202                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1203                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1204
1205                 if (nb_dd != ICE_LOOK_AHEAD)
1206                         break;
1207         }
1208
1209         /* Clear software ring entries */
1210         for (i = 0; i < nb_rx; i++)
1211                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1212
1213         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1214                    "port_id=%u, queue_id=%u, nb_rx=%d",
1215                    rxq->port_id, rxq->queue_id, nb_rx);
1216
1217         return nb_rx;
1218 }
1219
1220 static inline uint16_t
1221 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1222                        struct rte_mbuf **rx_pkts,
1223                        uint16_t nb_pkts)
1224 {
1225         uint16_t i;
1226         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1227
1228         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1229
1230         for (i = 0; i < nb_pkts; i++)
1231                 rx_pkts[i] = stage[i];
1232
1233         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1234         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1235
1236         return nb_pkts;
1237 }
1238
1239 static inline int
1240 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1241 {
1242         volatile union ice_rx_flex_desc *rxdp;
1243         struct ice_rx_entry *rxep;
1244         struct rte_mbuf *mb;
1245         uint16_t alloc_idx, i;
1246         uint64_t dma_addr;
1247         int diag;
1248
1249         /* Allocate buffers in bulk */
1250         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1251                                (rxq->rx_free_thresh - 1));
1252         rxep = &rxq->sw_ring[alloc_idx];
1253         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1254                                     rxq->rx_free_thresh);
1255         if (unlikely(diag != 0)) {
1256                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1257                 return -ENOMEM;
1258         }
1259
1260         rxdp = &rxq->rx_ring[alloc_idx];
1261         for (i = 0; i < rxq->rx_free_thresh; i++) {
1262                 if (likely(i < (rxq->rx_free_thresh - 1)))
1263                         /* Prefetch next mbuf */
1264                         rte_prefetch0(rxep[i + 1].mbuf);
1265
1266                 mb = rxep[i].mbuf;
1267                 rte_mbuf_refcnt_set(mb, 1);
1268                 mb->next = NULL;
1269                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1270                 mb->nb_segs = 1;
1271                 mb->port = rxq->port_id;
1272                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1273                 rxdp[i].read.hdr_addr = 0;
1274                 rxdp[i].read.pkt_addr = dma_addr;
1275         }
1276
1277         /* Update rx tail regsiter */
1278         rte_wmb();
1279         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1280
1281         rxq->rx_free_trigger =
1282                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1283         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1284                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1285
1286         return 0;
1287 }
1288
1289 static inline uint16_t
1290 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1291 {
1292         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1293         uint16_t nb_rx = 0;
1294         struct rte_eth_dev *dev;
1295
1296         if (!nb_pkts)
1297                 return 0;
1298
1299         if (rxq->rx_nb_avail)
1300                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1301
1302         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1303         rxq->rx_next_avail = 0;
1304         rxq->rx_nb_avail = nb_rx;
1305         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1306
1307         if (rxq->rx_tail > rxq->rx_free_trigger) {
1308                 if (ice_rx_alloc_bufs(rxq) != 0) {
1309                         uint16_t i, j;
1310
1311                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1312                         dev->data->rx_mbuf_alloc_failed +=
1313                                 rxq->rx_free_thresh;
1314                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1315                                    "port_id=%u, queue_id=%u",
1316                                    rxq->port_id, rxq->queue_id);
1317                         rxq->rx_nb_avail = 0;
1318                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1319                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1320                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1321
1322                         return 0;
1323                 }
1324         }
1325
1326         if (rxq->rx_tail >= rxq->nb_rx_desc)
1327                 rxq->rx_tail = 0;
1328
1329         if (rxq->rx_nb_avail)
1330                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1331
1332         return 0;
1333 }
1334
1335 static uint16_t
1336 ice_recv_pkts_bulk_alloc(void *rx_queue,
1337                          struct rte_mbuf **rx_pkts,
1338                          uint16_t nb_pkts)
1339 {
1340         uint16_t nb_rx = 0;
1341         uint16_t n;
1342         uint16_t count;
1343
1344         if (unlikely(nb_pkts == 0))
1345                 return nb_rx;
1346
1347         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1348                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1349
1350         while (nb_pkts) {
1351                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1352                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1353                 nb_rx = (uint16_t)(nb_rx + count);
1354                 nb_pkts = (uint16_t)(nb_pkts - count);
1355                 if (count < n)
1356                         break;
1357         }
1358
1359         return nb_rx;
1360 }
1361 #else
1362 static uint16_t
1363 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1364                          struct rte_mbuf __rte_unused **rx_pkts,
1365                          uint16_t __rte_unused nb_pkts)
1366 {
1367         return 0;
1368 }
1369 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1370
1371 static uint16_t
1372 ice_recv_scattered_pkts(void *rx_queue,
1373                         struct rte_mbuf **rx_pkts,
1374                         uint16_t nb_pkts)
1375 {
1376         struct ice_rx_queue *rxq = rx_queue;
1377         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1378         volatile union ice_rx_flex_desc *rxdp;
1379         union ice_rx_flex_desc rxd;
1380         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1381         struct ice_rx_entry *rxe;
1382         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1383         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1384         struct rte_mbuf *nmb; /* new allocated mbuf */
1385         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1386         uint16_t rx_id = rxq->rx_tail;
1387         uint16_t nb_rx = 0;
1388         uint16_t nb_hold = 0;
1389         uint16_t rx_packet_len;
1390         uint16_t rx_stat_err0;
1391         uint64_t dma_addr;
1392         uint64_t pkt_flags;
1393         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1394         struct rte_eth_dev *dev;
1395
1396         while (nb_rx < nb_pkts) {
1397                 rxdp = &rx_ring[rx_id];
1398                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1399
1400                 /* Check the DD bit first */
1401                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1402                         break;
1403
1404                 /* allocate mbuf */
1405                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1406                 if (unlikely(!nmb)) {
1407                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1408                         dev->data->rx_mbuf_alloc_failed++;
1409                         break;
1410                 }
1411                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1412
1413                 nb_hold++;
1414                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1415                 rx_id++;
1416                 if (unlikely(rx_id == rxq->nb_rx_desc))
1417                         rx_id = 0;
1418
1419                 /* Prefetch next mbuf */
1420                 rte_prefetch0(sw_ring[rx_id].mbuf);
1421
1422                 /**
1423                  * When next RX descriptor is on a cache line boundary,
1424                  * prefetch the next 4 RX descriptors and next 8 pointers
1425                  * to mbufs.
1426                  */
1427                 if ((rx_id & 0x3) == 0) {
1428                         rte_prefetch0(&rx_ring[rx_id]);
1429                         rte_prefetch0(&sw_ring[rx_id]);
1430                 }
1431
1432                 rxm = rxe->mbuf;
1433                 rxe->mbuf = nmb;
1434                 dma_addr =
1435                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1436
1437                 /* Set data buffer address and data length of the mbuf */
1438                 rxdp->read.hdr_addr = 0;
1439                 rxdp->read.pkt_addr = dma_addr;
1440                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1441                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1442                 rxm->data_len = rx_packet_len;
1443                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1444
1445                 /**
1446                  * If this is the first buffer of the received packet, set the
1447                  * pointer to the first mbuf of the packet and initialize its
1448                  * context. Otherwise, update the total length and the number
1449                  * of segments of the current scattered packet, and update the
1450                  * pointer to the last mbuf of the current packet.
1451                  */
1452                 if (!first_seg) {
1453                         first_seg = rxm;
1454                         first_seg->nb_segs = 1;
1455                         first_seg->pkt_len = rx_packet_len;
1456                 } else {
1457                         first_seg->pkt_len =
1458                                 (uint16_t)(first_seg->pkt_len +
1459                                            rx_packet_len);
1460                         first_seg->nb_segs++;
1461                         last_seg->next = rxm;
1462                 }
1463
1464                 /**
1465                  * If this is not the last buffer of the received packet,
1466                  * update the pointer to the last mbuf of the current scattered
1467                  * packet and continue to parse the RX ring.
1468                  */
1469                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1470                         last_seg = rxm;
1471                         continue;
1472                 }
1473
1474                 /**
1475                  * This is the last buffer of the received packet. If the CRC
1476                  * is not stripped by the hardware:
1477                  *  - Subtract the CRC length from the total packet length.
1478                  *  - If the last buffer only contains the whole CRC or a part
1479                  *  of it, free the mbuf associated to the last buffer. If part
1480                  *  of the CRC is also contained in the previous mbuf, subtract
1481                  *  the length of that CRC part from the data length of the
1482                  *  previous mbuf.
1483                  */
1484                 rxm->next = NULL;
1485                 if (unlikely(rxq->crc_len > 0)) {
1486                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1487                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1488                                 rte_pktmbuf_free_seg(rxm);
1489                                 first_seg->nb_segs--;
1490                                 last_seg->data_len =
1491                                         (uint16_t)(last_seg->data_len -
1492                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1493                                 last_seg->next = NULL;
1494                         } else
1495                                 rxm->data_len = (uint16_t)(rx_packet_len -
1496                                                            RTE_ETHER_CRC_LEN);
1497                 }
1498
1499                 first_seg->port = rxq->port_id;
1500                 first_seg->ol_flags = 0;
1501                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1502                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1503                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1504                 ice_rxd_to_pkt_fields(first_seg, &rxd);
1505                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1506                 first_seg->ol_flags |= pkt_flags;
1507                 /* Prefetch data of first segment, if configured to do so. */
1508                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1509                                           first_seg->data_off));
1510                 rx_pkts[nb_rx++] = first_seg;
1511                 first_seg = NULL;
1512         }
1513
1514         /* Record index of the next RX descriptor to probe. */
1515         rxq->rx_tail = rx_id;
1516         rxq->pkt_first_seg = first_seg;
1517         rxq->pkt_last_seg = last_seg;
1518
1519         /**
1520          * If the number of free RX descriptors is greater than the RX free
1521          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1522          * register. Update the RDT with the value of the last processed RX
1523          * descriptor minus 1, to guarantee that the RDT register is never
1524          * equal to the RDH register, which creates a "full" ring situtation
1525          * from the hardware point of view.
1526          */
1527         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1528         if (nb_hold > rxq->rx_free_thresh) {
1529                 rx_id = (uint16_t)(rx_id == 0 ?
1530                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1531                 /* write TAIL register */
1532                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1533                 nb_hold = 0;
1534         }
1535         rxq->nb_rx_hold = nb_hold;
1536
1537         /* return received packet in the burst */
1538         return nb_rx;
1539 }
1540
1541 const uint32_t *
1542 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1543 {
1544         static const uint32_t ptypes[] = {
1545                 /* refers to ice_get_default_pkt_type() */
1546                 RTE_PTYPE_L2_ETHER,
1547                 RTE_PTYPE_L2_ETHER_LLDP,
1548                 RTE_PTYPE_L2_ETHER_ARP,
1549                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1550                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1551                 RTE_PTYPE_L4_FRAG,
1552                 RTE_PTYPE_L4_ICMP,
1553                 RTE_PTYPE_L4_NONFRAG,
1554                 RTE_PTYPE_L4_SCTP,
1555                 RTE_PTYPE_L4_TCP,
1556                 RTE_PTYPE_L4_UDP,
1557                 RTE_PTYPE_TUNNEL_GRENAT,
1558                 RTE_PTYPE_TUNNEL_IP,
1559                 RTE_PTYPE_INNER_L2_ETHER,
1560                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1561                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1562                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1563                 RTE_PTYPE_INNER_L4_FRAG,
1564                 RTE_PTYPE_INNER_L4_ICMP,
1565                 RTE_PTYPE_INNER_L4_NONFRAG,
1566                 RTE_PTYPE_INNER_L4_SCTP,
1567                 RTE_PTYPE_INNER_L4_TCP,
1568                 RTE_PTYPE_INNER_L4_UDP,
1569                 RTE_PTYPE_TUNNEL_GTPC,
1570                 RTE_PTYPE_TUNNEL_GTPU,
1571                 RTE_PTYPE_UNKNOWN
1572         };
1573
1574         if (dev->rx_pkt_burst == ice_recv_pkts ||
1575 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1576             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1577 #endif
1578             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1579                 return ptypes;
1580
1581 #ifdef RTE_ARCH_X86
1582         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1583             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1584             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1585             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1586                 return ptypes;
1587 #endif
1588
1589         return NULL;
1590 }
1591
1592 int
1593 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1594 {
1595         volatile union ice_rx_flex_desc *rxdp;
1596         struct ice_rx_queue *rxq = rx_queue;
1597         uint32_t desc;
1598
1599         if (unlikely(offset >= rxq->nb_rx_desc))
1600                 return -EINVAL;
1601
1602         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1603                 return RTE_ETH_RX_DESC_UNAVAIL;
1604
1605         desc = rxq->rx_tail + offset;
1606         if (desc >= rxq->nb_rx_desc)
1607                 desc -= rxq->nb_rx_desc;
1608
1609         rxdp = &rxq->rx_ring[desc];
1610         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1611             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1612                 return RTE_ETH_RX_DESC_DONE;
1613
1614         return RTE_ETH_RX_DESC_AVAIL;
1615 }
1616
1617 int
1618 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1619 {
1620         struct ice_tx_queue *txq = tx_queue;
1621         volatile uint64_t *status;
1622         uint64_t mask, expect;
1623         uint32_t desc;
1624
1625         if (unlikely(offset >= txq->nb_tx_desc))
1626                 return -EINVAL;
1627
1628         desc = txq->tx_tail + offset;
1629         /* go to next desc that has the RS bit */
1630         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1631                 txq->tx_rs_thresh;
1632         if (desc >= txq->nb_tx_desc) {
1633                 desc -= txq->nb_tx_desc;
1634                 if (desc >= txq->nb_tx_desc)
1635                         desc -= txq->nb_tx_desc;
1636         }
1637
1638         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1639         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1640         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1641                                   ICE_TXD_QW1_DTYPE_S);
1642         if ((*status & mask) == expect)
1643                 return RTE_ETH_TX_DESC_DONE;
1644
1645         return RTE_ETH_TX_DESC_FULL;
1646 }
1647
1648 void
1649 ice_clear_queues(struct rte_eth_dev *dev)
1650 {
1651         uint16_t i;
1652
1653         PMD_INIT_FUNC_TRACE();
1654
1655         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1656                 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1657                 ice_reset_tx_queue(dev->data->tx_queues[i]);
1658         }
1659
1660         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1661                 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1662                 ice_reset_rx_queue(dev->data->rx_queues[i]);
1663         }
1664 }
1665
1666 void
1667 ice_free_queues(struct rte_eth_dev *dev)
1668 {
1669         uint16_t i;
1670
1671         PMD_INIT_FUNC_TRACE();
1672
1673         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1674                 if (!dev->data->rx_queues[i])
1675                         continue;
1676                 ice_rx_queue_release(dev->data->rx_queues[i]);
1677                 dev->data->rx_queues[i] = NULL;
1678         }
1679         dev->data->nb_rx_queues = 0;
1680
1681         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1682                 if (!dev->data->tx_queues[i])
1683                         continue;
1684                 ice_tx_queue_release(dev->data->tx_queues[i]);
1685                 dev->data->tx_queues[i] = NULL;
1686         }
1687         dev->data->nb_tx_queues = 0;
1688 }
1689
1690 uint16_t
1691 ice_recv_pkts(void *rx_queue,
1692               struct rte_mbuf **rx_pkts,
1693               uint16_t nb_pkts)
1694 {
1695         struct ice_rx_queue *rxq = rx_queue;
1696         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1697         volatile union ice_rx_flex_desc *rxdp;
1698         union ice_rx_flex_desc rxd;
1699         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1700         struct ice_rx_entry *rxe;
1701         struct rte_mbuf *nmb; /* new allocated mbuf */
1702         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1703         uint16_t rx_id = rxq->rx_tail;
1704         uint16_t nb_rx = 0;
1705         uint16_t nb_hold = 0;
1706         uint16_t rx_packet_len;
1707         uint16_t rx_stat_err0;
1708         uint64_t dma_addr;
1709         uint64_t pkt_flags;
1710         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1711         struct rte_eth_dev *dev;
1712
1713         while (nb_rx < nb_pkts) {
1714                 rxdp = &rx_ring[rx_id];
1715                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1716
1717                 /* Check the DD bit first */
1718                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1719                         break;
1720
1721                 /* allocate mbuf */
1722                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1723                 if (unlikely(!nmb)) {
1724                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1725                         dev->data->rx_mbuf_alloc_failed++;
1726                         break;
1727                 }
1728                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1729
1730                 nb_hold++;
1731                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1732                 rx_id++;
1733                 if (unlikely(rx_id == rxq->nb_rx_desc))
1734                         rx_id = 0;
1735                 rxm = rxe->mbuf;
1736                 rxe->mbuf = nmb;
1737                 dma_addr =
1738                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1739
1740                 /**
1741                  * fill the read format of descriptor with physic address in
1742                  * new allocated mbuf: nmb
1743                  */
1744                 rxdp->read.hdr_addr = 0;
1745                 rxdp->read.pkt_addr = dma_addr;
1746
1747                 /* calculate rx_packet_len of the received pkt */
1748                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1749                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1750
1751                 /* fill old mbuf with received descriptor: rxd */
1752                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1753                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1754                 rxm->nb_segs = 1;
1755                 rxm->next = NULL;
1756                 rxm->pkt_len = rx_packet_len;
1757                 rxm->data_len = rx_packet_len;
1758                 rxm->port = rxq->port_id;
1759                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1760                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1761                 ice_rxd_to_vlan_tci(rxm, &rxd);
1762                 ice_rxd_to_pkt_fields(rxm, &rxd);
1763                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1764                 rxm->ol_flags |= pkt_flags;
1765                 /* copy old mbuf to rx_pkts */
1766                 rx_pkts[nb_rx++] = rxm;
1767         }
1768         rxq->rx_tail = rx_id;
1769         /**
1770          * If the number of free RX descriptors is greater than the RX free
1771          * threshold of the queue, advance the receive tail register of queue.
1772          * Update that register with the value of the last processed RX
1773          * descriptor minus 1.
1774          */
1775         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1776         if (nb_hold > rxq->rx_free_thresh) {
1777                 rx_id = (uint16_t)(rx_id == 0 ?
1778                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1779                 /* write TAIL register */
1780                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1781                 nb_hold = 0;
1782         }
1783         rxq->nb_rx_hold = nb_hold;
1784
1785         /* return received packet in the burst */
1786         return nb_rx;
1787 }
1788
1789 static inline void
1790 ice_parse_tunneling_params(uint64_t ol_flags,
1791                             union ice_tx_offload tx_offload,
1792                             uint32_t *cd_tunneling)
1793 {
1794         /* EIPT: External (outer) IP header type */
1795         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
1796                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
1797         else if (ol_flags & PKT_TX_OUTER_IPV4)
1798                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
1799         else if (ol_flags & PKT_TX_OUTER_IPV6)
1800                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
1801
1802         /* EIPLEN: External (outer) IP header length, in DWords */
1803         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
1804                 ICE_TXD_CTX_QW0_EIPLEN_S;
1805
1806         /* L4TUNT: L4 Tunneling Type */
1807         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
1808         case PKT_TX_TUNNEL_IPIP:
1809                 /* for non UDP / GRE tunneling, set to 00b */
1810                 break;
1811         case PKT_TX_TUNNEL_VXLAN:
1812         case PKT_TX_TUNNEL_GENEVE:
1813                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
1814                 break;
1815         case PKT_TX_TUNNEL_GRE:
1816                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
1817                 break;
1818         default:
1819                 PMD_TX_LOG(ERR, "Tunnel type not supported");
1820                 return;
1821         }
1822
1823         /* L4TUNLEN: L4 Tunneling Length, in Words
1824          *
1825          * We depend on app to set rte_mbuf.l2_len correctly.
1826          * For IP in GRE it should be set to the length of the GRE
1827          * header;
1828          * For MAC in GRE or MAC in UDP it should be set to the length
1829          * of the GRE or UDP headers plus the inner MAC up to including
1830          * its last Ethertype.
1831          * If MPLS labels exists, it should include them as well.
1832          */
1833         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
1834                 ICE_TXD_CTX_QW0_NATLEN_S;
1835
1836         if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
1837             (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
1838             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
1839                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
1840 }
1841
1842 static inline void
1843 ice_txd_enable_checksum(uint64_t ol_flags,
1844                         uint32_t *td_cmd,
1845                         uint32_t *td_offset,
1846                         union ice_tx_offload tx_offload)
1847 {
1848         /* Set MACLEN */
1849         if (ol_flags & PKT_TX_TUNNEL_MASK)
1850                 *td_offset |= (tx_offload.outer_l2_len >> 1)
1851                         << ICE_TX_DESC_LEN_MACLEN_S;
1852         else
1853                 *td_offset |= (tx_offload.l2_len >> 1)
1854                         << ICE_TX_DESC_LEN_MACLEN_S;
1855
1856         /* Enable L3 checksum offloads */
1857         if (ol_flags & PKT_TX_IP_CKSUM) {
1858                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1859                 *td_offset |= (tx_offload.l3_len >> 2) <<
1860                               ICE_TX_DESC_LEN_IPLEN_S;
1861         } else if (ol_flags & PKT_TX_IPV4) {
1862                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1863                 *td_offset |= (tx_offload.l3_len >> 2) <<
1864                               ICE_TX_DESC_LEN_IPLEN_S;
1865         } else if (ol_flags & PKT_TX_IPV6) {
1866                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1867                 *td_offset |= (tx_offload.l3_len >> 2) <<
1868                               ICE_TX_DESC_LEN_IPLEN_S;
1869         }
1870
1871         if (ol_flags & PKT_TX_TCP_SEG) {
1872                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1873                 *td_offset |= (tx_offload.l4_len >> 2) <<
1874                               ICE_TX_DESC_LEN_L4_LEN_S;
1875                 return;
1876         }
1877
1878         /* Enable L4 checksum offloads */
1879         switch (ol_flags & PKT_TX_L4_MASK) {
1880         case PKT_TX_TCP_CKSUM:
1881                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1882                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
1883                               ICE_TX_DESC_LEN_L4_LEN_S;
1884                 break;
1885         case PKT_TX_SCTP_CKSUM:
1886                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1887                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
1888                               ICE_TX_DESC_LEN_L4_LEN_S;
1889                 break;
1890         case PKT_TX_UDP_CKSUM:
1891                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1892                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
1893                               ICE_TX_DESC_LEN_L4_LEN_S;
1894                 break;
1895         default:
1896                 break;
1897         }
1898 }
1899
1900 static inline int
1901 ice_xmit_cleanup(struct ice_tx_queue *txq)
1902 {
1903         struct ice_tx_entry *sw_ring = txq->sw_ring;
1904         volatile struct ice_tx_desc *txd = txq->tx_ring;
1905         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1906         uint16_t nb_tx_desc = txq->nb_tx_desc;
1907         uint16_t desc_to_clean_to;
1908         uint16_t nb_tx_to_clean;
1909
1910         /* Determine the last descriptor needing to be cleaned */
1911         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1912         if (desc_to_clean_to >= nb_tx_desc)
1913                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1914
1915         /* Check to make sure the last descriptor to clean is done */
1916         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1917         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
1918             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
1919                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1920                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
1921                                 desc_to_clean_to,
1922                                 txq->port_id, txq->queue_id,
1923                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
1924                 /* Failed to clean any descriptors */
1925                 return -1;
1926         }
1927
1928         /* Figure out how many descriptors will be cleaned */
1929         if (last_desc_cleaned > desc_to_clean_to)
1930                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1931                                             desc_to_clean_to);
1932         else
1933                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1934                                             last_desc_cleaned);
1935
1936         /* The last descriptor to clean is done, so that means all the
1937          * descriptors from the last descriptor that was cleaned
1938          * up to the last descriptor with the RS bit set
1939          * are done. Only reset the threshold descriptor.
1940          */
1941         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1942
1943         /* Update the txq to reflect the last descriptor that was cleaned */
1944         txq->last_desc_cleaned = desc_to_clean_to;
1945         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1946
1947         return 0;
1948 }
1949
1950 /* Construct the tx flags */
1951 static inline uint64_t
1952 ice_build_ctob(uint32_t td_cmd,
1953                uint32_t td_offset,
1954                uint16_t size,
1955                uint32_t td_tag)
1956 {
1957         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1958                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
1959                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1960                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
1961                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
1962 }
1963
1964 /* Check if the context descriptor is needed for TX offloading */
1965 static inline uint16_t
1966 ice_calc_context_desc(uint64_t flags)
1967 {
1968         static uint64_t mask = PKT_TX_TCP_SEG |
1969                 PKT_TX_QINQ |
1970                 PKT_TX_OUTER_IP_CKSUM |
1971                 PKT_TX_TUNNEL_MASK;
1972
1973         return (flags & mask) ? 1 : 0;
1974 }
1975
1976 /* set ice TSO context descriptor */
1977 static inline uint64_t
1978 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
1979 {
1980         uint64_t ctx_desc = 0;
1981         uint32_t cd_cmd, hdr_len, cd_tso_len;
1982
1983         if (!tx_offload.l4_len) {
1984                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1985                 return ctx_desc;
1986         }
1987
1988         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1989         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
1990                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1991
1992         cd_cmd = ICE_TX_CTX_DESC_TSO;
1993         cd_tso_len = mbuf->pkt_len - hdr_len;
1994         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
1995                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1996                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
1997
1998         return ctx_desc;
1999 }
2000
2001 uint16_t
2002 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2003 {
2004         struct ice_tx_queue *txq;
2005         volatile struct ice_tx_desc *tx_ring;
2006         volatile struct ice_tx_desc *txd;
2007         struct ice_tx_entry *sw_ring;
2008         struct ice_tx_entry *txe, *txn;
2009         struct rte_mbuf *tx_pkt;
2010         struct rte_mbuf *m_seg;
2011         uint32_t cd_tunneling_params;
2012         uint16_t tx_id;
2013         uint16_t nb_tx;
2014         uint16_t nb_used;
2015         uint16_t nb_ctx;
2016         uint32_t td_cmd = 0;
2017         uint32_t td_offset = 0;
2018         uint32_t td_tag = 0;
2019         uint16_t tx_last;
2020         uint64_t buf_dma_addr;
2021         uint64_t ol_flags;
2022         union ice_tx_offload tx_offload = {0};
2023
2024         txq = tx_queue;
2025         sw_ring = txq->sw_ring;
2026         tx_ring = txq->tx_ring;
2027         tx_id = txq->tx_tail;
2028         txe = &sw_ring[tx_id];
2029
2030         /* Check if the descriptor ring needs to be cleaned. */
2031         if (txq->nb_tx_free < txq->tx_free_thresh)
2032                 ice_xmit_cleanup(txq);
2033
2034         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2035                 tx_pkt = *tx_pkts++;
2036
2037                 td_cmd = 0;
2038                 ol_flags = tx_pkt->ol_flags;
2039                 tx_offload.l2_len = tx_pkt->l2_len;
2040                 tx_offload.l3_len = tx_pkt->l3_len;
2041                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2042                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2043                 tx_offload.l4_len = tx_pkt->l4_len;
2044                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2045                 /* Calculate the number of context descriptors needed. */
2046                 nb_ctx = ice_calc_context_desc(ol_flags);
2047
2048                 /* The number of descriptors that must be allocated for
2049                  * a packet equals to the number of the segments of that
2050                  * packet plus the number of context descriptor if needed.
2051                  */
2052                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2053                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2054
2055                 /* Circular ring */
2056                 if (tx_last >= txq->nb_tx_desc)
2057                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2058
2059                 if (nb_used > txq->nb_tx_free) {
2060                         if (ice_xmit_cleanup(txq) != 0) {
2061                                 if (nb_tx == 0)
2062                                         return 0;
2063                                 goto end_of_tx;
2064                         }
2065                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2066                                 while (nb_used > txq->nb_tx_free) {
2067                                         if (ice_xmit_cleanup(txq) != 0) {
2068                                                 if (nb_tx == 0)
2069                                                         return 0;
2070                                                 goto end_of_tx;
2071                                         }
2072                                 }
2073                         }
2074                 }
2075
2076                 /* Descriptor based VLAN insertion */
2077                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2078                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2079                         td_tag = tx_pkt->vlan_tci;
2080                 }
2081
2082                 /* Fill in tunneling parameters if necessary */
2083                 cd_tunneling_params = 0;
2084                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2085                         ice_parse_tunneling_params(ol_flags, tx_offload,
2086                                                    &cd_tunneling_params);
2087
2088                 /* Enable checksum offloading */
2089                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
2090                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2091                                                 &td_offset, tx_offload);
2092                 }
2093
2094                 if (nb_ctx) {
2095                         /* Setup TX context descriptor if required */
2096                         volatile struct ice_tx_ctx_desc *ctx_txd =
2097                                 (volatile struct ice_tx_ctx_desc *)
2098                                         &tx_ring[tx_id];
2099                         uint16_t cd_l2tag2 = 0;
2100                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2101
2102                         txn = &sw_ring[txe->next_id];
2103                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2104                         if (txe->mbuf) {
2105                                 rte_pktmbuf_free_seg(txe->mbuf);
2106                                 txe->mbuf = NULL;
2107                         }
2108
2109                         if (ol_flags & PKT_TX_TCP_SEG)
2110                                 cd_type_cmd_tso_mss |=
2111                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2112
2113                         ctx_txd->tunneling_params =
2114                                 rte_cpu_to_le_32(cd_tunneling_params);
2115
2116                         /* TX context descriptor based double VLAN insert */
2117                         if (ol_flags & PKT_TX_QINQ) {
2118                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2119                                 cd_type_cmd_tso_mss |=
2120                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2121                                          ICE_TXD_CTX_QW1_CMD_S);
2122                         }
2123                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2124                         ctx_txd->qw1 =
2125                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2126
2127                         txe->last_id = tx_last;
2128                         tx_id = txe->next_id;
2129                         txe = txn;
2130                 }
2131                 m_seg = tx_pkt;
2132
2133                 do {
2134                         txd = &tx_ring[tx_id];
2135                         txn = &sw_ring[txe->next_id];
2136
2137                         if (txe->mbuf)
2138                                 rte_pktmbuf_free_seg(txe->mbuf);
2139                         txe->mbuf = m_seg;
2140
2141                         /* Setup TX Descriptor */
2142                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2143                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2144                         txd->cmd_type_offset_bsz =
2145                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2146                                 ((uint64_t)td_cmd  << ICE_TXD_QW1_CMD_S) |
2147                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2148                                 ((uint64_t)m_seg->data_len  <<
2149                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2150                                 ((uint64_t)td_tag  << ICE_TXD_QW1_L2TAG1_S));
2151
2152                         txe->last_id = tx_last;
2153                         tx_id = txe->next_id;
2154                         txe = txn;
2155                         m_seg = m_seg->next;
2156                 } while (m_seg);
2157
2158                 /* fill the last descriptor with End of Packet (EOP) bit */
2159                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2160                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2161                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2162
2163                 /* set RS bit on the last descriptor of one packet */
2164                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2165                         PMD_TX_FREE_LOG(DEBUG,
2166                                         "Setting RS bit on TXD id="
2167                                         "%4u (port=%d queue=%d)",
2168                                         tx_last, txq->port_id, txq->queue_id);
2169
2170                         td_cmd |= ICE_TX_DESC_CMD_RS;
2171
2172                         /* Update txq RS bit counters */
2173                         txq->nb_tx_used = 0;
2174                 }
2175                 txd->cmd_type_offset_bsz |=
2176                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2177                                          ICE_TXD_QW1_CMD_S);
2178         }
2179 end_of_tx:
2180         rte_wmb();
2181
2182         /* update Tail register */
2183         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2184         txq->tx_tail = tx_id;
2185
2186         return nb_tx;
2187 }
2188
2189 static inline int __attribute__((always_inline))
2190 ice_tx_free_bufs(struct ice_tx_queue *txq)
2191 {
2192         struct ice_tx_entry *txep;
2193         uint16_t i;
2194
2195         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2196              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2197             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2198                 return 0;
2199
2200         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2201
2202         for (i = 0; i < txq->tx_rs_thresh; i++)
2203                 rte_prefetch0((txep + i)->mbuf);
2204
2205         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2206                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2207                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2208                         txep->mbuf = NULL;
2209                 }
2210         } else {
2211                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2212                         rte_pktmbuf_free_seg(txep->mbuf);
2213                         txep->mbuf = NULL;
2214                 }
2215         }
2216
2217         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2218         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2219         if (txq->tx_next_dd >= txq->nb_tx_desc)
2220                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2221
2222         return txq->tx_rs_thresh;
2223 }
2224
2225 /* Populate 4 descriptors with data from 4 mbufs */
2226 static inline void
2227 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2228 {
2229         uint64_t dma_addr;
2230         uint32_t i;
2231
2232         for (i = 0; i < 4; i++, txdp++, pkts++) {
2233                 dma_addr = rte_mbuf_data_iova(*pkts);
2234                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2235                 txdp->cmd_type_offset_bsz =
2236                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2237                                        (*pkts)->data_len, 0);
2238         }
2239 }
2240
2241 /* Populate 1 descriptor with data from 1 mbuf */
2242 static inline void
2243 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2244 {
2245         uint64_t dma_addr;
2246
2247         dma_addr = rte_mbuf_data_iova(*pkts);
2248         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2249         txdp->cmd_type_offset_bsz =
2250                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2251                                (*pkts)->data_len, 0);
2252 }
2253
2254 static inline void
2255 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2256                     uint16_t nb_pkts)
2257 {
2258         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2259         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2260         const int N_PER_LOOP = 4;
2261         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2262         int mainpart, leftover;
2263         int i, j;
2264
2265         /**
2266          * Process most of the packets in chunks of N pkts.  Any
2267          * leftover packets will get processed one at a time.
2268          */
2269         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2270         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2271         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2272                 /* Copy N mbuf pointers to the S/W ring */
2273                 for (j = 0; j < N_PER_LOOP; ++j)
2274                         (txep + i + j)->mbuf = *(pkts + i + j);
2275                 tx4(txdp + i, pkts + i);
2276         }
2277
2278         if (unlikely(leftover > 0)) {
2279                 for (i = 0; i < leftover; ++i) {
2280                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2281                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2282                 }
2283         }
2284 }
2285
2286 static inline uint16_t
2287 tx_xmit_pkts(struct ice_tx_queue *txq,
2288              struct rte_mbuf **tx_pkts,
2289              uint16_t nb_pkts)
2290 {
2291         volatile struct ice_tx_desc *txr = txq->tx_ring;
2292         uint16_t n = 0;
2293
2294         /**
2295          * Begin scanning the H/W ring for done descriptors when the number
2296          * of available descriptors drops below tx_free_thresh. For each done
2297          * descriptor, free the associated buffer.
2298          */
2299         if (txq->nb_tx_free < txq->tx_free_thresh)
2300                 ice_tx_free_bufs(txq);
2301
2302         /* Use available descriptor only */
2303         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2304         if (unlikely(!nb_pkts))
2305                 return 0;
2306
2307         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2308         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2309                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2310                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2311                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2312                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2313                                          ICE_TXD_QW1_CMD_S);
2314                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2315                 txq->tx_tail = 0;
2316         }
2317
2318         /* Fill hardware descriptor ring with mbuf data */
2319         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2320         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2321
2322         /* Determin if RS bit needs to be set */
2323         if (txq->tx_tail > txq->tx_next_rs) {
2324                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2325                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2326                                          ICE_TXD_QW1_CMD_S);
2327                 txq->tx_next_rs =
2328                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2329                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2330                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2331         }
2332
2333         if (txq->tx_tail >= txq->nb_tx_desc)
2334                 txq->tx_tail = 0;
2335
2336         /* Update the tx tail register */
2337         rte_wmb();
2338         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2339
2340         return nb_pkts;
2341 }
2342
2343 static uint16_t
2344 ice_xmit_pkts_simple(void *tx_queue,
2345                      struct rte_mbuf **tx_pkts,
2346                      uint16_t nb_pkts)
2347 {
2348         uint16_t nb_tx = 0;
2349
2350         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2351                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2352                                     tx_pkts, nb_pkts);
2353
2354         while (nb_pkts) {
2355                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2356                                                       ICE_TX_MAX_BURST);
2357
2358                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2359                                    &tx_pkts[nb_tx], num);
2360                 nb_tx = (uint16_t)(nb_tx + ret);
2361                 nb_pkts = (uint16_t)(nb_pkts - ret);
2362                 if (ret < num)
2363                         break;
2364         }
2365
2366         return nb_tx;
2367 }
2368
2369 void __attribute__((cold))
2370 ice_set_rx_function(struct rte_eth_dev *dev)
2371 {
2372         PMD_INIT_FUNC_TRACE();
2373         struct ice_adapter *ad =
2374                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2375 #ifdef RTE_ARCH_X86
2376         struct ice_rx_queue *rxq;
2377         int i;
2378         bool use_avx2 = false;
2379
2380         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2381                 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
2382                         ad->rx_vec_allowed = true;
2383                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2384                                 rxq = dev->data->rx_queues[i];
2385                                 if (rxq && ice_rxq_vec_setup(rxq)) {
2386                                         ad->rx_vec_allowed = false;
2387                                         break;
2388                                 }
2389                         }
2390
2391                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2392                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2393                                 use_avx2 = true;
2394
2395                 } else {
2396                         ad->rx_vec_allowed = false;
2397                 }
2398         }
2399
2400         if (ad->rx_vec_allowed) {
2401                 if (dev->data->scattered_rx) {
2402                         PMD_DRV_LOG(DEBUG,
2403                                         "Using %sVector Scattered Rx (port %d).",
2404                                         use_avx2 ? "avx2 " : "",
2405                                         dev->data->port_id);
2406                         dev->rx_pkt_burst = use_avx2 ?
2407                                         ice_recv_scattered_pkts_vec_avx2 :
2408                                         ice_recv_scattered_pkts_vec;
2409                 } else {
2410                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2411                                         use_avx2 ? "avx2 " : "",
2412                                         dev->data->port_id);
2413                         dev->rx_pkt_burst = use_avx2 ?
2414                                                 ice_recv_pkts_vec_avx2 :
2415                                                 ice_recv_pkts_vec;
2416                 }
2417                 return;
2418         }
2419
2420 #endif
2421
2422         if (dev->data->scattered_rx) {
2423                 /* Set the non-LRO scattered function */
2424                 PMD_INIT_LOG(DEBUG,
2425                              "Using a Scattered function on port %d.",
2426                              dev->data->port_id);
2427                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2428         } else if (ad->rx_bulk_alloc_allowed) {
2429                 PMD_INIT_LOG(DEBUG,
2430                              "Rx Burst Bulk Alloc Preconditions are "
2431                              "satisfied. Rx Burst Bulk Alloc function "
2432                              "will be used on port %d.",
2433                              dev->data->port_id);
2434                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2435         } else {
2436                 PMD_INIT_LOG(DEBUG,
2437                              "Rx Burst Bulk Alloc Preconditions are not "
2438                              "satisfied, Normal Rx will be used on port %d.",
2439                              dev->data->port_id);
2440                 dev->rx_pkt_burst = ice_recv_pkts;
2441         }
2442 }
2443
2444 void __attribute__((cold))
2445 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
2446 {
2447         struct ice_adapter *ad =
2448                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2449
2450         /* Use a simple Tx queue if possible (only fast free is allowed) */
2451         ad->tx_simple_allowed =
2452                 (txq->offloads ==
2453                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
2454                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
2455
2456         if (ad->tx_simple_allowed)
2457                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
2458                              txq->queue_id);
2459         else
2460                 PMD_INIT_LOG(DEBUG,
2461                              "Simple Tx can NOT be enabled on Tx queue %u.",
2462                              txq->queue_id);
2463 }
2464
2465 /*********************************************************************
2466  *
2467  *  TX prep functions
2468  *
2469  **********************************************************************/
2470 /* The default values of TSO MSS */
2471 #define ICE_MIN_TSO_MSS            64
2472 #define ICE_MAX_TSO_MSS            9728
2473 #define ICE_MAX_TSO_FRAME_SIZE     262144
2474 uint16_t
2475 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2476               uint16_t nb_pkts)
2477 {
2478         int i, ret;
2479         uint64_t ol_flags;
2480         struct rte_mbuf *m;
2481
2482         for (i = 0; i < nb_pkts; i++) {
2483                 m = tx_pkts[i];
2484                 ol_flags = m->ol_flags;
2485
2486                 if (ol_flags & PKT_TX_TCP_SEG &&
2487                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
2488                      m->tso_segsz > ICE_MAX_TSO_MSS ||
2489                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
2490                         /**
2491                          * MSS outside the range are considered malicious
2492                          */
2493                         rte_errno = EINVAL;
2494                         return i;
2495                 }
2496
2497 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2498                 ret = rte_validate_tx_offload(m);
2499                 if (ret != 0) {
2500                         rte_errno = -ret;
2501                         return i;
2502                 }
2503 #endif
2504                 ret = rte_net_intel_cksum_prepare(m);
2505                 if (ret != 0) {
2506                         rte_errno = -ret;
2507                         return i;
2508                 }
2509         }
2510         return i;
2511 }
2512
2513 void __attribute__((cold))
2514 ice_set_tx_function(struct rte_eth_dev *dev)
2515 {
2516         struct ice_adapter *ad =
2517                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2518 #ifdef RTE_ARCH_X86
2519         struct ice_tx_queue *txq;
2520         int i;
2521         bool use_avx2 = false;
2522
2523         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2524                 if (!ice_tx_vec_dev_check(dev)) {
2525                         ad->tx_vec_allowed = true;
2526                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2527                                 txq = dev->data->tx_queues[i];
2528                                 if (txq && ice_txq_vec_setup(txq)) {
2529                                         ad->tx_vec_allowed = false;
2530                                         break;
2531                                 }
2532                         }
2533
2534                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2535                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2536                                 use_avx2 = true;
2537
2538                 } else {
2539                         ad->tx_vec_allowed = false;
2540                 }
2541         }
2542
2543         if (ad->tx_vec_allowed) {
2544                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2545                             use_avx2 ? "avx2 " : "",
2546                             dev->data->port_id);
2547                 dev->tx_pkt_burst = use_avx2 ?
2548                                     ice_xmit_pkts_vec_avx2 :
2549                                     ice_xmit_pkts_vec;
2550                 dev->tx_pkt_prepare = NULL;
2551
2552                 return;
2553         }
2554 #endif
2555
2556         if (ad->tx_simple_allowed) {
2557                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2558                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
2559                 dev->tx_pkt_prepare = NULL;
2560         } else {
2561                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
2562                 dev->tx_pkt_burst = ice_xmit_pkts;
2563                 dev->tx_pkt_prepare = ice_prep_pkts;
2564         }
2565 }
2566
2567 /* For each value it means, datasheet of hardware can tell more details
2568  *
2569  * @note: fix ice_dev_supported_ptypes_get() if any change here.
2570  */
2571 static inline uint32_t
2572 ice_get_default_pkt_type(uint16_t ptype)
2573 {
2574         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
2575                 __rte_cache_aligned = {
2576                 /* L2 types */
2577                 /* [0] reserved */
2578                 [1] = RTE_PTYPE_L2_ETHER,
2579                 /* [2] - [5] reserved */
2580                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2581                 /* [7] - [10] reserved */
2582                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2583                 /* [12] - [21] reserved */
2584
2585                 /* Non tunneled IPv4 */
2586                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2587                        RTE_PTYPE_L4_FRAG,
2588                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2589                        RTE_PTYPE_L4_NONFRAG,
2590                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2591                        RTE_PTYPE_L4_UDP,
2592                 /* [25] reserved */
2593                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2594                        RTE_PTYPE_L4_TCP,
2595                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2596                        RTE_PTYPE_L4_SCTP,
2597                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2598                        RTE_PTYPE_L4_ICMP,
2599
2600                 /* IPv4 --> IPv4 */
2601                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2602                        RTE_PTYPE_TUNNEL_IP |
2603                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2604                        RTE_PTYPE_INNER_L4_FRAG,
2605                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2606                        RTE_PTYPE_TUNNEL_IP |
2607                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2608                        RTE_PTYPE_INNER_L4_NONFRAG,
2609                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2610                        RTE_PTYPE_TUNNEL_IP |
2611                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2612                        RTE_PTYPE_INNER_L4_UDP,
2613                 /* [32] reserved */
2614                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2615                        RTE_PTYPE_TUNNEL_IP |
2616                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2617                        RTE_PTYPE_INNER_L4_TCP,
2618                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2619                        RTE_PTYPE_TUNNEL_IP |
2620                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2621                        RTE_PTYPE_INNER_L4_SCTP,
2622                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2623                        RTE_PTYPE_TUNNEL_IP |
2624                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2625                        RTE_PTYPE_INNER_L4_ICMP,
2626
2627                 /* IPv4 --> IPv6 */
2628                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2629                        RTE_PTYPE_TUNNEL_IP |
2630                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2631                        RTE_PTYPE_INNER_L4_FRAG,
2632                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2633                        RTE_PTYPE_TUNNEL_IP |
2634                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2635                        RTE_PTYPE_INNER_L4_NONFRAG,
2636                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2637                        RTE_PTYPE_TUNNEL_IP |
2638                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2639                        RTE_PTYPE_INNER_L4_UDP,
2640                 /* [39] reserved */
2641                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2642                        RTE_PTYPE_TUNNEL_IP |
2643                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2644                        RTE_PTYPE_INNER_L4_TCP,
2645                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2646                        RTE_PTYPE_TUNNEL_IP |
2647                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2648                        RTE_PTYPE_INNER_L4_SCTP,
2649                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2650                        RTE_PTYPE_TUNNEL_IP |
2651                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2652                        RTE_PTYPE_INNER_L4_ICMP,
2653
2654                 /* IPv4 --> GRE/Teredo/VXLAN */
2655                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2656                        RTE_PTYPE_TUNNEL_GRENAT,
2657
2658                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2659                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2660                        RTE_PTYPE_TUNNEL_GRENAT |
2661                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2662                        RTE_PTYPE_INNER_L4_FRAG,
2663                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2664                        RTE_PTYPE_TUNNEL_GRENAT |
2665                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2666                        RTE_PTYPE_INNER_L4_NONFRAG,
2667                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2668                        RTE_PTYPE_TUNNEL_GRENAT |
2669                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2670                        RTE_PTYPE_INNER_L4_UDP,
2671                 /* [47] reserved */
2672                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2673                        RTE_PTYPE_TUNNEL_GRENAT |
2674                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2675                        RTE_PTYPE_INNER_L4_TCP,
2676                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2677                        RTE_PTYPE_TUNNEL_GRENAT |
2678                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2679                        RTE_PTYPE_INNER_L4_SCTP,
2680                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2681                        RTE_PTYPE_TUNNEL_GRENAT |
2682                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2683                        RTE_PTYPE_INNER_L4_ICMP,
2684
2685                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2686                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2687                        RTE_PTYPE_TUNNEL_GRENAT |
2688                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2689                        RTE_PTYPE_INNER_L4_FRAG,
2690                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2691                        RTE_PTYPE_TUNNEL_GRENAT |
2692                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2693                        RTE_PTYPE_INNER_L4_NONFRAG,
2694                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2695                        RTE_PTYPE_TUNNEL_GRENAT |
2696                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2697                        RTE_PTYPE_INNER_L4_UDP,
2698                 /* [54] reserved */
2699                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2700                        RTE_PTYPE_TUNNEL_GRENAT |
2701                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2702                        RTE_PTYPE_INNER_L4_TCP,
2703                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2704                        RTE_PTYPE_TUNNEL_GRENAT |
2705                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2706                        RTE_PTYPE_INNER_L4_SCTP,
2707                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2708                        RTE_PTYPE_TUNNEL_GRENAT |
2709                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2710                        RTE_PTYPE_INNER_L4_ICMP,
2711
2712                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2713                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2714                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2715
2716                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2717                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2718                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2719                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2720                        RTE_PTYPE_INNER_L4_FRAG,
2721                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2722                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2723                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2724                        RTE_PTYPE_INNER_L4_NONFRAG,
2725                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2726                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2727                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2728                        RTE_PTYPE_INNER_L4_UDP,
2729                 /* [62] reserved */
2730                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2731                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2732                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2733                        RTE_PTYPE_INNER_L4_TCP,
2734                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2735                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2736                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2737                        RTE_PTYPE_INNER_L4_SCTP,
2738                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2739                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2740                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2741                        RTE_PTYPE_INNER_L4_ICMP,
2742
2743                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2744                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2745                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2746                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2747                        RTE_PTYPE_INNER_L4_FRAG,
2748                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2749                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2750                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2751                        RTE_PTYPE_INNER_L4_NONFRAG,
2752                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2753                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2754                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2755                        RTE_PTYPE_INNER_L4_UDP,
2756                 /* [69] reserved */
2757                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2758                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2759                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2760                        RTE_PTYPE_INNER_L4_TCP,
2761                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2762                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2763                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2764                        RTE_PTYPE_INNER_L4_SCTP,
2765                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2766                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2767                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2768                        RTE_PTYPE_INNER_L4_ICMP,
2769
2770                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2771                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2772                        RTE_PTYPE_TUNNEL_GRENAT |
2773                        RTE_PTYPE_INNER_L2_ETHER_VLAN,
2774
2775                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2776                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2777                        RTE_PTYPE_TUNNEL_GRENAT |
2778                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2779                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2780                        RTE_PTYPE_INNER_L4_FRAG,
2781                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2782                        RTE_PTYPE_TUNNEL_GRENAT |
2783                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2784                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2785                        RTE_PTYPE_INNER_L4_NONFRAG,
2786                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2787                        RTE_PTYPE_TUNNEL_GRENAT |
2788                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2789                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2790                        RTE_PTYPE_INNER_L4_UDP,
2791                 /* [77] reserved */
2792                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2793                        RTE_PTYPE_TUNNEL_GRENAT |
2794                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2795                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2796                        RTE_PTYPE_INNER_L4_TCP,
2797                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2798                        RTE_PTYPE_TUNNEL_GRENAT |
2799                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2800                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2801                        RTE_PTYPE_INNER_L4_SCTP,
2802                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2803                        RTE_PTYPE_TUNNEL_GRENAT |
2804                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2805                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2806                        RTE_PTYPE_INNER_L4_ICMP,
2807
2808                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2809                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2810                        RTE_PTYPE_TUNNEL_GRENAT |
2811                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2812                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2813                        RTE_PTYPE_INNER_L4_FRAG,
2814                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2815                        RTE_PTYPE_TUNNEL_GRENAT |
2816                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2817                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2818                        RTE_PTYPE_INNER_L4_NONFRAG,
2819                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2820                        RTE_PTYPE_TUNNEL_GRENAT |
2821                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2822                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2823                        RTE_PTYPE_INNER_L4_UDP,
2824                 /* [84] reserved */
2825                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2826                        RTE_PTYPE_TUNNEL_GRENAT |
2827                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2828                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2829                        RTE_PTYPE_INNER_L4_TCP,
2830                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2831                        RTE_PTYPE_TUNNEL_GRENAT |
2832                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2833                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2834                        RTE_PTYPE_INNER_L4_SCTP,
2835                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2836                        RTE_PTYPE_TUNNEL_GRENAT |
2837                        RTE_PTYPE_INNER_L2_ETHER_VLAN |
2838                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2839                        RTE_PTYPE_INNER_L4_ICMP,
2840
2841                 /* Non tunneled IPv6 */
2842                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2843                        RTE_PTYPE_L4_FRAG,
2844                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2845                        RTE_PTYPE_L4_NONFRAG,
2846                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2847                        RTE_PTYPE_L4_UDP,
2848                 /* [91] reserved */
2849                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2850                        RTE_PTYPE_L4_TCP,
2851                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2852                        RTE_PTYPE_L4_SCTP,
2853                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2854                        RTE_PTYPE_L4_ICMP,
2855
2856                 /* IPv6 --> IPv4 */
2857                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2858                        RTE_PTYPE_TUNNEL_IP |
2859                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2860                        RTE_PTYPE_INNER_L4_FRAG,
2861                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2862                        RTE_PTYPE_TUNNEL_IP |
2863                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2864                        RTE_PTYPE_INNER_L4_NONFRAG,
2865                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2866                        RTE_PTYPE_TUNNEL_IP |
2867                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2868                        RTE_PTYPE_INNER_L4_UDP,
2869                 /* [98] reserved */
2870                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2871                        RTE_PTYPE_TUNNEL_IP |
2872                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2873                        RTE_PTYPE_INNER_L4_TCP,
2874                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2875                         RTE_PTYPE_TUNNEL_IP |
2876                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2877                         RTE_PTYPE_INNER_L4_SCTP,
2878                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2879                         RTE_PTYPE_TUNNEL_IP |
2880                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2881                         RTE_PTYPE_INNER_L4_ICMP,
2882
2883                 /* IPv6 --> IPv6 */
2884                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2885                         RTE_PTYPE_TUNNEL_IP |
2886                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2887                         RTE_PTYPE_INNER_L4_FRAG,
2888                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2889                         RTE_PTYPE_TUNNEL_IP |
2890                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2891                         RTE_PTYPE_INNER_L4_NONFRAG,
2892                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2893                         RTE_PTYPE_TUNNEL_IP |
2894                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2895                         RTE_PTYPE_INNER_L4_UDP,
2896                 /* [105] reserved */
2897                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2898                         RTE_PTYPE_TUNNEL_IP |
2899                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2900                         RTE_PTYPE_INNER_L4_TCP,
2901                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2902                         RTE_PTYPE_TUNNEL_IP |
2903                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2904                         RTE_PTYPE_INNER_L4_SCTP,
2905                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2906                         RTE_PTYPE_TUNNEL_IP |
2907                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2908                         RTE_PTYPE_INNER_L4_ICMP,
2909
2910                 /* IPv6 --> GRE/Teredo/VXLAN */
2911                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2912                         RTE_PTYPE_TUNNEL_GRENAT,
2913
2914                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2915                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2916                         RTE_PTYPE_TUNNEL_GRENAT |
2917                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2918                         RTE_PTYPE_INNER_L4_FRAG,
2919                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2920                         RTE_PTYPE_TUNNEL_GRENAT |
2921                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2922                         RTE_PTYPE_INNER_L4_NONFRAG,
2923                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2924                         RTE_PTYPE_TUNNEL_GRENAT |
2925                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2926                         RTE_PTYPE_INNER_L4_UDP,
2927                 /* [113] reserved */
2928                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2929                         RTE_PTYPE_TUNNEL_GRENAT |
2930                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2931                         RTE_PTYPE_INNER_L4_TCP,
2932                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2933                         RTE_PTYPE_TUNNEL_GRENAT |
2934                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2935                         RTE_PTYPE_INNER_L4_SCTP,
2936                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2937                         RTE_PTYPE_TUNNEL_GRENAT |
2938                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2939                         RTE_PTYPE_INNER_L4_ICMP,
2940
2941                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2942                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2943                         RTE_PTYPE_TUNNEL_GRENAT |
2944                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2945                         RTE_PTYPE_INNER_L4_FRAG,
2946                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2947                         RTE_PTYPE_TUNNEL_GRENAT |
2948                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2949                         RTE_PTYPE_INNER_L4_NONFRAG,
2950                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2951                         RTE_PTYPE_TUNNEL_GRENAT |
2952                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2953                         RTE_PTYPE_INNER_L4_UDP,
2954                 /* [120] reserved */
2955                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2956                         RTE_PTYPE_TUNNEL_GRENAT |
2957                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2958                         RTE_PTYPE_INNER_L4_TCP,
2959                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2960                         RTE_PTYPE_TUNNEL_GRENAT |
2961                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2962                         RTE_PTYPE_INNER_L4_SCTP,
2963                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2964                         RTE_PTYPE_TUNNEL_GRENAT |
2965                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2966                         RTE_PTYPE_INNER_L4_ICMP,
2967
2968                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2969                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2970                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2971
2972                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2973                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2974                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2975                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2976                         RTE_PTYPE_INNER_L4_FRAG,
2977                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2978                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2979                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2980                         RTE_PTYPE_INNER_L4_NONFRAG,
2981                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2982                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2983                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2984                         RTE_PTYPE_INNER_L4_UDP,
2985                 /* [128] reserved */
2986                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2987                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2988                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2989                         RTE_PTYPE_INNER_L4_TCP,
2990                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2991                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2992                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2993                         RTE_PTYPE_INNER_L4_SCTP,
2994                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2995                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2996                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2997                         RTE_PTYPE_INNER_L4_ICMP,
2998
2999                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3000                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3001                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3002                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3003                         RTE_PTYPE_INNER_L4_FRAG,
3004                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3005                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3006                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3007                         RTE_PTYPE_INNER_L4_NONFRAG,
3008                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3009                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3010                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3011                         RTE_PTYPE_INNER_L4_UDP,
3012                 /* [135] reserved */
3013                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3014                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3015                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3016                         RTE_PTYPE_INNER_L4_TCP,
3017                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3018                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3019                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3020                         RTE_PTYPE_INNER_L4_SCTP,
3021                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3022                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3023                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3024                         RTE_PTYPE_INNER_L4_ICMP,
3025
3026                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
3027                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3028                         RTE_PTYPE_TUNNEL_GRENAT |
3029                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
3030
3031                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
3032                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3033                         RTE_PTYPE_TUNNEL_GRENAT |
3034                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3035                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3036                         RTE_PTYPE_INNER_L4_FRAG,
3037                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3038                         RTE_PTYPE_TUNNEL_GRENAT |
3039                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3040                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3041                         RTE_PTYPE_INNER_L4_NONFRAG,
3042                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3043                         RTE_PTYPE_TUNNEL_GRENAT |
3044                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3045                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3046                         RTE_PTYPE_INNER_L4_UDP,
3047                 /* [143] reserved */
3048                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3049                         RTE_PTYPE_TUNNEL_GRENAT |
3050                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3051                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3052                         RTE_PTYPE_INNER_L4_TCP,
3053                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3054                         RTE_PTYPE_TUNNEL_GRENAT |
3055                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3056                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3057                         RTE_PTYPE_INNER_L4_SCTP,
3058                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3059                         RTE_PTYPE_TUNNEL_GRENAT |
3060                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3061                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3062                         RTE_PTYPE_INNER_L4_ICMP,
3063
3064                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
3065                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3066                         RTE_PTYPE_TUNNEL_GRENAT |
3067                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3068                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3069                         RTE_PTYPE_INNER_L4_FRAG,
3070                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3071                         RTE_PTYPE_TUNNEL_GRENAT |
3072                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3073                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3074                         RTE_PTYPE_INNER_L4_NONFRAG,
3075                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3076                         RTE_PTYPE_TUNNEL_GRENAT |
3077                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3078                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3079                         RTE_PTYPE_INNER_L4_UDP,
3080                 /* [150] reserved */
3081                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3082                         RTE_PTYPE_TUNNEL_GRENAT |
3083                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3084                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3085                         RTE_PTYPE_INNER_L4_TCP,
3086                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3087                         RTE_PTYPE_TUNNEL_GRENAT |
3088                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3089                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3090                         RTE_PTYPE_INNER_L4_SCTP,
3091                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3092                         RTE_PTYPE_TUNNEL_GRENAT |
3093                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
3094                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3095                         RTE_PTYPE_INNER_L4_ICMP,
3096                 /* [154] - [255] reserved */
3097                 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3098                         RTE_PTYPE_TUNNEL_GTPC,
3099                 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3100                         RTE_PTYPE_TUNNEL_GTPC,
3101                 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3102                                 RTE_PTYPE_TUNNEL_GTPU,
3103                 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3104                                 RTE_PTYPE_TUNNEL_GTPU,
3105                 /* [260] - [263] reserved */
3106                 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3107                         RTE_PTYPE_TUNNEL_GTPC,
3108                 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3109                         RTE_PTYPE_TUNNEL_GTPC,
3110                 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3111                                 RTE_PTYPE_TUNNEL_GTPU,
3112                 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3113                                 RTE_PTYPE_TUNNEL_GTPU,
3114
3115                 /* All others reserved */
3116         };
3117
3118         return type_table[ptype];
3119 }
3120
3121 void __attribute__((cold))
3122 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3123 {
3124         struct ice_adapter *ad =
3125                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3126         int i;
3127
3128         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3129                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3130 }