drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <ethdev_driver.h>
   6 #include <rte_net.h>
   7 #include <rte_vect.h>
   8
   9 #include "rte_pmd_ice.h"
  10 #include "ice_rxtx.h"
  11 #include "ice_rxtx_vec_common.h"
  12
  13 #define ICE_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM |              \
  14                 RTE_MBUF_F_TX_L4_MASK |          \
  15                 RTE_MBUF_F_TX_TCP_SEG |          \
  16                 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
  17
  18 /* Offset of mbuf dynamic field for protocol extraction data */
  19 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  20
  21 /* Mask of mbuf dynamic flags for protocol extraction type */
  22 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  27 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  28
  29 static int
  30 ice_monitor_callback(const uint64_t value,
  31                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  32 {
  33         const uint64_t m = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
  34         /*
  35          * we expect the DD bit to be set to 1 if this descriptor was already
  36          * written to.
  37          */
  38         return (value & m) == m ? -1 : 0;
  39 }
  40
  41 int
  42 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  43 {
  44         volatile union ice_rx_flex_desc *rxdp;
  45         struct ice_rx_queue *rxq = rx_queue;
  46         uint16_t desc;
  47
  48         desc = rxq->rx_tail;
  49         rxdp = &rxq->rx_ring[desc];
  50         /* watch for changes in status bit */
  51         pmc->addr = &rxdp->wb.status_error0;
  52
  53         /* comparison callback */
  54         pmc->fn = ice_monitor_callback;
  55
  56         /* register is 16-bit */
  57         pmc->size = sizeof(uint16_t);
  58
  59         return 0;
  60 }
  61
  62
  63 static inline uint8_t
  64 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  65 {
  66         static uint8_t rxdid_map[] = {
  67                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_OVS,
  68                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  69                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  70                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  71                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  72                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  73                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  74         };
  75
  76         return xtr_type < RTE_DIM(rxdid_map) ?
  77                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
  78 }
  79
  80 static inline void
  81 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
  82                                        struct rte_mbuf *mb,
  83                                        volatile union ice_rx_flex_desc *rxdp)
  84 {
  85         volatile struct ice_32b_rx_flex_desc_comms *desc =
  86                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
  87         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
  88
  89         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  90                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
  91                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  92         }
  93
  94 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  95         if (desc->flow_id != 0xFFFFFFFF) {
  96                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
  97                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  98         }
  99 #endif
 100 }
 101
 102 static inline void
 103 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
 104                                    struct rte_mbuf *mb,
 105                                    volatile union ice_rx_flex_desc *rxdp)
 106 {
 107         volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
 108                         (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
 109 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 110         uint16_t stat_err;
 111 #endif
 112
 113         if (desc->flow_id != 0xFFFFFFFF) {
 114                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 115                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 116         }
 117
 118 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 119         stat_err = rte_le_to_cpu_16(desc->status_error0);
 120         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 121                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 122                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 123         }
 124 #endif
 125 }
 126
 127 static inline void
 128 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
 129                                       struct rte_mbuf *mb,
 130                                       volatile union ice_rx_flex_desc *rxdp)
 131 {
 132         volatile struct ice_32b_rx_flex_desc_comms *desc =
 133                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 134         uint16_t stat_err;
 135
 136         stat_err = rte_le_to_cpu_16(desc->status_error0);
 137         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 138                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 139                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 140         }
 141
 142 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 143         if (desc->flow_id != 0xFFFFFFFF) {
 144                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 145                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 146         }
 147
 148         if (rxq->xtr_ol_flag) {
 149                 uint32_t metadata = 0;
 150
 151                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 152
 153                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 154                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 155
 156                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 157                         metadata |=
 158                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 159
 160                 if (metadata) {
 161                         mb->ol_flags |= rxq->xtr_ol_flag;
 162
 163                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 164                 }
 165         }
 166 #endif
 167 }
 168
 169 static inline void
 170 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
 171                                       struct rte_mbuf *mb,
 172                                       volatile union ice_rx_flex_desc *rxdp)
 173 {
 174         volatile struct ice_32b_rx_flex_desc_comms *desc =
 175                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 176         uint16_t stat_err;
 177
 178         stat_err = rte_le_to_cpu_16(desc->status_error0);
 179         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 180                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 181                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 182         }
 183
 184 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 185         if (desc->flow_id != 0xFFFFFFFF) {
 186                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 187                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 188         }
 189
 190         if (rxq->xtr_ol_flag) {
 191                 uint32_t metadata = 0;
 192
 193                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 194                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 195                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 196                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 197
 198                 if (metadata) {
 199                         mb->ol_flags |= rxq->xtr_ol_flag;
 200
 201                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 202                 }
 203         }
 204 #endif
 205 }
 206
 207 static const ice_rxd_to_pkt_fields_t rxd_to_pkt_fields_ops[] = {
 208         [ICE_RXDID_COMMS_AUX_VLAN] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 209         [ICE_RXDID_COMMS_AUX_IPV4] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 210         [ICE_RXDID_COMMS_AUX_IPV6] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 211         [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 212         [ICE_RXDID_COMMS_AUX_TCP] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 213         [ICE_RXDID_COMMS_AUX_IP_OFFSET] = ice_rxd_to_pkt_fields_by_comms_aux_v2,
 214         [ICE_RXDID_COMMS_GENERIC] = ice_rxd_to_pkt_fields_by_comms_generic,
 215         [ICE_RXDID_COMMS_OVS] = ice_rxd_to_pkt_fields_by_comms_ovs,
 216 };
 217
 218 void
 219 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
 220 {
 221         rxq->rxdid = rxdid;
 222
 223         switch (rxdid) {
 224         case ICE_RXDID_COMMS_AUX_VLAN:
 225                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
 226                 break;
 227
 228         case ICE_RXDID_COMMS_AUX_IPV4:
 229                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
 230                 break;
 231
 232         case ICE_RXDID_COMMS_AUX_IPV6:
 233                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
 234                 break;
 235
 236         case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
 237                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
 238                 break;
 239
 240         case ICE_RXDID_COMMS_AUX_TCP:
 241                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
 242                 break;
 243
 244         case ICE_RXDID_COMMS_AUX_IP_OFFSET:
 245                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
 246                 break;
 247
 248         case ICE_RXDID_COMMS_GENERIC:
 249                 /* fallthrough */
 250         case ICE_RXDID_COMMS_OVS:
 251                 break;
 252
 253         default:
 254                 /* update this according to the RXDID for PROTO_XTR_NONE */
 255                 rxq->rxdid = ICE_RXDID_COMMS_OVS;
 256                 break;
 257         }
 258
 259         if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
 260                 rxq->xtr_ol_flag = 0;
 261 }
 262
 263 static enum ice_status
 264 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
 265 {
 266         struct ice_vsi *vsi = rxq->vsi;
 267         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 268         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
 269         struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
 270         struct ice_rlan_ctx rx_ctx;
 271         enum ice_status err;
 272         uint16_t buf_size;
 273         uint32_t rxdid = ICE_RXDID_COMMS_OVS;
 274         uint32_t regval;
 275         struct ice_adapter *ad = rxq->vsi->adapter;
 276         uint32_t frame_size = dev_data->mtu + ICE_ETH_OVERHEAD;
 277
 278         /* Set buffer size as the head split is disabled. */
 279         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 280                               RTE_PKTMBUF_HEADROOM);
 281         rxq->rx_hdr_len = 0;
 282         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
 283         rxq->max_pkt_len =
 284                 RTE_MIN((uint32_t)ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
 285                         frame_size);
 286
 287         if (rxq->max_pkt_len <= RTE_ETHER_MIN_LEN ||
 288             rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 289                 PMD_DRV_LOG(ERR, "maximum packet length must "
 290                             "be larger than %u and smaller than %u",
 291                             (uint32_t)RTE_ETHER_MIN_LEN,
 292                             (uint32_t)ICE_FRAME_SIZE_MAX);
 293                 return -EINVAL;
 294         }
 295
 296         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
 297                 /* Register mbuf field and flag for Rx timestamp */
 298                 err = rte_mbuf_dyn_rx_timestamp_register(
 299                                 &ice_timestamp_dynfield_offset,
 300                                 &ice_timestamp_dynflag);
 301                 if (err) {
 302                         PMD_DRV_LOG(ERR,
 303                                 "Cannot register mbuf field/flag for timestamp");
 304                         return -EINVAL;
 305                 }
 306         }
 307
 308         memset(&rx_ctx, 0, sizeof(rx_ctx));
 309
 310         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 311         rx_ctx.qlen = rxq->nb_rx_desc;
 312         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 313         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 314         rx_ctx.dtype = 0; /* No Header Split mode */
 315 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 316         rx_ctx.dsize = 1; /* 32B descriptors */
 317 #endif
 318         rx_ctx.rxmax = rxq->max_pkt_len;
 319         /* TPH: Transaction Layer Packet (TLP) processing hints */
 320         rx_ctx.tphrdesc_ena = 1;
 321         rx_ctx.tphwdesc_ena = 1;
 322         rx_ctx.tphdata_ena = 1;
 323         rx_ctx.tphhead_ena = 1;
 324         /* Low Receive Queue Threshold defined in 64 descriptors units.
 325          * When the number of free descriptors goes below the lrxqthresh,
 326          * an immediate interrupt is triggered.
 327          */
 328         rx_ctx.lrxqthresh = 2;
 329         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 330         rx_ctx.l2tsel = 1;
 331         rx_ctx.showiv = 0;
 332         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 333
 334         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 335
 336         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 337                     rxq->port_id, rxq->queue_id, rxdid);
 338
 339         if (!(pf->supported_rxdid & BIT(rxdid))) {
 340                 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
 341                             rxdid);
 342                 return -EINVAL;
 343         }
 344
 345         ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
 346
 347         /* Enable Flexible Descriptors in the queue context which
 348          * allows this driver to select a specific receive descriptor format
 349          */
 350         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 351                 QRXFLXP_CNTXT_RXDID_IDX_M;
 352
 353         /* increasing context priority to pick up profile ID;
 354          * default is 0x01; setting to 0x03 to ensure profile
 355          * is programming if prev context is of same priority
 356          */
 357         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 358                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 359
 360         if (ad->ptp_ena || rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
 361                 regval |= QRXFLXP_CNTXT_TS_M;
 362
 363         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 364
 365         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 366         if (err) {
 367                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 368                             rxq->queue_id);
 369                 return -EINVAL;
 370         }
 371         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 372         if (err) {
 373                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 374                             rxq->queue_id);
 375                 return -EINVAL;
 376         }
 377
 378         /* Check if scattered RX needs to be used. */
 379         if (frame_size > buf_size)
 380                 dev_data->scattered_rx = 1;
 381
 382         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 383
 384         /* Init the Rx tail register*/
 385         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 386
 387         return 0;
 388 }
 389
 390 /* Allocate mbufs for all descriptors in rx queue */
 391 static int
 392 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 393 {
 394         struct ice_rx_entry *rxe = rxq->sw_ring;
 395         uint64_t dma_addr;
 396         uint16_t i;
 397
 398         for (i = 0; i < rxq->nb_rx_desc; i++) {
 399                 volatile union ice_rx_flex_desc *rxd;
 400                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 401
 402                 if (unlikely(!mbuf)) {
 403                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 404                         return -ENOMEM;
 405                 }
 406
 407                 rte_mbuf_refcnt_set(mbuf, 1);
 408                 mbuf->next = NULL;
 409                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 410                 mbuf->nb_segs = 1;
 411                 mbuf->port = rxq->port_id;
 412
 413                 dma_addr =
 414                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 415
 416                 rxd = &rxq->rx_ring[i];
 417                 rxd->read.pkt_addr = dma_addr;
 418                 rxd->read.hdr_addr = 0;
 419 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 420                 rxd->read.rsvd1 = 0;
 421                 rxd->read.rsvd2 = 0;
 422 #endif
 423                 rxe[i].mbuf = mbuf;
 424         }
 425
 426         return 0;
 427 }
 428
 429 /* Free all mbufs for descriptors in rx queue */
 430 static void
 431 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 432 {
 433         uint16_t i;
 434
 435         if (!rxq || !rxq->sw_ring) {
 436                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 437                 return;
 438         }
 439
 440         for (i = 0; i < rxq->nb_rx_desc; i++) {
 441                 if (rxq->sw_ring[i].mbuf) {
 442                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 443                         rxq->sw_ring[i].mbuf = NULL;
 444                 }
 445         }
 446         if (rxq->rx_nb_avail == 0)
 447                 return;
 448         for (i = 0; i < rxq->rx_nb_avail; i++)
 449                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 450
 451         rxq->rx_nb_avail = 0;
 452 }
 453
 454 /* turn on or off rx queue
 455  * @q_idx: queue index in pf scope
 456  * @on: turn on or off the queue
 457  */
 458 static int
 459 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 460 {
 461         uint32_t reg;
 462         uint16_t j;
 463
 464         /* QRX_CTRL = QRX_ENA */
 465         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 466
 467         if (on) {
 468                 if (reg & QRX_CTRL_QENA_STAT_M)
 469                         return 0; /* Already on, skip */
 470                 reg |= QRX_CTRL_QENA_REQ_M;
 471         } else {
 472                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 473                         return 0; /* Already off, skip */
 474                 reg &= ~QRX_CTRL_QENA_REQ_M;
 475         }
 476
 477         /* Write the register */
 478         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 479         /* Check the result. It is said that QENA_STAT
 480          * follows the QENA_REQ not more than 10 use.
 481          * TODO: need to change the wait counter later
 482          */
 483         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 484                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 485                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 486                 if (on) {
 487                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 488                             (reg & QRX_CTRL_QENA_STAT_M))
 489                                 break;
 490                 } else {
 491                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 492                             !(reg & QRX_CTRL_QENA_STAT_M))
 493                                 break;
 494                 }
 495         }
 496
 497         /* Check if it is timeout */
 498         if (j >= ICE_CHK_Q_ENA_COUNT) {
 499                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 500                             (on ? "enable" : "disable"), q_idx);
 501                 return -ETIMEDOUT;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static inline int
 508 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 509 {
 510         int ret = 0;
 511
 512         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 513                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 514                              "rxq->rx_free_thresh=%d, "
 515                              "ICE_RX_MAX_BURST=%d",
 516                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 517                 ret = -EINVAL;
 518         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 519                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 520                              "rxq->rx_free_thresh=%d, "
 521                              "rxq->nb_rx_desc=%d",
 522                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 523                 ret = -EINVAL;
 524         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 525                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 526                              "rxq->nb_rx_desc=%d, "
 527                              "rxq->rx_free_thresh=%d",
 528                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 529                 ret = -EINVAL;
 530         }
 531
 532         return ret;
 533 }
 534
 535 /* reset fields in ice_rx_queue back to default */
 536 static void
 537 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 538 {
 539         unsigned int i;
 540         uint16_t len;
 541
 542         if (!rxq) {
 543                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 544                 return;
 545         }
 546
 547         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 548
 549         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 550                 ((volatile char *)rxq->rx_ring)[i] = 0;
 551
 552         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 553         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 554                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 555
 556         rxq->rx_nb_avail = 0;
 557         rxq->rx_next_avail = 0;
 558         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 559
 560         rxq->rx_tail = 0;
 561         rxq->nb_rx_hold = 0;
 562         rxq->pkt_first_seg = NULL;
 563         rxq->pkt_last_seg = NULL;
 564
 565         rxq->rxrearm_start = 0;
 566         rxq->rxrearm_nb = 0;
 567 }
 568
 569 int
 570 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 571 {
 572         struct ice_rx_queue *rxq;
 573         int err;
 574         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 575
 576         PMD_INIT_FUNC_TRACE();
 577
 578         if (rx_queue_id >= dev->data->nb_rx_queues) {
 579                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 580                             rx_queue_id, dev->data->nb_rx_queues);
 581                 return -EINVAL;
 582         }
 583
 584         rxq = dev->data->rx_queues[rx_queue_id];
 585         if (!rxq || !rxq->q_set) {
 586                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 587                             rx_queue_id);
 588                 return -EINVAL;
 589         }
 590
 591         err = ice_program_hw_rx_queue(rxq);
 592         if (err) {
 593                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 594                             rx_queue_id);
 595                 return -EIO;
 596         }
 597
 598         err = ice_alloc_rx_queue_mbufs(rxq);
 599         if (err) {
 600                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 601                 return -ENOMEM;
 602         }
 603
 604         /* Init the RX tail register. */
 605         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 606
 607         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 608         if (err) {
 609                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 610                             rx_queue_id);
 611
 612                 rxq->rx_rel_mbufs(rxq);
 613                 ice_reset_rx_queue(rxq);
 614                 return -EINVAL;
 615         }
 616
 617         dev->data->rx_queue_state[rx_queue_id] =
 618                 RTE_ETH_QUEUE_STATE_STARTED;
 619
 620         return 0;
 621 }
 622
 623 int
 624 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 625 {
 626         struct ice_rx_queue *rxq;
 627         int err;
 628         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 629
 630         if (rx_queue_id < dev->data->nb_rx_queues) {
 631                 rxq = dev->data->rx_queues[rx_queue_id];
 632
 633                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 634                 if (err) {
 635                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 636                                     rx_queue_id);
 637                         return -EINVAL;
 638                 }
 639                 rxq->rx_rel_mbufs(rxq);
 640                 ice_reset_rx_queue(rxq);
 641                 dev->data->rx_queue_state[rx_queue_id] =
 642                         RTE_ETH_QUEUE_STATE_STOPPED;
 643         }
 644
 645         return 0;
 646 }
 647
 648 int
 649 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 650 {
 651         struct ice_tx_queue *txq;
 652         int err;
 653         struct ice_vsi *vsi;
 654         struct ice_hw *hw;
 655         struct ice_aqc_add_tx_qgrp *txq_elem;
 656         struct ice_tlan_ctx tx_ctx;
 657         int buf_len;
 658
 659         PMD_INIT_FUNC_TRACE();
 660
 661         if (tx_queue_id >= dev->data->nb_tx_queues) {
 662                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 663                             tx_queue_id, dev->data->nb_tx_queues);
 664                 return -EINVAL;
 665         }
 666
 667         txq = dev->data->tx_queues[tx_queue_id];
 668         if (!txq || !txq->q_set) {
 669                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 670                             tx_queue_id);
 671                 return -EINVAL;
 672         }
 673
 674         buf_len = ice_struct_size(txq_elem, txqs, 1);
 675         txq_elem = ice_malloc(hw, buf_len);
 676         if (!txq_elem)
 677                 return -ENOMEM;
 678
 679         vsi = txq->vsi;
 680         hw = ICE_VSI_TO_HW(vsi);
 681
 682         memset(&tx_ctx, 0, sizeof(tx_ctx));
 683         txq_elem->num_txqs = 1;
 684         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 685
 686         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 687         tx_ctx.qlen = txq->nb_tx_desc;
 688         tx_ctx.pf_num = hw->pf_id;
 689         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 690         tx_ctx.src_vsi = vsi->vsi_id;
 691         tx_ctx.port_num = hw->port_info->lport;
 692         tx_ctx.tso_ena = 1; /* tso enable */
 693         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 694         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 695         tx_ctx.tsyn_ena = 1;
 696
 697         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 698                     ice_tlan_ctx_info);
 699
 700         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 701
 702         /* Init the Tx tail register*/
 703         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 704
 705         /* Fix me, we assume TC always 0 here */
 706         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 707                         txq_elem, buf_len, NULL);
 708         if (err) {
 709                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 710                 rte_free(txq_elem);
 711                 return -EIO;
 712         }
 713         /* store the schedule node id */
 714         txq->q_teid = txq_elem->txqs[0].q_teid;
 715
 716         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 717
 718         rte_free(txq_elem);
 719         return 0;
 720 }
 721
 722 static enum ice_status
 723 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 724 {
 725         struct ice_vsi *vsi = rxq->vsi;
 726         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 727         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 728         struct ice_rlan_ctx rx_ctx;
 729         enum ice_status err;
 730         uint32_t regval;
 731
 732         rxq->rx_hdr_len = 0;
 733         rxq->rx_buf_len = 1024;
 734
 735         memset(&rx_ctx, 0, sizeof(rx_ctx));
 736
 737         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 738         rx_ctx.qlen = rxq->nb_rx_desc;
 739         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 740         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 741         rx_ctx.dtype = 0; /* No Header Split mode */
 742         rx_ctx.dsize = 1; /* 32B descriptors */
 743         rx_ctx.rxmax = ICE_ETH_MAX_LEN;
 744         /* TPH: Transaction Layer Packet (TLP) processing hints */
 745         rx_ctx.tphrdesc_ena = 1;
 746         rx_ctx.tphwdesc_ena = 1;
 747         rx_ctx.tphdata_ena = 1;
 748         rx_ctx.tphhead_ena = 1;
 749         /* Low Receive Queue Threshold defined in 64 descriptors units.
 750          * When the number of free descriptors goes below the lrxqthresh,
 751          * an immediate interrupt is triggered.
 752          */
 753         rx_ctx.lrxqthresh = 2;
 754         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 755         rx_ctx.l2tsel = 1;
 756         rx_ctx.showiv = 0;
 757         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 758
 759         /* Enable Flexible Descriptors in the queue context which
 760          * allows this driver to select a specific receive descriptor format
 761          */
 762         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 763                 QRXFLXP_CNTXT_RXDID_IDX_M;
 764
 765         /* increasing context priority to pick up profile ID;
 766          * default is 0x01; setting to 0x03 to ensure profile
 767          * is programming if prev context is of same priority
 768          */
 769         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 770                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 771
 772         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 773
 774         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 775         if (err) {
 776                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 777                             rxq->queue_id);
 778                 return -EINVAL;
 779         }
 780         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 781         if (err) {
 782                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 783                             rxq->queue_id);
 784                 return -EINVAL;
 785         }
 786
 787         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 788
 789         /* Init the Rx tail register*/
 790         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 791
 792         return 0;
 793 }
 794
 795 int
 796 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 797 {
 798         struct ice_rx_queue *rxq;
 799         int err;
 800         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 801         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 802
 803         PMD_INIT_FUNC_TRACE();
 804
 805         rxq = pf->fdir.rxq;
 806         if (!rxq || !rxq->q_set) {
 807                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 808                             rx_queue_id);
 809                 return -EINVAL;
 810         }
 811
 812         err = ice_fdir_program_hw_rx_queue(rxq);
 813         if (err) {
 814                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 815                             rx_queue_id);
 816                 return -EIO;
 817         }
 818
 819         /* Init the RX tail register. */
 820         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 821
 822         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 823         if (err) {
 824                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 825                             rx_queue_id);
 826
 827                 ice_reset_rx_queue(rxq);
 828                 return -EINVAL;
 829         }
 830
 831         return 0;
 832 }
 833
 834 int
 835 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 836 {
 837         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 838         struct ice_tx_queue *txq;
 839         int err;
 840         struct ice_vsi *vsi;
 841         struct ice_hw *hw;
 842         struct ice_aqc_add_tx_qgrp *txq_elem;
 843         struct ice_tlan_ctx tx_ctx;
 844         int buf_len;
 845
 846         PMD_INIT_FUNC_TRACE();
 847
 848         txq = pf->fdir.txq;
 849         if (!txq || !txq->q_set) {
 850                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 851                             tx_queue_id);
 852                 return -EINVAL;
 853         }
 854
 855         buf_len = ice_struct_size(txq_elem, txqs, 1);
 856         txq_elem = ice_malloc(hw, buf_len);
 857         if (!txq_elem)
 858                 return -ENOMEM;
 859
 860         vsi = txq->vsi;
 861         hw = ICE_VSI_TO_HW(vsi);
 862
 863         memset(&tx_ctx, 0, sizeof(tx_ctx));
 864         txq_elem->num_txqs = 1;
 865         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 866
 867         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 868         tx_ctx.qlen = txq->nb_tx_desc;
 869         tx_ctx.pf_num = hw->pf_id;
 870         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 871         tx_ctx.src_vsi = vsi->vsi_id;
 872         tx_ctx.port_num = hw->port_info->lport;
 873         tx_ctx.tso_ena = 1; /* tso enable */
 874         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 875         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 876
 877         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 878                     ice_tlan_ctx_info);
 879
 880         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 881
 882         /* Init the Tx tail register*/
 883         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 884
 885         /* Fix me, we assume TC always 0 here */
 886         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 887                               txq_elem, buf_len, NULL);
 888         if (err) {
 889                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 890                 rte_free(txq_elem);
 891                 return -EIO;
 892         }
 893         /* store the schedule node id */
 894         txq->q_teid = txq_elem->txqs[0].q_teid;
 895
 896         rte_free(txq_elem);
 897         return 0;
 898 }
 899
 900 /* Free all mbufs for descriptors in tx queue */
 901 static void
 902 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 903 {
 904         uint16_t i;
 905
 906         if (!txq || !txq->sw_ring) {
 907                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 908                 return;
 909         }
 910
 911         for (i = 0; i < txq->nb_tx_desc; i++) {
 912                 if (txq->sw_ring[i].mbuf) {
 913                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 914                         txq->sw_ring[i].mbuf = NULL;
 915                 }
 916         }
 917 }
 918
 919 static void
 920 ice_reset_tx_queue(struct ice_tx_queue *txq)
 921 {
 922         struct ice_tx_entry *txe;
 923         uint16_t i, prev, size;
 924
 925         if (!txq) {
 926                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 927                 return;
 928         }
 929
 930         txe = txq->sw_ring;
 931         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 932         for (i = 0; i < size; i++)
 933                 ((volatile char *)txq->tx_ring)[i] = 0;
 934
 935         prev = (uint16_t)(txq->nb_tx_desc - 1);
 936         for (i = 0; i < txq->nb_tx_desc; i++) {
 937                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 938
 939                 txd->cmd_type_offset_bsz =
 940                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 941                 txe[i].mbuf =  NULL;
 942                 txe[i].last_id = i;
 943                 txe[prev].next_id = i;
 944                 prev = i;
 945         }
 946
 947         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 948         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 949
 950         txq->tx_tail = 0;
 951         txq->nb_tx_used = 0;
 952
 953         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 954         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 955 }
 956
 957 int
 958 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 959 {
 960         struct ice_tx_queue *txq;
 961         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 962         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 963         struct ice_vsi *vsi = pf->main_vsi;
 964         enum ice_status status;
 965         uint16_t q_ids[1];
 966         uint32_t q_teids[1];
 967         uint16_t q_handle = tx_queue_id;
 968
 969         if (tx_queue_id >= dev->data->nb_tx_queues) {
 970                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 971                             tx_queue_id, dev->data->nb_tx_queues);
 972                 return -EINVAL;
 973         }
 974
 975         txq = dev->data->tx_queues[tx_queue_id];
 976         if (!txq) {
 977                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 978                             tx_queue_id);
 979                 return -EINVAL;
 980         }
 981
 982         q_ids[0] = txq->reg_idx;
 983         q_teids[0] = txq->q_teid;
 984
 985         /* Fix me, we assume TC always 0 here */
 986         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 987                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 988         if (status != ICE_SUCCESS) {
 989                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 990                 return -EINVAL;
 991         }
 992
 993         txq->tx_rel_mbufs(txq);
 994         ice_reset_tx_queue(txq);
 995         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 996
 997         return 0;
 998 }
 999
1000 int
1001 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1002 {
1003         struct ice_rx_queue *rxq;
1004         int err;
1005         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1007
1008         rxq = pf->fdir.rxq;
1009
1010         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1011         if (err) {
1012                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1013                             rx_queue_id);
1014                 return -EINVAL;
1015         }
1016         rxq->rx_rel_mbufs(rxq);
1017
1018         return 0;
1019 }
1020
1021 int
1022 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1023 {
1024         struct ice_tx_queue *txq;
1025         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1027         struct ice_vsi *vsi = pf->main_vsi;
1028         enum ice_status status;
1029         uint16_t q_ids[1];
1030         uint32_t q_teids[1];
1031         uint16_t q_handle = tx_queue_id;
1032
1033         txq = pf->fdir.txq;
1034         if (!txq) {
1035                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1036                             tx_queue_id);
1037                 return -EINVAL;
1038         }
1039         vsi = txq->vsi;
1040
1041         q_ids[0] = txq->reg_idx;
1042         q_teids[0] = txq->q_teid;
1043
1044         /* Fix me, we assume TC always 0 here */
1045         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1046                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1047         if (status != ICE_SUCCESS) {
1048                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1049                 return -EINVAL;
1050         }
1051
1052         txq->tx_rel_mbufs(txq);
1053
1054         return 0;
1055 }
1056
1057 int
1058 ice_rx_queue_setup(struct rte_eth_dev *dev,
1059                    uint16_t queue_idx,
1060                    uint16_t nb_desc,
1061                    unsigned int socket_id,
1062                    const struct rte_eth_rxconf *rx_conf,
1063                    struct rte_mempool *mp)
1064 {
1065         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1066         struct ice_adapter *ad =
1067                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1068         struct ice_vsi *vsi = pf->main_vsi;
1069         struct ice_rx_queue *rxq;
1070         const struct rte_memzone *rz;
1071         uint32_t ring_size;
1072         uint16_t len;
1073         int use_def_burst_func = 1;
1074         uint64_t offloads;
1075
1076         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1077             nb_desc > ICE_MAX_RING_DESC ||
1078             nb_desc < ICE_MIN_RING_DESC) {
1079                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1080                              "invalid", nb_desc);
1081                 return -EINVAL;
1082         }
1083
1084         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1085
1086         /* Free memory if needed */
1087         if (dev->data->rx_queues[queue_idx]) {
1088                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1089                 dev->data->rx_queues[queue_idx] = NULL;
1090         }
1091
1092         /* Allocate the rx queue data structure */
1093         rxq = rte_zmalloc_socket(NULL,
1094                                  sizeof(struct ice_rx_queue),
1095                                  RTE_CACHE_LINE_SIZE,
1096                                  socket_id);
1097         if (!rxq) {
1098                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1099                              "rx queue data structure");
1100                 return -ENOMEM;
1101         }
1102         rxq->mp = mp;
1103         rxq->nb_rx_desc = nb_desc;
1104         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1105         rxq->queue_id = queue_idx;
1106         rxq->offloads = offloads;
1107
1108         rxq->reg_idx = vsi->base_queue + queue_idx;
1109         rxq->port_id = dev->data->port_id;
1110         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1111                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1112         else
1113                 rxq->crc_len = 0;
1114
1115         rxq->drop_en = rx_conf->rx_drop_en;
1116         rxq->vsi = vsi;
1117         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1118         rxq->proto_xtr = pf->proto_xtr != NULL ?
1119                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1120
1121         /* Allocate the maximum number of RX ring hardware descriptor. */
1122         len = ICE_MAX_RING_DESC;
1123
1124         /**
1125          * Allocating a little more memory because vectorized/bulk_alloc Rx
1126          * functions doesn't check boundaries each time.
1127          */
1128         len += ICE_RX_MAX_BURST;
1129
1130         /* Allocate the maximum number of RX ring hardware descriptor. */
1131         ring_size = sizeof(union ice_rx_flex_desc) * len;
1132         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1133         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1134                                       ring_size, ICE_RING_BASE_ALIGN,
1135                                       socket_id);
1136         if (!rz) {
1137                 ice_rx_queue_release(rxq);
1138                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1139                 return -ENOMEM;
1140         }
1141
1142         rxq->mz = rz;
1143         /* Zero all the descriptors in the ring. */
1144         memset(rz->addr, 0, ring_size);
1145
1146         rxq->rx_ring_dma = rz->iova;
1147         rxq->rx_ring = rz->addr;
1148
1149         /* always reserve more for bulk alloc */
1150         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1151
1152         /* Allocate the software ring. */
1153         rxq->sw_ring = rte_zmalloc_socket(NULL,
1154                                           sizeof(struct ice_rx_entry) * len,
1155                                           RTE_CACHE_LINE_SIZE,
1156                                           socket_id);
1157         if (!rxq->sw_ring) {
1158                 ice_rx_queue_release(rxq);
1159                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1160                 return -ENOMEM;
1161         }
1162
1163         ice_reset_rx_queue(rxq);
1164         rxq->q_set = true;
1165         dev->data->rx_queues[queue_idx] = rxq;
1166         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1167
1168         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1169
1170         if (!use_def_burst_func) {
1171                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1172                              "satisfied. Rx Burst Bulk Alloc function will be "
1173                              "used on port=%d, queue=%d.",
1174                              rxq->port_id, rxq->queue_id);
1175         } else {
1176                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1177                              "not satisfied, Scattered Rx is requested. "
1178                              "on port=%d, queue=%d.",
1179                              rxq->port_id, rxq->queue_id);
1180                 ad->rx_bulk_alloc_allowed = false;
1181         }
1182
1183         return 0;
1184 }
1185
1186 void
1187 ice_rx_queue_release(void *rxq)
1188 {
1189         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1190
1191         if (!q) {
1192                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1193                 return;
1194         }
1195
1196         q->rx_rel_mbufs(q);
1197         rte_free(q->sw_ring);
1198         rte_memzone_free(q->mz);
1199         rte_free(q);
1200 }
1201
1202 int
1203 ice_tx_queue_setup(struct rte_eth_dev *dev,
1204                    uint16_t queue_idx,
1205                    uint16_t nb_desc,
1206                    unsigned int socket_id,
1207                    const struct rte_eth_txconf *tx_conf)
1208 {
1209         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1210         struct ice_vsi *vsi = pf->main_vsi;
1211         struct ice_tx_queue *txq;
1212         const struct rte_memzone *tz;
1213         uint32_t ring_size;
1214         uint16_t tx_rs_thresh, tx_free_thresh;
1215         uint64_t offloads;
1216
1217         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1218
1219         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1220             nb_desc > ICE_MAX_RING_DESC ||
1221             nb_desc < ICE_MIN_RING_DESC) {
1222                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1223                              "invalid", nb_desc);
1224                 return -EINVAL;
1225         }
1226
1227         /**
1228          * The following two parameters control the setting of the RS bit on
1229          * transmit descriptors. TX descriptors will have their RS bit set
1230          * after txq->tx_rs_thresh descriptors have been used. The TX
1231          * descriptor ring will be cleaned after txq->tx_free_thresh
1232          * descriptors are used or if the number of descriptors required to
1233          * transmit a packet is greater than the number of free TX descriptors.
1234          *
1235          * The following constraints must be satisfied:
1236          *  - tx_rs_thresh must be greater than 0.
1237          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1238          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1239          *  - tx_rs_thresh must be a divisor of the ring size.
1240          *  - tx_free_thresh must be greater than 0.
1241          *  - tx_free_thresh must be less than the size of the ring minus 3.
1242          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1243          *
1244          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1245          * race condition, hence the maximum threshold constraints. When set
1246          * to zero use default values.
1247          */
1248         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1249                                     tx_conf->tx_free_thresh :
1250                                     ICE_DEFAULT_TX_FREE_THRESH);
1251         /* force tx_rs_thresh to adapt an aggressive tx_free_thresh */
1252         tx_rs_thresh =
1253                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1254                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1255         if (tx_conf->tx_rs_thresh)
1256                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1257         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1258                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1259                                 "exceed nb_desc. (tx_rs_thresh=%u "
1260                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1261                                 (unsigned int)tx_rs_thresh,
1262                                 (unsigned int)tx_free_thresh,
1263                                 (unsigned int)nb_desc,
1264                                 (int)dev->data->port_id,
1265                                 (int)queue_idx);
1266                 return -EINVAL;
1267         }
1268         if (tx_rs_thresh >= (nb_desc - 2)) {
1269                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1270                              "number of TX descriptors minus 2. "
1271                              "(tx_rs_thresh=%u port=%d queue=%d)",
1272                              (unsigned int)tx_rs_thresh,
1273                              (int)dev->data->port_id,
1274                              (int)queue_idx);
1275                 return -EINVAL;
1276         }
1277         if (tx_free_thresh >= (nb_desc - 3)) {
1278                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1279                              "tx_free_thresh must be less than the "
1280                              "number of TX descriptors minus 3. "
1281                              "(tx_free_thresh=%u port=%d queue=%d)",
1282                              (unsigned int)tx_free_thresh,
1283                              (int)dev->data->port_id,
1284                              (int)queue_idx);
1285                 return -EINVAL;
1286         }
1287         if (tx_rs_thresh > tx_free_thresh) {
1288                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1289                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1290                              " tx_rs_thresh=%u port=%d queue=%d)",
1291                              (unsigned int)tx_free_thresh,
1292                              (unsigned int)tx_rs_thresh,
1293                              (int)dev->data->port_id,
1294                              (int)queue_idx);
1295                 return -EINVAL;
1296         }
1297         if ((nb_desc % tx_rs_thresh) != 0) {
1298                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1299                              "number of TX descriptors. (tx_rs_thresh=%u"
1300                              " port=%d queue=%d)",
1301                              (unsigned int)tx_rs_thresh,
1302                              (int)dev->data->port_id,
1303                              (int)queue_idx);
1304                 return -EINVAL;
1305         }
1306         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1307                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1308                              "tx_rs_thresh is greater than 1. "
1309                              "(tx_rs_thresh=%u port=%d queue=%d)",
1310                              (unsigned int)tx_rs_thresh,
1311                              (int)dev->data->port_id,
1312                              (int)queue_idx);
1313                 return -EINVAL;
1314         }
1315
1316         /* Free memory if needed. */
1317         if (dev->data->tx_queues[queue_idx]) {
1318                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1319                 dev->data->tx_queues[queue_idx] = NULL;
1320         }
1321
1322         /* Allocate the TX queue data structure. */
1323         txq = rte_zmalloc_socket(NULL,
1324                                  sizeof(struct ice_tx_queue),
1325                                  RTE_CACHE_LINE_SIZE,
1326                                  socket_id);
1327         if (!txq) {
1328                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1329                              "tx queue structure");
1330                 return -ENOMEM;
1331         }
1332
1333         /* Allocate TX hardware ring descriptors. */
1334         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1335         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1336         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1337                                       ring_size, ICE_RING_BASE_ALIGN,
1338                                       socket_id);
1339         if (!tz) {
1340                 ice_tx_queue_release(txq);
1341                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1342                 return -ENOMEM;
1343         }
1344
1345         txq->mz = tz;
1346         txq->nb_tx_desc = nb_desc;
1347         txq->tx_rs_thresh = tx_rs_thresh;
1348         txq->tx_free_thresh = tx_free_thresh;
1349         txq->pthresh = tx_conf->tx_thresh.pthresh;
1350         txq->hthresh = tx_conf->tx_thresh.hthresh;
1351         txq->wthresh = tx_conf->tx_thresh.wthresh;
1352         txq->queue_id = queue_idx;
1353
1354         txq->reg_idx = vsi->base_queue + queue_idx;
1355         txq->port_id = dev->data->port_id;
1356         txq->offloads = offloads;
1357         txq->vsi = vsi;
1358         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1359
1360         txq->tx_ring_dma = tz->iova;
1361         txq->tx_ring = tz->addr;
1362
1363         /* Allocate software ring */
1364         txq->sw_ring =
1365                 rte_zmalloc_socket(NULL,
1366                                    sizeof(struct ice_tx_entry) * nb_desc,
1367                                    RTE_CACHE_LINE_SIZE,
1368                                    socket_id);
1369         if (!txq->sw_ring) {
1370                 ice_tx_queue_release(txq);
1371                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1372                 return -ENOMEM;
1373         }
1374
1375         ice_reset_tx_queue(txq);
1376         txq->q_set = true;
1377         dev->data->tx_queues[queue_idx] = txq;
1378         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1379         ice_set_tx_function_flag(dev, txq);
1380
1381         return 0;
1382 }
1383
1384 void
1385 ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1386 {
1387         ice_rx_queue_release(dev->data->rx_queues[qid]);
1388 }
1389
1390 void
1391 ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1392 {
1393         ice_tx_queue_release(dev->data->tx_queues[qid]);
1394 }
1395
1396 void
1397 ice_tx_queue_release(void *txq)
1398 {
1399         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1400
1401         if (!q) {
1402                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1403                 return;
1404         }
1405
1406         q->tx_rel_mbufs(q);
1407         rte_free(q->sw_ring);
1408         rte_memzone_free(q->mz);
1409         rte_free(q);
1410 }
1411
1412 void
1413 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1414                  struct rte_eth_rxq_info *qinfo)
1415 {
1416         struct ice_rx_queue *rxq;
1417
1418         rxq = dev->data->rx_queues[queue_id];
1419
1420         qinfo->mp = rxq->mp;
1421         qinfo->scattered_rx = dev->data->scattered_rx;
1422         qinfo->nb_desc = rxq->nb_rx_desc;
1423
1424         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1425         qinfo->conf.rx_drop_en = rxq->drop_en;
1426         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1427 }
1428
1429 void
1430 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1431                  struct rte_eth_txq_info *qinfo)
1432 {
1433         struct ice_tx_queue *txq;
1434
1435         txq = dev->data->tx_queues[queue_id];
1436
1437         qinfo->nb_desc = txq->nb_tx_desc;
1438
1439         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1440         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1441         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1442
1443         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1444         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1445         qinfo->conf.offloads = txq->offloads;
1446         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1447 }
1448
1449 uint32_t
1450 ice_rx_queue_count(void *rx_queue)
1451 {
1452 #define ICE_RXQ_SCAN_INTERVAL 4
1453         volatile union ice_rx_flex_desc *rxdp;
1454         struct ice_rx_queue *rxq;
1455         uint16_t desc = 0;
1456
1457         rxq = rx_queue;
1458         rxdp = &rxq->rx_ring[rxq->rx_tail];
1459         while ((desc < rxq->nb_rx_desc) &&
1460                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1461                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1462                 /**
1463                  * Check the DD bit of a rx descriptor of each 4 in a group,
1464                  * to avoid checking too frequently and downgrading performance
1465                  * too much.
1466                  */
1467                 desc += ICE_RXQ_SCAN_INTERVAL;
1468                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1469                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1470                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1471                                  desc - rxq->nb_rx_desc]);
1472         }
1473
1474         return desc;
1475 }
1476
1477 #define ICE_RX_FLEX_ERR0_BITS   \
1478         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1479          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1480          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1481          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1482          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1483          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1484
1485 /* Rx L3/L4 checksum */
1486 static inline uint64_t
1487 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1488 {
1489         uint64_t flags = 0;
1490
1491         /* check if HW has decoded the packet and checksum */
1492         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1493                 return 0;
1494
1495         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1496                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1497                 return flags;
1498         }
1499
1500         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1501                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1502         else
1503                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1504
1505         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1506                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1507         else
1508                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1509
1510         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1511                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1512
1513         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1514                 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;
1515         else
1516                 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD;
1517
1518         return flags;
1519 }
1520
1521 static inline void
1522 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1523 {
1524         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1525             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1526                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1527                 mb->vlan_tci =
1528                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1529                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1530                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1531         } else {
1532                 mb->vlan_tci = 0;
1533         }
1534
1535 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1536         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1537             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1538                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
1539                                 RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
1540                 mb->vlan_tci_outer = mb->vlan_tci;
1541                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1542                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1543                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1544                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1545         } else {
1546                 mb->vlan_tci_outer = 0;
1547         }
1548 #endif
1549         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1550                    mb->vlan_tci, mb->vlan_tci_outer);
1551 }
1552
1553 #define ICE_LOOK_AHEAD 8
1554 #if (ICE_LOOK_AHEAD != 8)
1555 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1556 #endif
1557 static inline int
1558 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1559 {
1560         volatile union ice_rx_flex_desc *rxdp;
1561         struct ice_rx_entry *rxep;
1562         struct rte_mbuf *mb;
1563         uint16_t stat_err0;
1564         uint16_t pkt_len;
1565         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1566         int32_t i, j, nb_rx = 0;
1567         uint64_t pkt_flags = 0;
1568         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1569 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1570         struct ice_vsi *vsi = rxq->vsi;
1571         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1572         uint64_t ts_ns;
1573         struct ice_adapter *ad = rxq->vsi->adapter;
1574 #endif
1575         rxdp = &rxq->rx_ring[rxq->rx_tail];
1576         rxep = &rxq->sw_ring[rxq->rx_tail];
1577
1578         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1579
1580         /* Make sure there is at least 1 packet to receive */
1581         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1582                 return 0;
1583
1584         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
1585                 rxq->hw_register_set = 1;
1586
1587         /**
1588          * Scan LOOK_AHEAD descriptors at a time to determine which
1589          * descriptors reference packets that are ready to be received.
1590          */
1591         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1592              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1593                 /* Read desc statuses backwards to avoid race condition */
1594                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1595                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1596
1597                 rte_smp_rmb();
1598
1599                 /* Compute how many status bits were set */
1600                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1601                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1602
1603                 nb_rx += nb_dd;
1604
1605                 /* Translate descriptor info to mbuf parameters */
1606                 for (j = 0; j < nb_dd; j++) {
1607                         mb = rxep[j].mbuf;
1608                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1609                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1610                         mb->data_len = pkt_len;
1611                         mb->pkt_len = pkt_len;
1612                         mb->ol_flags = 0;
1613                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1614                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1615                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1616                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1617                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1618                         rxd_to_pkt_fields_ops[rxq->rxdid](rxq, mb, &rxdp[j]);
1619 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1620                         if (ice_timestamp_dynflag > 0) {
1621                                 ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
1622                                         rxq->hw_register_set,
1623                                         rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high));
1624                                 rxq->hw_register_set = 0;
1625                                 *RTE_MBUF_DYNFIELD(mb,
1626                                         ice_timestamp_dynfield_offset,
1627                                         rte_mbuf_timestamp_t *) = ts_ns;
1628                                 mb->ol_flags |= ice_timestamp_dynflag;
1629                         }
1630
1631                         if (ad->ptp_ena && ((mb->packet_type &
1632                             RTE_PTYPE_L2_MASK) == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1633                                 rxq->time_high =
1634                                    rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high);
1635                                 mb->timesync = rxq->queue_id;
1636                                 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1637                         }
1638 #endif
1639                         mb->ol_flags |= pkt_flags;
1640                 }
1641
1642                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1643                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1644
1645                 if (nb_dd != ICE_LOOK_AHEAD)
1646                         break;
1647         }
1648
1649         /* Clear software ring entries */
1650         for (i = 0; i < nb_rx; i++)
1651                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1652
1653         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1654                    "port_id=%u, queue_id=%u, nb_rx=%d",
1655                    rxq->port_id, rxq->queue_id, nb_rx);
1656
1657         return nb_rx;
1658 }
1659
1660 static inline uint16_t
1661 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1662                        struct rte_mbuf **rx_pkts,
1663                        uint16_t nb_pkts)
1664 {
1665         uint16_t i;
1666         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1667
1668         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1669
1670         for (i = 0; i < nb_pkts; i++)
1671                 rx_pkts[i] = stage[i];
1672
1673         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1674         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1675
1676         return nb_pkts;
1677 }
1678
1679 static inline int
1680 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1681 {
1682         volatile union ice_rx_flex_desc *rxdp;
1683         struct ice_rx_entry *rxep;
1684         struct rte_mbuf *mb;
1685         uint16_t alloc_idx, i;
1686         uint64_t dma_addr;
1687         int diag;
1688
1689         /* Allocate buffers in bulk */
1690         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1691                                (rxq->rx_free_thresh - 1));
1692         rxep = &rxq->sw_ring[alloc_idx];
1693         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1694                                     rxq->rx_free_thresh);
1695         if (unlikely(diag != 0)) {
1696                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1697                 return -ENOMEM;
1698         }
1699
1700         rxdp = &rxq->rx_ring[alloc_idx];
1701         for (i = 0; i < rxq->rx_free_thresh; i++) {
1702                 if (likely(i < (rxq->rx_free_thresh - 1)))
1703                         /* Prefetch next mbuf */
1704                         rte_prefetch0(rxep[i + 1].mbuf);
1705
1706                 mb = rxep[i].mbuf;
1707                 rte_mbuf_refcnt_set(mb, 1);
1708                 mb->next = NULL;
1709                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1710                 mb->nb_segs = 1;
1711                 mb->port = rxq->port_id;
1712                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1713                 rxdp[i].read.hdr_addr = 0;
1714                 rxdp[i].read.pkt_addr = dma_addr;
1715         }
1716
1717         /* Update Rx tail register */
1718         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1719
1720         rxq->rx_free_trigger =
1721                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1722         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1723                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1724
1725         return 0;
1726 }
1727
1728 static inline uint16_t
1729 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1730 {
1731         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1732         uint16_t nb_rx = 0;
1733
1734         if (!nb_pkts)
1735                 return 0;
1736
1737         if (rxq->rx_nb_avail)
1738                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1739
1740         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1741         rxq->rx_next_avail = 0;
1742         rxq->rx_nb_avail = nb_rx;
1743         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1744
1745         if (rxq->rx_tail > rxq->rx_free_trigger) {
1746                 if (ice_rx_alloc_bufs(rxq) != 0) {
1747                         uint16_t i, j;
1748
1749                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1750                                 rxq->rx_free_thresh;
1751                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1752                                    "port_id=%u, queue_id=%u",
1753                                    rxq->port_id, rxq->queue_id);
1754                         rxq->rx_nb_avail = 0;
1755                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1756                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1757                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1758
1759                         return 0;
1760                 }
1761         }
1762
1763         if (rxq->rx_tail >= rxq->nb_rx_desc)
1764                 rxq->rx_tail = 0;
1765
1766         if (rxq->rx_nb_avail)
1767                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1768
1769         return 0;
1770 }
1771
1772 static uint16_t
1773 ice_recv_pkts_bulk_alloc(void *rx_queue,
1774                          struct rte_mbuf **rx_pkts,
1775                          uint16_t nb_pkts)
1776 {
1777         uint16_t nb_rx = 0;
1778         uint16_t n;
1779         uint16_t count;
1780
1781         if (unlikely(nb_pkts == 0))
1782                 return nb_rx;
1783
1784         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1785                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1786
1787         while (nb_pkts) {
1788                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1789                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1790                 nb_rx = (uint16_t)(nb_rx + count);
1791                 nb_pkts = (uint16_t)(nb_pkts - count);
1792                 if (count < n)
1793                         break;
1794         }
1795
1796         return nb_rx;
1797 }
1798
1799 static uint16_t
1800 ice_recv_scattered_pkts(void *rx_queue,
1801                         struct rte_mbuf **rx_pkts,
1802                         uint16_t nb_pkts)
1803 {
1804         struct ice_rx_queue *rxq = rx_queue;
1805         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1806         volatile union ice_rx_flex_desc *rxdp;
1807         union ice_rx_flex_desc rxd;
1808         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1809         struct ice_rx_entry *rxe;
1810         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1811         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1812         struct rte_mbuf *nmb; /* new allocated mbuf */
1813         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1814         uint16_t rx_id = rxq->rx_tail;
1815         uint16_t nb_rx = 0;
1816         uint16_t nb_hold = 0;
1817         uint16_t rx_packet_len;
1818         uint16_t rx_stat_err0;
1819         uint64_t dma_addr;
1820         uint64_t pkt_flags;
1821         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1822 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1823         struct ice_vsi *vsi = rxq->vsi;
1824         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1825         uint64_t ts_ns;
1826         struct ice_adapter *ad = rxq->vsi->adapter;
1827 #endif
1828
1829         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
1830                 rxq->hw_register_set = 1;
1831
1832         while (nb_rx < nb_pkts) {
1833                 rxdp = &rx_ring[rx_id];
1834                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1835
1836                 /* Check the DD bit first */
1837                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1838                         break;
1839
1840                 /* allocate mbuf */
1841                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1842                 if (unlikely(!nmb)) {
1843                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1844                         break;
1845                 }
1846                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1847
1848                 nb_hold++;
1849                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1850                 rx_id++;
1851                 if (unlikely(rx_id == rxq->nb_rx_desc))
1852                         rx_id = 0;
1853
1854                 /* Prefetch next mbuf */
1855                 rte_prefetch0(sw_ring[rx_id].mbuf);
1856
1857                 /**
1858                  * When next RX descriptor is on a cache line boundary,
1859                  * prefetch the next 4 RX descriptors and next 8 pointers
1860                  * to mbufs.
1861                  */
1862                 if ((rx_id & 0x3) == 0) {
1863                         rte_prefetch0(&rx_ring[rx_id]);
1864                         rte_prefetch0(&sw_ring[rx_id]);
1865                 }
1866
1867                 rxm = rxe->mbuf;
1868                 rxe->mbuf = nmb;
1869                 dma_addr =
1870                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1871
1872                 /* Set data buffer address and data length of the mbuf */
1873                 rxdp->read.hdr_addr = 0;
1874                 rxdp->read.pkt_addr = dma_addr;
1875                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1876                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1877                 rxm->data_len = rx_packet_len;
1878                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1879
1880                 /**
1881                  * If this is the first buffer of the received packet, set the
1882                  * pointer to the first mbuf of the packet and initialize its
1883                  * context. Otherwise, update the total length and the number
1884                  * of segments of the current scattered packet, and update the
1885                  * pointer to the last mbuf of the current packet.
1886                  */
1887                 if (!first_seg) {
1888                         first_seg = rxm;
1889                         first_seg->nb_segs = 1;
1890                         first_seg->pkt_len = rx_packet_len;
1891                 } else {
1892                         first_seg->pkt_len =
1893                                 (uint16_t)(first_seg->pkt_len +
1894                                            rx_packet_len);
1895                         first_seg->nb_segs++;
1896                         last_seg->next = rxm;
1897                 }
1898
1899                 /**
1900                  * If this is not the last buffer of the received packet,
1901                  * update the pointer to the last mbuf of the current scattered
1902                  * packet and continue to parse the RX ring.
1903                  */
1904                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1905                         last_seg = rxm;
1906                         continue;
1907                 }
1908
1909                 /**
1910                  * This is the last buffer of the received packet. If the CRC
1911                  * is not stripped by the hardware:
1912                  *  - Subtract the CRC length from the total packet length.
1913                  *  - If the last buffer only contains the whole CRC or a part
1914                  *  of it, free the mbuf associated to the last buffer. If part
1915                  *  of the CRC is also contained in the previous mbuf, subtract
1916                  *  the length of that CRC part from the data length of the
1917                  *  previous mbuf.
1918                  */
1919                 rxm->next = NULL;
1920                 if (unlikely(rxq->crc_len > 0)) {
1921                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1922                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1923                                 rte_pktmbuf_free_seg(rxm);
1924                                 first_seg->nb_segs--;
1925                                 last_seg->data_len =
1926                                         (uint16_t)(last_seg->data_len -
1927                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1928                                 last_seg->next = NULL;
1929                         } else
1930                                 rxm->data_len = (uint16_t)(rx_packet_len -
1931                                                            RTE_ETHER_CRC_LEN);
1932                 }
1933
1934                 first_seg->port = rxq->port_id;
1935                 first_seg->ol_flags = 0;
1936                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1937                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1938                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1939                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, first_seg, &rxd);
1940                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1941 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1942                 if (ice_timestamp_dynflag > 0) {
1943                         ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
1944                                 rxq->hw_register_set,
1945                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1946                         rxq->hw_register_set = 0;
1947                         *RTE_MBUF_DYNFIELD(first_seg,
1948                                 ice_timestamp_dynfield_offset,
1949                                 rte_mbuf_timestamp_t *) = ts_ns;
1950                         first_seg->ol_flags |= ice_timestamp_dynflag;
1951                 }
1952
1953                 if (ad->ptp_ena && ((first_seg->packet_type & RTE_PTYPE_L2_MASK)
1954                     == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1955                         rxq->time_high =
1956                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
1957                         first_seg->timesync = rxq->queue_id;
1958                         pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1959                 }
1960 #endif
1961                 first_seg->ol_flags |= pkt_flags;
1962                 /* Prefetch data of first segment, if configured to do so. */
1963                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1964                                           first_seg->data_off));
1965                 rx_pkts[nb_rx++] = first_seg;
1966                 first_seg = NULL;
1967         }
1968
1969         /* Record index of the next RX descriptor to probe. */
1970         rxq->rx_tail = rx_id;
1971         rxq->pkt_first_seg = first_seg;
1972         rxq->pkt_last_seg = last_seg;
1973
1974         /**
1975          * If the number of free RX descriptors is greater than the RX free
1976          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1977          * register. Update the RDT with the value of the last processed RX
1978          * descriptor minus 1, to guarantee that the RDT register is never
1979          * equal to the RDH register, which creates a "full" ring situation
1980          * from the hardware point of view.
1981          */
1982         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1983         if (nb_hold > rxq->rx_free_thresh) {
1984                 rx_id = (uint16_t)(rx_id == 0 ?
1985                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1986                 /* write TAIL register */
1987                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1988                 nb_hold = 0;
1989         }
1990         rxq->nb_rx_hold = nb_hold;
1991
1992         /* return received packet in the burst */
1993         return nb_rx;
1994 }
1995
1996 const uint32_t *
1997 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1998 {
1999         struct ice_adapter *ad =
2000                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2001         const uint32_t *ptypes;
2002
2003         static const uint32_t ptypes_os[] = {
2004                 /* refers to ice_get_default_pkt_type() */
2005                 RTE_PTYPE_L2_ETHER,
2006                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2007                 RTE_PTYPE_L2_ETHER_LLDP,
2008                 RTE_PTYPE_L2_ETHER_ARP,
2009                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2010                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2011                 RTE_PTYPE_L4_FRAG,
2012                 RTE_PTYPE_L4_ICMP,
2013                 RTE_PTYPE_L4_NONFRAG,
2014                 RTE_PTYPE_L4_SCTP,
2015                 RTE_PTYPE_L4_TCP,
2016                 RTE_PTYPE_L4_UDP,
2017                 RTE_PTYPE_TUNNEL_GRENAT,
2018                 RTE_PTYPE_TUNNEL_IP,
2019                 RTE_PTYPE_INNER_L2_ETHER,
2020                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2021                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2022                 RTE_PTYPE_INNER_L4_FRAG,
2023                 RTE_PTYPE_INNER_L4_ICMP,
2024                 RTE_PTYPE_INNER_L4_NONFRAG,
2025                 RTE_PTYPE_INNER_L4_SCTP,
2026                 RTE_PTYPE_INNER_L4_TCP,
2027                 RTE_PTYPE_INNER_L4_UDP,
2028                 RTE_PTYPE_UNKNOWN
2029         };
2030
2031         static const uint32_t ptypes_comms[] = {
2032                 /* refers to ice_get_default_pkt_type() */
2033                 RTE_PTYPE_L2_ETHER,
2034                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2035                 RTE_PTYPE_L2_ETHER_LLDP,
2036                 RTE_PTYPE_L2_ETHER_ARP,
2037                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2038                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2039                 RTE_PTYPE_L4_FRAG,
2040                 RTE_PTYPE_L4_ICMP,
2041                 RTE_PTYPE_L4_NONFRAG,
2042                 RTE_PTYPE_L4_SCTP,
2043                 RTE_PTYPE_L4_TCP,
2044                 RTE_PTYPE_L4_UDP,
2045                 RTE_PTYPE_TUNNEL_GRENAT,
2046                 RTE_PTYPE_TUNNEL_IP,
2047                 RTE_PTYPE_INNER_L2_ETHER,
2048                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2049                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2050                 RTE_PTYPE_INNER_L4_FRAG,
2051                 RTE_PTYPE_INNER_L4_ICMP,
2052                 RTE_PTYPE_INNER_L4_NONFRAG,
2053                 RTE_PTYPE_INNER_L4_SCTP,
2054                 RTE_PTYPE_INNER_L4_TCP,
2055                 RTE_PTYPE_INNER_L4_UDP,
2056                 RTE_PTYPE_TUNNEL_GTPC,
2057                 RTE_PTYPE_TUNNEL_GTPU,
2058                 RTE_PTYPE_L2_ETHER_PPPOE,
2059                 RTE_PTYPE_UNKNOWN
2060         };
2061
2062         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
2063                 ptypes = ptypes_comms;
2064         else
2065                 ptypes = ptypes_os;
2066
2067         if (dev->rx_pkt_burst == ice_recv_pkts ||
2068             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
2069             dev->rx_pkt_burst == ice_recv_scattered_pkts)
2070                 return ptypes;
2071
2072 #ifdef RTE_ARCH_X86
2073         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
2074             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
2075 #ifdef CC_AVX512_SUPPORT
2076             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
2077             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
2078             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
2079             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
2080 #endif
2081             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
2082             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
2083             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2084             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2085                 return ptypes;
2086 #endif
2087
2088         return NULL;
2089 }
2090
2091 int
2092 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2093 {
2094         volatile union ice_rx_flex_desc *rxdp;
2095         struct ice_rx_queue *rxq = rx_queue;
2096         uint32_t desc;
2097
2098         if (unlikely(offset >= rxq->nb_rx_desc))
2099                 return -EINVAL;
2100
2101         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2102                 return RTE_ETH_RX_DESC_UNAVAIL;
2103
2104         desc = rxq->rx_tail + offset;
2105         if (desc >= rxq->nb_rx_desc)
2106                 desc -= rxq->nb_rx_desc;
2107
2108         rxdp = &rxq->rx_ring[desc];
2109         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2110             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2111                 return RTE_ETH_RX_DESC_DONE;
2112
2113         return RTE_ETH_RX_DESC_AVAIL;
2114 }
2115
2116 int
2117 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2118 {
2119         struct ice_tx_queue *txq = tx_queue;
2120         volatile uint64_t *status;
2121         uint64_t mask, expect;
2122         uint32_t desc;
2123
2124         if (unlikely(offset >= txq->nb_tx_desc))
2125                 return -EINVAL;
2126
2127         desc = txq->tx_tail + offset;
2128         /* go to next desc that has the RS bit */
2129         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2130                 txq->tx_rs_thresh;
2131         if (desc >= txq->nb_tx_desc) {
2132                 desc -= txq->nb_tx_desc;
2133                 if (desc >= txq->nb_tx_desc)
2134                         desc -= txq->nb_tx_desc;
2135         }
2136
2137         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2138         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2139         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2140                                   ICE_TXD_QW1_DTYPE_S);
2141         if ((*status & mask) == expect)
2142                 return RTE_ETH_TX_DESC_DONE;
2143
2144         return RTE_ETH_TX_DESC_FULL;
2145 }
2146
2147 void
2148 ice_free_queues(struct rte_eth_dev *dev)
2149 {
2150         uint16_t i;
2151
2152         PMD_INIT_FUNC_TRACE();
2153
2154         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2155                 if (!dev->data->rx_queues[i])
2156                         continue;
2157                 ice_rx_queue_release(dev->data->rx_queues[i]);
2158                 dev->data->rx_queues[i] = NULL;
2159         }
2160         dev->data->nb_rx_queues = 0;
2161
2162         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2163                 if (!dev->data->tx_queues[i])
2164                         continue;
2165                 ice_tx_queue_release(dev->data->tx_queues[i]);
2166                 dev->data->tx_queues[i] = NULL;
2167         }
2168         dev->data->nb_tx_queues = 0;
2169 }
2170
2171 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
2172 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
2173
2174 int
2175 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2176 {
2177         struct ice_tx_queue *txq;
2178         const struct rte_memzone *tz = NULL;
2179         uint32_t ring_size;
2180         struct rte_eth_dev *dev;
2181
2182         if (!pf) {
2183                 PMD_DRV_LOG(ERR, "PF is not available");
2184                 return -EINVAL;
2185         }
2186
2187         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2188
2189         /* Allocate the TX queue data structure. */
2190         txq = rte_zmalloc_socket("ice fdir tx queue",
2191                                  sizeof(struct ice_tx_queue),
2192                                  RTE_CACHE_LINE_SIZE,
2193                                  SOCKET_ID_ANY);
2194         if (!txq) {
2195                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2196                             "tx queue structure.");
2197                 return -ENOMEM;
2198         }
2199
2200         /* Allocate TX hardware ring descriptors. */
2201         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2202         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2203
2204         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2205                                       ICE_FDIR_QUEUE_ID, ring_size,
2206                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2207         if (!tz) {
2208                 ice_tx_queue_release(txq);
2209                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2210                 return -ENOMEM;
2211         }
2212
2213         txq->mz = tz;
2214         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2215         txq->queue_id = ICE_FDIR_QUEUE_ID;
2216         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2217         txq->vsi = pf->fdir.fdir_vsi;
2218
2219         txq->tx_ring_dma = tz->iova;
2220         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2221         /*
2222          * don't need to allocate software ring and reset for the fdir
2223          * program queue just set the queue has been configured.
2224          */
2225         txq->q_set = true;
2226         pf->fdir.txq = txq;
2227
2228         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2229
2230         return ICE_SUCCESS;
2231 }
2232
2233 int
2234 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2235 {
2236         struct ice_rx_queue *rxq;
2237         const struct rte_memzone *rz = NULL;
2238         uint32_t ring_size;
2239         struct rte_eth_dev *dev;
2240
2241         if (!pf) {
2242                 PMD_DRV_LOG(ERR, "PF is not available");
2243                 return -EINVAL;
2244         }
2245
2246         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2247
2248         /* Allocate the RX queue data structure. */
2249         rxq = rte_zmalloc_socket("ice fdir rx queue",
2250                                  sizeof(struct ice_rx_queue),
2251                                  RTE_CACHE_LINE_SIZE,
2252                                  SOCKET_ID_ANY);
2253         if (!rxq) {
2254                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2255                             "rx queue structure.");
2256                 return -ENOMEM;
2257         }
2258
2259         /* Allocate RX hardware ring descriptors. */
2260         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2261         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2262
2263         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2264                                       ICE_FDIR_QUEUE_ID, ring_size,
2265                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2266         if (!rz) {
2267                 ice_rx_queue_release(rxq);
2268                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2269                 return -ENOMEM;
2270         }
2271
2272         rxq->mz = rz;
2273         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2274         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2275         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2276         rxq->vsi = pf->fdir.fdir_vsi;
2277
2278         rxq->rx_ring_dma = rz->iova;
2279         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2280                sizeof(union ice_32byte_rx_desc));
2281         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2282
2283         /*
2284          * Don't need to allocate software ring and reset for the fdir
2285          * rx queue, just set the queue has been configured.
2286          */
2287         rxq->q_set = true;
2288         pf->fdir.rxq = rxq;
2289
2290         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2291
2292         return ICE_SUCCESS;
2293 }
2294
2295 uint16_t
2296 ice_recv_pkts(void *rx_queue,
2297               struct rte_mbuf **rx_pkts,
2298               uint16_t nb_pkts)
2299 {
2300         struct ice_rx_queue *rxq = rx_queue;
2301         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2302         volatile union ice_rx_flex_desc *rxdp;
2303         union ice_rx_flex_desc rxd;
2304         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2305         struct ice_rx_entry *rxe;
2306         struct rte_mbuf *nmb; /* new allocated mbuf */
2307         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2308         uint16_t rx_id = rxq->rx_tail;
2309         uint16_t nb_rx = 0;
2310         uint16_t nb_hold = 0;
2311         uint16_t rx_packet_len;
2312         uint16_t rx_stat_err0;
2313         uint64_t dma_addr;
2314         uint64_t pkt_flags;
2315         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2316 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2317         struct ice_vsi *vsi = rxq->vsi;
2318         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2319         uint64_t ts_ns;
2320         struct ice_adapter *ad = rxq->vsi->adapter;
2321 #endif
2322
2323         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
2324                 rxq->hw_register_set = 1;
2325
2326         while (nb_rx < nb_pkts) {
2327                 rxdp = &rx_ring[rx_id];
2328                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2329
2330                 /* Check the DD bit first */
2331                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2332                         break;
2333
2334                 /* allocate mbuf */
2335                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2336                 if (unlikely(!nmb)) {
2337                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2338                         break;
2339                 }
2340                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2341
2342                 nb_hold++;
2343                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2344                 rx_id++;
2345                 if (unlikely(rx_id == rxq->nb_rx_desc))
2346                         rx_id = 0;
2347                 rxm = rxe->mbuf;
2348                 rxe->mbuf = nmb;
2349                 dma_addr =
2350                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2351
2352                 /**
2353                  * fill the read format of descriptor with physic address in
2354                  * new allocated mbuf: nmb
2355                  */
2356                 rxdp->read.hdr_addr = 0;
2357                 rxdp->read.pkt_addr = dma_addr;
2358
2359                 /* calculate rx_packet_len of the received pkt */
2360                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2361                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2362
2363                 /* fill old mbuf with received descriptor: rxd */
2364                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2365                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2366                 rxm->nb_segs = 1;
2367                 rxm->next = NULL;
2368                 rxm->pkt_len = rx_packet_len;
2369                 rxm->data_len = rx_packet_len;
2370                 rxm->port = rxq->port_id;
2371                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2372                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2373                 ice_rxd_to_vlan_tci(rxm, &rxd);
2374                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, rxm, &rxd);
2375                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2376 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2377                 if (ice_timestamp_dynflag > 0) {
2378                         ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
2379                                 rxq->hw_register_set,
2380                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
2381                         rxq->hw_register_set = 0;
2382                         *RTE_MBUF_DYNFIELD(rxm,
2383                                 ice_timestamp_dynfield_offset,
2384                                 rte_mbuf_timestamp_t *) = ts_ns;
2385                         rxm->ol_flags |= ice_timestamp_dynflag;
2386                 }
2387
2388                 if (ad->ptp_ena && ((rxm->packet_type & RTE_PTYPE_L2_MASK) ==
2389                     RTE_PTYPE_L2_ETHER_TIMESYNC)) {
2390                         rxq->time_high =
2391                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2392                         rxm->timesync = rxq->queue_id;
2393                         pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
2394                 }
2395 #endif
2396                 rxm->ol_flags |= pkt_flags;
2397                 /* copy old mbuf to rx_pkts */
2398                 rx_pkts[nb_rx++] = rxm;
2399         }
2400         rxq->rx_tail = rx_id;
2401         /**
2402          * If the number of free RX descriptors is greater than the RX free
2403          * threshold of the queue, advance the receive tail register of queue.
2404          * Update that register with the value of the last processed RX
2405          * descriptor minus 1.
2406          */
2407         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2408         if (nb_hold > rxq->rx_free_thresh) {
2409                 rx_id = (uint16_t)(rx_id == 0 ?
2410                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2411                 /* write TAIL register */
2412                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2413                 nb_hold = 0;
2414         }
2415         rxq->nb_rx_hold = nb_hold;
2416
2417         /* return received packet in the burst */
2418         return nb_rx;
2419 }
2420
2421 static inline void
2422 ice_parse_tunneling_params(uint64_t ol_flags,
2423                             union ice_tx_offload tx_offload,
2424                             uint32_t *cd_tunneling)
2425 {
2426         /* EIPT: External (outer) IP header type */
2427         if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
2428                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2429         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
2430                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2431         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
2432                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2433
2434         /* EIPLEN: External (outer) IP header length, in DWords */
2435         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2436                 ICE_TXD_CTX_QW0_EIPLEN_S;
2437
2438         /* L4TUNT: L4 Tunneling Type */
2439         switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
2440         case RTE_MBUF_F_TX_TUNNEL_IPIP:
2441                 /* for non UDP / GRE tunneling, set to 00b */
2442                 break;
2443         case RTE_MBUF_F_TX_TUNNEL_VXLAN:
2444         case RTE_MBUF_F_TX_TUNNEL_GTP:
2445         case RTE_MBUF_F_TX_TUNNEL_GENEVE:
2446                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2447                 break;
2448         case RTE_MBUF_F_TX_TUNNEL_GRE:
2449                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2450                 break;
2451         default:
2452                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2453                 return;
2454         }
2455
2456         /* L4TUNLEN: L4 Tunneling Length, in Words
2457          *
2458          * We depend on app to set rte_mbuf.l2_len correctly.
2459          * For IP in GRE it should be set to the length of the GRE
2460          * header;
2461          * For MAC in GRE or MAC in UDP it should be set to the length
2462          * of the GRE or UDP headers plus the inner MAC up to including
2463          * its last Ethertype.
2464          * If MPLS labels exists, it should include them as well.
2465          */
2466         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2467                 ICE_TXD_CTX_QW0_NATLEN_S;
2468
2469         /**
2470          * Calculate the tunneling UDP checksum.
2471          * Shall be set only if L4TUNT = 01b and EIPT is not zero
2472          */
2473         if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2474             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2475                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2476 }
2477
2478 static inline void
2479 ice_txd_enable_checksum(uint64_t ol_flags,
2480                         uint32_t *td_cmd,
2481                         uint32_t *td_offset,
2482                         union ice_tx_offload tx_offload)
2483 {
2484         /* Set MACLEN */
2485         if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2486                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2487                         << ICE_TX_DESC_LEN_MACLEN_S;
2488         else
2489                 *td_offset |= (tx_offload.l2_len >> 1)
2490                         << ICE_TX_DESC_LEN_MACLEN_S;
2491
2492         /* Enable L3 checksum offloads */
2493         /*Tunnel package usage outer len enable L3 checksum offload*/
2494         if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
2495                 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
2496                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2497                         *td_offset |= (tx_offload.outer_l3_len >> 2) <<
2498                                 ICE_TX_DESC_LEN_IPLEN_S;
2499                 } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2500                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2501                         *td_offset |= (tx_offload.outer_l3_len >> 2) <<
2502                                 ICE_TX_DESC_LEN_IPLEN_S;
2503                 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2504                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2505                         *td_offset |= (tx_offload.outer_l3_len >> 2) <<
2506                                 ICE_TX_DESC_LEN_IPLEN_S;
2507                 }
2508         } else {
2509                 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
2510                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2511                         *td_offset |= (tx_offload.l3_len >> 2) <<
2512                                 ICE_TX_DESC_LEN_IPLEN_S;
2513                 } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2514                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2515                         *td_offset |= (tx_offload.l3_len >> 2) <<
2516                                 ICE_TX_DESC_LEN_IPLEN_S;
2517                 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2518                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2519                         *td_offset |= (tx_offload.l3_len >> 2) <<
2520                                 ICE_TX_DESC_LEN_IPLEN_S;
2521                 }
2522         }
2523
2524         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2525                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2526                 *td_offset |= (tx_offload.l4_len >> 2) <<
2527                               ICE_TX_DESC_LEN_L4_LEN_S;
2528                 return;
2529         }
2530
2531         /* Enable L4 checksum offloads */
2532         switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2533         case RTE_MBUF_F_TX_TCP_CKSUM:
2534                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2535                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2536                               ICE_TX_DESC_LEN_L4_LEN_S;
2537                 break;
2538         case RTE_MBUF_F_TX_SCTP_CKSUM:
2539                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2540                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2541                               ICE_TX_DESC_LEN_L4_LEN_S;
2542                 break;
2543         case RTE_MBUF_F_TX_UDP_CKSUM:
2544                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2545                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2546                               ICE_TX_DESC_LEN_L4_LEN_S;
2547                 break;
2548         default:
2549                 break;
2550         }
2551 }
2552
2553 static inline int
2554 ice_xmit_cleanup(struct ice_tx_queue *txq)
2555 {
2556         struct ice_tx_entry *sw_ring = txq->sw_ring;
2557         volatile struct ice_tx_desc *txd = txq->tx_ring;
2558         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2559         uint16_t nb_tx_desc = txq->nb_tx_desc;
2560         uint16_t desc_to_clean_to;
2561         uint16_t nb_tx_to_clean;
2562
2563         /* Determine the last descriptor needing to be cleaned */
2564         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2565         if (desc_to_clean_to >= nb_tx_desc)
2566                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2567
2568         /* Check to make sure the last descriptor to clean is done */
2569         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2570         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2571             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2572                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2573                            "(port=%d queue=%d) value=0x%"PRIx64"\n",
2574                            desc_to_clean_to,
2575                            txq->port_id, txq->queue_id,
2576                            txd[desc_to_clean_to].cmd_type_offset_bsz);
2577                 /* Failed to clean any descriptors */
2578                 return -1;
2579         }
2580
2581         /* Figure out how many descriptors will be cleaned */
2582         if (last_desc_cleaned > desc_to_clean_to)
2583                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2584                                             desc_to_clean_to);
2585         else
2586                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2587                                             last_desc_cleaned);
2588
2589         /* The last descriptor to clean is done, so that means all the
2590          * descriptors from the last descriptor that was cleaned
2591          * up to the last descriptor with the RS bit set
2592          * are done. Only reset the threshold descriptor.
2593          */
2594         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2595
2596         /* Update the txq to reflect the last descriptor that was cleaned */
2597         txq->last_desc_cleaned = desc_to_clean_to;
2598         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2599
2600         return 0;
2601 }
2602
2603 /* Construct the tx flags */
2604 static inline uint64_t
2605 ice_build_ctob(uint32_t td_cmd,
2606                uint32_t td_offset,
2607                uint16_t size,
2608                uint32_t td_tag)
2609 {
2610         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2611                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2612                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2613                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2614                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2615 }
2616
2617 /* Check if the context descriptor is needed for TX offloading */
2618 static inline uint16_t
2619 ice_calc_context_desc(uint64_t flags)
2620 {
2621         static uint64_t mask = RTE_MBUF_F_TX_TCP_SEG |
2622                 RTE_MBUF_F_TX_QINQ |
2623                 RTE_MBUF_F_TX_OUTER_IP_CKSUM |
2624                 RTE_MBUF_F_TX_TUNNEL_MASK |
2625                 RTE_MBUF_F_TX_IEEE1588_TMST;
2626
2627         return (flags & mask) ? 1 : 0;
2628 }
2629
2630 /* set ice TSO context descriptor */
2631 static inline uint64_t
2632 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2633 {
2634         uint64_t ctx_desc = 0;
2635         uint32_t cd_cmd, hdr_len, cd_tso_len;
2636
2637         if (!tx_offload.l4_len) {
2638                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2639                 return ctx_desc;
2640         }
2641
2642         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2643         hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
2644                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2645
2646         cd_cmd = ICE_TX_CTX_DESC_TSO;
2647         cd_tso_len = mbuf->pkt_len - hdr_len;
2648         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2649                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2650                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2651
2652         return ctx_desc;
2653 }
2654
2655 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2656 #define ICE_MAX_DATA_PER_TXD \
2657         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2658 /* Calculate the number of TX descriptors needed for each pkt */
2659 static inline uint16_t
2660 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2661 {
2662         struct rte_mbuf *txd = tx_pkt;
2663         uint16_t count = 0;
2664
2665         while (txd != NULL) {
2666                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2667                 txd = txd->next;
2668         }
2669
2670         return count;
2671 }
2672
2673 uint16_t
2674 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2675 {
2676         struct ice_tx_queue *txq;
2677         volatile struct ice_tx_desc *tx_ring;
2678         volatile struct ice_tx_desc *txd;
2679         struct ice_tx_entry *sw_ring;
2680         struct ice_tx_entry *txe, *txn;
2681         struct rte_mbuf *tx_pkt;
2682         struct rte_mbuf *m_seg;
2683         uint32_t cd_tunneling_params;
2684         uint16_t tx_id;
2685         uint16_t nb_tx;
2686         uint16_t nb_used;
2687         uint16_t nb_ctx;
2688         uint32_t td_cmd = 0;
2689         uint32_t td_offset = 0;
2690         uint32_t td_tag = 0;
2691         uint16_t tx_last;
2692         uint16_t slen;
2693         uint64_t buf_dma_addr;
2694         uint64_t ol_flags;
2695         union ice_tx_offload tx_offload = {0};
2696
2697         txq = tx_queue;
2698         sw_ring = txq->sw_ring;
2699         tx_ring = txq->tx_ring;
2700         tx_id = txq->tx_tail;
2701         txe = &sw_ring[tx_id];
2702
2703         /* Check if the descriptor ring needs to be cleaned. */
2704         if (txq->nb_tx_free < txq->tx_free_thresh)
2705                 (void)ice_xmit_cleanup(txq);
2706
2707         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2708                 tx_pkt = *tx_pkts++;
2709
2710                 td_cmd = 0;
2711                 td_tag = 0;
2712                 td_offset = 0;
2713                 ol_flags = tx_pkt->ol_flags;
2714                 tx_offload.l2_len = tx_pkt->l2_len;
2715                 tx_offload.l3_len = tx_pkt->l3_len;
2716                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2717                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2718                 tx_offload.l4_len = tx_pkt->l4_len;
2719                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2720                 /* Calculate the number of context descriptors needed. */
2721                 nb_ctx = ice_calc_context_desc(ol_flags);
2722
2723                 /* The number of descriptors that must be allocated for
2724                  * a packet equals to the number of the segments of that
2725                  * packet plus the number of context descriptor if needed.
2726                  * Recalculate the needed tx descs when TSO enabled in case
2727                  * the mbuf data size exceeds max data size that hw allows
2728                  * per tx desc.
2729                  */
2730                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2731                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2732                                              nb_ctx);
2733                 else
2734                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2735                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2736
2737                 /* Circular ring */
2738                 if (tx_last >= txq->nb_tx_desc)
2739                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2740
2741                 if (nb_used > txq->nb_tx_free) {
2742                         if (ice_xmit_cleanup(txq) != 0) {
2743                                 if (nb_tx == 0)
2744                                         return 0;
2745                                 goto end_of_tx;
2746                         }
2747                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2748                                 while (nb_used > txq->nb_tx_free) {
2749                                         if (ice_xmit_cleanup(txq) != 0) {
2750                                                 if (nb_tx == 0)
2751                                                         return 0;
2752                                                 goto end_of_tx;
2753                                         }
2754                                 }
2755                         }
2756                 }
2757
2758                 /* Descriptor based VLAN insertion */
2759                 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
2760                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2761                         td_tag = tx_pkt->vlan_tci;
2762                 }
2763
2764                 /* Fill in tunneling parameters if necessary */
2765                 cd_tunneling_params = 0;
2766                 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2767                         ice_parse_tunneling_params(ol_flags, tx_offload,
2768                                                    &cd_tunneling_params);
2769
2770                 /* Enable checksum offloading */
2771                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2772                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2773                                                 &td_offset, tx_offload);
2774
2775                 if (nb_ctx) {
2776                         /* Setup TX context descriptor if required */
2777                         volatile struct ice_tx_ctx_desc *ctx_txd =
2778                                 (volatile struct ice_tx_ctx_desc *)
2779                                         &tx_ring[tx_id];
2780                         uint16_t cd_l2tag2 = 0;
2781                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2782
2783                         txn = &sw_ring[txe->next_id];
2784                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2785                         if (txe->mbuf) {
2786                                 rte_pktmbuf_free_seg(txe->mbuf);
2787                                 txe->mbuf = NULL;
2788                         }
2789
2790                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2791                                 cd_type_cmd_tso_mss |=
2792                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2793                         else if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
2794                                 cd_type_cmd_tso_mss |=
2795                                         ((uint64_t)ICE_TX_CTX_DESC_TSYN <<
2796                                         ICE_TXD_CTX_QW1_CMD_S);
2797
2798                         ctx_txd->tunneling_params =
2799                                 rte_cpu_to_le_32(cd_tunneling_params);
2800
2801                         /* TX context descriptor based double VLAN insert */
2802                         if (ol_flags & RTE_MBUF_F_TX_QINQ) {
2803                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2804                                 cd_type_cmd_tso_mss |=
2805                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2806                                          ICE_TXD_CTX_QW1_CMD_S);
2807                         }
2808                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2809                         ctx_txd->qw1 =
2810                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2811
2812                         txe->last_id = tx_last;
2813                         tx_id = txe->next_id;
2814                         txe = txn;
2815                 }
2816                 m_seg = tx_pkt;
2817
2818                 do {
2819                         txd = &tx_ring[tx_id];
2820                         txn = &sw_ring[txe->next_id];
2821
2822                         if (txe->mbuf)
2823                                 rte_pktmbuf_free_seg(txe->mbuf);
2824                         txe->mbuf = m_seg;
2825
2826                         /* Setup TX Descriptor */
2827                         slen = m_seg->data_len;
2828                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2829
2830                         while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
2831                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2832                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2833                                 txd->cmd_type_offset_bsz =
2834                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2835                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2836                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2837                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2838                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2839                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2840
2841                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2842                                 slen -= ICE_MAX_DATA_PER_TXD;
2843
2844                                 txe->last_id = tx_last;
2845                                 tx_id = txe->next_id;
2846                                 txe = txn;
2847                                 txd = &tx_ring[tx_id];
2848                                 txn = &sw_ring[txe->next_id];
2849                         }
2850
2851                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2852                         txd->cmd_type_offset_bsz =
2853                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2854                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2855                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2856                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2857                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2858
2859                         txe->last_id = tx_last;
2860                         tx_id = txe->next_id;
2861                         txe = txn;
2862                         m_seg = m_seg->next;
2863                 } while (m_seg);
2864
2865                 /* fill the last descriptor with End of Packet (EOP) bit */
2866                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2867                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2868                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2869
2870                 /* set RS bit on the last descriptor of one packet */
2871                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2872                         PMD_TX_LOG(DEBUG,
2873                                    "Setting RS bit on TXD id="
2874                                    "%4u (port=%d queue=%d)",
2875                                    tx_last, txq->port_id, txq->queue_id);
2876
2877                         td_cmd |= ICE_TX_DESC_CMD_RS;
2878
2879                         /* Update txq RS bit counters */
2880                         txq->nb_tx_used = 0;
2881                 }
2882                 txd->cmd_type_offset_bsz |=
2883                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2884                                          ICE_TXD_QW1_CMD_S);
2885         }
2886 end_of_tx:
2887         /* update Tail register */
2888         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2889         txq->tx_tail = tx_id;
2890
2891         return nb_tx;
2892 }
2893
2894 static __rte_always_inline int
2895 ice_tx_free_bufs(struct ice_tx_queue *txq)
2896 {
2897         struct ice_tx_entry *txep;
2898         uint16_t i;
2899
2900         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2901              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2902             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2903                 return 0;
2904
2905         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2906
2907         for (i = 0; i < txq->tx_rs_thresh; i++)
2908                 rte_prefetch0((txep + i)->mbuf);
2909
2910         if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
2911                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2912                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2913                         txep->mbuf = NULL;
2914                 }
2915         } else {
2916                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2917                         rte_pktmbuf_free_seg(txep->mbuf);
2918                         txep->mbuf = NULL;
2919                 }
2920         }
2921
2922         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2923         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2924         if (txq->tx_next_dd >= txq->nb_tx_desc)
2925                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2926
2927         return txq->tx_rs_thresh;
2928 }
2929
2930 static int
2931 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2932                         uint32_t free_cnt)
2933 {
2934         struct ice_tx_entry *swr_ring = txq->sw_ring;
2935         uint16_t i, tx_last, tx_id;
2936         uint16_t nb_tx_free_last;
2937         uint16_t nb_tx_to_clean;
2938         uint32_t pkt_cnt;
2939
2940         /* Start free mbuf from the next of tx_tail */
2941         tx_last = txq->tx_tail;
2942         tx_id  = swr_ring[tx_last].next_id;
2943
2944         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2945                 return 0;
2946
2947         nb_tx_to_clean = txq->nb_tx_free;
2948         nb_tx_free_last = txq->nb_tx_free;
2949         if (!free_cnt)
2950                 free_cnt = txq->nb_tx_desc;
2951
2952         /* Loop through swr_ring to count the amount of
2953          * freeable mubfs and packets.
2954          */
2955         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2956                 for (i = 0; i < nb_tx_to_clean &&
2957                         pkt_cnt < free_cnt &&
2958                         tx_id != tx_last; i++) {
2959                         if (swr_ring[tx_id].mbuf != NULL) {
2960                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2961                                 swr_ring[tx_id].mbuf = NULL;
2962
2963                                 /*
2964                                  * last segment in the packet,
2965                                  * increment packet count
2966                                  */
2967                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2968                         }
2969
2970                         tx_id = swr_ring[tx_id].next_id;
2971                 }
2972
2973                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2974                         txq->nb_tx_free || tx_id == tx_last)
2975                         break;
2976
2977                 if (pkt_cnt < free_cnt) {
2978                         if (ice_xmit_cleanup(txq))
2979                                 break;
2980
2981                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2982                         nb_tx_free_last = txq->nb_tx_free;
2983                 }
2984         }
2985
2986         return (int)pkt_cnt;
2987 }
2988
2989 #ifdef RTE_ARCH_X86
2990 static int
2991 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2992                         uint32_t free_cnt __rte_unused)
2993 {
2994         return -ENOTSUP;
2995 }
2996 #endif
2997
2998 static int
2999 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
3000                         uint32_t free_cnt)
3001 {
3002         int i, n, cnt;
3003
3004         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
3005                 free_cnt = txq->nb_tx_desc;
3006
3007         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
3008
3009         for (i = 0; i < cnt; i += n) {
3010                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
3011                         break;
3012
3013                 n = ice_tx_free_bufs(txq);
3014
3015                 if (n == 0)
3016                         break;
3017         }
3018
3019         return i;
3020 }
3021
3022 int
3023 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
3024 {
3025         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
3026         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
3027         struct ice_adapter *ad =
3028                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3029
3030 #ifdef RTE_ARCH_X86
3031         if (ad->tx_vec_allowed)
3032                 return ice_tx_done_cleanup_vec(q, free_cnt);
3033 #endif
3034         if (ad->tx_simple_allowed)
3035                 return ice_tx_done_cleanup_simple(q, free_cnt);
3036         else
3037                 return ice_tx_done_cleanup_full(q, free_cnt);
3038 }
3039
3040 /* Populate 4 descriptors with data from 4 mbufs */
3041 static inline void
3042 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3043 {
3044         uint64_t dma_addr;
3045         uint32_t i;
3046
3047         for (i = 0; i < 4; i++, txdp++, pkts++) {
3048                 dma_addr = rte_mbuf_data_iova(*pkts);
3049                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3050                 txdp->cmd_type_offset_bsz =
3051                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3052                                        (*pkts)->data_len, 0);
3053         }
3054 }
3055
3056 /* Populate 1 descriptor with data from 1 mbuf */
3057 static inline void
3058 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3059 {
3060         uint64_t dma_addr;
3061
3062         dma_addr = rte_mbuf_data_iova(*pkts);
3063         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3064         txdp->cmd_type_offset_bsz =
3065                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3066                                (*pkts)->data_len, 0);
3067 }
3068
3069 static inline void
3070 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
3071                     uint16_t nb_pkts)
3072 {
3073         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
3074         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
3075         const int N_PER_LOOP = 4;
3076         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
3077         int mainpart, leftover;
3078         int i, j;
3079
3080         /**
3081          * Process most of the packets in chunks of N pkts.  Any
3082          * leftover packets will get processed one at a time.
3083          */
3084         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
3085         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
3086         for (i = 0; i < mainpart; i += N_PER_LOOP) {
3087                 /* Copy N mbuf pointers to the S/W ring */
3088                 for (j = 0; j < N_PER_LOOP; ++j)
3089                         (txep + i + j)->mbuf = *(pkts + i + j);
3090                 tx4(txdp + i, pkts + i);
3091         }
3092
3093         if (unlikely(leftover > 0)) {
3094                 for (i = 0; i < leftover; ++i) {
3095                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
3096                         tx1(txdp + mainpart + i, pkts + mainpart + i);
3097                 }
3098         }
3099 }
3100
3101 static inline uint16_t
3102 tx_xmit_pkts(struct ice_tx_queue *txq,
3103              struct rte_mbuf **tx_pkts,
3104              uint16_t nb_pkts)
3105 {
3106         volatile struct ice_tx_desc *txr = txq->tx_ring;
3107         uint16_t n = 0;
3108
3109         /**
3110          * Begin scanning the H/W ring for done descriptors when the number
3111          * of available descriptors drops below tx_free_thresh. For each done
3112          * descriptor, free the associated buffer.
3113          */
3114         if (txq->nb_tx_free < txq->tx_free_thresh)
3115                 ice_tx_free_bufs(txq);
3116
3117         /* Use available descriptor only */
3118         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
3119         if (unlikely(!nb_pkts))
3120                 return 0;
3121
3122         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
3123         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
3124                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
3125                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
3126                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3127                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3128                                          ICE_TXD_QW1_CMD_S);
3129                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3130                 txq->tx_tail = 0;
3131         }
3132
3133         /* Fill hardware descriptor ring with mbuf data */
3134         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3135         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3136
3137         /* Determine if RS bit needs to be set */
3138         if (txq->tx_tail > txq->tx_next_rs) {
3139                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3140                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3141                                          ICE_TXD_QW1_CMD_S);
3142                 txq->tx_next_rs =
3143                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3144                 if (txq->tx_next_rs >= txq->nb_tx_desc)
3145                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3146         }
3147
3148         if (txq->tx_tail >= txq->nb_tx_desc)
3149                 txq->tx_tail = 0;
3150
3151         /* Update the tx tail register */
3152         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3153
3154         return nb_pkts;
3155 }
3156
3157 static uint16_t
3158 ice_xmit_pkts_simple(void *tx_queue,
3159                      struct rte_mbuf **tx_pkts,
3160                      uint16_t nb_pkts)
3161 {
3162         uint16_t nb_tx = 0;
3163
3164         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3165                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3166                                     tx_pkts, nb_pkts);
3167
3168         while (nb_pkts) {
3169                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3170                                                       ICE_TX_MAX_BURST);
3171
3172                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3173                                    &tx_pkts[nb_tx], num);
3174                 nb_tx = (uint16_t)(nb_tx + ret);
3175                 nb_pkts = (uint16_t)(nb_pkts - ret);
3176                 if (ret < num)
3177                         break;
3178         }
3179
3180         return nb_tx;
3181 }
3182
3183 void __rte_cold
3184 ice_set_rx_function(struct rte_eth_dev *dev)
3185 {
3186         PMD_INIT_FUNC_TRACE();
3187         struct ice_adapter *ad =
3188                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3189 #ifdef RTE_ARCH_X86
3190         struct ice_rx_queue *rxq;
3191         int i;
3192         int rx_check_ret = -1;
3193
3194         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3195                 ad->rx_use_avx512 = false;
3196                 ad->rx_use_avx2 = false;
3197                 rx_check_ret = ice_rx_vec_dev_check(dev);
3198                 if (ad->ptp_ena)
3199                         rx_check_ret = -1;
3200                 ad->rx_vec_offload_support =
3201                                 (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH);
3202                 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3203                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3204                         ad->rx_vec_allowed = true;
3205                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3206                                 rxq = dev->data->rx_queues[i];
3207                                 if (rxq && ice_rxq_vec_setup(rxq)) {
3208                                         ad->rx_vec_allowed = false;
3209                                         break;
3210                                 }
3211                         }
3212
3213                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3214                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3215                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3216 #ifdef CC_AVX512_SUPPORT
3217                                 ad->rx_use_avx512 = true;
3218 #else
3219                         PMD_DRV_LOG(NOTICE,
3220                                 "AVX512 is not supported in build env");
3221 #endif
3222                         if (!ad->rx_use_avx512 &&
3223                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3224                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3225                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3226                                 ad->rx_use_avx2 = true;
3227
3228                 } else {
3229                         ad->rx_vec_allowed = false;
3230                 }
3231         }
3232
3233         if (ad->rx_vec_allowed) {
3234                 if (dev->data->scattered_rx) {
3235                         if (ad->rx_use_avx512) {
3236 #ifdef CC_AVX512_SUPPORT
3237                                 if (ad->rx_vec_offload_support) {
3238                                         PMD_DRV_LOG(NOTICE,
3239                                                 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3240                                                 dev->data->port_id);
3241                                         dev->rx_pkt_burst =
3242                                                 ice_recv_scattered_pkts_vec_avx512_offload;
3243                                 } else {
3244                                         PMD_DRV_LOG(NOTICE,
3245                                                 "Using AVX512 Vector Scattered Rx (port %d).",
3246                                                 dev->data->port_id);
3247                                         dev->rx_pkt_burst =
3248                                                 ice_recv_scattered_pkts_vec_avx512;
3249                                 }
3250 #endif
3251                         } else if (ad->rx_use_avx2) {
3252                                 if (ad->rx_vec_offload_support) {
3253                                         PMD_DRV_LOG(NOTICE,
3254                                                     "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3255                                                     dev->data->port_id);
3256                                         dev->rx_pkt_burst =
3257                                                 ice_recv_scattered_pkts_vec_avx2_offload;
3258                                 } else {
3259                                         PMD_DRV_LOG(NOTICE,
3260                                                     "Using AVX2 Vector Scattered Rx (port %d).",
3261                                                     dev->data->port_id);
3262                                         dev->rx_pkt_burst =
3263                                                 ice_recv_scattered_pkts_vec_avx2;
3264                                 }
3265                         } else {
3266                                 PMD_DRV_LOG(DEBUG,
3267                                         "Using Vector Scattered Rx (port %d).",
3268                                         dev->data->port_id);
3269                                 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3270                         }
3271                 } else {
3272                         if (ad->rx_use_avx512) {
3273 #ifdef CC_AVX512_SUPPORT
3274                                 if (ad->rx_vec_offload_support) {
3275                                         PMD_DRV_LOG(NOTICE,
3276                                                 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3277                                                 dev->data->port_id);
3278                                         dev->rx_pkt_burst =
3279                                                 ice_recv_pkts_vec_avx512_offload;
3280                                 } else {
3281                                         PMD_DRV_LOG(NOTICE,
3282                                                 "Using AVX512 Vector Rx (port %d).",
3283                                                 dev->data->port_id);
3284                                         dev->rx_pkt_burst =
3285                                                 ice_recv_pkts_vec_avx512;
3286                                 }
3287 #endif
3288                         } else if (ad->rx_use_avx2) {
3289                                 if (ad->rx_vec_offload_support) {
3290                                         PMD_DRV_LOG(NOTICE,
3291                                                     "Using AVX2 OFFLOAD Vector Rx (port %d).",
3292                                                     dev->data->port_id);
3293                                         dev->rx_pkt_burst =
3294                                                 ice_recv_pkts_vec_avx2_offload;
3295                                 } else {
3296                                         PMD_DRV_LOG(NOTICE,
3297                                                     "Using AVX2 Vector Rx (port %d).",
3298                                                     dev->data->port_id);
3299                                         dev->rx_pkt_burst =
3300                                                 ice_recv_pkts_vec_avx2;
3301                                 }
3302                         } else {
3303                                 PMD_DRV_LOG(DEBUG,
3304                                         "Using Vector Rx (port %d).",
3305                                         dev->data->port_id);
3306                                 dev->rx_pkt_burst = ice_recv_pkts_vec;
3307                         }
3308                 }
3309                 return;
3310         }
3311
3312 #endif
3313
3314         if (dev->data->scattered_rx) {
3315                 /* Set the non-LRO scattered function */
3316                 PMD_INIT_LOG(DEBUG,
3317                              "Using a Scattered function on port %d.",
3318                              dev->data->port_id);
3319                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3320         } else if (ad->rx_bulk_alloc_allowed) {
3321                 PMD_INIT_LOG(DEBUG,
3322                              "Rx Burst Bulk Alloc Preconditions are "
3323                              "satisfied. Rx Burst Bulk Alloc function "
3324                              "will be used on port %d.",
3325                              dev->data->port_id);
3326                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3327         } else {
3328                 PMD_INIT_LOG(DEBUG,
3329                              "Rx Burst Bulk Alloc Preconditions are not "
3330                              "satisfied, Normal Rx will be used on port %d.",
3331                              dev->data->port_id);
3332                 dev->rx_pkt_burst = ice_recv_pkts;
3333         }
3334 }
3335
3336 static const struct {
3337         eth_rx_burst_t pkt_burst;
3338         const char *info;
3339 } ice_rx_burst_infos[] = {
3340         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3341         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3342         { ice_recv_pkts,                    "Scalar" },
3343 #ifdef RTE_ARCH_X86
3344 #ifdef CC_AVX512_SUPPORT
3345         { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3346         { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3347         { ice_recv_pkts_vec_avx512,           "Vector AVX512" },
3348         { ice_recv_pkts_vec_avx512_offload,   "Offload Vector AVX512" },
3349 #endif
3350         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3351         { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3352         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3353         { ice_recv_pkts_vec_avx2_offload,   "Offload Vector AVX2" },
3354         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3355         { ice_recv_pkts_vec,                "Vector SSE" },
3356 #endif
3357 };
3358
3359 int
3360 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3361                       struct rte_eth_burst_mode *mode)
3362 {
3363         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3364         int ret = -EINVAL;
3365         unsigned int i;
3366
3367         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3368                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3369                         snprintf(mode->info, sizeof(mode->info), "%s",
3370                                  ice_rx_burst_infos[i].info);
3371                         ret = 0;
3372                         break;
3373                 }
3374         }
3375
3376         return ret;
3377 }
3378
3379 void __rte_cold
3380 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3381 {
3382         struct ice_adapter *ad =
3383                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3384
3385         /* Use a simple Tx queue if possible (only fast free is allowed) */
3386         ad->tx_simple_allowed =
3387                 (txq->offloads ==
3388                 (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3389                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3390
3391         if (ad->tx_simple_allowed)
3392                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3393                              txq->queue_id);
3394         else
3395                 PMD_INIT_LOG(DEBUG,
3396                              "Simple Tx can NOT be enabled on Tx queue %u.",
3397                              txq->queue_id);
3398 }
3399
3400 /*********************************************************************
3401  *
3402  *  TX prep functions
3403  *
3404  **********************************************************************/
3405 /* The default values of TSO MSS */
3406 #define ICE_MIN_TSO_MSS            64
3407 #define ICE_MAX_TSO_MSS            9728
3408 #define ICE_MAX_TSO_FRAME_SIZE     262144
3409 uint16_t
3410 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3411               uint16_t nb_pkts)
3412 {
3413         int i, ret;
3414         uint64_t ol_flags;
3415         struct rte_mbuf *m;
3416
3417         for (i = 0; i < nb_pkts; i++) {
3418                 m = tx_pkts[i];
3419                 ol_flags = m->ol_flags;
3420
3421                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
3422                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3423                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3424                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3425                         /**
3426                          * MSS outside the range are considered malicious
3427                          */
3428                         rte_errno = EINVAL;
3429                         return i;
3430                 }
3431
3432 #ifdef RTE_ETHDEV_DEBUG_TX
3433                 ret = rte_validate_tx_offload(m);
3434                 if (ret != 0) {
3435                         rte_errno = -ret;
3436                         return i;
3437                 }
3438 #endif
3439                 ret = rte_net_intel_cksum_prepare(m);
3440                 if (ret != 0) {
3441                         rte_errno = -ret;
3442                         return i;
3443                 }
3444         }
3445         return i;
3446 }
3447
3448 void __rte_cold
3449 ice_set_tx_function(struct rte_eth_dev *dev)
3450 {
3451         struct ice_adapter *ad =
3452                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3453 #ifdef RTE_ARCH_X86
3454         struct ice_tx_queue *txq;
3455         int i;
3456         int tx_check_ret = -1;
3457
3458         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3459                 ad->tx_use_avx2 = false;
3460                 ad->tx_use_avx512 = false;
3461                 tx_check_ret = ice_tx_vec_dev_check(dev);
3462                 if (tx_check_ret >= 0 &&
3463                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3464                         ad->tx_vec_allowed = true;
3465
3466                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3467                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3468                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3469 #ifdef CC_AVX512_SUPPORT
3470                                 ad->tx_use_avx512 = true;
3471 #else
3472                         PMD_DRV_LOG(NOTICE,
3473                                 "AVX512 is not supported in build env");
3474 #endif
3475                         if (!ad->tx_use_avx512 &&
3476                                 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3477                                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3478                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3479                                 ad->tx_use_avx2 = true;
3480
3481                         if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3482                                 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3483                                 ad->tx_vec_allowed = false;
3484
3485                         if (ad->tx_vec_allowed) {
3486                                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3487                                         txq = dev->data->tx_queues[i];
3488                                         if (txq && ice_txq_vec_setup(txq)) {
3489                                                 ad->tx_vec_allowed = false;
3490                                                 break;
3491                                         }
3492                                 }
3493                         }
3494                 } else {
3495                         ad->tx_vec_allowed = false;
3496                 }
3497         }
3498
3499         if (ad->tx_vec_allowed) {
3500                 dev->tx_pkt_prepare = NULL;
3501                 if (ad->tx_use_avx512) {
3502 #ifdef CC_AVX512_SUPPORT
3503                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3504                                 PMD_DRV_LOG(NOTICE,
3505                                             "Using AVX512 OFFLOAD Vector Tx (port %d).",
3506                                             dev->data->port_id);
3507                                 dev->tx_pkt_burst =
3508                                         ice_xmit_pkts_vec_avx512_offload;
3509                                 dev->tx_pkt_prepare = ice_prep_pkts;
3510                         } else {
3511                                 PMD_DRV_LOG(NOTICE,
3512                                             "Using AVX512 Vector Tx (port %d).",
3513                                             dev->data->port_id);
3514                                 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3515                         }
3516 #endif
3517                 } else {
3518                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3519                                 PMD_DRV_LOG(NOTICE,
3520                                             "Using AVX2 OFFLOAD Vector Tx (port %d).",
3521                                             dev->data->port_id);
3522                                 dev->tx_pkt_burst =
3523                                         ice_xmit_pkts_vec_avx2_offload;
3524                                 dev->tx_pkt_prepare = ice_prep_pkts;
3525                         } else {
3526                                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3527                                             ad->tx_use_avx2 ? "avx2 " : "",
3528                                             dev->data->port_id);
3529                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3530                                                     ice_xmit_pkts_vec_avx2 :
3531                                                     ice_xmit_pkts_vec;
3532                         }
3533                 }
3534
3535                 return;
3536         }
3537 #endif
3538
3539         if (ad->tx_simple_allowed) {
3540                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3541                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3542                 dev->tx_pkt_prepare = NULL;
3543         } else {
3544                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3545                 dev->tx_pkt_burst = ice_xmit_pkts;
3546                 dev->tx_pkt_prepare = ice_prep_pkts;
3547         }
3548 }
3549
3550 static const struct {
3551         eth_tx_burst_t pkt_burst;
3552         const char *info;
3553 } ice_tx_burst_infos[] = {
3554         { ice_xmit_pkts_simple,   "Scalar Simple" },
3555         { ice_xmit_pkts,          "Scalar" },
3556 #ifdef RTE_ARCH_X86
3557 #ifdef CC_AVX512_SUPPORT
3558         { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3559         { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3560 #endif
3561         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3562         { ice_xmit_pkts_vec,      "Vector SSE" },
3563 #endif
3564 };
3565
3566 int
3567 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3568                       struct rte_eth_burst_mode *mode)
3569 {
3570         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3571         int ret = -EINVAL;
3572         unsigned int i;
3573
3574         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3575                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3576                         snprintf(mode->info, sizeof(mode->info), "%s",
3577                                  ice_tx_burst_infos[i].info);
3578                         ret = 0;
3579                         break;
3580                 }
3581         }
3582
3583         return ret;
3584 }
3585
3586 /* For each value it means, datasheet of hardware can tell more details
3587  *
3588  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3589  */
3590 static inline uint32_t
3591 ice_get_default_pkt_type(uint16_t ptype)
3592 {
3593         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3594                 __rte_cache_aligned = {
3595                 /* L2 types */
3596                 /* [0] reserved */
3597                 [1] = RTE_PTYPE_L2_ETHER,
3598                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3599                 /* [3] - [5] reserved */
3600                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3601                 /* [7] - [10] reserved */
3602                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3603                 /* [12] - [21] reserved */
3604
3605                 /* Non tunneled IPv4 */
3606                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3607                        RTE_PTYPE_L4_FRAG,
3608                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3609                        RTE_PTYPE_L4_NONFRAG,
3610                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3611                        RTE_PTYPE_L4_UDP,
3612                 /* [25] reserved */
3613                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3614                        RTE_PTYPE_L4_TCP,
3615                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3616                        RTE_PTYPE_L4_SCTP,
3617                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3618                        RTE_PTYPE_L4_ICMP,
3619
3620                 /* IPv4 --> IPv4 */
3621                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3622                        RTE_PTYPE_TUNNEL_IP |
3623                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3624                        RTE_PTYPE_INNER_L4_FRAG,
3625                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3626                        RTE_PTYPE_TUNNEL_IP |
3627                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3628                        RTE_PTYPE_INNER_L4_NONFRAG,
3629                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3630                        RTE_PTYPE_TUNNEL_IP |
3631                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3632                        RTE_PTYPE_INNER_L4_UDP,
3633                 /* [32] reserved */
3634                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3635                        RTE_PTYPE_TUNNEL_IP |
3636                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3637                        RTE_PTYPE_INNER_L4_TCP,
3638                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3639                        RTE_PTYPE_TUNNEL_IP |
3640                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3641                        RTE_PTYPE_INNER_L4_SCTP,
3642                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3643                        RTE_PTYPE_TUNNEL_IP |
3644                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3645                        RTE_PTYPE_INNER_L4_ICMP,
3646
3647                 /* IPv4 --> IPv6 */
3648                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3649                        RTE_PTYPE_TUNNEL_IP |
3650                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3651                        RTE_PTYPE_INNER_L4_FRAG,
3652                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3653                        RTE_PTYPE_TUNNEL_IP |
3654                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3655                        RTE_PTYPE_INNER_L4_NONFRAG,
3656                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3657                        RTE_PTYPE_TUNNEL_IP |
3658                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3659                        RTE_PTYPE_INNER_L4_UDP,
3660                 /* [39] reserved */
3661                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3662                        RTE_PTYPE_TUNNEL_IP |
3663                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3664                        RTE_PTYPE_INNER_L4_TCP,
3665                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3666                        RTE_PTYPE_TUNNEL_IP |
3667                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3668                        RTE_PTYPE_INNER_L4_SCTP,
3669                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3670                        RTE_PTYPE_TUNNEL_IP |
3671                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3672                        RTE_PTYPE_INNER_L4_ICMP,
3673
3674                 /* IPv4 --> GRE/Teredo/VXLAN */
3675                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3676                        RTE_PTYPE_TUNNEL_GRENAT,
3677
3678                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3679                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3680                        RTE_PTYPE_TUNNEL_GRENAT |
3681                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3682                        RTE_PTYPE_INNER_L4_FRAG,
3683                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3684                        RTE_PTYPE_TUNNEL_GRENAT |
3685                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3686                        RTE_PTYPE_INNER_L4_NONFRAG,
3687                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3688                        RTE_PTYPE_TUNNEL_GRENAT |
3689                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3690                        RTE_PTYPE_INNER_L4_UDP,
3691                 /* [47] reserved */
3692                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3693                        RTE_PTYPE_TUNNEL_GRENAT |
3694                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3695                        RTE_PTYPE_INNER_L4_TCP,
3696                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3697                        RTE_PTYPE_TUNNEL_GRENAT |
3698                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3699                        RTE_PTYPE_INNER_L4_SCTP,
3700                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3701                        RTE_PTYPE_TUNNEL_GRENAT |
3702                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3703                        RTE_PTYPE_INNER_L4_ICMP,
3704
3705                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3706                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3707                        RTE_PTYPE_TUNNEL_GRENAT |
3708                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3709                        RTE_PTYPE_INNER_L4_FRAG,
3710                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3711                        RTE_PTYPE_TUNNEL_GRENAT |
3712                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3713                        RTE_PTYPE_INNER_L4_NONFRAG,
3714                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3715                        RTE_PTYPE_TUNNEL_GRENAT |
3716                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3717                        RTE_PTYPE_INNER_L4_UDP,
3718                 /* [54] reserved */
3719                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3720                        RTE_PTYPE_TUNNEL_GRENAT |
3721                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3722                        RTE_PTYPE_INNER_L4_TCP,
3723                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3724                        RTE_PTYPE_TUNNEL_GRENAT |
3725                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3726                        RTE_PTYPE_INNER_L4_SCTP,
3727                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3728                        RTE_PTYPE_TUNNEL_GRENAT |
3729                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3730                        RTE_PTYPE_INNER_L4_ICMP,
3731
3732                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3733                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3734                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3735
3736                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3737                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3738                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3739                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3740                        RTE_PTYPE_INNER_L4_FRAG,
3741                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3742                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3743                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3744                        RTE_PTYPE_INNER_L4_NONFRAG,
3745                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3746                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3747                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3748                        RTE_PTYPE_INNER_L4_UDP,
3749                 /* [62] reserved */
3750                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3751                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3752                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3753                        RTE_PTYPE_INNER_L4_TCP,
3754                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3755                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3756                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3757                        RTE_PTYPE_INNER_L4_SCTP,
3758                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3759                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3760                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3761                        RTE_PTYPE_INNER_L4_ICMP,
3762
3763                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3764                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3765                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3766                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3767                        RTE_PTYPE_INNER_L4_FRAG,
3768                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3769                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3770                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3771                        RTE_PTYPE_INNER_L4_NONFRAG,
3772                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3773                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3774                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3775                        RTE_PTYPE_INNER_L4_UDP,
3776                 /* [69] reserved */
3777                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3778                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3779                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3780                        RTE_PTYPE_INNER_L4_TCP,
3781                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3782                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3783                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3784                        RTE_PTYPE_INNER_L4_SCTP,
3785                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3786                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3787                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3788                        RTE_PTYPE_INNER_L4_ICMP,
3789                 /* [73] - [87] reserved */
3790
3791                 /* Non tunneled IPv6 */
3792                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3793                        RTE_PTYPE_L4_FRAG,
3794                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3795                        RTE_PTYPE_L4_NONFRAG,
3796                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3797                        RTE_PTYPE_L4_UDP,
3798                 /* [91] reserved */
3799                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3800                        RTE_PTYPE_L4_TCP,
3801                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3802                        RTE_PTYPE_L4_SCTP,
3803                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3804                        RTE_PTYPE_L4_ICMP,
3805
3806                 /* IPv6 --> IPv4 */
3807                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3808                        RTE_PTYPE_TUNNEL_IP |
3809                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3810                        RTE_PTYPE_INNER_L4_FRAG,
3811                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3812                        RTE_PTYPE_TUNNEL_IP |
3813                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3814                        RTE_PTYPE_INNER_L4_NONFRAG,
3815                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3816                        RTE_PTYPE_TUNNEL_IP |
3817                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3818                        RTE_PTYPE_INNER_L4_UDP,
3819                 /* [98] reserved */
3820                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3821                        RTE_PTYPE_TUNNEL_IP |
3822                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3823                        RTE_PTYPE_INNER_L4_TCP,
3824                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3825                         RTE_PTYPE_TUNNEL_IP |
3826                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3827                         RTE_PTYPE_INNER_L4_SCTP,
3828                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3829                         RTE_PTYPE_TUNNEL_IP |
3830                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3831                         RTE_PTYPE_INNER_L4_ICMP,
3832
3833                 /* IPv6 --> IPv6 */
3834                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3835                         RTE_PTYPE_TUNNEL_IP |
3836                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3837                         RTE_PTYPE_INNER_L4_FRAG,
3838                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3839                         RTE_PTYPE_TUNNEL_IP |
3840                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3841                         RTE_PTYPE_INNER_L4_NONFRAG,
3842                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3843                         RTE_PTYPE_TUNNEL_IP |
3844                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3845                         RTE_PTYPE_INNER_L4_UDP,
3846                 /* [105] reserved */
3847                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3848                         RTE_PTYPE_TUNNEL_IP |
3849                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3850                         RTE_PTYPE_INNER_L4_TCP,
3851                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3852                         RTE_PTYPE_TUNNEL_IP |
3853                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3854                         RTE_PTYPE_INNER_L4_SCTP,
3855                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3856                         RTE_PTYPE_TUNNEL_IP |
3857                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3858                         RTE_PTYPE_INNER_L4_ICMP,
3859
3860                 /* IPv6 --> GRE/Teredo/VXLAN */
3861                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3862                         RTE_PTYPE_TUNNEL_GRENAT,
3863
3864                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3865                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3866                         RTE_PTYPE_TUNNEL_GRENAT |
3867                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3868                         RTE_PTYPE_INNER_L4_FRAG,
3869                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3870                         RTE_PTYPE_TUNNEL_GRENAT |
3871                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3872                         RTE_PTYPE_INNER_L4_NONFRAG,
3873                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3874                         RTE_PTYPE_TUNNEL_GRENAT |
3875                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3876                         RTE_PTYPE_INNER_L4_UDP,
3877                 /* [113] reserved */
3878                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3879                         RTE_PTYPE_TUNNEL_GRENAT |
3880                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3881                         RTE_PTYPE_INNER_L4_TCP,
3882                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3883                         RTE_PTYPE_TUNNEL_GRENAT |
3884                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3885                         RTE_PTYPE_INNER_L4_SCTP,
3886                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3887                         RTE_PTYPE_TUNNEL_GRENAT |
3888                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3889                         RTE_PTYPE_INNER_L4_ICMP,
3890
3891                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3892                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3893                         RTE_PTYPE_TUNNEL_GRENAT |
3894                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3895                         RTE_PTYPE_INNER_L4_FRAG,
3896                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3897                         RTE_PTYPE_TUNNEL_GRENAT |
3898                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3899                         RTE_PTYPE_INNER_L4_NONFRAG,
3900                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3901                         RTE_PTYPE_TUNNEL_GRENAT |
3902                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3903                         RTE_PTYPE_INNER_L4_UDP,
3904                 /* [120] reserved */
3905                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3906                         RTE_PTYPE_TUNNEL_GRENAT |
3907                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3908                         RTE_PTYPE_INNER_L4_TCP,
3909                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3910                         RTE_PTYPE_TUNNEL_GRENAT |
3911                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3912                         RTE_PTYPE_INNER_L4_SCTP,
3913                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3914                         RTE_PTYPE_TUNNEL_GRENAT |
3915                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3916                         RTE_PTYPE_INNER_L4_ICMP,
3917
3918                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3919                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3920                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3921
3922                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3923                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3924                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3925                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3926                         RTE_PTYPE_INNER_L4_FRAG,
3927                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3928                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3929                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3930                         RTE_PTYPE_INNER_L4_NONFRAG,
3931                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3932                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3933                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3934                         RTE_PTYPE_INNER_L4_UDP,
3935                 /* [128] reserved */
3936                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3937                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3938                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3939                         RTE_PTYPE_INNER_L4_TCP,
3940                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3941                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3942                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3943                         RTE_PTYPE_INNER_L4_SCTP,
3944                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3945                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3946                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3947                         RTE_PTYPE_INNER_L4_ICMP,
3948
3949                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3950                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3951                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3952                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3953                         RTE_PTYPE_INNER_L4_FRAG,
3954                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3955                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3956                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3957                         RTE_PTYPE_INNER_L4_NONFRAG,
3958                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3959                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3960                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3961                         RTE_PTYPE_INNER_L4_UDP,
3962                 /* [135] reserved */
3963                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3964                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3965                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3966                         RTE_PTYPE_INNER_L4_TCP,
3967                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3968                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3969                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3970                         RTE_PTYPE_INNER_L4_SCTP,
3971                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3972                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3973                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3974                         RTE_PTYPE_INNER_L4_ICMP,
3975                 /* [139] - [299] reserved */
3976
3977                 /* PPPoE */
3978                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3979                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3980
3981                 /* PPPoE --> IPv4 */
3982                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3983                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3984                         RTE_PTYPE_L4_FRAG,
3985                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3986                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3987                         RTE_PTYPE_L4_NONFRAG,
3988                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3989                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3990                         RTE_PTYPE_L4_UDP,
3991                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3992                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3993                         RTE_PTYPE_L4_TCP,
3994                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3995                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3996                         RTE_PTYPE_L4_SCTP,
3997                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3998                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3999                         RTE_PTYPE_L4_ICMP,
4000
4001                 /* PPPoE --> IPv6 */
4002                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
4003                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4004                         RTE_PTYPE_L4_FRAG,
4005                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
4006                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4007                         RTE_PTYPE_L4_NONFRAG,
4008                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
4009                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4010                         RTE_PTYPE_L4_UDP,
4011                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
4012                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4013                         RTE_PTYPE_L4_TCP,
4014                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
4015                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4016                         RTE_PTYPE_L4_SCTP,
4017                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
4018                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4019                         RTE_PTYPE_L4_ICMP,
4020                 /* [314] - [324] reserved */
4021
4022                 /* IPv4/IPv6 --> GTPC/GTPU */
4023                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4024                         RTE_PTYPE_TUNNEL_GTPC,
4025                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4026                         RTE_PTYPE_TUNNEL_GTPC,
4027                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4028                         RTE_PTYPE_TUNNEL_GTPC,
4029                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4030                         RTE_PTYPE_TUNNEL_GTPC,
4031                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4032                         RTE_PTYPE_TUNNEL_GTPU,
4033                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4034                         RTE_PTYPE_TUNNEL_GTPU,
4035
4036                 /* IPv4 --> GTPU --> IPv4 */
4037                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4038                         RTE_PTYPE_TUNNEL_GTPU |
4039                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4040                         RTE_PTYPE_INNER_L4_FRAG,
4041                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4042                         RTE_PTYPE_TUNNEL_GTPU |
4043                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4044                         RTE_PTYPE_INNER_L4_NONFRAG,
4045                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4046                         RTE_PTYPE_TUNNEL_GTPU |
4047                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4048                         RTE_PTYPE_INNER_L4_UDP,
4049                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4050                         RTE_PTYPE_TUNNEL_GTPU |
4051                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4052                         RTE_PTYPE_INNER_L4_TCP,
4053                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4054                         RTE_PTYPE_TUNNEL_GTPU |
4055                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4056                         RTE_PTYPE_INNER_L4_ICMP,
4057
4058                 /* IPv6 --> GTPU --> IPv4 */
4059                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4060                         RTE_PTYPE_TUNNEL_GTPU |
4061                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4062                         RTE_PTYPE_INNER_L4_FRAG,
4063                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4064                         RTE_PTYPE_TUNNEL_GTPU |
4065                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4066                         RTE_PTYPE_INNER_L4_NONFRAG,
4067                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4068                         RTE_PTYPE_TUNNEL_GTPU |
4069                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4070                         RTE_PTYPE_INNER_L4_UDP,
4071                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4072                         RTE_PTYPE_TUNNEL_GTPU |
4073                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4074                         RTE_PTYPE_INNER_L4_TCP,
4075                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4076                         RTE_PTYPE_TUNNEL_GTPU |
4077                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4078                         RTE_PTYPE_INNER_L4_ICMP,
4079
4080                 /* IPv4 --> GTPU --> IPv6 */
4081                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4082                         RTE_PTYPE_TUNNEL_GTPU |
4083                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4084                         RTE_PTYPE_INNER_L4_FRAG,
4085                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4086                         RTE_PTYPE_TUNNEL_GTPU |
4087                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4088                         RTE_PTYPE_INNER_L4_NONFRAG,
4089                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4090                         RTE_PTYPE_TUNNEL_GTPU |
4091                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4092                         RTE_PTYPE_INNER_L4_UDP,
4093                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4094                         RTE_PTYPE_TUNNEL_GTPU |
4095                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4096                         RTE_PTYPE_INNER_L4_TCP,
4097                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4098                         RTE_PTYPE_TUNNEL_GTPU |
4099                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4100                         RTE_PTYPE_INNER_L4_ICMP,
4101
4102                 /* IPv6 --> GTPU --> IPv6 */
4103                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4104                         RTE_PTYPE_TUNNEL_GTPU |
4105                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4106                         RTE_PTYPE_INNER_L4_FRAG,
4107                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4108                         RTE_PTYPE_TUNNEL_GTPU |
4109                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4110                         RTE_PTYPE_INNER_L4_NONFRAG,
4111                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4112                         RTE_PTYPE_TUNNEL_GTPU |
4113                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4114                         RTE_PTYPE_INNER_L4_UDP,
4115                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4116                         RTE_PTYPE_TUNNEL_GTPU |
4117                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4118                         RTE_PTYPE_INNER_L4_TCP,
4119                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4120                         RTE_PTYPE_TUNNEL_GTPU |
4121                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4122                         RTE_PTYPE_INNER_L4_ICMP,
4123
4124                 /* IPv4 --> UDP ECPRI */
4125                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4126                         RTE_PTYPE_L4_UDP,
4127                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4128                         RTE_PTYPE_L4_UDP,
4129                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4130                         RTE_PTYPE_L4_UDP,
4131                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4132                         RTE_PTYPE_L4_UDP,
4133                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4134                         RTE_PTYPE_L4_UDP,
4135                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4136                         RTE_PTYPE_L4_UDP,
4137                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4138                         RTE_PTYPE_L4_UDP,
4139                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4140                         RTE_PTYPE_L4_UDP,
4141                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4142                         RTE_PTYPE_L4_UDP,
4143                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4144                         RTE_PTYPE_L4_UDP,
4145
4146                 /* IPV6 --> UDP ECPRI */
4147                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4148                         RTE_PTYPE_L4_UDP,
4149                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4150                         RTE_PTYPE_L4_UDP,
4151                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4152                         RTE_PTYPE_L4_UDP,
4153                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4154                         RTE_PTYPE_L4_UDP,
4155                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4156                         RTE_PTYPE_L4_UDP,
4157                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4158                         RTE_PTYPE_L4_UDP,
4159                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4160                         RTE_PTYPE_L4_UDP,
4161                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4162                         RTE_PTYPE_L4_UDP,
4163                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4164                         RTE_PTYPE_L4_UDP,
4165                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4166                         RTE_PTYPE_L4_UDP,
4167                 /* All others reserved */
4168         };
4169
4170         return type_table[ptype];
4171 }
4172
4173 void __rte_cold
4174 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4175 {
4176         struct ice_adapter *ad =
4177                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4178         int i;
4179
4180         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4181                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4182 }
4183
4184 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4185 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4186                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4187 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4188 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4189
4190 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
4191 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
4192         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4193 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
4194 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
4195         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4196
4197 /*
4198  * check the programming status descriptor in rx queue.
4199  * done after Programming Flow Director is programmed on
4200  * tx queue
4201  */
4202 static inline int
4203 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4204 {
4205         volatile union ice_32byte_rx_desc *rxdp;
4206         uint64_t qword1;
4207         uint32_t rx_status;
4208         uint32_t error;
4209         uint32_t id;
4210         int ret = -EAGAIN;
4211
4212         rxdp = (volatile union ice_32byte_rx_desc *)
4213                 (&rxq->rx_ring[rxq->rx_tail]);
4214         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4215         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4216                         >> ICE_RXD_QW1_STATUS_S;
4217
4218         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4219                 ret = 0;
4220                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4221                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4222                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4223                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4224                 if (error) {
4225                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4226                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4227                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4228                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4229                         ret = -EINVAL;
4230                         goto err;
4231                 }
4232                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4233                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4234                 if (error) {
4235                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4236                         ret = -EINVAL;
4237                 }
4238 err:
4239                 rxdp->wb.qword1.status_error_len = 0;
4240                 rxq->rx_tail++;
4241                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4242                         rxq->rx_tail = 0;
4243                 if (rxq->rx_tail == 0)
4244                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4245                 else
4246                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4247         }
4248
4249         return ret;
4250 }
4251
4252 #define ICE_FDIR_MAX_WAIT_US 10000
4253
4254 int
4255 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4256 {
4257         struct ice_tx_queue *txq = pf->fdir.txq;
4258         struct ice_rx_queue *rxq = pf->fdir.rxq;
4259         volatile struct ice_fltr_desc *fdirdp;
4260         volatile struct ice_tx_desc *txdp;
4261         uint32_t td_cmd;
4262         uint16_t i;
4263
4264         fdirdp = (volatile struct ice_fltr_desc *)
4265                 (&txq->tx_ring[txq->tx_tail]);
4266         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4267         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4268
4269         txdp = &txq->tx_ring[txq->tx_tail + 1];
4270         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4271         td_cmd = ICE_TX_DESC_CMD_EOP |
4272                 ICE_TX_DESC_CMD_RS  |
4273                 ICE_TX_DESC_CMD_DUMMY;
4274
4275         txdp->cmd_type_offset_bsz =
4276                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4277
4278         txq->tx_tail += 2;
4279         if (txq->tx_tail >= txq->nb_tx_desc)
4280                 txq->tx_tail = 0;
4281         /* Update the tx tail register */
4282         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4283         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4284                 if ((txdp->cmd_type_offset_bsz &
4285                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4286                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4287                         break;
4288                 rte_delay_us(1);
4289         }
4290         if (i >= ICE_FDIR_MAX_WAIT_US) {
4291                 PMD_DRV_LOG(ERR,
4292                             "Failed to program FDIR filter: time out to get DD on tx queue.");
4293                 return -ETIMEDOUT;
4294         }
4295
4296         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4297                 int ret;
4298
4299                 ret = ice_check_fdir_programming_status(rxq);
4300                 if (ret == -EAGAIN)
4301                         rte_delay_us(1);
4302                 else
4303                         return ret;
4304         }
4305
4306         PMD_DRV_LOG(ERR,
4307                     "Failed to program FDIR filter: programming status reported.");
4308         return -ETIMEDOUT;
4309
4310
4311 }