drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <ethdev_driver.h>
   6 #include <rte_net.h>
   7 #include <rte_vect.h>
   8
   9 #include "rte_pmd_ice.h"
  10 #include "ice_rxtx.h"
  11 #include "ice_rxtx_vec_common.h"
  12
  13 #define ICE_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM |              \
  14                 RTE_MBUF_F_TX_L4_MASK |          \
  15                 RTE_MBUF_F_TX_TCP_SEG |          \
  16                 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
  17
  18 /* Offset of mbuf dynamic field for protocol extraction data */
  19 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  20
  21 /* Mask of mbuf dynamic flags for protocol extraction type */
  22 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  27 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  28
  29 static int
  30 ice_monitor_callback(const uint64_t value,
  31                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  32 {
  33         const uint64_t m = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
  34         /*
  35          * we expect the DD bit to be set to 1 if this descriptor was already
  36          * written to.
  37          */
  38         return (value & m) == m ? -1 : 0;
  39 }
  40
  41 int
  42 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  43 {
  44         volatile union ice_rx_flex_desc *rxdp;
  45         struct ice_rx_queue *rxq = rx_queue;
  46         uint16_t desc;
  47
  48         desc = rxq->rx_tail;
  49         rxdp = &rxq->rx_ring[desc];
  50         /* watch for changes in status bit */
  51         pmc->addr = &rxdp->wb.status_error0;
  52
  53         /* comparison callback */
  54         pmc->fn = ice_monitor_callback;
  55
  56         /* register is 16-bit */
  57         pmc->size = sizeof(uint16_t);
  58
  59         return 0;
  60 }
  61
  62
  63 static inline uint8_t
  64 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  65 {
  66         static uint8_t rxdid_map[] = {
  67                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_OVS,
  68                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  69                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  70                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  71                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  72                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  73                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  74         };
  75
  76         return xtr_type < RTE_DIM(rxdid_map) ?
  77                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
  78 }
  79
  80 static inline void
  81 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
  82                                        struct rte_mbuf *mb,
  83                                        volatile union ice_rx_flex_desc *rxdp)
  84 {
  85         volatile struct ice_32b_rx_flex_desc_comms *desc =
  86                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
  87         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
  88
  89         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  90                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
  91                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  92         }
  93
  94 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  95         if (desc->flow_id != 0xFFFFFFFF) {
  96                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
  97                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  98         }
  99 #endif
 100 }
 101
 102 static inline void
 103 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
 104                                    struct rte_mbuf *mb,
 105                                    volatile union ice_rx_flex_desc *rxdp)
 106 {
 107         volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
 108                         (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
 109 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 110         uint16_t stat_err;
 111 #endif
 112
 113         if (desc->flow_id != 0xFFFFFFFF) {
 114                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 115                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 116         }
 117
 118 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 119         stat_err = rte_le_to_cpu_16(desc->status_error0);
 120         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 121                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 122                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 123         }
 124 #endif
 125 }
 126
 127 static inline void
 128 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
 129                                       struct rte_mbuf *mb,
 130                                       volatile union ice_rx_flex_desc *rxdp)
 131 {
 132         volatile struct ice_32b_rx_flex_desc_comms *desc =
 133                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 134         uint16_t stat_err;
 135
 136         stat_err = rte_le_to_cpu_16(desc->status_error0);
 137         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 138                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 139                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 140         }
 141
 142 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 143         if (desc->flow_id != 0xFFFFFFFF) {
 144                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 145                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 146         }
 147
 148         if (rxq->xtr_ol_flag) {
 149                 uint32_t metadata = 0;
 150
 151                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 152
 153                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 154                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 155
 156                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 157                         metadata |=
 158                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 159
 160                 if (metadata) {
 161                         mb->ol_flags |= rxq->xtr_ol_flag;
 162
 163                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 164                 }
 165         }
 166 #else
 167         RTE_SET_USED(rxq);
 168 #endif
 169 }
 170
 171 static inline void
 172 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
 173                                       struct rte_mbuf *mb,
 174                                       volatile union ice_rx_flex_desc *rxdp)
 175 {
 176         volatile struct ice_32b_rx_flex_desc_comms *desc =
 177                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 178         uint16_t stat_err;
 179
 180         stat_err = rte_le_to_cpu_16(desc->status_error0);
 181         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 182                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 183                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 184         }
 185
 186 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 187         if (desc->flow_id != 0xFFFFFFFF) {
 188                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 189                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 190         }
 191
 192         if (rxq->xtr_ol_flag) {
 193                 uint32_t metadata = 0;
 194
 195                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 196                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 197                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 198                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 199
 200                 if (metadata) {
 201                         mb->ol_flags |= rxq->xtr_ol_flag;
 202
 203                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 204                 }
 205         }
 206 #else
 207         RTE_SET_USED(rxq);
 208 #endif
 209 }
 210
 211 static const ice_rxd_to_pkt_fields_t rxd_to_pkt_fields_ops[] = {
 212         [ICE_RXDID_COMMS_AUX_VLAN] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 213         [ICE_RXDID_COMMS_AUX_IPV4] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 214         [ICE_RXDID_COMMS_AUX_IPV6] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 215         [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 216         [ICE_RXDID_COMMS_AUX_TCP] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 217         [ICE_RXDID_COMMS_AUX_IP_OFFSET] = ice_rxd_to_pkt_fields_by_comms_aux_v2,
 218         [ICE_RXDID_COMMS_GENERIC] = ice_rxd_to_pkt_fields_by_comms_generic,
 219         [ICE_RXDID_COMMS_OVS] = ice_rxd_to_pkt_fields_by_comms_ovs,
 220 };
 221
 222 void
 223 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
 224 {
 225         rxq->rxdid = rxdid;
 226
 227         switch (rxdid) {
 228         case ICE_RXDID_COMMS_AUX_VLAN:
 229                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
 230                 break;
 231
 232         case ICE_RXDID_COMMS_AUX_IPV4:
 233                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
 234                 break;
 235
 236         case ICE_RXDID_COMMS_AUX_IPV6:
 237                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
 238                 break;
 239
 240         case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
 241                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
 242                 break;
 243
 244         case ICE_RXDID_COMMS_AUX_TCP:
 245                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
 246                 break;
 247
 248         case ICE_RXDID_COMMS_AUX_IP_OFFSET:
 249                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
 250                 break;
 251
 252         case ICE_RXDID_COMMS_GENERIC:
 253                 /* fallthrough */
 254         case ICE_RXDID_COMMS_OVS:
 255                 break;
 256
 257         default:
 258                 /* update this according to the RXDID for PROTO_XTR_NONE */
 259                 rxq->rxdid = ICE_RXDID_COMMS_OVS;
 260                 break;
 261         }
 262
 263         if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
 264                 rxq->xtr_ol_flag = 0;
 265 }
 266
 267 static enum ice_status
 268 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
 269 {
 270         struct ice_vsi *vsi = rxq->vsi;
 271         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 272         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
 273         struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
 274         struct ice_rlan_ctx rx_ctx;
 275         enum ice_status err;
 276         uint16_t buf_size;
 277         uint32_t rxdid = ICE_RXDID_COMMS_OVS;
 278         uint32_t regval;
 279         struct ice_adapter *ad = rxq->vsi->adapter;
 280         uint32_t frame_size = dev_data->mtu + ICE_ETH_OVERHEAD;
 281
 282         /* Set buffer size as the head split is disabled. */
 283         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 284                               RTE_PKTMBUF_HEADROOM);
 285         rxq->rx_hdr_len = 0;
 286         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
 287         rxq->max_pkt_len =
 288                 RTE_MIN((uint32_t)ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
 289                         frame_size);
 290
 291         if (rxq->max_pkt_len <= RTE_ETHER_MIN_LEN ||
 292             rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 293                 PMD_DRV_LOG(ERR, "maximum packet length must "
 294                             "be larger than %u and smaller than %u",
 295                             (uint32_t)RTE_ETHER_MIN_LEN,
 296                             (uint32_t)ICE_FRAME_SIZE_MAX);
 297                 return -EINVAL;
 298         }
 299
 300         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
 301                 /* Register mbuf field and flag for Rx timestamp */
 302                 err = rte_mbuf_dyn_rx_timestamp_register(
 303                                 &ice_timestamp_dynfield_offset,
 304                                 &ice_timestamp_dynflag);
 305                 if (err) {
 306                         PMD_DRV_LOG(ERR,
 307                                 "Cannot register mbuf field/flag for timestamp");
 308                         return -EINVAL;
 309                 }
 310         }
 311
 312         memset(&rx_ctx, 0, sizeof(rx_ctx));
 313
 314         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 315         rx_ctx.qlen = rxq->nb_rx_desc;
 316         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 317         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 318         rx_ctx.dtype = 0; /* No Header Split mode */
 319 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 320         rx_ctx.dsize = 1; /* 32B descriptors */
 321 #endif
 322         rx_ctx.rxmax = rxq->max_pkt_len;
 323         /* TPH: Transaction Layer Packet (TLP) processing hints */
 324         rx_ctx.tphrdesc_ena = 1;
 325         rx_ctx.tphwdesc_ena = 1;
 326         rx_ctx.tphdata_ena = 1;
 327         rx_ctx.tphhead_ena = 1;
 328         /* Low Receive Queue Threshold defined in 64 descriptors units.
 329          * When the number of free descriptors goes below the lrxqthresh,
 330          * an immediate interrupt is triggered.
 331          */
 332         rx_ctx.lrxqthresh = 2;
 333         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 334         rx_ctx.l2tsel = 1;
 335         rx_ctx.showiv = 0;
 336         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 337
 338         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 339
 340         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 341                     rxq->port_id, rxq->queue_id, rxdid);
 342
 343         if (!(pf->supported_rxdid & BIT(rxdid))) {
 344                 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
 345                             rxdid);
 346                 return -EINVAL;
 347         }
 348
 349         ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
 350
 351         /* Enable Flexible Descriptors in the queue context which
 352          * allows this driver to select a specific receive descriptor format
 353          */
 354         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 355                 QRXFLXP_CNTXT_RXDID_IDX_M;
 356
 357         /* increasing context priority to pick up profile ID;
 358          * default is 0x01; setting to 0x03 to ensure profile
 359          * is programming if prev context is of same priority
 360          */
 361         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 362                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 363
 364         if (ad->ptp_ena || rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
 365                 regval |= QRXFLXP_CNTXT_TS_M;
 366
 367         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 368
 369         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 370         if (err) {
 371                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 372                             rxq->queue_id);
 373                 return -EINVAL;
 374         }
 375         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 376         if (err) {
 377                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 378                             rxq->queue_id);
 379                 return -EINVAL;
 380         }
 381
 382         /* Check if scattered RX needs to be used. */
 383         if (frame_size > buf_size)
 384                 dev_data->scattered_rx = 1;
 385
 386         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 387
 388         /* Init the Rx tail register*/
 389         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 390
 391         return 0;
 392 }
 393
 394 /* Allocate mbufs for all descriptors in rx queue */
 395 static int
 396 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 397 {
 398         struct ice_rx_entry *rxe = rxq->sw_ring;
 399         uint64_t dma_addr;
 400         uint16_t i;
 401
 402         for (i = 0; i < rxq->nb_rx_desc; i++) {
 403                 volatile union ice_rx_flex_desc *rxd;
 404                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 405
 406                 if (unlikely(!mbuf)) {
 407                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 408                         return -ENOMEM;
 409                 }
 410
 411                 rte_mbuf_refcnt_set(mbuf, 1);
 412                 mbuf->next = NULL;
 413                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 414                 mbuf->nb_segs = 1;
 415                 mbuf->port = rxq->port_id;
 416
 417                 dma_addr =
 418                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 419
 420                 rxd = &rxq->rx_ring[i];
 421                 rxd->read.pkt_addr = dma_addr;
 422                 rxd->read.hdr_addr = 0;
 423 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 424                 rxd->read.rsvd1 = 0;
 425                 rxd->read.rsvd2 = 0;
 426 #endif
 427                 rxe[i].mbuf = mbuf;
 428         }
 429
 430         return 0;
 431 }
 432
 433 /* Free all mbufs for descriptors in rx queue */
 434 static void
 435 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 436 {
 437         uint16_t i;
 438
 439         if (!rxq || !rxq->sw_ring) {
 440                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 441                 return;
 442         }
 443
 444         for (i = 0; i < rxq->nb_rx_desc; i++) {
 445                 if (rxq->sw_ring[i].mbuf) {
 446                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 447                         rxq->sw_ring[i].mbuf = NULL;
 448                 }
 449         }
 450         if (rxq->rx_nb_avail == 0)
 451                 return;
 452         for (i = 0; i < rxq->rx_nb_avail; i++)
 453                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 454
 455         rxq->rx_nb_avail = 0;
 456 }
 457
 458 /* turn on or off rx queue
 459  * @q_idx: queue index in pf scope
 460  * @on: turn on or off the queue
 461  */
 462 static int
 463 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 464 {
 465         uint32_t reg;
 466         uint16_t j;
 467
 468         /* QRX_CTRL = QRX_ENA */
 469         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 470
 471         if (on) {
 472                 if (reg & QRX_CTRL_QENA_STAT_M)
 473                         return 0; /* Already on, skip */
 474                 reg |= QRX_CTRL_QENA_REQ_M;
 475         } else {
 476                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 477                         return 0; /* Already off, skip */
 478                 reg &= ~QRX_CTRL_QENA_REQ_M;
 479         }
 480
 481         /* Write the register */
 482         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 483         /* Check the result. It is said that QENA_STAT
 484          * follows the QENA_REQ not more than 10 use.
 485          * TODO: need to change the wait counter later
 486          */
 487         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 488                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 489                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 490                 if (on) {
 491                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 492                             (reg & QRX_CTRL_QENA_STAT_M))
 493                                 break;
 494                 } else {
 495                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 496                             !(reg & QRX_CTRL_QENA_STAT_M))
 497                                 break;
 498                 }
 499         }
 500
 501         /* Check if it is timeout */
 502         if (j >= ICE_CHK_Q_ENA_COUNT) {
 503                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 504                             (on ? "enable" : "disable"), q_idx);
 505                 return -ETIMEDOUT;
 506         }
 507
 508         return 0;
 509 }
 510
 511 static inline int
 512 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 513 {
 514         int ret = 0;
 515
 516         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 517                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 518                              "rxq->rx_free_thresh=%d, "
 519                              "ICE_RX_MAX_BURST=%d",
 520                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 521                 ret = -EINVAL;
 522         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 523                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 524                              "rxq->rx_free_thresh=%d, "
 525                              "rxq->nb_rx_desc=%d",
 526                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 527                 ret = -EINVAL;
 528         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 529                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 530                              "rxq->nb_rx_desc=%d, "
 531                              "rxq->rx_free_thresh=%d",
 532                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 533                 ret = -EINVAL;
 534         }
 535
 536         return ret;
 537 }
 538
 539 /* reset fields in ice_rx_queue back to default */
 540 static void
 541 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 542 {
 543         unsigned int i;
 544         uint16_t len;
 545
 546         if (!rxq) {
 547                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 548                 return;
 549         }
 550
 551         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 552
 553         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 554                 ((volatile char *)rxq->rx_ring)[i] = 0;
 555
 556         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 557         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 558                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 559
 560         rxq->rx_nb_avail = 0;
 561         rxq->rx_next_avail = 0;
 562         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 563
 564         rxq->rx_tail = 0;
 565         rxq->nb_rx_hold = 0;
 566         rxq->pkt_first_seg = NULL;
 567         rxq->pkt_last_seg = NULL;
 568
 569         rxq->rxrearm_start = 0;
 570         rxq->rxrearm_nb = 0;
 571 }
 572
 573 int
 574 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 575 {
 576         struct ice_rx_queue *rxq;
 577         int err;
 578         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 579
 580         PMD_INIT_FUNC_TRACE();
 581
 582         if (rx_queue_id >= dev->data->nb_rx_queues) {
 583                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 584                             rx_queue_id, dev->data->nb_rx_queues);
 585                 return -EINVAL;
 586         }
 587
 588         rxq = dev->data->rx_queues[rx_queue_id];
 589         if (!rxq || !rxq->q_set) {
 590                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 591                             rx_queue_id);
 592                 return -EINVAL;
 593         }
 594
 595         err = ice_program_hw_rx_queue(rxq);
 596         if (err) {
 597                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 598                             rx_queue_id);
 599                 return -EIO;
 600         }
 601
 602         err = ice_alloc_rx_queue_mbufs(rxq);
 603         if (err) {
 604                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 605                 return -ENOMEM;
 606         }
 607
 608         /* Init the RX tail register. */
 609         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 610
 611         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 612         if (err) {
 613                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 614                             rx_queue_id);
 615
 616                 rxq->rx_rel_mbufs(rxq);
 617                 ice_reset_rx_queue(rxq);
 618                 return -EINVAL;
 619         }
 620
 621         dev->data->rx_queue_state[rx_queue_id] =
 622                 RTE_ETH_QUEUE_STATE_STARTED;
 623
 624         return 0;
 625 }
 626
 627 int
 628 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 629 {
 630         struct ice_rx_queue *rxq;
 631         int err;
 632         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 633
 634         if (rx_queue_id < dev->data->nb_rx_queues) {
 635                 rxq = dev->data->rx_queues[rx_queue_id];
 636
 637                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 638                 if (err) {
 639                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 640                                     rx_queue_id);
 641                         return -EINVAL;
 642                 }
 643                 rxq->rx_rel_mbufs(rxq);
 644                 ice_reset_rx_queue(rxq);
 645                 dev->data->rx_queue_state[rx_queue_id] =
 646                         RTE_ETH_QUEUE_STATE_STOPPED;
 647         }
 648
 649         return 0;
 650 }
 651
 652 int
 653 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 654 {
 655         struct ice_tx_queue *txq;
 656         int err;
 657         struct ice_vsi *vsi;
 658         struct ice_hw *hw;
 659         struct ice_aqc_add_tx_qgrp *txq_elem;
 660         struct ice_tlan_ctx tx_ctx;
 661         int buf_len;
 662
 663         PMD_INIT_FUNC_TRACE();
 664
 665         if (tx_queue_id >= dev->data->nb_tx_queues) {
 666                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 667                             tx_queue_id, dev->data->nb_tx_queues);
 668                 return -EINVAL;
 669         }
 670
 671         txq = dev->data->tx_queues[tx_queue_id];
 672         if (!txq || !txq->q_set) {
 673                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 674                             tx_queue_id);
 675                 return -EINVAL;
 676         }
 677
 678         buf_len = ice_struct_size(txq_elem, txqs, 1);
 679         txq_elem = ice_malloc(hw, buf_len);
 680         if (!txq_elem)
 681                 return -ENOMEM;
 682
 683         vsi = txq->vsi;
 684         hw = ICE_VSI_TO_HW(vsi);
 685
 686         memset(&tx_ctx, 0, sizeof(tx_ctx));
 687         txq_elem->num_txqs = 1;
 688         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 689
 690         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 691         tx_ctx.qlen = txq->nb_tx_desc;
 692         tx_ctx.pf_num = hw->pf_id;
 693         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 694         tx_ctx.src_vsi = vsi->vsi_id;
 695         tx_ctx.port_num = hw->port_info->lport;
 696         tx_ctx.tso_ena = 1; /* tso enable */
 697         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 698         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 699         tx_ctx.tsyn_ena = 1;
 700
 701         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 702                     ice_tlan_ctx_info);
 703
 704         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 705
 706         /* Init the Tx tail register*/
 707         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 708
 709         /* Fix me, we assume TC always 0 here */
 710         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 711                         txq_elem, buf_len, NULL);
 712         if (err) {
 713                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 714                 rte_free(txq_elem);
 715                 return -EIO;
 716         }
 717         /* store the schedule node id */
 718         txq->q_teid = txq_elem->txqs[0].q_teid;
 719
 720         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 721
 722         rte_free(txq_elem);
 723         return 0;
 724 }
 725
 726 static enum ice_status
 727 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 728 {
 729         struct ice_vsi *vsi = rxq->vsi;
 730         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 731         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 732         struct ice_rlan_ctx rx_ctx;
 733         enum ice_status err;
 734         uint32_t regval;
 735
 736         rxq->rx_hdr_len = 0;
 737         rxq->rx_buf_len = 1024;
 738
 739         memset(&rx_ctx, 0, sizeof(rx_ctx));
 740
 741         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 742         rx_ctx.qlen = rxq->nb_rx_desc;
 743         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 744         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 745         rx_ctx.dtype = 0; /* No Header Split mode */
 746         rx_ctx.dsize = 1; /* 32B descriptors */
 747         rx_ctx.rxmax = ICE_ETH_MAX_LEN;
 748         /* TPH: Transaction Layer Packet (TLP) processing hints */
 749         rx_ctx.tphrdesc_ena = 1;
 750         rx_ctx.tphwdesc_ena = 1;
 751         rx_ctx.tphdata_ena = 1;
 752         rx_ctx.tphhead_ena = 1;
 753         /* Low Receive Queue Threshold defined in 64 descriptors units.
 754          * When the number of free descriptors goes below the lrxqthresh,
 755          * an immediate interrupt is triggered.
 756          */
 757         rx_ctx.lrxqthresh = 2;
 758         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 759         rx_ctx.l2tsel = 1;
 760         rx_ctx.showiv = 0;
 761         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 762
 763         /* Enable Flexible Descriptors in the queue context which
 764          * allows this driver to select a specific receive descriptor format
 765          */
 766         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 767                 QRXFLXP_CNTXT_RXDID_IDX_M;
 768
 769         /* increasing context priority to pick up profile ID;
 770          * default is 0x01; setting to 0x03 to ensure profile
 771          * is programming if prev context is of same priority
 772          */
 773         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 774                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 775
 776         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 777
 778         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 779         if (err) {
 780                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 781                             rxq->queue_id);
 782                 return -EINVAL;
 783         }
 784         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 785         if (err) {
 786                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 787                             rxq->queue_id);
 788                 return -EINVAL;
 789         }
 790
 791         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 792
 793         /* Init the Rx tail register*/
 794         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 795
 796         return 0;
 797 }
 798
 799 int
 800 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 801 {
 802         struct ice_rx_queue *rxq;
 803         int err;
 804         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 805         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 806
 807         PMD_INIT_FUNC_TRACE();
 808
 809         rxq = pf->fdir.rxq;
 810         if (!rxq || !rxq->q_set) {
 811                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 812                             rx_queue_id);
 813                 return -EINVAL;
 814         }
 815
 816         err = ice_fdir_program_hw_rx_queue(rxq);
 817         if (err) {
 818                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 819                             rx_queue_id);
 820                 return -EIO;
 821         }
 822
 823         /* Init the RX tail register. */
 824         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 825
 826         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 827         if (err) {
 828                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 829                             rx_queue_id);
 830
 831                 ice_reset_rx_queue(rxq);
 832                 return -EINVAL;
 833         }
 834
 835         return 0;
 836 }
 837
 838 int
 839 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 840 {
 841         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 842         struct ice_tx_queue *txq;
 843         int err;
 844         struct ice_vsi *vsi;
 845         struct ice_hw *hw;
 846         struct ice_aqc_add_tx_qgrp *txq_elem;
 847         struct ice_tlan_ctx tx_ctx;
 848         int buf_len;
 849
 850         PMD_INIT_FUNC_TRACE();
 851
 852         txq = pf->fdir.txq;
 853         if (!txq || !txq->q_set) {
 854                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 855                             tx_queue_id);
 856                 return -EINVAL;
 857         }
 858
 859         buf_len = ice_struct_size(txq_elem, txqs, 1);
 860         txq_elem = ice_malloc(hw, buf_len);
 861         if (!txq_elem)
 862                 return -ENOMEM;
 863
 864         vsi = txq->vsi;
 865         hw = ICE_VSI_TO_HW(vsi);
 866
 867         memset(&tx_ctx, 0, sizeof(tx_ctx));
 868         txq_elem->num_txqs = 1;
 869         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 870
 871         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 872         tx_ctx.qlen = txq->nb_tx_desc;
 873         tx_ctx.pf_num = hw->pf_id;
 874         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 875         tx_ctx.src_vsi = vsi->vsi_id;
 876         tx_ctx.port_num = hw->port_info->lport;
 877         tx_ctx.tso_ena = 1; /* tso enable */
 878         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 879         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 880
 881         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 882                     ice_tlan_ctx_info);
 883
 884         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 885
 886         /* Init the Tx tail register*/
 887         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 888
 889         /* Fix me, we assume TC always 0 here */
 890         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 891                               txq_elem, buf_len, NULL);
 892         if (err) {
 893                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 894                 rte_free(txq_elem);
 895                 return -EIO;
 896         }
 897         /* store the schedule node id */
 898         txq->q_teid = txq_elem->txqs[0].q_teid;
 899
 900         rte_free(txq_elem);
 901         return 0;
 902 }
 903
 904 /* Free all mbufs for descriptors in tx queue */
 905 static void
 906 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 907 {
 908         uint16_t i;
 909
 910         if (!txq || !txq->sw_ring) {
 911                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 912                 return;
 913         }
 914
 915         for (i = 0; i < txq->nb_tx_desc; i++) {
 916                 if (txq->sw_ring[i].mbuf) {
 917                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 918                         txq->sw_ring[i].mbuf = NULL;
 919                 }
 920         }
 921 }
 922
 923 static void
 924 ice_reset_tx_queue(struct ice_tx_queue *txq)
 925 {
 926         struct ice_tx_entry *txe;
 927         uint16_t i, prev, size;
 928
 929         if (!txq) {
 930                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 931                 return;
 932         }
 933
 934         txe = txq->sw_ring;
 935         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 936         for (i = 0; i < size; i++)
 937                 ((volatile char *)txq->tx_ring)[i] = 0;
 938
 939         prev = (uint16_t)(txq->nb_tx_desc - 1);
 940         for (i = 0; i < txq->nb_tx_desc; i++) {
 941                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 942
 943                 txd->cmd_type_offset_bsz =
 944                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 945                 txe[i].mbuf =  NULL;
 946                 txe[i].last_id = i;
 947                 txe[prev].next_id = i;
 948                 prev = i;
 949         }
 950
 951         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 952         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 953
 954         txq->tx_tail = 0;
 955         txq->nb_tx_used = 0;
 956
 957         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 958         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 959 }
 960
 961 int
 962 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 963 {
 964         struct ice_tx_queue *txq;
 965         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 966         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 967         struct ice_vsi *vsi = pf->main_vsi;
 968         enum ice_status status;
 969         uint16_t q_ids[1];
 970         uint32_t q_teids[1];
 971         uint16_t q_handle = tx_queue_id;
 972
 973         if (tx_queue_id >= dev->data->nb_tx_queues) {
 974                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 975                             tx_queue_id, dev->data->nb_tx_queues);
 976                 return -EINVAL;
 977         }
 978
 979         txq = dev->data->tx_queues[tx_queue_id];
 980         if (!txq) {
 981                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 982                             tx_queue_id);
 983                 return -EINVAL;
 984         }
 985
 986         q_ids[0] = txq->reg_idx;
 987         q_teids[0] = txq->q_teid;
 988
 989         /* Fix me, we assume TC always 0 here */
 990         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 991                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 992         if (status != ICE_SUCCESS) {
 993                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 994                 return -EINVAL;
 995         }
 996
 997         txq->tx_rel_mbufs(txq);
 998         ice_reset_tx_queue(txq);
 999         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1000
1001         return 0;
1002 }
1003
1004 int
1005 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1006 {
1007         struct ice_rx_queue *rxq;
1008         int err;
1009         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1010         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1011
1012         rxq = pf->fdir.rxq;
1013
1014         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1015         if (err) {
1016                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1017                             rx_queue_id);
1018                 return -EINVAL;
1019         }
1020         rxq->rx_rel_mbufs(rxq);
1021
1022         return 0;
1023 }
1024
1025 int
1026 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1027 {
1028         struct ice_tx_queue *txq;
1029         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031         struct ice_vsi *vsi = pf->main_vsi;
1032         enum ice_status status;
1033         uint16_t q_ids[1];
1034         uint32_t q_teids[1];
1035         uint16_t q_handle = tx_queue_id;
1036
1037         txq = pf->fdir.txq;
1038         if (!txq) {
1039                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1040                             tx_queue_id);
1041                 return -EINVAL;
1042         }
1043         vsi = txq->vsi;
1044
1045         q_ids[0] = txq->reg_idx;
1046         q_teids[0] = txq->q_teid;
1047
1048         /* Fix me, we assume TC always 0 here */
1049         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1050                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1051         if (status != ICE_SUCCESS) {
1052                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1053                 return -EINVAL;
1054         }
1055
1056         txq->tx_rel_mbufs(txq);
1057
1058         return 0;
1059 }
1060
1061 int
1062 ice_rx_queue_setup(struct rte_eth_dev *dev,
1063                    uint16_t queue_idx,
1064                    uint16_t nb_desc,
1065                    unsigned int socket_id,
1066                    const struct rte_eth_rxconf *rx_conf,
1067                    struct rte_mempool *mp)
1068 {
1069         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1070         struct ice_adapter *ad =
1071                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1072         struct ice_vsi *vsi = pf->main_vsi;
1073         struct ice_rx_queue *rxq;
1074         const struct rte_memzone *rz;
1075         uint32_t ring_size;
1076         uint16_t len;
1077         int use_def_burst_func = 1;
1078         uint64_t offloads;
1079
1080         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1081             nb_desc > ICE_MAX_RING_DESC ||
1082             nb_desc < ICE_MIN_RING_DESC) {
1083                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1084                              "invalid", nb_desc);
1085                 return -EINVAL;
1086         }
1087
1088         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1089
1090         /* Free memory if needed */
1091         if (dev->data->rx_queues[queue_idx]) {
1092                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1093                 dev->data->rx_queues[queue_idx] = NULL;
1094         }
1095
1096         /* Allocate the rx queue data structure */
1097         rxq = rte_zmalloc_socket(NULL,
1098                                  sizeof(struct ice_rx_queue),
1099                                  RTE_CACHE_LINE_SIZE,
1100                                  socket_id);
1101         if (!rxq) {
1102                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1103                              "rx queue data structure");
1104                 return -ENOMEM;
1105         }
1106         rxq->mp = mp;
1107         rxq->nb_rx_desc = nb_desc;
1108         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1109         rxq->queue_id = queue_idx;
1110         rxq->offloads = offloads;
1111
1112         rxq->reg_idx = vsi->base_queue + queue_idx;
1113         rxq->port_id = dev->data->port_id;
1114         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1115                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1116         else
1117                 rxq->crc_len = 0;
1118
1119         rxq->drop_en = rx_conf->rx_drop_en;
1120         rxq->vsi = vsi;
1121         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1122         rxq->proto_xtr = pf->proto_xtr != NULL ?
1123                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1124
1125         /* Allocate the maximum number of RX ring hardware descriptor. */
1126         len = ICE_MAX_RING_DESC;
1127
1128         /**
1129          * Allocating a little more memory because vectorized/bulk_alloc Rx
1130          * functions doesn't check boundaries each time.
1131          */
1132         len += ICE_RX_MAX_BURST;
1133
1134         /* Allocate the maximum number of RX ring hardware descriptor. */
1135         ring_size = sizeof(union ice_rx_flex_desc) * len;
1136         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1137         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1138                                       ring_size, ICE_RING_BASE_ALIGN,
1139                                       socket_id);
1140         if (!rz) {
1141                 ice_rx_queue_release(rxq);
1142                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1143                 return -ENOMEM;
1144         }
1145
1146         rxq->mz = rz;
1147         /* Zero all the descriptors in the ring. */
1148         memset(rz->addr, 0, ring_size);
1149
1150         rxq->rx_ring_dma = rz->iova;
1151         rxq->rx_ring = rz->addr;
1152
1153         /* always reserve more for bulk alloc */
1154         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1155
1156         /* Allocate the software ring. */
1157         rxq->sw_ring = rte_zmalloc_socket(NULL,
1158                                           sizeof(struct ice_rx_entry) * len,
1159                                           RTE_CACHE_LINE_SIZE,
1160                                           socket_id);
1161         if (!rxq->sw_ring) {
1162                 ice_rx_queue_release(rxq);
1163                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1164                 return -ENOMEM;
1165         }
1166
1167         ice_reset_rx_queue(rxq);
1168         rxq->q_set = true;
1169         dev->data->rx_queues[queue_idx] = rxq;
1170         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1171
1172         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1173
1174         if (!use_def_burst_func) {
1175                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1176                              "satisfied. Rx Burst Bulk Alloc function will be "
1177                              "used on port=%d, queue=%d.",
1178                              rxq->port_id, rxq->queue_id);
1179         } else {
1180                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1181                              "not satisfied, Scattered Rx is requested. "
1182                              "on port=%d, queue=%d.",
1183                              rxq->port_id, rxq->queue_id);
1184                 ad->rx_bulk_alloc_allowed = false;
1185         }
1186
1187         return 0;
1188 }
1189
1190 void
1191 ice_rx_queue_release(void *rxq)
1192 {
1193         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1194
1195         if (!q) {
1196                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1197                 return;
1198         }
1199
1200         q->rx_rel_mbufs(q);
1201         rte_free(q->sw_ring);
1202         rte_memzone_free(q->mz);
1203         rte_free(q);
1204 }
1205
1206 int
1207 ice_tx_queue_setup(struct rte_eth_dev *dev,
1208                    uint16_t queue_idx,
1209                    uint16_t nb_desc,
1210                    unsigned int socket_id,
1211                    const struct rte_eth_txconf *tx_conf)
1212 {
1213         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1214         struct ice_vsi *vsi = pf->main_vsi;
1215         struct ice_tx_queue *txq;
1216         const struct rte_memzone *tz;
1217         uint32_t ring_size;
1218         uint16_t tx_rs_thresh, tx_free_thresh;
1219         uint64_t offloads;
1220
1221         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1222
1223         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1224             nb_desc > ICE_MAX_RING_DESC ||
1225             nb_desc < ICE_MIN_RING_DESC) {
1226                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1227                              "invalid", nb_desc);
1228                 return -EINVAL;
1229         }
1230
1231         /**
1232          * The following two parameters control the setting of the RS bit on
1233          * transmit descriptors. TX descriptors will have their RS bit set
1234          * after txq->tx_rs_thresh descriptors have been used. The TX
1235          * descriptor ring will be cleaned after txq->tx_free_thresh
1236          * descriptors are used or if the number of descriptors required to
1237          * transmit a packet is greater than the number of free TX descriptors.
1238          *
1239          * The following constraints must be satisfied:
1240          *  - tx_rs_thresh must be greater than 0.
1241          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1242          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1243          *  - tx_rs_thresh must be a divisor of the ring size.
1244          *  - tx_free_thresh must be greater than 0.
1245          *  - tx_free_thresh must be less than the size of the ring minus 3.
1246          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1247          *
1248          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1249          * race condition, hence the maximum threshold constraints. When set
1250          * to zero use default values.
1251          */
1252         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1253                                     tx_conf->tx_free_thresh :
1254                                     ICE_DEFAULT_TX_FREE_THRESH);
1255         /* force tx_rs_thresh to adapt an aggressive tx_free_thresh */
1256         tx_rs_thresh =
1257                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1258                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1259         if (tx_conf->tx_rs_thresh)
1260                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1261         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1262                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1263                                 "exceed nb_desc. (tx_rs_thresh=%u "
1264                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1265                                 (unsigned int)tx_rs_thresh,
1266                                 (unsigned int)tx_free_thresh,
1267                                 (unsigned int)nb_desc,
1268                                 (int)dev->data->port_id,
1269                                 (int)queue_idx);
1270                 return -EINVAL;
1271         }
1272         if (tx_rs_thresh >= (nb_desc - 2)) {
1273                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1274                              "number of TX descriptors minus 2. "
1275                              "(tx_rs_thresh=%u port=%d queue=%d)",
1276                              (unsigned int)tx_rs_thresh,
1277                              (int)dev->data->port_id,
1278                              (int)queue_idx);
1279                 return -EINVAL;
1280         }
1281         if (tx_free_thresh >= (nb_desc - 3)) {
1282                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1283                              "tx_free_thresh must be less than the "
1284                              "number of TX descriptors minus 3. "
1285                              "(tx_free_thresh=%u port=%d queue=%d)",
1286                              (unsigned int)tx_free_thresh,
1287                              (int)dev->data->port_id,
1288                              (int)queue_idx);
1289                 return -EINVAL;
1290         }
1291         if (tx_rs_thresh > tx_free_thresh) {
1292                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1293                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1294                              " tx_rs_thresh=%u port=%d queue=%d)",
1295                              (unsigned int)tx_free_thresh,
1296                              (unsigned int)tx_rs_thresh,
1297                              (int)dev->data->port_id,
1298                              (int)queue_idx);
1299                 return -EINVAL;
1300         }
1301         if ((nb_desc % tx_rs_thresh) != 0) {
1302                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1303                              "number of TX descriptors. (tx_rs_thresh=%u"
1304                              " port=%d queue=%d)",
1305                              (unsigned int)tx_rs_thresh,
1306                              (int)dev->data->port_id,
1307                              (int)queue_idx);
1308                 return -EINVAL;
1309         }
1310         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1311                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1312                              "tx_rs_thresh is greater than 1. "
1313                              "(tx_rs_thresh=%u port=%d queue=%d)",
1314                              (unsigned int)tx_rs_thresh,
1315                              (int)dev->data->port_id,
1316                              (int)queue_idx);
1317                 return -EINVAL;
1318         }
1319
1320         /* Free memory if needed. */
1321         if (dev->data->tx_queues[queue_idx]) {
1322                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1323                 dev->data->tx_queues[queue_idx] = NULL;
1324         }
1325
1326         /* Allocate the TX queue data structure. */
1327         txq = rte_zmalloc_socket(NULL,
1328                                  sizeof(struct ice_tx_queue),
1329                                  RTE_CACHE_LINE_SIZE,
1330                                  socket_id);
1331         if (!txq) {
1332                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1333                              "tx queue structure");
1334                 return -ENOMEM;
1335         }
1336
1337         /* Allocate TX hardware ring descriptors. */
1338         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1339         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1340         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1341                                       ring_size, ICE_RING_BASE_ALIGN,
1342                                       socket_id);
1343         if (!tz) {
1344                 ice_tx_queue_release(txq);
1345                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1346                 return -ENOMEM;
1347         }
1348
1349         txq->mz = tz;
1350         txq->nb_tx_desc = nb_desc;
1351         txq->tx_rs_thresh = tx_rs_thresh;
1352         txq->tx_free_thresh = tx_free_thresh;
1353         txq->pthresh = tx_conf->tx_thresh.pthresh;
1354         txq->hthresh = tx_conf->tx_thresh.hthresh;
1355         txq->wthresh = tx_conf->tx_thresh.wthresh;
1356         txq->queue_id = queue_idx;
1357
1358         txq->reg_idx = vsi->base_queue + queue_idx;
1359         txq->port_id = dev->data->port_id;
1360         txq->offloads = offloads;
1361         txq->vsi = vsi;
1362         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1363
1364         txq->tx_ring_dma = tz->iova;
1365         txq->tx_ring = tz->addr;
1366
1367         /* Allocate software ring */
1368         txq->sw_ring =
1369                 rte_zmalloc_socket(NULL,
1370                                    sizeof(struct ice_tx_entry) * nb_desc,
1371                                    RTE_CACHE_LINE_SIZE,
1372                                    socket_id);
1373         if (!txq->sw_ring) {
1374                 ice_tx_queue_release(txq);
1375                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1376                 return -ENOMEM;
1377         }
1378
1379         ice_reset_tx_queue(txq);
1380         txq->q_set = true;
1381         dev->data->tx_queues[queue_idx] = txq;
1382         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1383         ice_set_tx_function_flag(dev, txq);
1384
1385         return 0;
1386 }
1387
1388 void
1389 ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1390 {
1391         ice_rx_queue_release(dev->data->rx_queues[qid]);
1392 }
1393
1394 void
1395 ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1396 {
1397         ice_tx_queue_release(dev->data->tx_queues[qid]);
1398 }
1399
1400 void
1401 ice_tx_queue_release(void *txq)
1402 {
1403         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1404
1405         if (!q) {
1406                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1407                 return;
1408         }
1409
1410         q->tx_rel_mbufs(q);
1411         rte_free(q->sw_ring);
1412         rte_memzone_free(q->mz);
1413         rte_free(q);
1414 }
1415
1416 void
1417 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1418                  struct rte_eth_rxq_info *qinfo)
1419 {
1420         struct ice_rx_queue *rxq;
1421
1422         rxq = dev->data->rx_queues[queue_id];
1423
1424         qinfo->mp = rxq->mp;
1425         qinfo->scattered_rx = dev->data->scattered_rx;
1426         qinfo->nb_desc = rxq->nb_rx_desc;
1427
1428         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1429         qinfo->conf.rx_drop_en = rxq->drop_en;
1430         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1431 }
1432
1433 void
1434 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1435                  struct rte_eth_txq_info *qinfo)
1436 {
1437         struct ice_tx_queue *txq;
1438
1439         txq = dev->data->tx_queues[queue_id];
1440
1441         qinfo->nb_desc = txq->nb_tx_desc;
1442
1443         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1444         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1445         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1446
1447         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1448         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1449         qinfo->conf.offloads = txq->offloads;
1450         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1451 }
1452
1453 uint32_t
1454 ice_rx_queue_count(void *rx_queue)
1455 {
1456 #define ICE_RXQ_SCAN_INTERVAL 4
1457         volatile union ice_rx_flex_desc *rxdp;
1458         struct ice_rx_queue *rxq;
1459         uint16_t desc = 0;
1460
1461         rxq = rx_queue;
1462         rxdp = &rxq->rx_ring[rxq->rx_tail];
1463         while ((desc < rxq->nb_rx_desc) &&
1464                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1465                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1466                 /**
1467                  * Check the DD bit of a rx descriptor of each 4 in a group,
1468                  * to avoid checking too frequently and downgrading performance
1469                  * too much.
1470                  */
1471                 desc += ICE_RXQ_SCAN_INTERVAL;
1472                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1473                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1474                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1475                                  desc - rxq->nb_rx_desc]);
1476         }
1477
1478         return desc;
1479 }
1480
1481 #define ICE_RX_FLEX_ERR0_BITS   \
1482         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1483          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1484          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1485          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1486          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1487          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1488
1489 /* Rx L3/L4 checksum */
1490 static inline uint64_t
1491 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1492 {
1493         uint64_t flags = 0;
1494
1495         /* check if HW has decoded the packet and checksum */
1496         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1497                 return 0;
1498
1499         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1500                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
1501                           RTE_MBUF_F_RX_L4_CKSUM_GOOD |
1502                           RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD);
1503                 return flags;
1504         }
1505
1506         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1507                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1508         else
1509                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1510
1511         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1512                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1513         else
1514                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1515
1516         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1517                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1518
1519         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1520                 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;
1521         else
1522                 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD;
1523
1524         return flags;
1525 }
1526
1527 static inline void
1528 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1529 {
1530         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1531             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1532                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1533                 mb->vlan_tci =
1534                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1535                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1536                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1537         } else {
1538                 mb->vlan_tci = 0;
1539         }
1540
1541 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1542         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1543             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1544                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
1545                                 RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
1546                 mb->vlan_tci_outer = mb->vlan_tci;
1547                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1548                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1549                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1550                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1551         } else {
1552                 mb->vlan_tci_outer = 0;
1553         }
1554 #endif
1555         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1556                    mb->vlan_tci, mb->vlan_tci_outer);
1557 }
1558
1559 #define ICE_LOOK_AHEAD 8
1560 #if (ICE_LOOK_AHEAD != 8)
1561 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1562 #endif
1563
1564 #define ICE_PTP_TS_VALID 0x1
1565
1566 static inline int
1567 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1568 {
1569         volatile union ice_rx_flex_desc *rxdp;
1570         struct ice_rx_entry *rxep;
1571         struct rte_mbuf *mb;
1572         uint16_t stat_err0;
1573         uint16_t pkt_len;
1574         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1575         int32_t i, j, nb_rx = 0;
1576         uint64_t pkt_flags = 0;
1577         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1578 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1579         bool is_tsinit = false;
1580         uint64_t ts_ns;
1581         struct ice_vsi *vsi = rxq->vsi;
1582         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1583         struct ice_adapter *ad = rxq->vsi->adapter;
1584 #endif
1585         rxdp = &rxq->rx_ring[rxq->rx_tail];
1586         rxep = &rxq->sw_ring[rxq->rx_tail];
1587
1588         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1589
1590         /* Make sure there is at least 1 packet to receive */
1591         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1592                 return 0;
1593
1594 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1595         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1596                 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1597
1598                 if (unlikely(sw_cur_time - rxq->hw_time_update > 4))
1599                         is_tsinit = 1;
1600         }
1601 #endif
1602
1603         /**
1604          * Scan LOOK_AHEAD descriptors at a time to determine which
1605          * descriptors reference packets that are ready to be received.
1606          */
1607         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1608              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1609                 /* Read desc statuses backwards to avoid race condition */
1610                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1611                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1612
1613                 rte_smp_rmb();
1614
1615                 /* Compute how many status bits were set */
1616                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1617                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1618
1619                 nb_rx += nb_dd;
1620
1621                 /* Translate descriptor info to mbuf parameters */
1622                 for (j = 0; j < nb_dd; j++) {
1623                         mb = rxep[j].mbuf;
1624                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1625                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1626                         mb->data_len = pkt_len;
1627                         mb->pkt_len = pkt_len;
1628                         mb->ol_flags = 0;
1629                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1630                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1631                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1632                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1633                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1634                         rxd_to_pkt_fields_ops[rxq->rxdid](rxq, mb, &rxdp[j]);
1635 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1636                         if (ice_timestamp_dynflag > 0) {
1637                                 rxq->time_high =
1638                                 rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high);
1639                                 if (unlikely(is_tsinit)) {
1640                                         ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1,
1641                                                                            rxq->time_high);
1642                                         rxq->hw_time_low = (uint32_t)ts_ns;
1643                                         rxq->hw_time_high = (uint32_t)(ts_ns >> 32);
1644                                         is_tsinit = false;
1645                                 } else {
1646                                         if (rxq->time_high < rxq->hw_time_low)
1647                                                 rxq->hw_time_high += 1;
1648                                         ts_ns = (uint64_t)rxq->hw_time_high << 32 | rxq->time_high;
1649                                         rxq->hw_time_low = rxq->time_high;
1650                                 }
1651                                 rxq->hw_time_update = rte_get_timer_cycles() /
1652                                                      (rte_get_timer_hz() / 1000);
1653                                 *RTE_MBUF_DYNFIELD(mb,
1654                                                    ice_timestamp_dynfield_offset,
1655                                                    rte_mbuf_timestamp_t *) = ts_ns;
1656                                 pkt_flags |= ice_timestamp_dynflag;
1657                         }
1658
1659                         if (ad->ptp_ena && ((mb->packet_type &
1660                             RTE_PTYPE_L2_MASK) == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1661                                 rxq->time_high =
1662                                    rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high);
1663                                 mb->timesync = rxq->queue_id;
1664                                 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1665                                 if (rxdp[j].wb.time_stamp_low &
1666                                     ICE_PTP_TS_VALID)
1667                                         pkt_flags |=
1668                                                 RTE_MBUF_F_RX_IEEE1588_TMST;
1669                         }
1670 #endif
1671                         mb->ol_flags |= pkt_flags;
1672                 }
1673
1674                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1675                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1676
1677                 if (nb_dd != ICE_LOOK_AHEAD)
1678                         break;
1679         }
1680
1681         /* Clear software ring entries */
1682         for (i = 0; i < nb_rx; i++)
1683                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1684
1685         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1686                    "port_id=%u, queue_id=%u, nb_rx=%d",
1687                    rxq->port_id, rxq->queue_id, nb_rx);
1688
1689         return nb_rx;
1690 }
1691
1692 static inline uint16_t
1693 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1694                        struct rte_mbuf **rx_pkts,
1695                        uint16_t nb_pkts)
1696 {
1697         uint16_t i;
1698         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1699
1700         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1701
1702         for (i = 0; i < nb_pkts; i++)
1703                 rx_pkts[i] = stage[i];
1704
1705         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1706         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1707
1708         return nb_pkts;
1709 }
1710
1711 static inline int
1712 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1713 {
1714         volatile union ice_rx_flex_desc *rxdp;
1715         struct ice_rx_entry *rxep;
1716         struct rte_mbuf *mb;
1717         uint16_t alloc_idx, i;
1718         uint64_t dma_addr;
1719         int diag;
1720
1721         /* Allocate buffers in bulk */
1722         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1723                                (rxq->rx_free_thresh - 1));
1724         rxep = &rxq->sw_ring[alloc_idx];
1725         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1726                                     rxq->rx_free_thresh);
1727         if (unlikely(diag != 0)) {
1728                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1729                 return -ENOMEM;
1730         }
1731
1732         rxdp = &rxq->rx_ring[alloc_idx];
1733         for (i = 0; i < rxq->rx_free_thresh; i++) {
1734                 if (likely(i < (rxq->rx_free_thresh - 1)))
1735                         /* Prefetch next mbuf */
1736                         rte_prefetch0(rxep[i + 1].mbuf);
1737
1738                 mb = rxep[i].mbuf;
1739                 rte_mbuf_refcnt_set(mb, 1);
1740                 mb->next = NULL;
1741                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1742                 mb->nb_segs = 1;
1743                 mb->port = rxq->port_id;
1744                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1745                 rxdp[i].read.hdr_addr = 0;
1746                 rxdp[i].read.pkt_addr = dma_addr;
1747         }
1748
1749         /* Update Rx tail register */
1750         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1751
1752         rxq->rx_free_trigger =
1753                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1754         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1755                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1756
1757         return 0;
1758 }
1759
1760 static inline uint16_t
1761 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1762 {
1763         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1764         uint16_t nb_rx = 0;
1765
1766         if (!nb_pkts)
1767                 return 0;
1768
1769         if (rxq->rx_nb_avail)
1770                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1771
1772         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1773         rxq->rx_next_avail = 0;
1774         rxq->rx_nb_avail = nb_rx;
1775         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1776
1777         if (rxq->rx_tail > rxq->rx_free_trigger) {
1778                 if (ice_rx_alloc_bufs(rxq) != 0) {
1779                         uint16_t i, j;
1780
1781                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1782                                 rxq->rx_free_thresh;
1783                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1784                                    "port_id=%u, queue_id=%u",
1785                                    rxq->port_id, rxq->queue_id);
1786                         rxq->rx_nb_avail = 0;
1787                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1788                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1789                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1790
1791                         return 0;
1792                 }
1793         }
1794
1795         if (rxq->rx_tail >= rxq->nb_rx_desc)
1796                 rxq->rx_tail = 0;
1797
1798         if (rxq->rx_nb_avail)
1799                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1800
1801         return 0;
1802 }
1803
1804 static uint16_t
1805 ice_recv_pkts_bulk_alloc(void *rx_queue,
1806                          struct rte_mbuf **rx_pkts,
1807                          uint16_t nb_pkts)
1808 {
1809         uint16_t nb_rx = 0;
1810         uint16_t n;
1811         uint16_t count;
1812
1813         if (unlikely(nb_pkts == 0))
1814                 return nb_rx;
1815
1816         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1817                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1818
1819         while (nb_pkts) {
1820                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1821                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1822                 nb_rx = (uint16_t)(nb_rx + count);
1823                 nb_pkts = (uint16_t)(nb_pkts - count);
1824                 if (count < n)
1825                         break;
1826         }
1827
1828         return nb_rx;
1829 }
1830
1831 static uint16_t
1832 ice_recv_scattered_pkts(void *rx_queue,
1833                         struct rte_mbuf **rx_pkts,
1834                         uint16_t nb_pkts)
1835 {
1836         struct ice_rx_queue *rxq = rx_queue;
1837         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1838         volatile union ice_rx_flex_desc *rxdp;
1839         union ice_rx_flex_desc rxd;
1840         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1841         struct ice_rx_entry *rxe;
1842         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1843         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1844         struct rte_mbuf *nmb; /* new allocated mbuf */
1845         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1846         uint16_t rx_id = rxq->rx_tail;
1847         uint16_t nb_rx = 0;
1848         uint16_t nb_hold = 0;
1849         uint16_t rx_packet_len;
1850         uint16_t rx_stat_err0;
1851         uint64_t dma_addr;
1852         uint64_t pkt_flags;
1853         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1854 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1855         bool is_tsinit = false;
1856         uint64_t ts_ns;
1857         struct ice_vsi *vsi = rxq->vsi;
1858         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1859         struct ice_adapter *ad = rxq->vsi->adapter;
1860
1861         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1862                 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1863
1864                 if (unlikely(sw_cur_time - rxq->hw_time_update > 4))
1865                         is_tsinit = true;
1866         }
1867 #endif
1868
1869         while (nb_rx < nb_pkts) {
1870                 rxdp = &rx_ring[rx_id];
1871                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1872
1873                 /* Check the DD bit first */
1874                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1875                         break;
1876
1877                 /* allocate mbuf */
1878                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1879                 if (unlikely(!nmb)) {
1880                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1881                         break;
1882                 }
1883                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1884
1885                 nb_hold++;
1886                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1887                 rx_id++;
1888                 if (unlikely(rx_id == rxq->nb_rx_desc))
1889                         rx_id = 0;
1890
1891                 /* Prefetch next mbuf */
1892                 rte_prefetch0(sw_ring[rx_id].mbuf);
1893
1894                 /**
1895                  * When next RX descriptor is on a cache line boundary,
1896                  * prefetch the next 4 RX descriptors and next 8 pointers
1897                  * to mbufs.
1898                  */
1899                 if ((rx_id & 0x3) == 0) {
1900                         rte_prefetch0(&rx_ring[rx_id]);
1901                         rte_prefetch0(&sw_ring[rx_id]);
1902                 }
1903
1904                 rxm = rxe->mbuf;
1905                 rxe->mbuf = nmb;
1906                 dma_addr =
1907                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1908
1909                 /* Set data buffer address and data length of the mbuf */
1910                 rxdp->read.hdr_addr = 0;
1911                 rxdp->read.pkt_addr = dma_addr;
1912                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1913                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1914                 rxm->data_len = rx_packet_len;
1915                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1916
1917                 /**
1918                  * If this is the first buffer of the received packet, set the
1919                  * pointer to the first mbuf of the packet and initialize its
1920                  * context. Otherwise, update the total length and the number
1921                  * of segments of the current scattered packet, and update the
1922                  * pointer to the last mbuf of the current packet.
1923                  */
1924                 if (!first_seg) {
1925                         first_seg = rxm;
1926                         first_seg->nb_segs = 1;
1927                         first_seg->pkt_len = rx_packet_len;
1928                 } else {
1929                         first_seg->pkt_len =
1930                                 (uint16_t)(first_seg->pkt_len +
1931                                            rx_packet_len);
1932                         first_seg->nb_segs++;
1933                         last_seg->next = rxm;
1934                 }
1935
1936                 /**
1937                  * If this is not the last buffer of the received packet,
1938                  * update the pointer to the last mbuf of the current scattered
1939                  * packet and continue to parse the RX ring.
1940                  */
1941                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1942                         last_seg = rxm;
1943                         continue;
1944                 }
1945
1946                 /**
1947                  * This is the last buffer of the received packet. If the CRC
1948                  * is not stripped by the hardware:
1949                  *  - Subtract the CRC length from the total packet length.
1950                  *  - If the last buffer only contains the whole CRC or a part
1951                  *  of it, free the mbuf associated to the last buffer. If part
1952                  *  of the CRC is also contained in the previous mbuf, subtract
1953                  *  the length of that CRC part from the data length of the
1954                  *  previous mbuf.
1955                  */
1956                 rxm->next = NULL;
1957                 if (unlikely(rxq->crc_len > 0)) {
1958                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1959                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1960                                 rte_pktmbuf_free_seg(rxm);
1961                                 first_seg->nb_segs--;
1962                                 last_seg->data_len =
1963                                         (uint16_t)(last_seg->data_len -
1964                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1965                                 last_seg->next = NULL;
1966                         } else
1967                                 rxm->data_len = (uint16_t)(rx_packet_len -
1968                                                            RTE_ETHER_CRC_LEN);
1969                 }
1970
1971                 first_seg->port = rxq->port_id;
1972                 first_seg->ol_flags = 0;
1973                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1974                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1975                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1976                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, first_seg, &rxd);
1977                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1978 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1979                 if (ice_timestamp_dynflag > 0) {
1980                         rxq->time_high =
1981                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
1982                         if (unlikely(is_tsinit)) {
1983                                 ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, rxq->time_high);
1984                                 rxq->hw_time_low = (uint32_t)ts_ns;
1985                                 rxq->hw_time_high = (uint32_t)(ts_ns >> 32);
1986                                 is_tsinit = false;
1987                         } else {
1988                                 if (rxq->time_high < rxq->hw_time_low)
1989                                         rxq->hw_time_high += 1;
1990                                 ts_ns = (uint64_t)rxq->hw_time_high << 32 | rxq->time_high;
1991                                 rxq->hw_time_low = rxq->time_high;
1992                         }
1993                         rxq->hw_time_update = rte_get_timer_cycles() /
1994                                              (rte_get_timer_hz() / 1000);
1995                         *RTE_MBUF_DYNFIELD(rxm,
1996                                            (ice_timestamp_dynfield_offset),
1997                                            rte_mbuf_timestamp_t *) = ts_ns;
1998                         pkt_flags |= ice_timestamp_dynflag;
1999                 }
2000
2001                 if (ad->ptp_ena && ((first_seg->packet_type & RTE_PTYPE_L2_MASK)
2002                     == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
2003                         rxq->time_high =
2004                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2005                         first_seg->timesync = rxq->queue_id;
2006                         pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
2007                 }
2008 #endif
2009                 first_seg->ol_flags |= pkt_flags;
2010                 /* Prefetch data of first segment, if configured to do so. */
2011                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
2012                                           first_seg->data_off));
2013                 rx_pkts[nb_rx++] = first_seg;
2014                 first_seg = NULL;
2015         }
2016
2017         /* Record index of the next RX descriptor to probe. */
2018         rxq->rx_tail = rx_id;
2019         rxq->pkt_first_seg = first_seg;
2020         rxq->pkt_last_seg = last_seg;
2021
2022         /**
2023          * If the number of free RX descriptors is greater than the RX free
2024          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
2025          * register. Update the RDT with the value of the last processed RX
2026          * descriptor minus 1, to guarantee that the RDT register is never
2027          * equal to the RDH register, which creates a "full" ring situation
2028          * from the hardware point of view.
2029          */
2030         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2031         if (nb_hold > rxq->rx_free_thresh) {
2032                 rx_id = (uint16_t)(rx_id == 0 ?
2033                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2034                 /* write TAIL register */
2035                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2036                 nb_hold = 0;
2037         }
2038         rxq->nb_rx_hold = nb_hold;
2039
2040         /* return received packet in the burst */
2041         return nb_rx;
2042 }
2043
2044 const uint32_t *
2045 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2046 {
2047         struct ice_adapter *ad =
2048                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2049         const uint32_t *ptypes;
2050
2051         static const uint32_t ptypes_os[] = {
2052                 /* refers to ice_get_default_pkt_type() */
2053                 RTE_PTYPE_L2_ETHER,
2054                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2055                 RTE_PTYPE_L2_ETHER_LLDP,
2056                 RTE_PTYPE_L2_ETHER_ARP,
2057                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2058                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2059                 RTE_PTYPE_L4_FRAG,
2060                 RTE_PTYPE_L4_ICMP,
2061                 RTE_PTYPE_L4_NONFRAG,
2062                 RTE_PTYPE_L4_SCTP,
2063                 RTE_PTYPE_L4_TCP,
2064                 RTE_PTYPE_L4_UDP,
2065                 RTE_PTYPE_TUNNEL_GRENAT,
2066                 RTE_PTYPE_TUNNEL_IP,
2067                 RTE_PTYPE_INNER_L2_ETHER,
2068                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2069                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2070                 RTE_PTYPE_INNER_L4_FRAG,
2071                 RTE_PTYPE_INNER_L4_ICMP,
2072                 RTE_PTYPE_INNER_L4_NONFRAG,
2073                 RTE_PTYPE_INNER_L4_SCTP,
2074                 RTE_PTYPE_INNER_L4_TCP,
2075                 RTE_PTYPE_INNER_L4_UDP,
2076                 RTE_PTYPE_UNKNOWN
2077         };
2078
2079         static const uint32_t ptypes_comms[] = {
2080                 /* refers to ice_get_default_pkt_type() */
2081                 RTE_PTYPE_L2_ETHER,
2082                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2083                 RTE_PTYPE_L2_ETHER_LLDP,
2084                 RTE_PTYPE_L2_ETHER_ARP,
2085                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2086                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2087                 RTE_PTYPE_L4_FRAG,
2088                 RTE_PTYPE_L4_ICMP,
2089                 RTE_PTYPE_L4_NONFRAG,
2090                 RTE_PTYPE_L4_SCTP,
2091                 RTE_PTYPE_L4_TCP,
2092                 RTE_PTYPE_L4_UDP,
2093                 RTE_PTYPE_TUNNEL_GRENAT,
2094                 RTE_PTYPE_TUNNEL_IP,
2095                 RTE_PTYPE_INNER_L2_ETHER,
2096                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2097                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2098                 RTE_PTYPE_INNER_L4_FRAG,
2099                 RTE_PTYPE_INNER_L4_ICMP,
2100                 RTE_PTYPE_INNER_L4_NONFRAG,
2101                 RTE_PTYPE_INNER_L4_SCTP,
2102                 RTE_PTYPE_INNER_L4_TCP,
2103                 RTE_PTYPE_INNER_L4_UDP,
2104                 RTE_PTYPE_TUNNEL_GTPC,
2105                 RTE_PTYPE_TUNNEL_GTPU,
2106                 RTE_PTYPE_L2_ETHER_PPPOE,
2107                 RTE_PTYPE_UNKNOWN
2108         };
2109
2110         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
2111                 ptypes = ptypes_comms;
2112         else
2113                 ptypes = ptypes_os;
2114
2115         if (dev->rx_pkt_burst == ice_recv_pkts ||
2116             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
2117             dev->rx_pkt_burst == ice_recv_scattered_pkts)
2118                 return ptypes;
2119
2120 #ifdef RTE_ARCH_X86
2121         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
2122             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
2123 #ifdef CC_AVX512_SUPPORT
2124             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
2125             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
2126             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
2127             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
2128 #endif
2129             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
2130             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
2131             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2132             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2133                 return ptypes;
2134 #endif
2135
2136         return NULL;
2137 }
2138
2139 int
2140 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2141 {
2142         volatile union ice_rx_flex_desc *rxdp;
2143         struct ice_rx_queue *rxq = rx_queue;
2144         uint32_t desc;
2145
2146         if (unlikely(offset >= rxq->nb_rx_desc))
2147                 return -EINVAL;
2148
2149         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2150                 return RTE_ETH_RX_DESC_UNAVAIL;
2151
2152         desc = rxq->rx_tail + offset;
2153         if (desc >= rxq->nb_rx_desc)
2154                 desc -= rxq->nb_rx_desc;
2155
2156         rxdp = &rxq->rx_ring[desc];
2157         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2158             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2159                 return RTE_ETH_RX_DESC_DONE;
2160
2161         return RTE_ETH_RX_DESC_AVAIL;
2162 }
2163
2164 int
2165 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2166 {
2167         struct ice_tx_queue *txq = tx_queue;
2168         volatile uint64_t *status;
2169         uint64_t mask, expect;
2170         uint32_t desc;
2171
2172         if (unlikely(offset >= txq->nb_tx_desc))
2173                 return -EINVAL;
2174
2175         desc = txq->tx_tail + offset;
2176         /* go to next desc that has the RS bit */
2177         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2178                 txq->tx_rs_thresh;
2179         if (desc >= txq->nb_tx_desc) {
2180                 desc -= txq->nb_tx_desc;
2181                 if (desc >= txq->nb_tx_desc)
2182                         desc -= txq->nb_tx_desc;
2183         }
2184
2185         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2186         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2187         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2188                                   ICE_TXD_QW1_DTYPE_S);
2189         if ((*status & mask) == expect)
2190                 return RTE_ETH_TX_DESC_DONE;
2191
2192         return RTE_ETH_TX_DESC_FULL;
2193 }
2194
2195 void
2196 ice_free_queues(struct rte_eth_dev *dev)
2197 {
2198         uint16_t i;
2199
2200         PMD_INIT_FUNC_TRACE();
2201
2202         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2203                 if (!dev->data->rx_queues[i])
2204                         continue;
2205                 ice_rx_queue_release(dev->data->rx_queues[i]);
2206                 dev->data->rx_queues[i] = NULL;
2207         }
2208         dev->data->nb_rx_queues = 0;
2209
2210         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2211                 if (!dev->data->tx_queues[i])
2212                         continue;
2213                 ice_tx_queue_release(dev->data->tx_queues[i]);
2214                 dev->data->tx_queues[i] = NULL;
2215         }
2216         dev->data->nb_tx_queues = 0;
2217 }
2218
2219 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
2220 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
2221
2222 int
2223 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2224 {
2225         struct ice_tx_queue *txq;
2226         const struct rte_memzone *tz = NULL;
2227         uint32_t ring_size;
2228         struct rte_eth_dev *dev;
2229
2230         if (!pf) {
2231                 PMD_DRV_LOG(ERR, "PF is not available");
2232                 return -EINVAL;
2233         }
2234
2235         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2236
2237         /* Allocate the TX queue data structure. */
2238         txq = rte_zmalloc_socket("ice fdir tx queue",
2239                                  sizeof(struct ice_tx_queue),
2240                                  RTE_CACHE_LINE_SIZE,
2241                                  SOCKET_ID_ANY);
2242         if (!txq) {
2243                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2244                             "tx queue structure.");
2245                 return -ENOMEM;
2246         }
2247
2248         /* Allocate TX hardware ring descriptors. */
2249         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2250         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2251
2252         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2253                                       ICE_FDIR_QUEUE_ID, ring_size,
2254                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2255         if (!tz) {
2256                 ice_tx_queue_release(txq);
2257                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2258                 return -ENOMEM;
2259         }
2260
2261         txq->mz = tz;
2262         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2263         txq->queue_id = ICE_FDIR_QUEUE_ID;
2264         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2265         txq->vsi = pf->fdir.fdir_vsi;
2266
2267         txq->tx_ring_dma = tz->iova;
2268         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2269         /*
2270          * don't need to allocate software ring and reset for the fdir
2271          * program queue just set the queue has been configured.
2272          */
2273         txq->q_set = true;
2274         pf->fdir.txq = txq;
2275
2276         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2277
2278         return ICE_SUCCESS;
2279 }
2280
2281 int
2282 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2283 {
2284         struct ice_rx_queue *rxq;
2285         const struct rte_memzone *rz = NULL;
2286         uint32_t ring_size;
2287         struct rte_eth_dev *dev;
2288
2289         if (!pf) {
2290                 PMD_DRV_LOG(ERR, "PF is not available");
2291                 return -EINVAL;
2292         }
2293
2294         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2295
2296         /* Allocate the RX queue data structure. */
2297         rxq = rte_zmalloc_socket("ice fdir rx queue",
2298                                  sizeof(struct ice_rx_queue),
2299                                  RTE_CACHE_LINE_SIZE,
2300                                  SOCKET_ID_ANY);
2301         if (!rxq) {
2302                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2303                             "rx queue structure.");
2304                 return -ENOMEM;
2305         }
2306
2307         /* Allocate RX hardware ring descriptors. */
2308         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2309         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2310
2311         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2312                                       ICE_FDIR_QUEUE_ID, ring_size,
2313                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2314         if (!rz) {
2315                 ice_rx_queue_release(rxq);
2316                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2317                 return -ENOMEM;
2318         }
2319
2320         rxq->mz = rz;
2321         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2322         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2323         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2324         rxq->vsi = pf->fdir.fdir_vsi;
2325
2326         rxq->rx_ring_dma = rz->iova;
2327         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2328                sizeof(union ice_32byte_rx_desc));
2329         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2330
2331         /*
2332          * Don't need to allocate software ring and reset for the fdir
2333          * rx queue, just set the queue has been configured.
2334          */
2335         rxq->q_set = true;
2336         pf->fdir.rxq = rxq;
2337
2338         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2339
2340         return ICE_SUCCESS;
2341 }
2342
2343 uint16_t
2344 ice_recv_pkts(void *rx_queue,
2345               struct rte_mbuf **rx_pkts,
2346               uint16_t nb_pkts)
2347 {
2348         struct ice_rx_queue *rxq = rx_queue;
2349         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2350         volatile union ice_rx_flex_desc *rxdp;
2351         union ice_rx_flex_desc rxd;
2352         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2353         struct ice_rx_entry *rxe;
2354         struct rte_mbuf *nmb; /* new allocated mbuf */
2355         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2356         uint16_t rx_id = rxq->rx_tail;
2357         uint16_t nb_rx = 0;
2358         uint16_t nb_hold = 0;
2359         uint16_t rx_packet_len;
2360         uint16_t rx_stat_err0;
2361         uint64_t dma_addr;
2362         uint64_t pkt_flags;
2363         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2364 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2365         bool is_tsinit = false;
2366         uint64_t ts_ns;
2367         struct ice_vsi *vsi = rxq->vsi;
2368         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2369         struct ice_adapter *ad = rxq->vsi->adapter;
2370
2371         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
2372                 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
2373
2374                 if (unlikely(sw_cur_time - rxq->hw_time_update > 4))
2375                         is_tsinit = 1;
2376         }
2377 #endif
2378
2379         while (nb_rx < nb_pkts) {
2380                 rxdp = &rx_ring[rx_id];
2381                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2382
2383                 /* Check the DD bit first */
2384                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2385                         break;
2386
2387                 /* allocate mbuf */
2388                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2389                 if (unlikely(!nmb)) {
2390                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2391                         break;
2392                 }
2393                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2394
2395                 nb_hold++;
2396                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2397                 rx_id++;
2398                 if (unlikely(rx_id == rxq->nb_rx_desc))
2399                         rx_id = 0;
2400                 rxm = rxe->mbuf;
2401                 rxe->mbuf = nmb;
2402                 dma_addr =
2403                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2404
2405                 /**
2406                  * fill the read format of descriptor with physic address in
2407                  * new allocated mbuf: nmb
2408                  */
2409                 rxdp->read.hdr_addr = 0;
2410                 rxdp->read.pkt_addr = dma_addr;
2411
2412                 /* calculate rx_packet_len of the received pkt */
2413                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2414                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2415
2416                 /* fill old mbuf with received descriptor: rxd */
2417                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2418                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2419                 rxm->nb_segs = 1;
2420                 rxm->next = NULL;
2421                 rxm->pkt_len = rx_packet_len;
2422                 rxm->data_len = rx_packet_len;
2423                 rxm->port = rxq->port_id;
2424                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2425                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2426                 ice_rxd_to_vlan_tci(rxm, &rxd);
2427                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, rxm, &rxd);
2428                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2429 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2430                 if (ice_timestamp_dynflag > 0) {
2431                         rxq->time_high =
2432                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2433                         if (unlikely(is_tsinit)) {
2434                                 ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, rxq->time_high);
2435                                 rxq->hw_time_low = (uint32_t)ts_ns;
2436                                 rxq->hw_time_high = (uint32_t)(ts_ns >> 32);
2437                                 is_tsinit = false;
2438                         } else {
2439                                 if (rxq->time_high < rxq->hw_time_low)
2440                                         rxq->hw_time_high += 1;
2441                                 ts_ns = (uint64_t)rxq->hw_time_high << 32 | rxq->time_high;
2442                                 rxq->hw_time_low = rxq->time_high;
2443                         }
2444                         rxq->hw_time_update = rte_get_timer_cycles() /
2445                                              (rte_get_timer_hz() / 1000);
2446                         *RTE_MBUF_DYNFIELD(rxm,
2447                                            (ice_timestamp_dynfield_offset),
2448                                            rte_mbuf_timestamp_t *) = ts_ns;
2449                         pkt_flags |= ice_timestamp_dynflag;
2450                 }
2451
2452                 if (ad->ptp_ena && ((rxm->packet_type & RTE_PTYPE_L2_MASK) ==
2453                     RTE_PTYPE_L2_ETHER_TIMESYNC)) {
2454                         rxq->time_high =
2455                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2456                         rxm->timesync = rxq->queue_id;
2457                         pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
2458                 }
2459 #endif
2460                 rxm->ol_flags |= pkt_flags;
2461                 /* copy old mbuf to rx_pkts */
2462                 rx_pkts[nb_rx++] = rxm;
2463         }
2464
2465         rxq->rx_tail = rx_id;
2466         /**
2467          * If the number of free RX descriptors is greater than the RX free
2468          * threshold of the queue, advance the receive tail register of queue.
2469          * Update that register with the value of the last processed RX
2470          * descriptor minus 1.
2471          */
2472         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2473         if (nb_hold > rxq->rx_free_thresh) {
2474                 rx_id = (uint16_t)(rx_id == 0 ?
2475                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2476                 /* write TAIL register */
2477                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2478                 nb_hold = 0;
2479         }
2480         rxq->nb_rx_hold = nb_hold;
2481
2482         /* return received packet in the burst */
2483         return nb_rx;
2484 }
2485
2486 static inline void
2487 ice_parse_tunneling_params(uint64_t ol_flags,
2488                             union ice_tx_offload tx_offload,
2489                             uint32_t *cd_tunneling)
2490 {
2491         /* EIPT: External (outer) IP header type */
2492         if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
2493                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2494         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
2495                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2496         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
2497                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2498
2499         /* EIPLEN: External (outer) IP header length, in DWords */
2500         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2501                 ICE_TXD_CTX_QW0_EIPLEN_S;
2502
2503         /* L4TUNT: L4 Tunneling Type */
2504         switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
2505         case RTE_MBUF_F_TX_TUNNEL_IPIP:
2506                 /* for non UDP / GRE tunneling, set to 00b */
2507                 break;
2508         case RTE_MBUF_F_TX_TUNNEL_VXLAN:
2509         case RTE_MBUF_F_TX_TUNNEL_GTP:
2510         case RTE_MBUF_F_TX_TUNNEL_GENEVE:
2511                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2512                 break;
2513         case RTE_MBUF_F_TX_TUNNEL_GRE:
2514                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2515                 break;
2516         default:
2517                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2518                 return;
2519         }
2520
2521         /* L4TUNLEN: L4 Tunneling Length, in Words
2522          *
2523          * We depend on app to set rte_mbuf.l2_len correctly.
2524          * For IP in GRE it should be set to the length of the GRE
2525          * header;
2526          * For MAC in GRE or MAC in UDP it should be set to the length
2527          * of the GRE or UDP headers plus the inner MAC up to including
2528          * its last Ethertype.
2529          * If MPLS labels exists, it should include them as well.
2530          */
2531         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2532                 ICE_TXD_CTX_QW0_NATLEN_S;
2533
2534         /**
2535          * Calculate the tunneling UDP checksum.
2536          * Shall be set only if L4TUNT = 01b and EIPT is not zero
2537          */
2538         if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2539             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2540                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2541 }
2542
2543 static inline void
2544 ice_txd_enable_checksum(uint64_t ol_flags,
2545                         uint32_t *td_cmd,
2546                         uint32_t *td_offset,
2547                         union ice_tx_offload tx_offload)
2548 {
2549         /* Set MACLEN */
2550         if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2551                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2552                         << ICE_TX_DESC_LEN_MACLEN_S;
2553         else
2554                 *td_offset |= (tx_offload.l2_len >> 1)
2555                         << ICE_TX_DESC_LEN_MACLEN_S;
2556
2557         /* Enable L3 checksum offloads */
2558         if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
2559                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2560                 *td_offset |= (tx_offload.l3_len >> 2) <<
2561                         ICE_TX_DESC_LEN_IPLEN_S;
2562         } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2563                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2564                 *td_offset |= (tx_offload.l3_len >> 2) <<
2565                         ICE_TX_DESC_LEN_IPLEN_S;
2566         } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2567                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2568                 *td_offset |= (tx_offload.l3_len >> 2) <<
2569                         ICE_TX_DESC_LEN_IPLEN_S;
2570         }
2571
2572         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2573                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2574                 *td_offset |= (tx_offload.l4_len >> 2) <<
2575                               ICE_TX_DESC_LEN_L4_LEN_S;
2576                 return;
2577         }
2578
2579         /* Enable L4 checksum offloads */
2580         switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2581         case RTE_MBUF_F_TX_TCP_CKSUM:
2582                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2583                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2584                               ICE_TX_DESC_LEN_L4_LEN_S;
2585                 break;
2586         case RTE_MBUF_F_TX_SCTP_CKSUM:
2587                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2588                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2589                               ICE_TX_DESC_LEN_L4_LEN_S;
2590                 break;
2591         case RTE_MBUF_F_TX_UDP_CKSUM:
2592                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2593                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2594                               ICE_TX_DESC_LEN_L4_LEN_S;
2595                 break;
2596         default:
2597                 break;
2598         }
2599 }
2600
2601 static inline int
2602 ice_xmit_cleanup(struct ice_tx_queue *txq)
2603 {
2604         struct ice_tx_entry *sw_ring = txq->sw_ring;
2605         volatile struct ice_tx_desc *txd = txq->tx_ring;
2606         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2607         uint16_t nb_tx_desc = txq->nb_tx_desc;
2608         uint16_t desc_to_clean_to;
2609         uint16_t nb_tx_to_clean;
2610
2611         /* Determine the last descriptor needing to be cleaned */
2612         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2613         if (desc_to_clean_to >= nb_tx_desc)
2614                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2615
2616         /* Check to make sure the last descriptor to clean is done */
2617         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2618         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2619             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2620                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2621                            "(port=%d queue=%d) value=0x%"PRIx64"\n",
2622                            desc_to_clean_to,
2623                            txq->port_id, txq->queue_id,
2624                            txd[desc_to_clean_to].cmd_type_offset_bsz);
2625                 /* Failed to clean any descriptors */
2626                 return -1;
2627         }
2628
2629         /* Figure out how many descriptors will be cleaned */
2630         if (last_desc_cleaned > desc_to_clean_to)
2631                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2632                                             desc_to_clean_to);
2633         else
2634                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2635                                             last_desc_cleaned);
2636
2637         /* The last descriptor to clean is done, so that means all the
2638          * descriptors from the last descriptor that was cleaned
2639          * up to the last descriptor with the RS bit set
2640          * are done. Only reset the threshold descriptor.
2641          */
2642         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2643
2644         /* Update the txq to reflect the last descriptor that was cleaned */
2645         txq->last_desc_cleaned = desc_to_clean_to;
2646         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2647
2648         return 0;
2649 }
2650
2651 /* Construct the tx flags */
2652 static inline uint64_t
2653 ice_build_ctob(uint32_t td_cmd,
2654                uint32_t td_offset,
2655                uint16_t size,
2656                uint32_t td_tag)
2657 {
2658         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2659                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2660                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2661                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2662                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2663 }
2664
2665 /* Check if the context descriptor is needed for TX offloading */
2666 static inline uint16_t
2667 ice_calc_context_desc(uint64_t flags)
2668 {
2669         static uint64_t mask = RTE_MBUF_F_TX_TCP_SEG |
2670                 RTE_MBUF_F_TX_QINQ |
2671                 RTE_MBUF_F_TX_OUTER_IP_CKSUM |
2672                 RTE_MBUF_F_TX_TUNNEL_MASK |
2673                 RTE_MBUF_F_TX_IEEE1588_TMST;
2674
2675         return (flags & mask) ? 1 : 0;
2676 }
2677
2678 /* set ice TSO context descriptor */
2679 static inline uint64_t
2680 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2681 {
2682         uint64_t ctx_desc = 0;
2683         uint32_t cd_cmd, hdr_len, cd_tso_len;
2684
2685         if (!tx_offload.l4_len) {
2686                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2687                 return ctx_desc;
2688         }
2689
2690         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2691         hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
2692                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2693
2694         cd_cmd = ICE_TX_CTX_DESC_TSO;
2695         cd_tso_len = mbuf->pkt_len - hdr_len;
2696         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2697                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2698                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2699
2700         return ctx_desc;
2701 }
2702
2703 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2704 #define ICE_MAX_DATA_PER_TXD \
2705         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2706 /* Calculate the number of TX descriptors needed for each pkt */
2707 static inline uint16_t
2708 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2709 {
2710         struct rte_mbuf *txd = tx_pkt;
2711         uint16_t count = 0;
2712
2713         while (txd != NULL) {
2714                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2715                 txd = txd->next;
2716         }
2717
2718         return count;
2719 }
2720
2721 uint16_t
2722 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2723 {
2724         struct ice_tx_queue *txq;
2725         volatile struct ice_tx_desc *tx_ring;
2726         volatile struct ice_tx_desc *txd;
2727         struct ice_tx_entry *sw_ring;
2728         struct ice_tx_entry *txe, *txn;
2729         struct rte_mbuf *tx_pkt;
2730         struct rte_mbuf *m_seg;
2731         uint32_t cd_tunneling_params;
2732         uint16_t tx_id;
2733         uint16_t nb_tx;
2734         uint16_t nb_used;
2735         uint16_t nb_ctx;
2736         uint32_t td_cmd = 0;
2737         uint32_t td_offset = 0;
2738         uint32_t td_tag = 0;
2739         uint16_t tx_last;
2740         uint16_t slen;
2741         uint64_t buf_dma_addr;
2742         uint64_t ol_flags;
2743         union ice_tx_offload tx_offload = {0};
2744
2745         txq = tx_queue;
2746         sw_ring = txq->sw_ring;
2747         tx_ring = txq->tx_ring;
2748         tx_id = txq->tx_tail;
2749         txe = &sw_ring[tx_id];
2750
2751         /* Check if the descriptor ring needs to be cleaned. */
2752         if (txq->nb_tx_free < txq->tx_free_thresh)
2753                 (void)ice_xmit_cleanup(txq);
2754
2755         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2756                 tx_pkt = *tx_pkts++;
2757
2758                 td_cmd = 0;
2759                 td_tag = 0;
2760                 td_offset = 0;
2761                 ol_flags = tx_pkt->ol_flags;
2762                 tx_offload.l2_len = tx_pkt->l2_len;
2763                 tx_offload.l3_len = tx_pkt->l3_len;
2764                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2765                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2766                 tx_offload.l4_len = tx_pkt->l4_len;
2767                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2768                 /* Calculate the number of context descriptors needed. */
2769                 nb_ctx = ice_calc_context_desc(ol_flags);
2770
2771                 /* The number of descriptors that must be allocated for
2772                  * a packet equals to the number of the segments of that
2773                  * packet plus the number of context descriptor if needed.
2774                  * Recalculate the needed tx descs when TSO enabled in case
2775                  * the mbuf data size exceeds max data size that hw allows
2776                  * per tx desc.
2777                  */
2778                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2779                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2780                                              nb_ctx);
2781                 else
2782                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2783                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2784
2785                 /* Circular ring */
2786                 if (tx_last >= txq->nb_tx_desc)
2787                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2788
2789                 if (nb_used > txq->nb_tx_free) {
2790                         if (ice_xmit_cleanup(txq) != 0) {
2791                                 if (nb_tx == 0)
2792                                         return 0;
2793                                 goto end_of_tx;
2794                         }
2795                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2796                                 while (nb_used > txq->nb_tx_free) {
2797                                         if (ice_xmit_cleanup(txq) != 0) {
2798                                                 if (nb_tx == 0)
2799                                                         return 0;
2800                                                 goto end_of_tx;
2801                                         }
2802                                 }
2803                         }
2804                 }
2805
2806                 /* Descriptor based VLAN insertion */
2807                 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
2808                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2809                         td_tag = tx_pkt->vlan_tci;
2810                 }
2811
2812                 /* Fill in tunneling parameters if necessary */
2813                 cd_tunneling_params = 0;
2814                 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2815                         ice_parse_tunneling_params(ol_flags, tx_offload,
2816                                                    &cd_tunneling_params);
2817
2818                 /* Enable checksum offloading */
2819                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2820                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2821                                                 &td_offset, tx_offload);
2822
2823                 if (nb_ctx) {
2824                         /* Setup TX context descriptor if required */
2825                         volatile struct ice_tx_ctx_desc *ctx_txd =
2826                                 (volatile struct ice_tx_ctx_desc *)
2827                                         &tx_ring[tx_id];
2828                         uint16_t cd_l2tag2 = 0;
2829                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2830
2831                         txn = &sw_ring[txe->next_id];
2832                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2833                         if (txe->mbuf) {
2834                                 rte_pktmbuf_free_seg(txe->mbuf);
2835                                 txe->mbuf = NULL;
2836                         }
2837
2838                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2839                                 cd_type_cmd_tso_mss |=
2840                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2841                         else if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
2842                                 cd_type_cmd_tso_mss |=
2843                                         ((uint64_t)ICE_TX_CTX_DESC_TSYN <<
2844                                         ICE_TXD_CTX_QW1_CMD_S);
2845
2846                         ctx_txd->tunneling_params =
2847                                 rte_cpu_to_le_32(cd_tunneling_params);
2848
2849                         /* TX context descriptor based double VLAN insert */
2850                         if (ol_flags & RTE_MBUF_F_TX_QINQ) {
2851                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2852                                 cd_type_cmd_tso_mss |=
2853                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2854                                          ICE_TXD_CTX_QW1_CMD_S);
2855                         }
2856                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2857                         ctx_txd->qw1 =
2858                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2859
2860                         txe->last_id = tx_last;
2861                         tx_id = txe->next_id;
2862                         txe = txn;
2863                 }
2864                 m_seg = tx_pkt;
2865
2866                 do {
2867                         txd = &tx_ring[tx_id];
2868                         txn = &sw_ring[txe->next_id];
2869
2870                         if (txe->mbuf)
2871                                 rte_pktmbuf_free_seg(txe->mbuf);
2872                         txe->mbuf = m_seg;
2873
2874                         /* Setup TX Descriptor */
2875                         slen = m_seg->data_len;
2876                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2877
2878                         while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
2879                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2880                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2881                                 txd->cmd_type_offset_bsz =
2882                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2883                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2884                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2885                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2886                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2887                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2888
2889                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2890                                 slen -= ICE_MAX_DATA_PER_TXD;
2891
2892                                 txe->last_id = tx_last;
2893                                 tx_id = txe->next_id;
2894                                 txe = txn;
2895                                 txd = &tx_ring[tx_id];
2896                                 txn = &sw_ring[txe->next_id];
2897                         }
2898
2899                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2900                         txd->cmd_type_offset_bsz =
2901                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2902                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2903                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2904                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2905                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2906
2907                         txe->last_id = tx_last;
2908                         tx_id = txe->next_id;
2909                         txe = txn;
2910                         m_seg = m_seg->next;
2911                 } while (m_seg);
2912
2913                 /* fill the last descriptor with End of Packet (EOP) bit */
2914                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2915                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2916                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2917
2918                 /* set RS bit on the last descriptor of one packet */
2919                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2920                         PMD_TX_LOG(DEBUG,
2921                                    "Setting RS bit on TXD id="
2922                                    "%4u (port=%d queue=%d)",
2923                                    tx_last, txq->port_id, txq->queue_id);
2924
2925                         td_cmd |= ICE_TX_DESC_CMD_RS;
2926
2927                         /* Update txq RS bit counters */
2928                         txq->nb_tx_used = 0;
2929                 }
2930                 txd->cmd_type_offset_bsz |=
2931                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2932                                          ICE_TXD_QW1_CMD_S);
2933         }
2934 end_of_tx:
2935         /* update Tail register */
2936         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2937         txq->tx_tail = tx_id;
2938
2939         return nb_tx;
2940 }
2941
2942 static __rte_always_inline int
2943 ice_tx_free_bufs(struct ice_tx_queue *txq)
2944 {
2945         struct ice_tx_entry *txep;
2946         uint16_t i;
2947
2948         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2949              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2950             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2951                 return 0;
2952
2953         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2954
2955         for (i = 0; i < txq->tx_rs_thresh; i++)
2956                 rte_prefetch0((txep + i)->mbuf);
2957
2958         if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
2959                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2960                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2961                         txep->mbuf = NULL;
2962                 }
2963         } else {
2964                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2965                         rte_pktmbuf_free_seg(txep->mbuf);
2966                         txep->mbuf = NULL;
2967                 }
2968         }
2969
2970         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2971         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2972         if (txq->tx_next_dd >= txq->nb_tx_desc)
2973                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2974
2975         return txq->tx_rs_thresh;
2976 }
2977
2978 static int
2979 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2980                         uint32_t free_cnt)
2981 {
2982         struct ice_tx_entry *swr_ring = txq->sw_ring;
2983         uint16_t i, tx_last, tx_id;
2984         uint16_t nb_tx_free_last;
2985         uint16_t nb_tx_to_clean;
2986         uint32_t pkt_cnt;
2987
2988         /* Start free mbuf from the next of tx_tail */
2989         tx_last = txq->tx_tail;
2990         tx_id  = swr_ring[tx_last].next_id;
2991
2992         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2993                 return 0;
2994
2995         nb_tx_to_clean = txq->nb_tx_free;
2996         nb_tx_free_last = txq->nb_tx_free;
2997         if (!free_cnt)
2998                 free_cnt = txq->nb_tx_desc;
2999
3000         /* Loop through swr_ring to count the amount of
3001          * freeable mubfs and packets.
3002          */
3003         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
3004                 for (i = 0; i < nb_tx_to_clean &&
3005                         pkt_cnt < free_cnt &&
3006                         tx_id != tx_last; i++) {
3007                         if (swr_ring[tx_id].mbuf != NULL) {
3008                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
3009                                 swr_ring[tx_id].mbuf = NULL;
3010
3011                                 /*
3012                                  * last segment in the packet,
3013                                  * increment packet count
3014                                  */
3015                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
3016                         }
3017
3018                         tx_id = swr_ring[tx_id].next_id;
3019                 }
3020
3021                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
3022                         txq->nb_tx_free || tx_id == tx_last)
3023                         break;
3024
3025                 if (pkt_cnt < free_cnt) {
3026                         if (ice_xmit_cleanup(txq))
3027                                 break;
3028
3029                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
3030                         nb_tx_free_last = txq->nb_tx_free;
3031                 }
3032         }
3033
3034         return (int)pkt_cnt;
3035 }
3036
3037 #ifdef RTE_ARCH_X86
3038 static int
3039 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
3040                         uint32_t free_cnt __rte_unused)
3041 {
3042         return -ENOTSUP;
3043 }
3044 #endif
3045
3046 static int
3047 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
3048                         uint32_t free_cnt)
3049 {
3050         int i, n, cnt;
3051
3052         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
3053                 free_cnt = txq->nb_tx_desc;
3054
3055         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
3056
3057         for (i = 0; i < cnt; i += n) {
3058                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
3059                         break;
3060
3061                 n = ice_tx_free_bufs(txq);
3062
3063                 if (n == 0)
3064                         break;
3065         }
3066
3067         return i;
3068 }
3069
3070 int
3071 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
3072 {
3073         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
3074         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
3075         struct ice_adapter *ad =
3076                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3077
3078 #ifdef RTE_ARCH_X86
3079         if (ad->tx_vec_allowed)
3080                 return ice_tx_done_cleanup_vec(q, free_cnt);
3081 #endif
3082         if (ad->tx_simple_allowed)
3083                 return ice_tx_done_cleanup_simple(q, free_cnt);
3084         else
3085                 return ice_tx_done_cleanup_full(q, free_cnt);
3086 }
3087
3088 /* Populate 4 descriptors with data from 4 mbufs */
3089 static inline void
3090 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3091 {
3092         uint64_t dma_addr;
3093         uint32_t i;
3094
3095         for (i = 0; i < 4; i++, txdp++, pkts++) {
3096                 dma_addr = rte_mbuf_data_iova(*pkts);
3097                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3098                 txdp->cmd_type_offset_bsz =
3099                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3100                                        (*pkts)->data_len, 0);
3101         }
3102 }
3103
3104 /* Populate 1 descriptor with data from 1 mbuf */
3105 static inline void
3106 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3107 {
3108         uint64_t dma_addr;
3109
3110         dma_addr = rte_mbuf_data_iova(*pkts);
3111         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3112         txdp->cmd_type_offset_bsz =
3113                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3114                                (*pkts)->data_len, 0);
3115 }
3116
3117 static inline void
3118 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
3119                     uint16_t nb_pkts)
3120 {
3121         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
3122         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
3123         const int N_PER_LOOP = 4;
3124         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
3125         int mainpart, leftover;
3126         int i, j;
3127
3128         /**
3129          * Process most of the packets in chunks of N pkts.  Any
3130          * leftover packets will get processed one at a time.
3131          */
3132         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
3133         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
3134         for (i = 0; i < mainpart; i += N_PER_LOOP) {
3135                 /* Copy N mbuf pointers to the S/W ring */
3136                 for (j = 0; j < N_PER_LOOP; ++j)
3137                         (txep + i + j)->mbuf = *(pkts + i + j);
3138                 tx4(txdp + i, pkts + i);
3139         }
3140
3141         if (unlikely(leftover > 0)) {
3142                 for (i = 0; i < leftover; ++i) {
3143                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
3144                         tx1(txdp + mainpart + i, pkts + mainpart + i);
3145                 }
3146         }
3147 }
3148
3149 static inline uint16_t
3150 tx_xmit_pkts(struct ice_tx_queue *txq,
3151              struct rte_mbuf **tx_pkts,
3152              uint16_t nb_pkts)
3153 {
3154         volatile struct ice_tx_desc *txr = txq->tx_ring;
3155         uint16_t n = 0;
3156
3157         /**
3158          * Begin scanning the H/W ring for done descriptors when the number
3159          * of available descriptors drops below tx_free_thresh. For each done
3160          * descriptor, free the associated buffer.
3161          */
3162         if (txq->nb_tx_free < txq->tx_free_thresh)
3163                 ice_tx_free_bufs(txq);
3164
3165         /* Use available descriptor only */
3166         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
3167         if (unlikely(!nb_pkts))
3168                 return 0;
3169
3170         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
3171         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
3172                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
3173                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
3174                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3175                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3176                                          ICE_TXD_QW1_CMD_S);
3177                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3178                 txq->tx_tail = 0;
3179         }
3180
3181         /* Fill hardware descriptor ring with mbuf data */
3182         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3183         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3184
3185         /* Determine if RS bit needs to be set */
3186         if (txq->tx_tail > txq->tx_next_rs) {
3187                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3188                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3189                                          ICE_TXD_QW1_CMD_S);
3190                 txq->tx_next_rs =
3191                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3192                 if (txq->tx_next_rs >= txq->nb_tx_desc)
3193                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3194         }
3195
3196         if (txq->tx_tail >= txq->nb_tx_desc)
3197                 txq->tx_tail = 0;
3198
3199         /* Update the tx tail register */
3200         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3201
3202         return nb_pkts;
3203 }
3204
3205 static uint16_t
3206 ice_xmit_pkts_simple(void *tx_queue,
3207                      struct rte_mbuf **tx_pkts,
3208                      uint16_t nb_pkts)
3209 {
3210         uint16_t nb_tx = 0;
3211
3212         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3213                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3214                                     tx_pkts, nb_pkts);
3215
3216         while (nb_pkts) {
3217                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3218                                                       ICE_TX_MAX_BURST);
3219
3220                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3221                                    &tx_pkts[nb_tx], num);
3222                 nb_tx = (uint16_t)(nb_tx + ret);
3223                 nb_pkts = (uint16_t)(nb_pkts - ret);
3224                 if (ret < num)
3225                         break;
3226         }
3227
3228         return nb_tx;
3229 }
3230
3231 void __rte_cold
3232 ice_set_rx_function(struct rte_eth_dev *dev)
3233 {
3234         PMD_INIT_FUNC_TRACE();
3235         struct ice_adapter *ad =
3236                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3237 #ifdef RTE_ARCH_X86
3238         struct ice_rx_queue *rxq;
3239         int i;
3240         int rx_check_ret = -1;
3241
3242         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3243                 ad->rx_use_avx512 = false;
3244                 ad->rx_use_avx2 = false;
3245                 rx_check_ret = ice_rx_vec_dev_check(dev);
3246                 if (ad->ptp_ena)
3247                         rx_check_ret = -1;
3248                 ad->rx_vec_offload_support =
3249                                 (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH);
3250                 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3251                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3252                         ad->rx_vec_allowed = true;
3253                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3254                                 rxq = dev->data->rx_queues[i];
3255                                 if (rxq && ice_rxq_vec_setup(rxq)) {
3256                                         ad->rx_vec_allowed = false;
3257                                         break;
3258                                 }
3259                         }
3260
3261                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3262                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3263                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3264 #ifdef CC_AVX512_SUPPORT
3265                                 ad->rx_use_avx512 = true;
3266 #else
3267                         PMD_DRV_LOG(NOTICE,
3268                                 "AVX512 is not supported in build env");
3269 #endif
3270                         if (!ad->rx_use_avx512 &&
3271                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3272                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3273                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3274                                 ad->rx_use_avx2 = true;
3275
3276                 } else {
3277                         ad->rx_vec_allowed = false;
3278                 }
3279         }
3280
3281         if (ad->rx_vec_allowed) {
3282                 if (dev->data->scattered_rx) {
3283                         if (ad->rx_use_avx512) {
3284 #ifdef CC_AVX512_SUPPORT
3285                                 if (ad->rx_vec_offload_support) {
3286                                         PMD_DRV_LOG(NOTICE,
3287                                                 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3288                                                 dev->data->port_id);
3289                                         dev->rx_pkt_burst =
3290                                                 ice_recv_scattered_pkts_vec_avx512_offload;
3291                                 } else {
3292                                         PMD_DRV_LOG(NOTICE,
3293                                                 "Using AVX512 Vector Scattered Rx (port %d).",
3294                                                 dev->data->port_id);
3295                                         dev->rx_pkt_burst =
3296                                                 ice_recv_scattered_pkts_vec_avx512;
3297                                 }
3298 #endif
3299                         } else if (ad->rx_use_avx2) {
3300                                 if (ad->rx_vec_offload_support) {
3301                                         PMD_DRV_LOG(NOTICE,
3302                                                     "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3303                                                     dev->data->port_id);
3304                                         dev->rx_pkt_burst =
3305                                                 ice_recv_scattered_pkts_vec_avx2_offload;
3306                                 } else {
3307                                         PMD_DRV_LOG(NOTICE,
3308                                                     "Using AVX2 Vector Scattered Rx (port %d).",
3309                                                     dev->data->port_id);
3310                                         dev->rx_pkt_burst =
3311                                                 ice_recv_scattered_pkts_vec_avx2;
3312                                 }
3313                         } else {
3314                                 PMD_DRV_LOG(DEBUG,
3315                                         "Using Vector Scattered Rx (port %d).",
3316                                         dev->data->port_id);
3317                                 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3318                         }
3319                 } else {
3320                         if (ad->rx_use_avx512) {
3321 #ifdef CC_AVX512_SUPPORT
3322                                 if (ad->rx_vec_offload_support) {
3323                                         PMD_DRV_LOG(NOTICE,
3324                                                 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3325                                                 dev->data->port_id);
3326                                         dev->rx_pkt_burst =
3327                                                 ice_recv_pkts_vec_avx512_offload;
3328                                 } else {
3329                                         PMD_DRV_LOG(NOTICE,
3330                                                 "Using AVX512 Vector Rx (port %d).",
3331                                                 dev->data->port_id);
3332                                         dev->rx_pkt_burst =
3333                                                 ice_recv_pkts_vec_avx512;
3334                                 }
3335 #endif
3336                         } else if (ad->rx_use_avx2) {
3337                                 if (ad->rx_vec_offload_support) {
3338                                         PMD_DRV_LOG(NOTICE,
3339                                                     "Using AVX2 OFFLOAD Vector Rx (port %d).",
3340                                                     dev->data->port_id);
3341                                         dev->rx_pkt_burst =
3342                                                 ice_recv_pkts_vec_avx2_offload;
3343                                 } else {
3344                                         PMD_DRV_LOG(NOTICE,
3345                                                     "Using AVX2 Vector Rx (port %d).",
3346                                                     dev->data->port_id);
3347                                         dev->rx_pkt_burst =
3348                                                 ice_recv_pkts_vec_avx2;
3349                                 }
3350                         } else {
3351                                 PMD_DRV_LOG(DEBUG,
3352                                         "Using Vector Rx (port %d).",
3353                                         dev->data->port_id);
3354                                 dev->rx_pkt_burst = ice_recv_pkts_vec;
3355                         }
3356                 }
3357                 return;
3358         }
3359
3360 #endif
3361
3362         if (dev->data->scattered_rx) {
3363                 /* Set the non-LRO scattered function */
3364                 PMD_INIT_LOG(DEBUG,
3365                              "Using a Scattered function on port %d.",
3366                              dev->data->port_id);
3367                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3368         } else if (ad->rx_bulk_alloc_allowed) {
3369                 PMD_INIT_LOG(DEBUG,
3370                              "Rx Burst Bulk Alloc Preconditions are "
3371                              "satisfied. Rx Burst Bulk Alloc function "
3372                              "will be used on port %d.",
3373                              dev->data->port_id);
3374                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3375         } else {
3376                 PMD_INIT_LOG(DEBUG,
3377                              "Rx Burst Bulk Alloc Preconditions are not "
3378                              "satisfied, Normal Rx will be used on port %d.",
3379                              dev->data->port_id);
3380                 dev->rx_pkt_burst = ice_recv_pkts;
3381         }
3382 }
3383
3384 static const struct {
3385         eth_rx_burst_t pkt_burst;
3386         const char *info;
3387 } ice_rx_burst_infos[] = {
3388         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3389         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3390         { ice_recv_pkts,                    "Scalar" },
3391 #ifdef RTE_ARCH_X86
3392 #ifdef CC_AVX512_SUPPORT
3393         { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3394         { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3395         { ice_recv_pkts_vec_avx512,           "Vector AVX512" },
3396         { ice_recv_pkts_vec_avx512_offload,   "Offload Vector AVX512" },
3397 #endif
3398         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3399         { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3400         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3401         { ice_recv_pkts_vec_avx2_offload,   "Offload Vector AVX2" },
3402         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3403         { ice_recv_pkts_vec,                "Vector SSE" },
3404 #endif
3405 };
3406
3407 int
3408 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3409                       struct rte_eth_burst_mode *mode)
3410 {
3411         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3412         int ret = -EINVAL;
3413         unsigned int i;
3414
3415         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3416                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3417                         snprintf(mode->info, sizeof(mode->info), "%s",
3418                                  ice_rx_burst_infos[i].info);
3419                         ret = 0;
3420                         break;
3421                 }
3422         }
3423
3424         return ret;
3425 }
3426
3427 void __rte_cold
3428 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3429 {
3430         struct ice_adapter *ad =
3431                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3432
3433         /* Use a simple Tx queue if possible (only fast free is allowed) */
3434         ad->tx_simple_allowed =
3435                 (txq->offloads ==
3436                 (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3437                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3438
3439         if (ad->tx_simple_allowed)
3440                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3441                              txq->queue_id);
3442         else
3443                 PMD_INIT_LOG(DEBUG,
3444                              "Simple Tx can NOT be enabled on Tx queue %u.",
3445                              txq->queue_id);
3446 }
3447
3448 /*********************************************************************
3449  *
3450  *  TX prep functions
3451  *
3452  **********************************************************************/
3453 /* The default values of TSO MSS */
3454 #define ICE_MIN_TSO_MSS            64
3455 #define ICE_MAX_TSO_MSS            9728
3456 #define ICE_MAX_TSO_FRAME_SIZE     262144
3457 uint16_t
3458 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3459               uint16_t nb_pkts)
3460 {
3461         int i, ret;
3462         uint64_t ol_flags;
3463         struct rte_mbuf *m;
3464
3465         for (i = 0; i < nb_pkts; i++) {
3466                 m = tx_pkts[i];
3467                 ol_flags = m->ol_flags;
3468
3469                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
3470                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3471                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3472                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3473                         /**
3474                          * MSS outside the range are considered malicious
3475                          */
3476                         rte_errno = EINVAL;
3477                         return i;
3478                 }
3479
3480 #ifdef RTE_ETHDEV_DEBUG_TX
3481                 ret = rte_validate_tx_offload(m);
3482                 if (ret != 0) {
3483                         rte_errno = -ret;
3484                         return i;
3485                 }
3486 #endif
3487                 ret = rte_net_intel_cksum_prepare(m);
3488                 if (ret != 0) {
3489                         rte_errno = -ret;
3490                         return i;
3491                 }
3492         }
3493         return i;
3494 }
3495
3496 void __rte_cold
3497 ice_set_tx_function(struct rte_eth_dev *dev)
3498 {
3499         struct ice_adapter *ad =
3500                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3501 #ifdef RTE_ARCH_X86
3502         struct ice_tx_queue *txq;
3503         int i;
3504         int tx_check_ret = -1;
3505
3506         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3507                 ad->tx_use_avx2 = false;
3508                 ad->tx_use_avx512 = false;
3509                 tx_check_ret = ice_tx_vec_dev_check(dev);
3510                 if (tx_check_ret >= 0 &&
3511                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3512                         ad->tx_vec_allowed = true;
3513
3514                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3515                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3516                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3517 #ifdef CC_AVX512_SUPPORT
3518                                 ad->tx_use_avx512 = true;
3519 #else
3520                         PMD_DRV_LOG(NOTICE,
3521                                 "AVX512 is not supported in build env");
3522 #endif
3523                         if (!ad->tx_use_avx512 &&
3524                                 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3525                                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3526                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3527                                 ad->tx_use_avx2 = true;
3528
3529                         if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3530                                 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3531                                 ad->tx_vec_allowed = false;
3532
3533                         if (ad->tx_vec_allowed) {
3534                                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3535                                         txq = dev->data->tx_queues[i];
3536                                         if (txq && ice_txq_vec_setup(txq)) {
3537                                                 ad->tx_vec_allowed = false;
3538                                                 break;
3539                                         }
3540                                 }
3541                         }
3542                 } else {
3543                         ad->tx_vec_allowed = false;
3544                 }
3545         }
3546
3547         if (ad->tx_vec_allowed) {
3548                 dev->tx_pkt_prepare = NULL;
3549                 if (ad->tx_use_avx512) {
3550 #ifdef CC_AVX512_SUPPORT
3551                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3552                                 PMD_DRV_LOG(NOTICE,
3553                                             "Using AVX512 OFFLOAD Vector Tx (port %d).",
3554                                             dev->data->port_id);
3555                                 dev->tx_pkt_burst =
3556                                         ice_xmit_pkts_vec_avx512_offload;
3557                                 dev->tx_pkt_prepare = ice_prep_pkts;
3558                         } else {
3559                                 PMD_DRV_LOG(NOTICE,
3560                                             "Using AVX512 Vector Tx (port %d).",
3561                                             dev->data->port_id);
3562                                 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3563                         }
3564 #endif
3565                 } else {
3566                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3567                                 PMD_DRV_LOG(NOTICE,
3568                                             "Using AVX2 OFFLOAD Vector Tx (port %d).",
3569                                             dev->data->port_id);
3570                                 dev->tx_pkt_burst =
3571                                         ice_xmit_pkts_vec_avx2_offload;
3572                                 dev->tx_pkt_prepare = ice_prep_pkts;
3573                         } else {
3574                                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3575                                             ad->tx_use_avx2 ? "avx2 " : "",
3576                                             dev->data->port_id);
3577                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3578                                                     ice_xmit_pkts_vec_avx2 :
3579                                                     ice_xmit_pkts_vec;
3580                         }
3581                 }
3582
3583                 return;
3584         }
3585 #endif
3586
3587         if (ad->tx_simple_allowed) {
3588                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3589                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3590                 dev->tx_pkt_prepare = NULL;
3591         } else {
3592                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3593                 dev->tx_pkt_burst = ice_xmit_pkts;
3594                 dev->tx_pkt_prepare = ice_prep_pkts;
3595         }
3596 }
3597
3598 static const struct {
3599         eth_tx_burst_t pkt_burst;
3600         const char *info;
3601 } ice_tx_burst_infos[] = {
3602         { ice_xmit_pkts_simple,   "Scalar Simple" },
3603         { ice_xmit_pkts,          "Scalar" },
3604 #ifdef RTE_ARCH_X86
3605 #ifdef CC_AVX512_SUPPORT
3606         { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3607         { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3608 #endif
3609         { ice_xmit_pkts_vec_avx2,         "Vector AVX2" },
3610         { ice_xmit_pkts_vec_avx2_offload, "Offload Vector AVX2" },
3611         { ice_xmit_pkts_vec,              "Vector SSE" },
3612 #endif
3613 };
3614
3615 int
3616 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3617                       struct rte_eth_burst_mode *mode)
3618 {
3619         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3620         int ret = -EINVAL;
3621         unsigned int i;
3622
3623         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3624                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3625                         snprintf(mode->info, sizeof(mode->info), "%s",
3626                                  ice_tx_burst_infos[i].info);
3627                         ret = 0;
3628                         break;
3629                 }
3630         }
3631
3632         return ret;
3633 }
3634
3635 /* For each value it means, datasheet of hardware can tell more details
3636  *
3637  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3638  */
3639 static inline uint32_t
3640 ice_get_default_pkt_type(uint16_t ptype)
3641 {
3642         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3643                 __rte_cache_aligned = {
3644                 /* L2 types */
3645                 /* [0] reserved */
3646                 [1] = RTE_PTYPE_L2_ETHER,
3647                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3648                 /* [3] - [5] reserved */
3649                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3650                 /* [7] - [10] reserved */
3651                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3652                 /* [12] - [21] reserved */
3653
3654                 /* Non tunneled IPv4 */
3655                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3656                        RTE_PTYPE_L4_FRAG,
3657                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3658                        RTE_PTYPE_L4_NONFRAG,
3659                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3660                        RTE_PTYPE_L4_UDP,
3661                 /* [25] reserved */
3662                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3663                        RTE_PTYPE_L4_TCP,
3664                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3665                        RTE_PTYPE_L4_SCTP,
3666                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3667                        RTE_PTYPE_L4_ICMP,
3668
3669                 /* IPv4 --> IPv4 */
3670                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3671                        RTE_PTYPE_TUNNEL_IP |
3672                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3673                        RTE_PTYPE_INNER_L4_FRAG,
3674                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3675                        RTE_PTYPE_TUNNEL_IP |
3676                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3677                        RTE_PTYPE_INNER_L4_NONFRAG,
3678                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3679                        RTE_PTYPE_TUNNEL_IP |
3680                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3681                        RTE_PTYPE_INNER_L4_UDP,
3682                 /* [32] reserved */
3683                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3684                        RTE_PTYPE_TUNNEL_IP |
3685                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3686                        RTE_PTYPE_INNER_L4_TCP,
3687                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3688                        RTE_PTYPE_TUNNEL_IP |
3689                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3690                        RTE_PTYPE_INNER_L4_SCTP,
3691                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3692                        RTE_PTYPE_TUNNEL_IP |
3693                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3694                        RTE_PTYPE_INNER_L4_ICMP,
3695
3696                 /* IPv4 --> IPv6 */
3697                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3698                        RTE_PTYPE_TUNNEL_IP |
3699                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3700                        RTE_PTYPE_INNER_L4_FRAG,
3701                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3702                        RTE_PTYPE_TUNNEL_IP |
3703                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3704                        RTE_PTYPE_INNER_L4_NONFRAG,
3705                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3706                        RTE_PTYPE_TUNNEL_IP |
3707                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3708                        RTE_PTYPE_INNER_L4_UDP,
3709                 /* [39] reserved */
3710                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3711                        RTE_PTYPE_TUNNEL_IP |
3712                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3713                        RTE_PTYPE_INNER_L4_TCP,
3714                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3715                        RTE_PTYPE_TUNNEL_IP |
3716                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3717                        RTE_PTYPE_INNER_L4_SCTP,
3718                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3719                        RTE_PTYPE_TUNNEL_IP |
3720                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3721                        RTE_PTYPE_INNER_L4_ICMP,
3722
3723                 /* IPv4 --> GRE/Teredo/VXLAN */
3724                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3725                        RTE_PTYPE_TUNNEL_GRENAT,
3726
3727                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3728                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3729                        RTE_PTYPE_TUNNEL_GRENAT |
3730                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3731                        RTE_PTYPE_INNER_L4_FRAG,
3732                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3733                        RTE_PTYPE_TUNNEL_GRENAT |
3734                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3735                        RTE_PTYPE_INNER_L4_NONFRAG,
3736                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3737                        RTE_PTYPE_TUNNEL_GRENAT |
3738                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3739                        RTE_PTYPE_INNER_L4_UDP,
3740                 /* [47] reserved */
3741                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3742                        RTE_PTYPE_TUNNEL_GRENAT |
3743                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3744                        RTE_PTYPE_INNER_L4_TCP,
3745                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3746                        RTE_PTYPE_TUNNEL_GRENAT |
3747                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3748                        RTE_PTYPE_INNER_L4_SCTP,
3749                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3750                        RTE_PTYPE_TUNNEL_GRENAT |
3751                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3752                        RTE_PTYPE_INNER_L4_ICMP,
3753
3754                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3755                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3756                        RTE_PTYPE_TUNNEL_GRENAT |
3757                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3758                        RTE_PTYPE_INNER_L4_FRAG,
3759                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3760                        RTE_PTYPE_TUNNEL_GRENAT |
3761                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3762                        RTE_PTYPE_INNER_L4_NONFRAG,
3763                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3764                        RTE_PTYPE_TUNNEL_GRENAT |
3765                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3766                        RTE_PTYPE_INNER_L4_UDP,
3767                 /* [54] reserved */
3768                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3769                        RTE_PTYPE_TUNNEL_GRENAT |
3770                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3771                        RTE_PTYPE_INNER_L4_TCP,
3772                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3773                        RTE_PTYPE_TUNNEL_GRENAT |
3774                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3775                        RTE_PTYPE_INNER_L4_SCTP,
3776                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3777                        RTE_PTYPE_TUNNEL_GRENAT |
3778                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3779                        RTE_PTYPE_INNER_L4_ICMP,
3780
3781                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3782                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3783                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3784
3785                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3786                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3787                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3788                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3789                        RTE_PTYPE_INNER_L4_FRAG,
3790                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3791                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3792                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3793                        RTE_PTYPE_INNER_L4_NONFRAG,
3794                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3795                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3796                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3797                        RTE_PTYPE_INNER_L4_UDP,
3798                 /* [62] reserved */
3799                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3800                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3801                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3802                        RTE_PTYPE_INNER_L4_TCP,
3803                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3804                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3805                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3806                        RTE_PTYPE_INNER_L4_SCTP,
3807                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3808                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3809                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3810                        RTE_PTYPE_INNER_L4_ICMP,
3811
3812                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3813                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3814                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3815                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3816                        RTE_PTYPE_INNER_L4_FRAG,
3817                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3818                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3819                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3820                        RTE_PTYPE_INNER_L4_NONFRAG,
3821                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3822                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3823                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3824                        RTE_PTYPE_INNER_L4_UDP,
3825                 /* [69] reserved */
3826                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3827                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3828                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3829                        RTE_PTYPE_INNER_L4_TCP,
3830                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3831                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3832                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3833                        RTE_PTYPE_INNER_L4_SCTP,
3834                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3835                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3836                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3837                        RTE_PTYPE_INNER_L4_ICMP,
3838                 /* [73] - [87] reserved */
3839
3840                 /* Non tunneled IPv6 */
3841                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3842                        RTE_PTYPE_L4_FRAG,
3843                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3844                        RTE_PTYPE_L4_NONFRAG,
3845                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3846                        RTE_PTYPE_L4_UDP,
3847                 /* [91] reserved */
3848                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3849                        RTE_PTYPE_L4_TCP,
3850                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3851                        RTE_PTYPE_L4_SCTP,
3852                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3853                        RTE_PTYPE_L4_ICMP,
3854
3855                 /* IPv6 --> IPv4 */
3856                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3857                        RTE_PTYPE_TUNNEL_IP |
3858                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3859                        RTE_PTYPE_INNER_L4_FRAG,
3860                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3861                        RTE_PTYPE_TUNNEL_IP |
3862                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3863                        RTE_PTYPE_INNER_L4_NONFRAG,
3864                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3865                        RTE_PTYPE_TUNNEL_IP |
3866                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3867                        RTE_PTYPE_INNER_L4_UDP,
3868                 /* [98] reserved */
3869                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3870                        RTE_PTYPE_TUNNEL_IP |
3871                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3872                        RTE_PTYPE_INNER_L4_TCP,
3873                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3874                         RTE_PTYPE_TUNNEL_IP |
3875                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3876                         RTE_PTYPE_INNER_L4_SCTP,
3877                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3878                         RTE_PTYPE_TUNNEL_IP |
3879                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3880                         RTE_PTYPE_INNER_L4_ICMP,
3881
3882                 /* IPv6 --> IPv6 */
3883                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3884                         RTE_PTYPE_TUNNEL_IP |
3885                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3886                         RTE_PTYPE_INNER_L4_FRAG,
3887                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3888                         RTE_PTYPE_TUNNEL_IP |
3889                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3890                         RTE_PTYPE_INNER_L4_NONFRAG,
3891                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3892                         RTE_PTYPE_TUNNEL_IP |
3893                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3894                         RTE_PTYPE_INNER_L4_UDP,
3895                 /* [105] reserved */
3896                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3897                         RTE_PTYPE_TUNNEL_IP |
3898                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3899                         RTE_PTYPE_INNER_L4_TCP,
3900                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3901                         RTE_PTYPE_TUNNEL_IP |
3902                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3903                         RTE_PTYPE_INNER_L4_SCTP,
3904                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3905                         RTE_PTYPE_TUNNEL_IP |
3906                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3907                         RTE_PTYPE_INNER_L4_ICMP,
3908
3909                 /* IPv6 --> GRE/Teredo/VXLAN */
3910                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3911                         RTE_PTYPE_TUNNEL_GRENAT,
3912
3913                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3914                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3915                         RTE_PTYPE_TUNNEL_GRENAT |
3916                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3917                         RTE_PTYPE_INNER_L4_FRAG,
3918                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3919                         RTE_PTYPE_TUNNEL_GRENAT |
3920                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3921                         RTE_PTYPE_INNER_L4_NONFRAG,
3922                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3923                         RTE_PTYPE_TUNNEL_GRENAT |
3924                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3925                         RTE_PTYPE_INNER_L4_UDP,
3926                 /* [113] reserved */
3927                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3928                         RTE_PTYPE_TUNNEL_GRENAT |
3929                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3930                         RTE_PTYPE_INNER_L4_TCP,
3931                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3932                         RTE_PTYPE_TUNNEL_GRENAT |
3933                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3934                         RTE_PTYPE_INNER_L4_SCTP,
3935                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3936                         RTE_PTYPE_TUNNEL_GRENAT |
3937                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3938                         RTE_PTYPE_INNER_L4_ICMP,
3939
3940                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3941                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3942                         RTE_PTYPE_TUNNEL_GRENAT |
3943                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3944                         RTE_PTYPE_INNER_L4_FRAG,
3945                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3946                         RTE_PTYPE_TUNNEL_GRENAT |
3947                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3948                         RTE_PTYPE_INNER_L4_NONFRAG,
3949                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3950                         RTE_PTYPE_TUNNEL_GRENAT |
3951                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3952                         RTE_PTYPE_INNER_L4_UDP,
3953                 /* [120] reserved */
3954                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3955                         RTE_PTYPE_TUNNEL_GRENAT |
3956                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3957                         RTE_PTYPE_INNER_L4_TCP,
3958                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3959                         RTE_PTYPE_TUNNEL_GRENAT |
3960                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3961                         RTE_PTYPE_INNER_L4_SCTP,
3962                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3963                         RTE_PTYPE_TUNNEL_GRENAT |
3964                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3965                         RTE_PTYPE_INNER_L4_ICMP,
3966
3967                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3968                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3969                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3970
3971                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3972                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3973                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3974                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3975                         RTE_PTYPE_INNER_L4_FRAG,
3976                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3977                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3978                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3979                         RTE_PTYPE_INNER_L4_NONFRAG,
3980                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3981                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3982                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3983                         RTE_PTYPE_INNER_L4_UDP,
3984                 /* [128] reserved */
3985                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3986                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3987                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3988                         RTE_PTYPE_INNER_L4_TCP,
3989                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3990                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3991                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3992                         RTE_PTYPE_INNER_L4_SCTP,
3993                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3994                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3995                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3996                         RTE_PTYPE_INNER_L4_ICMP,
3997
3998                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3999                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4000                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4001                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4002                         RTE_PTYPE_INNER_L4_FRAG,
4003                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4004                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4005                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4006                         RTE_PTYPE_INNER_L4_NONFRAG,
4007                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4008                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4009                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4010                         RTE_PTYPE_INNER_L4_UDP,
4011                 /* [135] reserved */
4012                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4013                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4014                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4015                         RTE_PTYPE_INNER_L4_TCP,
4016                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4017                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4018                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4019                         RTE_PTYPE_INNER_L4_SCTP,
4020                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4021                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4022                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4023                         RTE_PTYPE_INNER_L4_ICMP,
4024                 /* [139] - [299] reserved */
4025
4026                 /* PPPoE */
4027                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
4028                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
4029
4030                 /* PPPoE --> IPv4 */
4031                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
4032                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4033                         RTE_PTYPE_L4_FRAG,
4034                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
4035                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4036                         RTE_PTYPE_L4_NONFRAG,
4037                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
4038                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4039                         RTE_PTYPE_L4_UDP,
4040                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
4041                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4042                         RTE_PTYPE_L4_TCP,
4043                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
4044                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4045                         RTE_PTYPE_L4_SCTP,
4046                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
4047                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4048                         RTE_PTYPE_L4_ICMP,
4049
4050                 /* PPPoE --> IPv6 */
4051                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
4052                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4053                         RTE_PTYPE_L4_FRAG,
4054                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
4055                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4056                         RTE_PTYPE_L4_NONFRAG,
4057                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
4058                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4059                         RTE_PTYPE_L4_UDP,
4060                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
4061                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4062                         RTE_PTYPE_L4_TCP,
4063                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
4064                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4065                         RTE_PTYPE_L4_SCTP,
4066                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
4067                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4068                         RTE_PTYPE_L4_ICMP,
4069                 /* [314] - [324] reserved */
4070
4071                 /* IPv4/IPv6 --> GTPC/GTPU */
4072                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4073                         RTE_PTYPE_TUNNEL_GTPC,
4074                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4075                         RTE_PTYPE_TUNNEL_GTPC,
4076                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4077                         RTE_PTYPE_TUNNEL_GTPC,
4078                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4079                         RTE_PTYPE_TUNNEL_GTPC,
4080                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4081                         RTE_PTYPE_TUNNEL_GTPU,
4082                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4083                         RTE_PTYPE_TUNNEL_GTPU,
4084
4085                 /* IPv4 --> GTPU --> IPv4 */
4086                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4087                         RTE_PTYPE_TUNNEL_GTPU |
4088                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4089                         RTE_PTYPE_INNER_L4_FRAG,
4090                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4091                         RTE_PTYPE_TUNNEL_GTPU |
4092                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4093                         RTE_PTYPE_INNER_L4_NONFRAG,
4094                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4095                         RTE_PTYPE_TUNNEL_GTPU |
4096                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4097                         RTE_PTYPE_INNER_L4_UDP,
4098                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4099                         RTE_PTYPE_TUNNEL_GTPU |
4100                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4101                         RTE_PTYPE_INNER_L4_TCP,
4102                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4103                         RTE_PTYPE_TUNNEL_GTPU |
4104                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4105                         RTE_PTYPE_INNER_L4_ICMP,
4106
4107                 /* IPv6 --> GTPU --> IPv4 */
4108                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4109                         RTE_PTYPE_TUNNEL_GTPU |
4110                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4111                         RTE_PTYPE_INNER_L4_FRAG,
4112                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4113                         RTE_PTYPE_TUNNEL_GTPU |
4114                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4115                         RTE_PTYPE_INNER_L4_NONFRAG,
4116                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4117                         RTE_PTYPE_TUNNEL_GTPU |
4118                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4119                         RTE_PTYPE_INNER_L4_UDP,
4120                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4121                         RTE_PTYPE_TUNNEL_GTPU |
4122                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4123                         RTE_PTYPE_INNER_L4_TCP,
4124                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4125                         RTE_PTYPE_TUNNEL_GTPU |
4126                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4127                         RTE_PTYPE_INNER_L4_ICMP,
4128
4129                 /* IPv4 --> GTPU --> IPv6 */
4130                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4131                         RTE_PTYPE_TUNNEL_GTPU |
4132                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4133                         RTE_PTYPE_INNER_L4_FRAG,
4134                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4135                         RTE_PTYPE_TUNNEL_GTPU |
4136                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4137                         RTE_PTYPE_INNER_L4_NONFRAG,
4138                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4139                         RTE_PTYPE_TUNNEL_GTPU |
4140                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4141                         RTE_PTYPE_INNER_L4_UDP,
4142                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4143                         RTE_PTYPE_TUNNEL_GTPU |
4144                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4145                         RTE_PTYPE_INNER_L4_TCP,
4146                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4147                         RTE_PTYPE_TUNNEL_GTPU |
4148                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4149                         RTE_PTYPE_INNER_L4_ICMP,
4150
4151                 /* IPv6 --> GTPU --> IPv6 */
4152                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4153                         RTE_PTYPE_TUNNEL_GTPU |
4154                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4155                         RTE_PTYPE_INNER_L4_FRAG,
4156                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4157                         RTE_PTYPE_TUNNEL_GTPU |
4158                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4159                         RTE_PTYPE_INNER_L4_NONFRAG,
4160                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4161                         RTE_PTYPE_TUNNEL_GTPU |
4162                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4163                         RTE_PTYPE_INNER_L4_UDP,
4164                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4165                         RTE_PTYPE_TUNNEL_GTPU |
4166                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4167                         RTE_PTYPE_INNER_L4_TCP,
4168                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4169                         RTE_PTYPE_TUNNEL_GTPU |
4170                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4171                         RTE_PTYPE_INNER_L4_ICMP,
4172
4173                 /* IPv4 --> UDP ECPRI */
4174                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4175                         RTE_PTYPE_L4_UDP,
4176                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4177                         RTE_PTYPE_L4_UDP,
4178                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4179                         RTE_PTYPE_L4_UDP,
4180                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4181                         RTE_PTYPE_L4_UDP,
4182                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4183                         RTE_PTYPE_L4_UDP,
4184                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4185                         RTE_PTYPE_L4_UDP,
4186                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4187                         RTE_PTYPE_L4_UDP,
4188                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4189                         RTE_PTYPE_L4_UDP,
4190                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4191                         RTE_PTYPE_L4_UDP,
4192                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4193                         RTE_PTYPE_L4_UDP,
4194
4195                 /* IPV6 --> UDP ECPRI */
4196                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4197                         RTE_PTYPE_L4_UDP,
4198                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4199                         RTE_PTYPE_L4_UDP,
4200                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4201                         RTE_PTYPE_L4_UDP,
4202                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4203                         RTE_PTYPE_L4_UDP,
4204                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4205                         RTE_PTYPE_L4_UDP,
4206                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4207                         RTE_PTYPE_L4_UDP,
4208                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4209                         RTE_PTYPE_L4_UDP,
4210                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4211                         RTE_PTYPE_L4_UDP,
4212                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4213                         RTE_PTYPE_L4_UDP,
4214                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4215                         RTE_PTYPE_L4_UDP,
4216                 /* All others reserved */
4217         };
4218
4219         return type_table[ptype];
4220 }
4221
4222 void __rte_cold
4223 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4224 {
4225         struct ice_adapter *ad =
4226                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4227         int i;
4228
4229         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4230                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4231 }
4232
4233 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4234 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4235                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4236 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4237 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4238
4239 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
4240 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
4241         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4242 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
4243 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
4244         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4245
4246 /*
4247  * check the programming status descriptor in rx queue.
4248  * done after Programming Flow Director is programmed on
4249  * tx queue
4250  */
4251 static inline int
4252 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4253 {
4254         volatile union ice_32byte_rx_desc *rxdp;
4255         uint64_t qword1;
4256         uint32_t rx_status;
4257         uint32_t error;
4258         uint32_t id;
4259         int ret = -EAGAIN;
4260
4261         rxdp = (volatile union ice_32byte_rx_desc *)
4262                 (&rxq->rx_ring[rxq->rx_tail]);
4263         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4264         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4265                         >> ICE_RXD_QW1_STATUS_S;
4266
4267         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4268                 ret = 0;
4269                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4270                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4271                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4272                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4273                 if (error) {
4274                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4275                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4276                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4277                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4278                         ret = -EINVAL;
4279                         goto err;
4280                 }
4281                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4282                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4283                 if (error) {
4284                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4285                         ret = -EINVAL;
4286                 }
4287 err:
4288                 rxdp->wb.qword1.status_error_len = 0;
4289                 rxq->rx_tail++;
4290                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4291                         rxq->rx_tail = 0;
4292                 if (rxq->rx_tail == 0)
4293                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4294                 else
4295                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4296         }
4297
4298         return ret;
4299 }
4300
4301 #define ICE_FDIR_MAX_WAIT_US 10000
4302
4303 int
4304 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4305 {
4306         struct ice_tx_queue *txq = pf->fdir.txq;
4307         struct ice_rx_queue *rxq = pf->fdir.rxq;
4308         volatile struct ice_fltr_desc *fdirdp;
4309         volatile struct ice_tx_desc *txdp;
4310         uint32_t td_cmd;
4311         uint16_t i;
4312
4313         fdirdp = (volatile struct ice_fltr_desc *)
4314                 (&txq->tx_ring[txq->tx_tail]);
4315         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4316         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4317
4318         txdp = &txq->tx_ring[txq->tx_tail + 1];
4319         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4320         td_cmd = ICE_TX_DESC_CMD_EOP |
4321                 ICE_TX_DESC_CMD_RS  |
4322                 ICE_TX_DESC_CMD_DUMMY;
4323
4324         txdp->cmd_type_offset_bsz =
4325                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4326
4327         txq->tx_tail += 2;
4328         if (txq->tx_tail >= txq->nb_tx_desc)
4329                 txq->tx_tail = 0;
4330         /* Update the tx tail register */
4331         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4332         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4333                 if ((txdp->cmd_type_offset_bsz &
4334                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4335                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4336                         break;
4337                 rte_delay_us(1);
4338         }
4339         if (i >= ICE_FDIR_MAX_WAIT_US) {
4340                 PMD_DRV_LOG(ERR,
4341                             "Failed to program FDIR filter: time out to get DD on tx queue.");
4342                 return -ETIMEDOUT;
4343         }
4344
4345         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4346                 int ret;
4347
4348                 ret = ice_check_fdir_programming_status(rxq);
4349                 if (ret == -EAGAIN)
4350                         rte_delay_us(1);
4351                 else
4352                         return ret;
4353         }
4354
4355         PMD_DRV_LOG(ERR,
4356                     "Failed to program FDIR filter: programming status reported.");
4357         return -ETIMEDOUT;
4358
4359
4360 }