1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <ethdev_driver.h>
9 #include "rte_pmd_ice.h"
11 #include "ice_rxtx_vec_common.h"
13 #define ICE_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM | \
14 RTE_MBUF_F_TX_L4_MASK | \
15 RTE_MBUF_F_TX_TCP_SEG | \
16 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
18 /* Offset of mbuf dynamic field for protocol extraction data */
19 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
21 /* Mask of mbuf dynamic flags for protocol extraction type */
22 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
26 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
27 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
30 ice_monitor_callback(const uint64_t value,
31 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
33 const uint64_t m = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
35 * we expect the DD bit to be set to 1 if this descriptor was already
38 return (value & m) == m ? -1 : 0;
42 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
44 volatile union ice_rx_flex_desc *rxdp;
45 struct ice_rx_queue *rxq = rx_queue;
49 rxdp = &rxq->rx_ring[desc];
50 /* watch for changes in status bit */
51 pmc->addr = &rxdp->wb.status_error0;
53 /* comparison callback */
54 pmc->fn = ice_monitor_callback;
56 /* register is 16-bit */
57 pmc->size = sizeof(uint16_t);
64 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
66 static uint8_t rxdid_map[] = {
67 [PROTO_XTR_NONE] = ICE_RXDID_COMMS_OVS,
68 [PROTO_XTR_VLAN] = ICE_RXDID_COMMS_AUX_VLAN,
69 [PROTO_XTR_IPV4] = ICE_RXDID_COMMS_AUX_IPV4,
70 [PROTO_XTR_IPV6] = ICE_RXDID_COMMS_AUX_IPV6,
71 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
72 [PROTO_XTR_TCP] = ICE_RXDID_COMMS_AUX_TCP,
73 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
76 return xtr_type < RTE_DIM(rxdid_map) ?
77 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
81 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
83 volatile union ice_rx_flex_desc *rxdp)
85 volatile struct ice_32b_rx_flex_desc_comms *desc =
86 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
87 uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
89 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
90 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
91 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
94 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
95 if (desc->flow_id != 0xFFFFFFFF) {
96 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
97 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
103 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
105 volatile union ice_rx_flex_desc *rxdp)
107 volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
108 (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
109 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
113 if (desc->flow_id != 0xFFFFFFFF) {
114 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
115 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
118 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
119 stat_err = rte_le_to_cpu_16(desc->status_error0);
120 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
121 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
122 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
128 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
130 volatile union ice_rx_flex_desc *rxdp)
132 volatile struct ice_32b_rx_flex_desc_comms *desc =
133 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
136 stat_err = rte_le_to_cpu_16(desc->status_error0);
137 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
138 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
139 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
142 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
143 if (desc->flow_id != 0xFFFFFFFF) {
144 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
145 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
148 if (rxq->xtr_ol_flag) {
149 uint32_t metadata = 0;
151 stat_err = rte_le_to_cpu_16(desc->status_error1);
153 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
154 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
156 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
158 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
161 mb->ol_flags |= rxq->xtr_ol_flag;
163 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
172 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
174 volatile union ice_rx_flex_desc *rxdp)
176 volatile struct ice_32b_rx_flex_desc_comms *desc =
177 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
180 stat_err = rte_le_to_cpu_16(desc->status_error0);
181 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
182 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
183 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
186 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
187 if (desc->flow_id != 0xFFFFFFFF) {
188 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
189 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
192 if (rxq->xtr_ol_flag) {
193 uint32_t metadata = 0;
195 if (desc->flex_ts.flex.aux0 != 0xFFFF)
196 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
197 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
198 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
201 mb->ol_flags |= rxq->xtr_ol_flag;
203 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
211 static const ice_rxd_to_pkt_fields_t rxd_to_pkt_fields_ops[] = {
212 [ICE_RXDID_COMMS_AUX_VLAN] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
213 [ICE_RXDID_COMMS_AUX_IPV4] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
214 [ICE_RXDID_COMMS_AUX_IPV6] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
215 [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
216 [ICE_RXDID_COMMS_AUX_TCP] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
217 [ICE_RXDID_COMMS_AUX_IP_OFFSET] = ice_rxd_to_pkt_fields_by_comms_aux_v2,
218 [ICE_RXDID_COMMS_GENERIC] = ice_rxd_to_pkt_fields_by_comms_generic,
219 [ICE_RXDID_COMMS_OVS] = ice_rxd_to_pkt_fields_by_comms_ovs,
223 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
228 case ICE_RXDID_COMMS_AUX_VLAN:
229 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
232 case ICE_RXDID_COMMS_AUX_IPV4:
233 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
236 case ICE_RXDID_COMMS_AUX_IPV6:
237 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
240 case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
241 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
244 case ICE_RXDID_COMMS_AUX_TCP:
245 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
248 case ICE_RXDID_COMMS_AUX_IP_OFFSET:
249 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
252 case ICE_RXDID_COMMS_GENERIC:
254 case ICE_RXDID_COMMS_OVS:
258 /* update this according to the RXDID for PROTO_XTR_NONE */
259 rxq->rxdid = ICE_RXDID_COMMS_OVS;
263 if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
264 rxq->xtr_ol_flag = 0;
267 static enum ice_status
268 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
270 struct ice_vsi *vsi = rxq->vsi;
271 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
272 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
273 struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
274 struct ice_rlan_ctx rx_ctx;
277 uint32_t rxdid = ICE_RXDID_COMMS_OVS;
279 struct ice_adapter *ad = rxq->vsi->adapter;
280 uint32_t frame_size = dev_data->mtu + ICE_ETH_OVERHEAD;
282 /* Set buffer size as the head split is disabled. */
283 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
284 RTE_PKTMBUF_HEADROOM);
286 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
288 RTE_MIN((uint32_t)ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
291 if (rxq->max_pkt_len <= RTE_ETHER_MIN_LEN ||
292 rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
293 PMD_DRV_LOG(ERR, "maximum packet length must "
294 "be larger than %u and smaller than %u",
295 (uint32_t)RTE_ETHER_MIN_LEN,
296 (uint32_t)ICE_FRAME_SIZE_MAX);
300 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
301 /* Register mbuf field and flag for Rx timestamp */
302 err = rte_mbuf_dyn_rx_timestamp_register(
303 &ice_timestamp_dynfield_offset,
304 &ice_timestamp_dynflag);
307 "Cannot register mbuf field/flag for timestamp");
312 memset(&rx_ctx, 0, sizeof(rx_ctx));
314 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
315 rx_ctx.qlen = rxq->nb_rx_desc;
316 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
317 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
318 rx_ctx.dtype = 0; /* No Header Split mode */
319 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
320 rx_ctx.dsize = 1; /* 32B descriptors */
322 rx_ctx.rxmax = rxq->max_pkt_len;
323 /* TPH: Transaction Layer Packet (TLP) processing hints */
324 rx_ctx.tphrdesc_ena = 1;
325 rx_ctx.tphwdesc_ena = 1;
326 rx_ctx.tphdata_ena = 1;
327 rx_ctx.tphhead_ena = 1;
328 /* Low Receive Queue Threshold defined in 64 descriptors units.
329 * When the number of free descriptors goes below the lrxqthresh,
330 * an immediate interrupt is triggered.
332 rx_ctx.lrxqthresh = 2;
333 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
336 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
338 rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
340 PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
341 rxq->port_id, rxq->queue_id, rxdid);
343 if (!(pf->supported_rxdid & BIT(rxdid))) {
344 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
349 ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
351 /* Enable Flexible Descriptors in the queue context which
352 * allows this driver to select a specific receive descriptor format
354 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
355 QRXFLXP_CNTXT_RXDID_IDX_M;
357 /* increasing context priority to pick up profile ID;
358 * default is 0x01; setting to 0x03 to ensure profile
359 * is programming if prev context is of same priority
361 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
362 QRXFLXP_CNTXT_RXDID_PRIO_M;
364 if (ad->ptp_ena || rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
365 regval |= QRXFLXP_CNTXT_TS_M;
367 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
369 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
371 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
375 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
377 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
382 /* Check if scattered RX needs to be used. */
383 if (frame_size > buf_size)
384 dev_data->scattered_rx = 1;
386 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
388 /* Init the Rx tail register*/
389 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
394 /* Allocate mbufs for all descriptors in rx queue */
396 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
398 struct ice_rx_entry *rxe = rxq->sw_ring;
402 for (i = 0; i < rxq->nb_rx_desc; i++) {
403 volatile union ice_rx_flex_desc *rxd;
404 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
406 if (unlikely(!mbuf)) {
407 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
411 rte_mbuf_refcnt_set(mbuf, 1);
413 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
415 mbuf->port = rxq->port_id;
418 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
420 rxd = &rxq->rx_ring[i];
421 rxd->read.pkt_addr = dma_addr;
422 rxd->read.hdr_addr = 0;
423 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
433 /* Free all mbufs for descriptors in rx queue */
435 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
439 if (!rxq || !rxq->sw_ring) {
440 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
444 for (i = 0; i < rxq->nb_rx_desc; i++) {
445 if (rxq->sw_ring[i].mbuf) {
446 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
447 rxq->sw_ring[i].mbuf = NULL;
450 if (rxq->rx_nb_avail == 0)
452 for (i = 0; i < rxq->rx_nb_avail; i++)
453 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
455 rxq->rx_nb_avail = 0;
458 /* turn on or off rx queue
459 * @q_idx: queue index in pf scope
460 * @on: turn on or off the queue
463 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
468 /* QRX_CTRL = QRX_ENA */
469 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
472 if (reg & QRX_CTRL_QENA_STAT_M)
473 return 0; /* Already on, skip */
474 reg |= QRX_CTRL_QENA_REQ_M;
476 if (!(reg & QRX_CTRL_QENA_STAT_M))
477 return 0; /* Already off, skip */
478 reg &= ~QRX_CTRL_QENA_REQ_M;
481 /* Write the register */
482 ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
483 /* Check the result. It is said that QENA_STAT
484 * follows the QENA_REQ not more than 10 use.
485 * TODO: need to change the wait counter later
487 for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
488 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
489 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
491 if ((reg & QRX_CTRL_QENA_REQ_M) &&
492 (reg & QRX_CTRL_QENA_STAT_M))
495 if (!(reg & QRX_CTRL_QENA_REQ_M) &&
496 !(reg & QRX_CTRL_QENA_STAT_M))
501 /* Check if it is timeout */
502 if (j >= ICE_CHK_Q_ENA_COUNT) {
503 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
504 (on ? "enable" : "disable"), q_idx);
512 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
516 if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
517 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
518 "rxq->rx_free_thresh=%d, "
519 "ICE_RX_MAX_BURST=%d",
520 rxq->rx_free_thresh, ICE_RX_MAX_BURST);
522 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
523 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
524 "rxq->rx_free_thresh=%d, "
525 "rxq->nb_rx_desc=%d",
526 rxq->rx_free_thresh, rxq->nb_rx_desc);
528 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
529 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
530 "rxq->nb_rx_desc=%d, "
531 "rxq->rx_free_thresh=%d",
532 rxq->nb_rx_desc, rxq->rx_free_thresh);
539 /* reset fields in ice_rx_queue back to default */
541 ice_reset_rx_queue(struct ice_rx_queue *rxq)
547 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
551 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
553 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
554 ((volatile char *)rxq->rx_ring)[i] = 0;
556 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
557 for (i = 0; i < ICE_RX_MAX_BURST; ++i)
558 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
560 rxq->rx_nb_avail = 0;
561 rxq->rx_next_avail = 0;
562 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
566 rxq->pkt_first_seg = NULL;
567 rxq->pkt_last_seg = NULL;
569 rxq->rxrearm_start = 0;
574 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
576 struct ice_rx_queue *rxq;
578 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
580 PMD_INIT_FUNC_TRACE();
582 if (rx_queue_id >= dev->data->nb_rx_queues) {
583 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
584 rx_queue_id, dev->data->nb_rx_queues);
588 rxq = dev->data->rx_queues[rx_queue_id];
589 if (!rxq || !rxq->q_set) {
590 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
595 err = ice_program_hw_rx_queue(rxq);
597 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
602 err = ice_alloc_rx_queue_mbufs(rxq);
604 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
608 /* Init the RX tail register. */
609 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
611 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
613 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
616 rxq->rx_rel_mbufs(rxq);
617 ice_reset_rx_queue(rxq);
621 dev->data->rx_queue_state[rx_queue_id] =
622 RTE_ETH_QUEUE_STATE_STARTED;
628 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
630 struct ice_rx_queue *rxq;
632 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
634 if (rx_queue_id < dev->data->nb_rx_queues) {
635 rxq = dev->data->rx_queues[rx_queue_id];
637 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
639 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
643 rxq->rx_rel_mbufs(rxq);
644 ice_reset_rx_queue(rxq);
645 dev->data->rx_queue_state[rx_queue_id] =
646 RTE_ETH_QUEUE_STATE_STOPPED;
653 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
655 struct ice_tx_queue *txq;
659 struct ice_aqc_add_tx_qgrp *txq_elem;
660 struct ice_tlan_ctx tx_ctx;
663 PMD_INIT_FUNC_TRACE();
665 if (tx_queue_id >= dev->data->nb_tx_queues) {
666 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
667 tx_queue_id, dev->data->nb_tx_queues);
671 txq = dev->data->tx_queues[tx_queue_id];
672 if (!txq || !txq->q_set) {
673 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
678 buf_len = ice_struct_size(txq_elem, txqs, 1);
679 txq_elem = ice_malloc(hw, buf_len);
684 hw = ICE_VSI_TO_HW(vsi);
686 memset(&tx_ctx, 0, sizeof(tx_ctx));
687 txq_elem->num_txqs = 1;
688 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
690 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
691 tx_ctx.qlen = txq->nb_tx_desc;
692 tx_ctx.pf_num = hw->pf_id;
693 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
694 tx_ctx.src_vsi = vsi->vsi_id;
695 tx_ctx.port_num = hw->port_info->lport;
696 tx_ctx.tso_ena = 1; /* tso enable */
697 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
698 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
701 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
704 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
706 /* Init the Tx tail register*/
707 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
709 /* Fix me, we assume TC always 0 here */
710 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
711 txq_elem, buf_len, NULL);
713 PMD_DRV_LOG(ERR, "Failed to add lan txq");
717 /* store the schedule node id */
718 txq->q_teid = txq_elem->txqs[0].q_teid;
720 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
726 static enum ice_status
727 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
729 struct ice_vsi *vsi = rxq->vsi;
730 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
731 uint32_t rxdid = ICE_RXDID_LEGACY_1;
732 struct ice_rlan_ctx rx_ctx;
737 rxq->rx_buf_len = 1024;
739 memset(&rx_ctx, 0, sizeof(rx_ctx));
741 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
742 rx_ctx.qlen = rxq->nb_rx_desc;
743 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
744 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
745 rx_ctx.dtype = 0; /* No Header Split mode */
746 rx_ctx.dsize = 1; /* 32B descriptors */
747 rx_ctx.rxmax = ICE_ETH_MAX_LEN;
748 /* TPH: Transaction Layer Packet (TLP) processing hints */
749 rx_ctx.tphrdesc_ena = 1;
750 rx_ctx.tphwdesc_ena = 1;
751 rx_ctx.tphdata_ena = 1;
752 rx_ctx.tphhead_ena = 1;
753 /* Low Receive Queue Threshold defined in 64 descriptors units.
754 * When the number of free descriptors goes below the lrxqthresh,
755 * an immediate interrupt is triggered.
757 rx_ctx.lrxqthresh = 2;
758 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
761 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
763 /* Enable Flexible Descriptors in the queue context which
764 * allows this driver to select a specific receive descriptor format
766 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
767 QRXFLXP_CNTXT_RXDID_IDX_M;
769 /* increasing context priority to pick up profile ID;
770 * default is 0x01; setting to 0x03 to ensure profile
771 * is programming if prev context is of same priority
773 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
774 QRXFLXP_CNTXT_RXDID_PRIO_M;
776 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
778 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
780 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
784 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
786 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
791 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
793 /* Init the Rx tail register*/
794 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
800 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
802 struct ice_rx_queue *rxq;
804 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
805 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
807 PMD_INIT_FUNC_TRACE();
810 if (!rxq || !rxq->q_set) {
811 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
816 err = ice_fdir_program_hw_rx_queue(rxq);
818 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
823 /* Init the RX tail register. */
824 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
826 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
828 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
831 ice_reset_rx_queue(rxq);
839 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
841 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
842 struct ice_tx_queue *txq;
846 struct ice_aqc_add_tx_qgrp *txq_elem;
847 struct ice_tlan_ctx tx_ctx;
850 PMD_INIT_FUNC_TRACE();
853 if (!txq || !txq->q_set) {
854 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
859 buf_len = ice_struct_size(txq_elem, txqs, 1);
860 txq_elem = ice_malloc(hw, buf_len);
865 hw = ICE_VSI_TO_HW(vsi);
867 memset(&tx_ctx, 0, sizeof(tx_ctx));
868 txq_elem->num_txqs = 1;
869 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
871 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
872 tx_ctx.qlen = txq->nb_tx_desc;
873 tx_ctx.pf_num = hw->pf_id;
874 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
875 tx_ctx.src_vsi = vsi->vsi_id;
876 tx_ctx.port_num = hw->port_info->lport;
877 tx_ctx.tso_ena = 1; /* tso enable */
878 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
879 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
881 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
884 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
886 /* Init the Tx tail register*/
887 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
889 /* Fix me, we assume TC always 0 here */
890 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
891 txq_elem, buf_len, NULL);
893 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
897 /* store the schedule node id */
898 txq->q_teid = txq_elem->txqs[0].q_teid;
904 /* Free all mbufs for descriptors in tx queue */
906 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
910 if (!txq || !txq->sw_ring) {
911 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
915 for (i = 0; i < txq->nb_tx_desc; i++) {
916 if (txq->sw_ring[i].mbuf) {
917 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
918 txq->sw_ring[i].mbuf = NULL;
924 ice_reset_tx_queue(struct ice_tx_queue *txq)
926 struct ice_tx_entry *txe;
927 uint16_t i, prev, size;
930 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
935 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
936 for (i = 0; i < size; i++)
937 ((volatile char *)txq->tx_ring)[i] = 0;
939 prev = (uint16_t)(txq->nb_tx_desc - 1);
940 for (i = 0; i < txq->nb_tx_desc; i++) {
941 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
943 txd->cmd_type_offset_bsz =
944 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
947 txe[prev].next_id = i;
951 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
952 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
957 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
958 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
962 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
964 struct ice_tx_queue *txq;
965 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
966 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
967 struct ice_vsi *vsi = pf->main_vsi;
968 enum ice_status status;
971 uint16_t q_handle = tx_queue_id;
973 if (tx_queue_id >= dev->data->nb_tx_queues) {
974 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
975 tx_queue_id, dev->data->nb_tx_queues);
979 txq = dev->data->tx_queues[tx_queue_id];
981 PMD_DRV_LOG(ERR, "TX queue %u is not available",
986 q_ids[0] = txq->reg_idx;
987 q_teids[0] = txq->q_teid;
989 /* Fix me, we assume TC always 0 here */
990 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
991 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
992 if (status != ICE_SUCCESS) {
993 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
997 txq->tx_rel_mbufs(txq);
998 ice_reset_tx_queue(txq);
999 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1005 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1007 struct ice_rx_queue *rxq;
1009 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1010 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1014 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1016 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1020 rxq->rx_rel_mbufs(rxq);
1026 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1028 struct ice_tx_queue *txq;
1029 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1030 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1031 struct ice_vsi *vsi = pf->main_vsi;
1032 enum ice_status status;
1034 uint32_t q_teids[1];
1035 uint16_t q_handle = tx_queue_id;
1039 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1045 q_ids[0] = txq->reg_idx;
1046 q_teids[0] = txq->q_teid;
1048 /* Fix me, we assume TC always 0 here */
1049 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1050 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1051 if (status != ICE_SUCCESS) {
1052 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1056 txq->tx_rel_mbufs(txq);
1062 ice_rx_queue_setup(struct rte_eth_dev *dev,
1065 unsigned int socket_id,
1066 const struct rte_eth_rxconf *rx_conf,
1067 struct rte_mempool *mp)
1069 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1070 struct ice_adapter *ad =
1071 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1072 struct ice_vsi *vsi = pf->main_vsi;
1073 struct ice_rx_queue *rxq;
1074 const struct rte_memzone *rz;
1077 int use_def_burst_func = 1;
1080 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1081 nb_desc > ICE_MAX_RING_DESC ||
1082 nb_desc < ICE_MIN_RING_DESC) {
1083 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1084 "invalid", nb_desc);
1088 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1090 /* Free memory if needed */
1091 if (dev->data->rx_queues[queue_idx]) {
1092 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1093 dev->data->rx_queues[queue_idx] = NULL;
1096 /* Allocate the rx queue data structure */
1097 rxq = rte_zmalloc_socket(NULL,
1098 sizeof(struct ice_rx_queue),
1099 RTE_CACHE_LINE_SIZE,
1102 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1103 "rx queue data structure");
1107 rxq->nb_rx_desc = nb_desc;
1108 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1109 rxq->queue_id = queue_idx;
1110 rxq->offloads = offloads;
1112 rxq->reg_idx = vsi->base_queue + queue_idx;
1113 rxq->port_id = dev->data->port_id;
1114 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1115 rxq->crc_len = RTE_ETHER_CRC_LEN;
1119 rxq->drop_en = rx_conf->rx_drop_en;
1121 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1122 rxq->proto_xtr = pf->proto_xtr != NULL ?
1123 pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1125 /* Allocate the maximum number of RX ring hardware descriptor. */
1126 len = ICE_MAX_RING_DESC;
1129 * Allocating a little more memory because vectorized/bulk_alloc Rx
1130 * functions doesn't check boundaries each time.
1132 len += ICE_RX_MAX_BURST;
1134 /* Allocate the maximum number of RX ring hardware descriptor. */
1135 ring_size = sizeof(union ice_rx_flex_desc) * len;
1136 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1137 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1138 ring_size, ICE_RING_BASE_ALIGN,
1141 ice_rx_queue_release(rxq);
1142 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1147 /* Zero all the descriptors in the ring. */
1148 memset(rz->addr, 0, ring_size);
1150 rxq->rx_ring_dma = rz->iova;
1151 rxq->rx_ring = rz->addr;
1153 /* always reserve more for bulk alloc */
1154 len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1156 /* Allocate the software ring. */
1157 rxq->sw_ring = rte_zmalloc_socket(NULL,
1158 sizeof(struct ice_rx_entry) * len,
1159 RTE_CACHE_LINE_SIZE,
1161 if (!rxq->sw_ring) {
1162 ice_rx_queue_release(rxq);
1163 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1167 ice_reset_rx_queue(rxq);
1169 dev->data->rx_queues[queue_idx] = rxq;
1170 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1172 use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1174 if (!use_def_burst_func) {
1175 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1176 "satisfied. Rx Burst Bulk Alloc function will be "
1177 "used on port=%d, queue=%d.",
1178 rxq->port_id, rxq->queue_id);
1180 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1181 "not satisfied, Scattered Rx is requested. "
1182 "on port=%d, queue=%d.",
1183 rxq->port_id, rxq->queue_id);
1184 ad->rx_bulk_alloc_allowed = false;
1191 ice_rx_queue_release(void *rxq)
1193 struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1196 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1201 rte_free(q->sw_ring);
1202 rte_memzone_free(q->mz);
1207 ice_tx_queue_setup(struct rte_eth_dev *dev,
1210 unsigned int socket_id,
1211 const struct rte_eth_txconf *tx_conf)
1213 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1214 struct ice_vsi *vsi = pf->main_vsi;
1215 struct ice_tx_queue *txq;
1216 const struct rte_memzone *tz;
1218 uint16_t tx_rs_thresh, tx_free_thresh;
1221 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1223 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1224 nb_desc > ICE_MAX_RING_DESC ||
1225 nb_desc < ICE_MIN_RING_DESC) {
1226 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1227 "invalid", nb_desc);
1232 * The following two parameters control the setting of the RS bit on
1233 * transmit descriptors. TX descriptors will have their RS bit set
1234 * after txq->tx_rs_thresh descriptors have been used. The TX
1235 * descriptor ring will be cleaned after txq->tx_free_thresh
1236 * descriptors are used or if the number of descriptors required to
1237 * transmit a packet is greater than the number of free TX descriptors.
1239 * The following constraints must be satisfied:
1240 * - tx_rs_thresh must be greater than 0.
1241 * - tx_rs_thresh must be less than the size of the ring minus 2.
1242 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1243 * - tx_rs_thresh must be a divisor of the ring size.
1244 * - tx_free_thresh must be greater than 0.
1245 * - tx_free_thresh must be less than the size of the ring minus 3.
1246 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1248 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1249 * race condition, hence the maximum threshold constraints. When set
1250 * to zero use default values.
1252 tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1253 tx_conf->tx_free_thresh :
1254 ICE_DEFAULT_TX_FREE_THRESH);
1255 /* force tx_rs_thresh to adapt an aggressive tx_free_thresh */
1257 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1258 nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1259 if (tx_conf->tx_rs_thresh)
1260 tx_rs_thresh = tx_conf->tx_rs_thresh;
1261 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1262 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1263 "exceed nb_desc. (tx_rs_thresh=%u "
1264 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1265 (unsigned int)tx_rs_thresh,
1266 (unsigned int)tx_free_thresh,
1267 (unsigned int)nb_desc,
1268 (int)dev->data->port_id,
1272 if (tx_rs_thresh >= (nb_desc - 2)) {
1273 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1274 "number of TX descriptors minus 2. "
1275 "(tx_rs_thresh=%u port=%d queue=%d)",
1276 (unsigned int)tx_rs_thresh,
1277 (int)dev->data->port_id,
1281 if (tx_free_thresh >= (nb_desc - 3)) {
1282 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1283 "tx_free_thresh must be less than the "
1284 "number of TX descriptors minus 3. "
1285 "(tx_free_thresh=%u port=%d queue=%d)",
1286 (unsigned int)tx_free_thresh,
1287 (int)dev->data->port_id,
1291 if (tx_rs_thresh > tx_free_thresh) {
1292 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1293 "equal to tx_free_thresh. (tx_free_thresh=%u"
1294 " tx_rs_thresh=%u port=%d queue=%d)",
1295 (unsigned int)tx_free_thresh,
1296 (unsigned int)tx_rs_thresh,
1297 (int)dev->data->port_id,
1301 if ((nb_desc % tx_rs_thresh) != 0) {
1302 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1303 "number of TX descriptors. (tx_rs_thresh=%u"
1304 " port=%d queue=%d)",
1305 (unsigned int)tx_rs_thresh,
1306 (int)dev->data->port_id,
1310 if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1311 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1312 "tx_rs_thresh is greater than 1. "
1313 "(tx_rs_thresh=%u port=%d queue=%d)",
1314 (unsigned int)tx_rs_thresh,
1315 (int)dev->data->port_id,
1320 /* Free memory if needed. */
1321 if (dev->data->tx_queues[queue_idx]) {
1322 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1323 dev->data->tx_queues[queue_idx] = NULL;
1326 /* Allocate the TX queue data structure. */
1327 txq = rte_zmalloc_socket(NULL,
1328 sizeof(struct ice_tx_queue),
1329 RTE_CACHE_LINE_SIZE,
1332 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1333 "tx queue structure");
1337 /* Allocate TX hardware ring descriptors. */
1338 ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1339 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1340 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1341 ring_size, ICE_RING_BASE_ALIGN,
1344 ice_tx_queue_release(txq);
1345 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1350 txq->nb_tx_desc = nb_desc;
1351 txq->tx_rs_thresh = tx_rs_thresh;
1352 txq->tx_free_thresh = tx_free_thresh;
1353 txq->pthresh = tx_conf->tx_thresh.pthresh;
1354 txq->hthresh = tx_conf->tx_thresh.hthresh;
1355 txq->wthresh = tx_conf->tx_thresh.wthresh;
1356 txq->queue_id = queue_idx;
1358 txq->reg_idx = vsi->base_queue + queue_idx;
1359 txq->port_id = dev->data->port_id;
1360 txq->offloads = offloads;
1362 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1364 txq->tx_ring_dma = tz->iova;
1365 txq->tx_ring = tz->addr;
1367 /* Allocate software ring */
1369 rte_zmalloc_socket(NULL,
1370 sizeof(struct ice_tx_entry) * nb_desc,
1371 RTE_CACHE_LINE_SIZE,
1373 if (!txq->sw_ring) {
1374 ice_tx_queue_release(txq);
1375 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1379 ice_reset_tx_queue(txq);
1381 dev->data->tx_queues[queue_idx] = txq;
1382 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1383 ice_set_tx_function_flag(dev, txq);
1389 ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1391 ice_rx_queue_release(dev->data->rx_queues[qid]);
1395 ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1397 ice_tx_queue_release(dev->data->tx_queues[qid]);
1401 ice_tx_queue_release(void *txq)
1403 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1406 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1411 rte_free(q->sw_ring);
1412 rte_memzone_free(q->mz);
1417 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1418 struct rte_eth_rxq_info *qinfo)
1420 struct ice_rx_queue *rxq;
1422 rxq = dev->data->rx_queues[queue_id];
1424 qinfo->mp = rxq->mp;
1425 qinfo->scattered_rx = dev->data->scattered_rx;
1426 qinfo->nb_desc = rxq->nb_rx_desc;
1428 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1429 qinfo->conf.rx_drop_en = rxq->drop_en;
1430 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1434 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1435 struct rte_eth_txq_info *qinfo)
1437 struct ice_tx_queue *txq;
1439 txq = dev->data->tx_queues[queue_id];
1441 qinfo->nb_desc = txq->nb_tx_desc;
1443 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1444 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1445 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1447 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1448 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1449 qinfo->conf.offloads = txq->offloads;
1450 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1454 ice_rx_queue_count(void *rx_queue)
1456 #define ICE_RXQ_SCAN_INTERVAL 4
1457 volatile union ice_rx_flex_desc *rxdp;
1458 struct ice_rx_queue *rxq;
1462 rxdp = &rxq->rx_ring[rxq->rx_tail];
1463 while ((desc < rxq->nb_rx_desc) &&
1464 rte_le_to_cpu_16(rxdp->wb.status_error0) &
1465 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1467 * Check the DD bit of a rx descriptor of each 4 in a group,
1468 * to avoid checking too frequently and downgrading performance
1471 desc += ICE_RXQ_SCAN_INTERVAL;
1472 rxdp += ICE_RXQ_SCAN_INTERVAL;
1473 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1474 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1475 desc - rxq->nb_rx_desc]);
1481 #define ICE_RX_FLEX_ERR0_BITS \
1482 ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) | \
1483 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1484 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1485 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1486 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1487 (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1489 /* Rx L3/L4 checksum */
1490 static inline uint64_t
1491 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1495 /* check if HW has decoded the packet and checksum */
1496 if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1499 if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1500 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD |
1501 RTE_MBUF_F_RX_L4_CKSUM_GOOD |
1502 RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD);
1506 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1507 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1509 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1511 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1512 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1514 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1516 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1517 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1519 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1520 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;
1522 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD;
1528 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1530 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1531 (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1532 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1534 rte_le_to_cpu_16(rxdp->wb.l2tag1);
1535 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1536 rte_le_to_cpu_16(rxdp->wb.l2tag1));
1541 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1542 if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1543 (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1544 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
1545 RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
1546 mb->vlan_tci_outer = mb->vlan_tci;
1547 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1548 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1549 rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1550 rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1552 mb->vlan_tci_outer = 0;
1555 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1556 mb->vlan_tci, mb->vlan_tci_outer);
1559 #define ICE_LOOK_AHEAD 8
1560 #if (ICE_LOOK_AHEAD != 8)
1561 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1564 #define ICE_PTP_TS_VALID 0x1
1567 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1569 volatile union ice_rx_flex_desc *rxdp;
1570 struct ice_rx_entry *rxep;
1571 struct rte_mbuf *mb;
1574 int32_t s[ICE_LOOK_AHEAD], nb_dd;
1575 int32_t i, j, nb_rx = 0;
1576 uint64_t pkt_flags = 0;
1577 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1578 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1579 bool is_tsinit = false;
1581 struct ice_vsi *vsi = rxq->vsi;
1582 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1583 struct ice_adapter *ad = rxq->vsi->adapter;
1585 rxdp = &rxq->rx_ring[rxq->rx_tail];
1586 rxep = &rxq->sw_ring[rxq->rx_tail];
1588 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1590 /* Make sure there is at least 1 packet to receive */
1591 if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1594 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1595 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1596 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1598 if (unlikely(sw_cur_time - rxq->hw_time_update > 4))
1604 * Scan LOOK_AHEAD descriptors at a time to determine which
1605 * descriptors reference packets that are ready to be received.
1607 for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1608 rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1609 /* Read desc statuses backwards to avoid race condition */
1610 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1611 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1615 /* Compute how many status bits were set */
1616 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1617 nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1621 /* Translate descriptor info to mbuf parameters */
1622 for (j = 0; j < nb_dd; j++) {
1624 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1625 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1626 mb->data_len = pkt_len;
1627 mb->pkt_len = pkt_len;
1629 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1630 pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1631 mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1632 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1633 ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1634 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, mb, &rxdp[j]);
1635 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1636 if (ice_timestamp_dynflag > 0) {
1638 rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high);
1639 if (unlikely(is_tsinit)) {
1640 ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1,
1642 rxq->hw_time_low = (uint32_t)ts_ns;
1643 rxq->hw_time_high = (uint32_t)(ts_ns >> 32);
1646 if (rxq->time_high < rxq->hw_time_low)
1647 rxq->hw_time_high += 1;
1648 ts_ns = (uint64_t)rxq->hw_time_high << 32 | rxq->time_high;
1649 rxq->hw_time_low = rxq->time_high;
1651 rxq->hw_time_update = rte_get_timer_cycles() /
1652 (rte_get_timer_hz() / 1000);
1653 *RTE_MBUF_DYNFIELD(mb,
1654 ice_timestamp_dynfield_offset,
1655 rte_mbuf_timestamp_t *) = ts_ns;
1656 pkt_flags |= ice_timestamp_dynflag;
1659 if (ad->ptp_ena && ((mb->packet_type &
1660 RTE_PTYPE_L2_MASK) == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1662 rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high);
1663 mb->timesync = rxq->queue_id;
1664 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1665 if (rxdp[j].wb.time_stamp_low &
1668 RTE_MBUF_F_RX_IEEE1588_TMST;
1671 mb->ol_flags |= pkt_flags;
1674 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1675 rxq->rx_stage[i + j] = rxep[j].mbuf;
1677 if (nb_dd != ICE_LOOK_AHEAD)
1681 /* Clear software ring entries */
1682 for (i = 0; i < nb_rx; i++)
1683 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1685 PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1686 "port_id=%u, queue_id=%u, nb_rx=%d",
1687 rxq->port_id, rxq->queue_id, nb_rx);
1692 static inline uint16_t
1693 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1694 struct rte_mbuf **rx_pkts,
1698 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1700 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1702 for (i = 0; i < nb_pkts; i++)
1703 rx_pkts[i] = stage[i];
1705 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1706 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1712 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1714 volatile union ice_rx_flex_desc *rxdp;
1715 struct ice_rx_entry *rxep;
1716 struct rte_mbuf *mb;
1717 uint16_t alloc_idx, i;
1721 /* Allocate buffers in bulk */
1722 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1723 (rxq->rx_free_thresh - 1));
1724 rxep = &rxq->sw_ring[alloc_idx];
1725 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1726 rxq->rx_free_thresh);
1727 if (unlikely(diag != 0)) {
1728 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1732 rxdp = &rxq->rx_ring[alloc_idx];
1733 for (i = 0; i < rxq->rx_free_thresh; i++) {
1734 if (likely(i < (rxq->rx_free_thresh - 1)))
1735 /* Prefetch next mbuf */
1736 rte_prefetch0(rxep[i + 1].mbuf);
1739 rte_mbuf_refcnt_set(mb, 1);
1741 mb->data_off = RTE_PKTMBUF_HEADROOM;
1743 mb->port = rxq->port_id;
1744 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1745 rxdp[i].read.hdr_addr = 0;
1746 rxdp[i].read.pkt_addr = dma_addr;
1749 /* Update Rx tail register */
1750 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1752 rxq->rx_free_trigger =
1753 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1754 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1755 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1760 static inline uint16_t
1761 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1763 struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1769 if (rxq->rx_nb_avail)
1770 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1772 nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1773 rxq->rx_next_avail = 0;
1774 rxq->rx_nb_avail = nb_rx;
1775 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1777 if (rxq->rx_tail > rxq->rx_free_trigger) {
1778 if (ice_rx_alloc_bufs(rxq) != 0) {
1781 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1782 rxq->rx_free_thresh;
1783 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1784 "port_id=%u, queue_id=%u",
1785 rxq->port_id, rxq->queue_id);
1786 rxq->rx_nb_avail = 0;
1787 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1788 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1789 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1795 if (rxq->rx_tail >= rxq->nb_rx_desc)
1798 if (rxq->rx_nb_avail)
1799 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1805 ice_recv_pkts_bulk_alloc(void *rx_queue,
1806 struct rte_mbuf **rx_pkts,
1813 if (unlikely(nb_pkts == 0))
1816 if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1817 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1820 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1821 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1822 nb_rx = (uint16_t)(nb_rx + count);
1823 nb_pkts = (uint16_t)(nb_pkts - count);
1832 ice_recv_scattered_pkts(void *rx_queue,
1833 struct rte_mbuf **rx_pkts,
1836 struct ice_rx_queue *rxq = rx_queue;
1837 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1838 volatile union ice_rx_flex_desc *rxdp;
1839 union ice_rx_flex_desc rxd;
1840 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1841 struct ice_rx_entry *rxe;
1842 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1843 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1844 struct rte_mbuf *nmb; /* new allocated mbuf */
1845 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1846 uint16_t rx_id = rxq->rx_tail;
1848 uint16_t nb_hold = 0;
1849 uint16_t rx_packet_len;
1850 uint16_t rx_stat_err0;
1853 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1854 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1855 bool is_tsinit = false;
1857 struct ice_vsi *vsi = rxq->vsi;
1858 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1859 struct ice_adapter *ad = rxq->vsi->adapter;
1861 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
1862 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
1864 if (unlikely(sw_cur_time - rxq->hw_time_update > 4))
1869 while (nb_rx < nb_pkts) {
1870 rxdp = &rx_ring[rx_id];
1871 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1873 /* Check the DD bit first */
1874 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1878 nmb = rte_mbuf_raw_alloc(rxq->mp);
1879 if (unlikely(!nmb)) {
1880 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1883 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1886 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1888 if (unlikely(rx_id == rxq->nb_rx_desc))
1891 /* Prefetch next mbuf */
1892 rte_prefetch0(sw_ring[rx_id].mbuf);
1895 * When next RX descriptor is on a cache line boundary,
1896 * prefetch the next 4 RX descriptors and next 8 pointers
1899 if ((rx_id & 0x3) == 0) {
1900 rte_prefetch0(&rx_ring[rx_id]);
1901 rte_prefetch0(&sw_ring[rx_id]);
1907 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1909 /* Set data buffer address and data length of the mbuf */
1910 rxdp->read.hdr_addr = 0;
1911 rxdp->read.pkt_addr = dma_addr;
1912 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1913 ICE_RX_FLX_DESC_PKT_LEN_M;
1914 rxm->data_len = rx_packet_len;
1915 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1918 * If this is the first buffer of the received packet, set the
1919 * pointer to the first mbuf of the packet and initialize its
1920 * context. Otherwise, update the total length and the number
1921 * of segments of the current scattered packet, and update the
1922 * pointer to the last mbuf of the current packet.
1926 first_seg->nb_segs = 1;
1927 first_seg->pkt_len = rx_packet_len;
1929 first_seg->pkt_len =
1930 (uint16_t)(first_seg->pkt_len +
1932 first_seg->nb_segs++;
1933 last_seg->next = rxm;
1937 * If this is not the last buffer of the received packet,
1938 * update the pointer to the last mbuf of the current scattered
1939 * packet and continue to parse the RX ring.
1941 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1947 * This is the last buffer of the received packet. If the CRC
1948 * is not stripped by the hardware:
1949 * - Subtract the CRC length from the total packet length.
1950 * - If the last buffer only contains the whole CRC or a part
1951 * of it, free the mbuf associated to the last buffer. If part
1952 * of the CRC is also contained in the previous mbuf, subtract
1953 * the length of that CRC part from the data length of the
1957 if (unlikely(rxq->crc_len > 0)) {
1958 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1959 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1960 rte_pktmbuf_free_seg(rxm);
1961 first_seg->nb_segs--;
1962 last_seg->data_len =
1963 (uint16_t)(last_seg->data_len -
1964 (RTE_ETHER_CRC_LEN - rx_packet_len));
1965 last_seg->next = NULL;
1967 rxm->data_len = (uint16_t)(rx_packet_len -
1971 first_seg->port = rxq->port_id;
1972 first_seg->ol_flags = 0;
1973 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1974 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1975 ice_rxd_to_vlan_tci(first_seg, &rxd);
1976 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, first_seg, &rxd);
1977 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1978 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1979 if (ice_timestamp_dynflag > 0) {
1981 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
1982 if (unlikely(is_tsinit)) {
1983 ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, rxq->time_high);
1984 rxq->hw_time_low = (uint32_t)ts_ns;
1985 rxq->hw_time_high = (uint32_t)(ts_ns >> 32);
1988 if (rxq->time_high < rxq->hw_time_low)
1989 rxq->hw_time_high += 1;
1990 ts_ns = (uint64_t)rxq->hw_time_high << 32 | rxq->time_high;
1991 rxq->hw_time_low = rxq->time_high;
1993 rxq->hw_time_update = rte_get_timer_cycles() /
1994 (rte_get_timer_hz() / 1000);
1995 *RTE_MBUF_DYNFIELD(rxm,
1996 (ice_timestamp_dynfield_offset),
1997 rte_mbuf_timestamp_t *) = ts_ns;
1998 pkt_flags |= ice_timestamp_dynflag;
2001 if (ad->ptp_ena && ((first_seg->packet_type & RTE_PTYPE_L2_MASK)
2002 == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
2004 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2005 first_seg->timesync = rxq->queue_id;
2006 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
2009 first_seg->ol_flags |= pkt_flags;
2010 /* Prefetch data of first segment, if configured to do so. */
2011 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
2012 first_seg->data_off));
2013 rx_pkts[nb_rx++] = first_seg;
2017 /* Record index of the next RX descriptor to probe. */
2018 rxq->rx_tail = rx_id;
2019 rxq->pkt_first_seg = first_seg;
2020 rxq->pkt_last_seg = last_seg;
2023 * If the number of free RX descriptors is greater than the RX free
2024 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
2025 * register. Update the RDT with the value of the last processed RX
2026 * descriptor minus 1, to guarantee that the RDT register is never
2027 * equal to the RDH register, which creates a "full" ring situation
2028 * from the hardware point of view.
2030 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2031 if (nb_hold > rxq->rx_free_thresh) {
2032 rx_id = (uint16_t)(rx_id == 0 ?
2033 (rxq->nb_rx_desc - 1) : (rx_id - 1));
2034 /* write TAIL register */
2035 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2038 rxq->nb_rx_hold = nb_hold;
2040 /* return received packet in the burst */
2045 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2047 struct ice_adapter *ad =
2048 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2049 const uint32_t *ptypes;
2051 static const uint32_t ptypes_os[] = {
2052 /* refers to ice_get_default_pkt_type() */
2054 RTE_PTYPE_L2_ETHER_TIMESYNC,
2055 RTE_PTYPE_L2_ETHER_LLDP,
2056 RTE_PTYPE_L2_ETHER_ARP,
2057 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2058 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2061 RTE_PTYPE_L4_NONFRAG,
2065 RTE_PTYPE_TUNNEL_GRENAT,
2066 RTE_PTYPE_TUNNEL_IP,
2067 RTE_PTYPE_INNER_L2_ETHER,
2068 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2069 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2070 RTE_PTYPE_INNER_L4_FRAG,
2071 RTE_PTYPE_INNER_L4_ICMP,
2072 RTE_PTYPE_INNER_L4_NONFRAG,
2073 RTE_PTYPE_INNER_L4_SCTP,
2074 RTE_PTYPE_INNER_L4_TCP,
2075 RTE_PTYPE_INNER_L4_UDP,
2079 static const uint32_t ptypes_comms[] = {
2080 /* refers to ice_get_default_pkt_type() */
2082 RTE_PTYPE_L2_ETHER_TIMESYNC,
2083 RTE_PTYPE_L2_ETHER_LLDP,
2084 RTE_PTYPE_L2_ETHER_ARP,
2085 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2086 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2089 RTE_PTYPE_L4_NONFRAG,
2093 RTE_PTYPE_TUNNEL_GRENAT,
2094 RTE_PTYPE_TUNNEL_IP,
2095 RTE_PTYPE_INNER_L2_ETHER,
2096 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2097 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2098 RTE_PTYPE_INNER_L4_FRAG,
2099 RTE_PTYPE_INNER_L4_ICMP,
2100 RTE_PTYPE_INNER_L4_NONFRAG,
2101 RTE_PTYPE_INNER_L4_SCTP,
2102 RTE_PTYPE_INNER_L4_TCP,
2103 RTE_PTYPE_INNER_L4_UDP,
2104 RTE_PTYPE_TUNNEL_GTPC,
2105 RTE_PTYPE_TUNNEL_GTPU,
2106 RTE_PTYPE_L2_ETHER_PPPOE,
2110 if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
2111 ptypes = ptypes_comms;
2115 if (dev->rx_pkt_burst == ice_recv_pkts ||
2116 dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
2117 dev->rx_pkt_burst == ice_recv_scattered_pkts)
2121 if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
2122 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
2123 #ifdef CC_AVX512_SUPPORT
2124 dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
2125 dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
2126 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
2127 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
2129 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
2130 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
2131 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2132 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2140 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2142 volatile union ice_rx_flex_desc *rxdp;
2143 struct ice_rx_queue *rxq = rx_queue;
2146 if (unlikely(offset >= rxq->nb_rx_desc))
2149 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2150 return RTE_ETH_RX_DESC_UNAVAIL;
2152 desc = rxq->rx_tail + offset;
2153 if (desc >= rxq->nb_rx_desc)
2154 desc -= rxq->nb_rx_desc;
2156 rxdp = &rxq->rx_ring[desc];
2157 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2158 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2159 return RTE_ETH_RX_DESC_DONE;
2161 return RTE_ETH_RX_DESC_AVAIL;
2165 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2167 struct ice_tx_queue *txq = tx_queue;
2168 volatile uint64_t *status;
2169 uint64_t mask, expect;
2172 if (unlikely(offset >= txq->nb_tx_desc))
2175 desc = txq->tx_tail + offset;
2176 /* go to next desc that has the RS bit */
2177 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2179 if (desc >= txq->nb_tx_desc) {
2180 desc -= txq->nb_tx_desc;
2181 if (desc >= txq->nb_tx_desc)
2182 desc -= txq->nb_tx_desc;
2185 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2186 mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2187 expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2188 ICE_TXD_QW1_DTYPE_S);
2189 if ((*status & mask) == expect)
2190 return RTE_ETH_TX_DESC_DONE;
2192 return RTE_ETH_TX_DESC_FULL;
2196 ice_free_queues(struct rte_eth_dev *dev)
2200 PMD_INIT_FUNC_TRACE();
2202 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2203 if (!dev->data->rx_queues[i])
2205 ice_rx_queue_release(dev->data->rx_queues[i]);
2206 dev->data->rx_queues[i] = NULL;
2208 dev->data->nb_rx_queues = 0;
2210 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2211 if (!dev->data->tx_queues[i])
2213 ice_tx_queue_release(dev->data->tx_queues[i]);
2214 dev->data->tx_queues[i] = NULL;
2216 dev->data->nb_tx_queues = 0;
2219 #define ICE_FDIR_NUM_TX_DESC ICE_MIN_RING_DESC
2220 #define ICE_FDIR_NUM_RX_DESC ICE_MIN_RING_DESC
2223 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2225 struct ice_tx_queue *txq;
2226 const struct rte_memzone *tz = NULL;
2228 struct rte_eth_dev *dev;
2231 PMD_DRV_LOG(ERR, "PF is not available");
2235 dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2237 /* Allocate the TX queue data structure. */
2238 txq = rte_zmalloc_socket("ice fdir tx queue",
2239 sizeof(struct ice_tx_queue),
2240 RTE_CACHE_LINE_SIZE,
2243 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2244 "tx queue structure.");
2248 /* Allocate TX hardware ring descriptors. */
2249 ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2250 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2252 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2253 ICE_FDIR_QUEUE_ID, ring_size,
2254 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2256 ice_tx_queue_release(txq);
2257 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2262 txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2263 txq->queue_id = ICE_FDIR_QUEUE_ID;
2264 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2265 txq->vsi = pf->fdir.fdir_vsi;
2267 txq->tx_ring_dma = tz->iova;
2268 txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2270 * don't need to allocate software ring and reset for the fdir
2271 * program queue just set the queue has been configured.
2276 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2282 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2284 struct ice_rx_queue *rxq;
2285 const struct rte_memzone *rz = NULL;
2287 struct rte_eth_dev *dev;
2290 PMD_DRV_LOG(ERR, "PF is not available");
2294 dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2296 /* Allocate the RX queue data structure. */
2297 rxq = rte_zmalloc_socket("ice fdir rx queue",
2298 sizeof(struct ice_rx_queue),
2299 RTE_CACHE_LINE_SIZE,
2302 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2303 "rx queue structure.");
2307 /* Allocate RX hardware ring descriptors. */
2308 ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2309 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2311 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2312 ICE_FDIR_QUEUE_ID, ring_size,
2313 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2315 ice_rx_queue_release(rxq);
2316 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2321 rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2322 rxq->queue_id = ICE_FDIR_QUEUE_ID;
2323 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2324 rxq->vsi = pf->fdir.fdir_vsi;
2326 rxq->rx_ring_dma = rz->iova;
2327 memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2328 sizeof(union ice_32byte_rx_desc));
2329 rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2332 * Don't need to allocate software ring and reset for the fdir
2333 * rx queue, just set the queue has been configured.
2338 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2344 ice_recv_pkts(void *rx_queue,
2345 struct rte_mbuf **rx_pkts,
2348 struct ice_rx_queue *rxq = rx_queue;
2349 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2350 volatile union ice_rx_flex_desc *rxdp;
2351 union ice_rx_flex_desc rxd;
2352 struct ice_rx_entry *sw_ring = rxq->sw_ring;
2353 struct ice_rx_entry *rxe;
2354 struct rte_mbuf *nmb; /* new allocated mbuf */
2355 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2356 uint16_t rx_id = rxq->rx_tail;
2358 uint16_t nb_hold = 0;
2359 uint16_t rx_packet_len;
2360 uint16_t rx_stat_err0;
2363 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2364 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2365 bool is_tsinit = false;
2367 struct ice_vsi *vsi = rxq->vsi;
2368 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2369 struct ice_adapter *ad = rxq->vsi->adapter;
2371 if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
2372 uint64_t sw_cur_time = rte_get_timer_cycles() / (rte_get_timer_hz() / 1000);
2374 if (unlikely(sw_cur_time - rxq->hw_time_update > 4))
2379 while (nb_rx < nb_pkts) {
2380 rxdp = &rx_ring[rx_id];
2381 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2383 /* Check the DD bit first */
2384 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2388 nmb = rte_mbuf_raw_alloc(rxq->mp);
2389 if (unlikely(!nmb)) {
2390 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2393 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2396 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2398 if (unlikely(rx_id == rxq->nb_rx_desc))
2403 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2406 * fill the read format of descriptor with physic address in
2407 * new allocated mbuf: nmb
2409 rxdp->read.hdr_addr = 0;
2410 rxdp->read.pkt_addr = dma_addr;
2412 /* calculate rx_packet_len of the received pkt */
2413 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2414 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2416 /* fill old mbuf with received descriptor: rxd */
2417 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2418 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2421 rxm->pkt_len = rx_packet_len;
2422 rxm->data_len = rx_packet_len;
2423 rxm->port = rxq->port_id;
2424 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2425 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2426 ice_rxd_to_vlan_tci(rxm, &rxd);
2427 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, rxm, &rxd);
2428 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2429 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2430 if (ice_timestamp_dynflag > 0) {
2432 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2433 if (unlikely(is_tsinit)) {
2434 ts_ns = ice_tstamp_convert_32b_64b(hw, ad, 1, rxq->time_high);
2435 rxq->hw_time_low = (uint32_t)ts_ns;
2436 rxq->hw_time_high = (uint32_t)(ts_ns >> 32);
2439 if (rxq->time_high < rxq->hw_time_low)
2440 rxq->hw_time_high += 1;
2441 ts_ns = (uint64_t)rxq->hw_time_high << 32 | rxq->time_high;
2442 rxq->hw_time_low = rxq->time_high;
2444 rxq->hw_time_update = rte_get_timer_cycles() /
2445 (rte_get_timer_hz() / 1000);
2446 *RTE_MBUF_DYNFIELD(rxm,
2447 (ice_timestamp_dynfield_offset),
2448 rte_mbuf_timestamp_t *) = ts_ns;
2449 pkt_flags |= ice_timestamp_dynflag;
2452 if (ad->ptp_ena && ((rxm->packet_type & RTE_PTYPE_L2_MASK) ==
2453 RTE_PTYPE_L2_ETHER_TIMESYNC)) {
2455 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2456 rxm->timesync = rxq->queue_id;
2457 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
2460 rxm->ol_flags |= pkt_flags;
2461 /* copy old mbuf to rx_pkts */
2462 rx_pkts[nb_rx++] = rxm;
2465 rxq->rx_tail = rx_id;
2467 * If the number of free RX descriptors is greater than the RX free
2468 * threshold of the queue, advance the receive tail register of queue.
2469 * Update that register with the value of the last processed RX
2470 * descriptor minus 1.
2472 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2473 if (nb_hold > rxq->rx_free_thresh) {
2474 rx_id = (uint16_t)(rx_id == 0 ?
2475 (rxq->nb_rx_desc - 1) : (rx_id - 1));
2476 /* write TAIL register */
2477 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2480 rxq->nb_rx_hold = nb_hold;
2482 /* return received packet in the burst */
2487 ice_parse_tunneling_params(uint64_t ol_flags,
2488 union ice_tx_offload tx_offload,
2489 uint32_t *cd_tunneling)
2491 /* EIPT: External (outer) IP header type */
2492 if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
2493 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2494 else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
2495 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2496 else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
2497 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2499 /* EIPLEN: External (outer) IP header length, in DWords */
2500 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2501 ICE_TXD_CTX_QW0_EIPLEN_S;
2503 /* L4TUNT: L4 Tunneling Type */
2504 switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
2505 case RTE_MBUF_F_TX_TUNNEL_IPIP:
2506 /* for non UDP / GRE tunneling, set to 00b */
2508 case RTE_MBUF_F_TX_TUNNEL_VXLAN:
2509 case RTE_MBUF_F_TX_TUNNEL_GTP:
2510 case RTE_MBUF_F_TX_TUNNEL_GENEVE:
2511 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2513 case RTE_MBUF_F_TX_TUNNEL_GRE:
2514 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2517 PMD_TX_LOG(ERR, "Tunnel type not supported");
2521 /* L4TUNLEN: L4 Tunneling Length, in Words
2523 * We depend on app to set rte_mbuf.l2_len correctly.
2524 * For IP in GRE it should be set to the length of the GRE
2526 * For MAC in GRE or MAC in UDP it should be set to the length
2527 * of the GRE or UDP headers plus the inner MAC up to including
2528 * its last Ethertype.
2529 * If MPLS labels exists, it should include them as well.
2531 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2532 ICE_TXD_CTX_QW0_NATLEN_S;
2535 * Calculate the tunneling UDP checksum.
2536 * Shall be set only if L4TUNT = 01b and EIPT is not zero
2538 if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2539 (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2540 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2544 ice_txd_enable_checksum(uint64_t ol_flags,
2546 uint32_t *td_offset,
2547 union ice_tx_offload tx_offload)
2550 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2551 *td_offset |= (tx_offload.outer_l2_len >> 1)
2552 << ICE_TX_DESC_LEN_MACLEN_S;
2554 *td_offset |= (tx_offload.l2_len >> 1)
2555 << ICE_TX_DESC_LEN_MACLEN_S;
2557 /* Enable L3 checksum offloads */
2558 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
2559 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2560 *td_offset |= (tx_offload.l3_len >> 2) <<
2561 ICE_TX_DESC_LEN_IPLEN_S;
2562 } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2563 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2564 *td_offset |= (tx_offload.l3_len >> 2) <<
2565 ICE_TX_DESC_LEN_IPLEN_S;
2566 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2567 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2568 *td_offset |= (tx_offload.l3_len >> 2) <<
2569 ICE_TX_DESC_LEN_IPLEN_S;
2572 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2573 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2574 *td_offset |= (tx_offload.l4_len >> 2) <<
2575 ICE_TX_DESC_LEN_L4_LEN_S;
2579 /* Enable L4 checksum offloads */
2580 switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2581 case RTE_MBUF_F_TX_TCP_CKSUM:
2582 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2583 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2584 ICE_TX_DESC_LEN_L4_LEN_S;
2586 case RTE_MBUF_F_TX_SCTP_CKSUM:
2587 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2588 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2589 ICE_TX_DESC_LEN_L4_LEN_S;
2591 case RTE_MBUF_F_TX_UDP_CKSUM:
2592 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2593 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2594 ICE_TX_DESC_LEN_L4_LEN_S;
2602 ice_xmit_cleanup(struct ice_tx_queue *txq)
2604 struct ice_tx_entry *sw_ring = txq->sw_ring;
2605 volatile struct ice_tx_desc *txd = txq->tx_ring;
2606 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2607 uint16_t nb_tx_desc = txq->nb_tx_desc;
2608 uint16_t desc_to_clean_to;
2609 uint16_t nb_tx_to_clean;
2611 /* Determine the last descriptor needing to be cleaned */
2612 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2613 if (desc_to_clean_to >= nb_tx_desc)
2614 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2616 /* Check to make sure the last descriptor to clean is done */
2617 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2618 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2619 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2620 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2621 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2623 txq->port_id, txq->queue_id,
2624 txd[desc_to_clean_to].cmd_type_offset_bsz);
2625 /* Failed to clean any descriptors */
2629 /* Figure out how many descriptors will be cleaned */
2630 if (last_desc_cleaned > desc_to_clean_to)
2631 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2634 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2637 /* The last descriptor to clean is done, so that means all the
2638 * descriptors from the last descriptor that was cleaned
2639 * up to the last descriptor with the RS bit set
2640 * are done. Only reset the threshold descriptor.
2642 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2644 /* Update the txq to reflect the last descriptor that was cleaned */
2645 txq->last_desc_cleaned = desc_to_clean_to;
2646 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2651 /* Construct the tx flags */
2652 static inline uint64_t
2653 ice_build_ctob(uint32_t td_cmd,
2658 return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2659 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2660 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2661 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2662 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2665 /* Check if the context descriptor is needed for TX offloading */
2666 static inline uint16_t
2667 ice_calc_context_desc(uint64_t flags)
2669 static uint64_t mask = RTE_MBUF_F_TX_TCP_SEG |
2670 RTE_MBUF_F_TX_QINQ |
2671 RTE_MBUF_F_TX_OUTER_IP_CKSUM |
2672 RTE_MBUF_F_TX_TUNNEL_MASK |
2673 RTE_MBUF_F_TX_IEEE1588_TMST;
2675 return (flags & mask) ? 1 : 0;
2678 /* set ice TSO context descriptor */
2679 static inline uint64_t
2680 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2682 uint64_t ctx_desc = 0;
2683 uint32_t cd_cmd, hdr_len, cd_tso_len;
2685 if (!tx_offload.l4_len) {
2686 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2690 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2691 hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
2692 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2694 cd_cmd = ICE_TX_CTX_DESC_TSO;
2695 cd_tso_len = mbuf->pkt_len - hdr_len;
2696 ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2697 ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2698 ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2703 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2704 #define ICE_MAX_DATA_PER_TXD \
2705 (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2706 /* Calculate the number of TX descriptors needed for each pkt */
2707 static inline uint16_t
2708 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2710 struct rte_mbuf *txd = tx_pkt;
2713 while (txd != NULL) {
2714 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2722 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2724 struct ice_tx_queue *txq;
2725 volatile struct ice_tx_desc *tx_ring;
2726 volatile struct ice_tx_desc *txd;
2727 struct ice_tx_entry *sw_ring;
2728 struct ice_tx_entry *txe, *txn;
2729 struct rte_mbuf *tx_pkt;
2730 struct rte_mbuf *m_seg;
2731 uint32_t cd_tunneling_params;
2736 uint32_t td_cmd = 0;
2737 uint32_t td_offset = 0;
2738 uint32_t td_tag = 0;
2741 uint64_t buf_dma_addr;
2743 union ice_tx_offload tx_offload = {0};
2746 sw_ring = txq->sw_ring;
2747 tx_ring = txq->tx_ring;
2748 tx_id = txq->tx_tail;
2749 txe = &sw_ring[tx_id];
2751 /* Check if the descriptor ring needs to be cleaned. */
2752 if (txq->nb_tx_free < txq->tx_free_thresh)
2753 (void)ice_xmit_cleanup(txq);
2755 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2756 tx_pkt = *tx_pkts++;
2761 ol_flags = tx_pkt->ol_flags;
2762 tx_offload.l2_len = tx_pkt->l2_len;
2763 tx_offload.l3_len = tx_pkt->l3_len;
2764 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2765 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2766 tx_offload.l4_len = tx_pkt->l4_len;
2767 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2768 /* Calculate the number of context descriptors needed. */
2769 nb_ctx = ice_calc_context_desc(ol_flags);
2771 /* The number of descriptors that must be allocated for
2772 * a packet equals to the number of the segments of that
2773 * packet plus the number of context descriptor if needed.
2774 * Recalculate the needed tx descs when TSO enabled in case
2775 * the mbuf data size exceeds max data size that hw allows
2778 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2779 nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2782 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2783 tx_last = (uint16_t)(tx_id + nb_used - 1);
2786 if (tx_last >= txq->nb_tx_desc)
2787 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2789 if (nb_used > txq->nb_tx_free) {
2790 if (ice_xmit_cleanup(txq) != 0) {
2795 if (unlikely(nb_used > txq->tx_rs_thresh)) {
2796 while (nb_used > txq->nb_tx_free) {
2797 if (ice_xmit_cleanup(txq) != 0) {
2806 /* Descriptor based VLAN insertion */
2807 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
2808 td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2809 td_tag = tx_pkt->vlan_tci;
2812 /* Fill in tunneling parameters if necessary */
2813 cd_tunneling_params = 0;
2814 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2815 ice_parse_tunneling_params(ol_flags, tx_offload,
2816 &cd_tunneling_params);
2818 /* Enable checksum offloading */
2819 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2820 ice_txd_enable_checksum(ol_flags, &td_cmd,
2821 &td_offset, tx_offload);
2824 /* Setup TX context descriptor if required */
2825 volatile struct ice_tx_ctx_desc *ctx_txd =
2826 (volatile struct ice_tx_ctx_desc *)
2828 uint16_t cd_l2tag2 = 0;
2829 uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2831 txn = &sw_ring[txe->next_id];
2832 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2834 rte_pktmbuf_free_seg(txe->mbuf);
2838 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2839 cd_type_cmd_tso_mss |=
2840 ice_set_tso_ctx(tx_pkt, tx_offload);
2841 else if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
2842 cd_type_cmd_tso_mss |=
2843 ((uint64_t)ICE_TX_CTX_DESC_TSYN <<
2844 ICE_TXD_CTX_QW1_CMD_S);
2846 ctx_txd->tunneling_params =
2847 rte_cpu_to_le_32(cd_tunneling_params);
2849 /* TX context descriptor based double VLAN insert */
2850 if (ol_flags & RTE_MBUF_F_TX_QINQ) {
2851 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2852 cd_type_cmd_tso_mss |=
2853 ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2854 ICE_TXD_CTX_QW1_CMD_S);
2856 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2858 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2860 txe->last_id = tx_last;
2861 tx_id = txe->next_id;
2867 txd = &tx_ring[tx_id];
2868 txn = &sw_ring[txe->next_id];
2871 rte_pktmbuf_free_seg(txe->mbuf);
2874 /* Setup TX Descriptor */
2875 slen = m_seg->data_len;
2876 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2878 while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
2879 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2880 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2881 txd->cmd_type_offset_bsz =
2882 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2883 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2884 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2885 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2886 ICE_TXD_QW1_TX_BUF_SZ_S) |
2887 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2889 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2890 slen -= ICE_MAX_DATA_PER_TXD;
2892 txe->last_id = tx_last;
2893 tx_id = txe->next_id;
2895 txd = &tx_ring[tx_id];
2896 txn = &sw_ring[txe->next_id];
2899 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2900 txd->cmd_type_offset_bsz =
2901 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2902 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2903 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2904 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2905 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2907 txe->last_id = tx_last;
2908 tx_id = txe->next_id;
2910 m_seg = m_seg->next;
2913 /* fill the last descriptor with End of Packet (EOP) bit */
2914 td_cmd |= ICE_TX_DESC_CMD_EOP;
2915 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2916 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2918 /* set RS bit on the last descriptor of one packet */
2919 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2921 "Setting RS bit on TXD id="
2922 "%4u (port=%d queue=%d)",
2923 tx_last, txq->port_id, txq->queue_id);
2925 td_cmd |= ICE_TX_DESC_CMD_RS;
2927 /* Update txq RS bit counters */
2928 txq->nb_tx_used = 0;
2930 txd->cmd_type_offset_bsz |=
2931 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2935 /* update Tail register */
2936 ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2937 txq->tx_tail = tx_id;
2942 static __rte_always_inline int
2943 ice_tx_free_bufs(struct ice_tx_queue *txq)
2945 struct ice_tx_entry *txep;
2948 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2949 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2950 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2953 txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2955 for (i = 0; i < txq->tx_rs_thresh; i++)
2956 rte_prefetch0((txep + i)->mbuf);
2958 if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
2959 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2960 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2964 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2965 rte_pktmbuf_free_seg(txep->mbuf);
2970 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2971 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2972 if (txq->tx_next_dd >= txq->nb_tx_desc)
2973 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2975 return txq->tx_rs_thresh;
2979 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2982 struct ice_tx_entry *swr_ring = txq->sw_ring;
2983 uint16_t i, tx_last, tx_id;
2984 uint16_t nb_tx_free_last;
2985 uint16_t nb_tx_to_clean;
2988 /* Start free mbuf from the next of tx_tail */
2989 tx_last = txq->tx_tail;
2990 tx_id = swr_ring[tx_last].next_id;
2992 if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2995 nb_tx_to_clean = txq->nb_tx_free;
2996 nb_tx_free_last = txq->nb_tx_free;
2998 free_cnt = txq->nb_tx_desc;
3000 /* Loop through swr_ring to count the amount of
3001 * freeable mubfs and packets.
3003 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
3004 for (i = 0; i < nb_tx_to_clean &&
3005 pkt_cnt < free_cnt &&
3006 tx_id != tx_last; i++) {
3007 if (swr_ring[tx_id].mbuf != NULL) {
3008 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
3009 swr_ring[tx_id].mbuf = NULL;
3012 * last segment in the packet,
3013 * increment packet count
3015 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
3018 tx_id = swr_ring[tx_id].next_id;
3021 if (txq->tx_rs_thresh > txq->nb_tx_desc -
3022 txq->nb_tx_free || tx_id == tx_last)
3025 if (pkt_cnt < free_cnt) {
3026 if (ice_xmit_cleanup(txq))
3029 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
3030 nb_tx_free_last = txq->nb_tx_free;
3034 return (int)pkt_cnt;
3039 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
3040 uint32_t free_cnt __rte_unused)
3047 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
3052 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
3053 free_cnt = txq->nb_tx_desc;
3055 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
3057 for (i = 0; i < cnt; i += n) {
3058 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
3061 n = ice_tx_free_bufs(txq);
3071 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
3073 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
3074 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
3075 struct ice_adapter *ad =
3076 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3079 if (ad->tx_vec_allowed)
3080 return ice_tx_done_cleanup_vec(q, free_cnt);
3082 if (ad->tx_simple_allowed)
3083 return ice_tx_done_cleanup_simple(q, free_cnt);
3085 return ice_tx_done_cleanup_full(q, free_cnt);
3088 /* Populate 4 descriptors with data from 4 mbufs */
3090 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3095 for (i = 0; i < 4; i++, txdp++, pkts++) {
3096 dma_addr = rte_mbuf_data_iova(*pkts);
3097 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3098 txdp->cmd_type_offset_bsz =
3099 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3100 (*pkts)->data_len, 0);
3104 /* Populate 1 descriptor with data from 1 mbuf */
3106 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3110 dma_addr = rte_mbuf_data_iova(*pkts);
3111 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3112 txdp->cmd_type_offset_bsz =
3113 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3114 (*pkts)->data_len, 0);
3118 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
3121 volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
3122 struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
3123 const int N_PER_LOOP = 4;
3124 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
3125 int mainpart, leftover;
3129 * Process most of the packets in chunks of N pkts. Any
3130 * leftover packets will get processed one at a time.
3132 mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
3133 leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
3134 for (i = 0; i < mainpart; i += N_PER_LOOP) {
3135 /* Copy N mbuf pointers to the S/W ring */
3136 for (j = 0; j < N_PER_LOOP; ++j)
3137 (txep + i + j)->mbuf = *(pkts + i + j);
3138 tx4(txdp + i, pkts + i);
3141 if (unlikely(leftover > 0)) {
3142 for (i = 0; i < leftover; ++i) {
3143 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
3144 tx1(txdp + mainpart + i, pkts + mainpart + i);
3149 static inline uint16_t
3150 tx_xmit_pkts(struct ice_tx_queue *txq,
3151 struct rte_mbuf **tx_pkts,
3154 volatile struct ice_tx_desc *txr = txq->tx_ring;
3158 * Begin scanning the H/W ring for done descriptors when the number
3159 * of available descriptors drops below tx_free_thresh. For each done
3160 * descriptor, free the associated buffer.
3162 if (txq->nb_tx_free < txq->tx_free_thresh)
3163 ice_tx_free_bufs(txq);
3165 /* Use available descriptor only */
3166 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
3167 if (unlikely(!nb_pkts))
3170 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
3171 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
3172 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
3173 ice_tx_fill_hw_ring(txq, tx_pkts, n);
3174 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3175 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3177 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3181 /* Fill hardware descriptor ring with mbuf data */
3182 ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3183 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3185 /* Determine if RS bit needs to be set */
3186 if (txq->tx_tail > txq->tx_next_rs) {
3187 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3188 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3191 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3192 if (txq->tx_next_rs >= txq->nb_tx_desc)
3193 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3196 if (txq->tx_tail >= txq->nb_tx_desc)
3199 /* Update the tx tail register */
3200 ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3206 ice_xmit_pkts_simple(void *tx_queue,
3207 struct rte_mbuf **tx_pkts,
3212 if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3213 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3217 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3220 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3221 &tx_pkts[nb_tx], num);
3222 nb_tx = (uint16_t)(nb_tx + ret);
3223 nb_pkts = (uint16_t)(nb_pkts - ret);
3232 ice_set_rx_function(struct rte_eth_dev *dev)
3234 PMD_INIT_FUNC_TRACE();
3235 struct ice_adapter *ad =
3236 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3238 struct ice_rx_queue *rxq;
3240 int rx_check_ret = -1;
3242 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3243 ad->rx_use_avx512 = false;
3244 ad->rx_use_avx2 = false;
3245 rx_check_ret = ice_rx_vec_dev_check(dev);
3248 ad->rx_vec_offload_support =
3249 (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH);
3250 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3251 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3252 ad->rx_vec_allowed = true;
3253 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3254 rxq = dev->data->rx_queues[i];
3255 if (rxq && ice_rxq_vec_setup(rxq)) {
3256 ad->rx_vec_allowed = false;
3261 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3262 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3263 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3264 #ifdef CC_AVX512_SUPPORT
3265 ad->rx_use_avx512 = true;
3268 "AVX512 is not supported in build env");
3270 if (!ad->rx_use_avx512 &&
3271 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3272 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3273 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3274 ad->rx_use_avx2 = true;
3277 ad->rx_vec_allowed = false;
3281 if (ad->rx_vec_allowed) {
3282 if (dev->data->scattered_rx) {
3283 if (ad->rx_use_avx512) {
3284 #ifdef CC_AVX512_SUPPORT
3285 if (ad->rx_vec_offload_support) {
3287 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3288 dev->data->port_id);
3290 ice_recv_scattered_pkts_vec_avx512_offload;
3293 "Using AVX512 Vector Scattered Rx (port %d).",
3294 dev->data->port_id);
3296 ice_recv_scattered_pkts_vec_avx512;
3299 } else if (ad->rx_use_avx2) {
3300 if (ad->rx_vec_offload_support) {
3302 "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3303 dev->data->port_id);
3305 ice_recv_scattered_pkts_vec_avx2_offload;
3308 "Using AVX2 Vector Scattered Rx (port %d).",
3309 dev->data->port_id);
3311 ice_recv_scattered_pkts_vec_avx2;
3315 "Using Vector Scattered Rx (port %d).",
3316 dev->data->port_id);
3317 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3320 if (ad->rx_use_avx512) {
3321 #ifdef CC_AVX512_SUPPORT
3322 if (ad->rx_vec_offload_support) {
3324 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3325 dev->data->port_id);
3327 ice_recv_pkts_vec_avx512_offload;
3330 "Using AVX512 Vector Rx (port %d).",
3331 dev->data->port_id);
3333 ice_recv_pkts_vec_avx512;
3336 } else if (ad->rx_use_avx2) {
3337 if (ad->rx_vec_offload_support) {
3339 "Using AVX2 OFFLOAD Vector Rx (port %d).",
3340 dev->data->port_id);
3342 ice_recv_pkts_vec_avx2_offload;
3345 "Using AVX2 Vector Rx (port %d).",
3346 dev->data->port_id);
3348 ice_recv_pkts_vec_avx2;
3352 "Using Vector Rx (port %d).",
3353 dev->data->port_id);
3354 dev->rx_pkt_burst = ice_recv_pkts_vec;
3362 if (dev->data->scattered_rx) {
3363 /* Set the non-LRO scattered function */
3365 "Using a Scattered function on port %d.",
3366 dev->data->port_id);
3367 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3368 } else if (ad->rx_bulk_alloc_allowed) {
3370 "Rx Burst Bulk Alloc Preconditions are "
3371 "satisfied. Rx Burst Bulk Alloc function "
3372 "will be used on port %d.",
3373 dev->data->port_id);
3374 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3377 "Rx Burst Bulk Alloc Preconditions are not "
3378 "satisfied, Normal Rx will be used on port %d.",
3379 dev->data->port_id);
3380 dev->rx_pkt_burst = ice_recv_pkts;
3384 static const struct {
3385 eth_rx_burst_t pkt_burst;
3387 } ice_rx_burst_infos[] = {
3388 { ice_recv_scattered_pkts, "Scalar Scattered" },
3389 { ice_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3390 { ice_recv_pkts, "Scalar" },
3392 #ifdef CC_AVX512_SUPPORT
3393 { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3394 { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3395 { ice_recv_pkts_vec_avx512, "Vector AVX512" },
3396 { ice_recv_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3398 { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3399 { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3400 { ice_recv_pkts_vec_avx2, "Vector AVX2" },
3401 { ice_recv_pkts_vec_avx2_offload, "Offload Vector AVX2" },
3402 { ice_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3403 { ice_recv_pkts_vec, "Vector SSE" },
3408 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3409 struct rte_eth_burst_mode *mode)
3411 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3415 for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3416 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3417 snprintf(mode->info, sizeof(mode->info), "%s",
3418 ice_rx_burst_infos[i].info);
3428 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3430 struct ice_adapter *ad =
3431 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3433 /* Use a simple Tx queue if possible (only fast free is allowed) */
3434 ad->tx_simple_allowed =
3436 (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3437 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3439 if (ad->tx_simple_allowed)
3440 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3444 "Simple Tx can NOT be enabled on Tx queue %u.",
3448 /*********************************************************************
3452 **********************************************************************/
3453 /* The default values of TSO MSS */
3454 #define ICE_MIN_TSO_MSS 64
3455 #define ICE_MAX_TSO_MSS 9728
3456 #define ICE_MAX_TSO_FRAME_SIZE 262144
3458 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3465 for (i = 0; i < nb_pkts; i++) {
3467 ol_flags = m->ol_flags;
3469 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
3470 (m->tso_segsz < ICE_MIN_TSO_MSS ||
3471 m->tso_segsz > ICE_MAX_TSO_MSS ||
3472 m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3474 * MSS outside the range are considered malicious
3480 #ifdef RTE_ETHDEV_DEBUG_TX
3481 ret = rte_validate_tx_offload(m);
3487 ret = rte_net_intel_cksum_prepare(m);
3497 ice_set_tx_function(struct rte_eth_dev *dev)
3499 struct ice_adapter *ad =
3500 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3502 struct ice_tx_queue *txq;
3504 int tx_check_ret = -1;
3506 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3507 ad->tx_use_avx2 = false;
3508 ad->tx_use_avx512 = false;
3509 tx_check_ret = ice_tx_vec_dev_check(dev);
3510 if (tx_check_ret >= 0 &&
3511 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3512 ad->tx_vec_allowed = true;
3514 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3515 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3516 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3517 #ifdef CC_AVX512_SUPPORT
3518 ad->tx_use_avx512 = true;
3521 "AVX512 is not supported in build env");
3523 if (!ad->tx_use_avx512 &&
3524 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3525 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3526 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3527 ad->tx_use_avx2 = true;
3529 if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3530 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3531 ad->tx_vec_allowed = false;
3533 if (ad->tx_vec_allowed) {
3534 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3535 txq = dev->data->tx_queues[i];
3536 if (txq && ice_txq_vec_setup(txq)) {
3537 ad->tx_vec_allowed = false;
3543 ad->tx_vec_allowed = false;
3547 if (ad->tx_vec_allowed) {
3548 dev->tx_pkt_prepare = NULL;
3549 if (ad->tx_use_avx512) {
3550 #ifdef CC_AVX512_SUPPORT
3551 if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3553 "Using AVX512 OFFLOAD Vector Tx (port %d).",
3554 dev->data->port_id);
3556 ice_xmit_pkts_vec_avx512_offload;
3557 dev->tx_pkt_prepare = ice_prep_pkts;
3560 "Using AVX512 Vector Tx (port %d).",
3561 dev->data->port_id);
3562 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3566 if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3568 "Using AVX2 OFFLOAD Vector Tx (port %d).",
3569 dev->data->port_id);
3571 ice_xmit_pkts_vec_avx2_offload;
3572 dev->tx_pkt_prepare = ice_prep_pkts;
3574 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3575 ad->tx_use_avx2 ? "avx2 " : "",
3576 dev->data->port_id);
3577 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3578 ice_xmit_pkts_vec_avx2 :
3587 if (ad->tx_simple_allowed) {
3588 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3589 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3590 dev->tx_pkt_prepare = NULL;
3592 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3593 dev->tx_pkt_burst = ice_xmit_pkts;
3594 dev->tx_pkt_prepare = ice_prep_pkts;
3598 static const struct {
3599 eth_tx_burst_t pkt_burst;
3601 } ice_tx_burst_infos[] = {
3602 { ice_xmit_pkts_simple, "Scalar Simple" },
3603 { ice_xmit_pkts, "Scalar" },
3605 #ifdef CC_AVX512_SUPPORT
3606 { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3607 { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3609 { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3610 { ice_xmit_pkts_vec_avx2_offload, "Offload Vector AVX2" },
3611 { ice_xmit_pkts_vec, "Vector SSE" },
3616 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3617 struct rte_eth_burst_mode *mode)
3619 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3623 for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3624 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3625 snprintf(mode->info, sizeof(mode->info), "%s",
3626 ice_tx_burst_infos[i].info);
3635 /* For each value it means, datasheet of hardware can tell more details
3637 * @note: fix ice_dev_supported_ptypes_get() if any change here.
3639 static inline uint32_t
3640 ice_get_default_pkt_type(uint16_t ptype)
3642 static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3643 __rte_cache_aligned = {
3646 [1] = RTE_PTYPE_L2_ETHER,
3647 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3648 /* [3] - [5] reserved */
3649 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3650 /* [7] - [10] reserved */
3651 [11] = RTE_PTYPE_L2_ETHER_ARP,
3652 /* [12] - [21] reserved */
3654 /* Non tunneled IPv4 */
3655 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3657 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3658 RTE_PTYPE_L4_NONFRAG,
3659 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3662 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3664 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3666 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3670 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3671 RTE_PTYPE_TUNNEL_IP |
3672 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3673 RTE_PTYPE_INNER_L4_FRAG,
3674 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3675 RTE_PTYPE_TUNNEL_IP |
3676 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3677 RTE_PTYPE_INNER_L4_NONFRAG,
3678 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3679 RTE_PTYPE_TUNNEL_IP |
3680 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3681 RTE_PTYPE_INNER_L4_UDP,
3683 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3684 RTE_PTYPE_TUNNEL_IP |
3685 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3686 RTE_PTYPE_INNER_L4_TCP,
3687 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3688 RTE_PTYPE_TUNNEL_IP |
3689 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3690 RTE_PTYPE_INNER_L4_SCTP,
3691 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3692 RTE_PTYPE_TUNNEL_IP |
3693 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3694 RTE_PTYPE_INNER_L4_ICMP,
3697 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3698 RTE_PTYPE_TUNNEL_IP |
3699 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3700 RTE_PTYPE_INNER_L4_FRAG,
3701 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3702 RTE_PTYPE_TUNNEL_IP |
3703 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3704 RTE_PTYPE_INNER_L4_NONFRAG,
3705 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3706 RTE_PTYPE_TUNNEL_IP |
3707 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3708 RTE_PTYPE_INNER_L4_UDP,
3710 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3711 RTE_PTYPE_TUNNEL_IP |
3712 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3713 RTE_PTYPE_INNER_L4_TCP,
3714 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3715 RTE_PTYPE_TUNNEL_IP |
3716 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3717 RTE_PTYPE_INNER_L4_SCTP,
3718 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3719 RTE_PTYPE_TUNNEL_IP |
3720 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3721 RTE_PTYPE_INNER_L4_ICMP,
3723 /* IPv4 --> GRE/Teredo/VXLAN */
3724 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3725 RTE_PTYPE_TUNNEL_GRENAT,
3727 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3728 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3729 RTE_PTYPE_TUNNEL_GRENAT |
3730 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3731 RTE_PTYPE_INNER_L4_FRAG,
3732 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3733 RTE_PTYPE_TUNNEL_GRENAT |
3734 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3735 RTE_PTYPE_INNER_L4_NONFRAG,
3736 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3737 RTE_PTYPE_TUNNEL_GRENAT |
3738 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3739 RTE_PTYPE_INNER_L4_UDP,
3741 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3742 RTE_PTYPE_TUNNEL_GRENAT |
3743 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3744 RTE_PTYPE_INNER_L4_TCP,
3745 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3746 RTE_PTYPE_TUNNEL_GRENAT |
3747 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3748 RTE_PTYPE_INNER_L4_SCTP,
3749 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3750 RTE_PTYPE_TUNNEL_GRENAT |
3751 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3752 RTE_PTYPE_INNER_L4_ICMP,
3754 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3755 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3756 RTE_PTYPE_TUNNEL_GRENAT |
3757 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3758 RTE_PTYPE_INNER_L4_FRAG,
3759 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3760 RTE_PTYPE_TUNNEL_GRENAT |
3761 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3762 RTE_PTYPE_INNER_L4_NONFRAG,
3763 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3764 RTE_PTYPE_TUNNEL_GRENAT |
3765 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3766 RTE_PTYPE_INNER_L4_UDP,
3768 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3769 RTE_PTYPE_TUNNEL_GRENAT |
3770 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3771 RTE_PTYPE_INNER_L4_TCP,
3772 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3773 RTE_PTYPE_TUNNEL_GRENAT |
3774 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3775 RTE_PTYPE_INNER_L4_SCTP,
3776 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3777 RTE_PTYPE_TUNNEL_GRENAT |
3778 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3779 RTE_PTYPE_INNER_L4_ICMP,
3781 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3782 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3783 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3785 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3786 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3787 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3788 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3789 RTE_PTYPE_INNER_L4_FRAG,
3790 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3791 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3792 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3793 RTE_PTYPE_INNER_L4_NONFRAG,
3794 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3795 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3796 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3797 RTE_PTYPE_INNER_L4_UDP,
3799 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3800 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3801 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3802 RTE_PTYPE_INNER_L4_TCP,
3803 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3804 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3805 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3806 RTE_PTYPE_INNER_L4_SCTP,
3807 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3808 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3809 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3810 RTE_PTYPE_INNER_L4_ICMP,
3812 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3813 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3814 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3815 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3816 RTE_PTYPE_INNER_L4_FRAG,
3817 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3818 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3819 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3820 RTE_PTYPE_INNER_L4_NONFRAG,
3821 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3822 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3823 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3824 RTE_PTYPE_INNER_L4_UDP,
3826 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3827 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3828 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3829 RTE_PTYPE_INNER_L4_TCP,
3830 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3831 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3832 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3833 RTE_PTYPE_INNER_L4_SCTP,
3834 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3835 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3836 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3837 RTE_PTYPE_INNER_L4_ICMP,
3838 /* [73] - [87] reserved */
3840 /* Non tunneled IPv6 */
3841 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3843 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3844 RTE_PTYPE_L4_NONFRAG,
3845 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3848 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3850 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3852 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3856 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3857 RTE_PTYPE_TUNNEL_IP |
3858 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3859 RTE_PTYPE_INNER_L4_FRAG,
3860 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3861 RTE_PTYPE_TUNNEL_IP |
3862 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3863 RTE_PTYPE_INNER_L4_NONFRAG,
3864 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3865 RTE_PTYPE_TUNNEL_IP |
3866 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3867 RTE_PTYPE_INNER_L4_UDP,
3869 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3870 RTE_PTYPE_TUNNEL_IP |
3871 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3872 RTE_PTYPE_INNER_L4_TCP,
3873 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3874 RTE_PTYPE_TUNNEL_IP |
3875 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3876 RTE_PTYPE_INNER_L4_SCTP,
3877 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3878 RTE_PTYPE_TUNNEL_IP |
3879 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3880 RTE_PTYPE_INNER_L4_ICMP,
3883 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3884 RTE_PTYPE_TUNNEL_IP |
3885 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3886 RTE_PTYPE_INNER_L4_FRAG,
3887 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3888 RTE_PTYPE_TUNNEL_IP |
3889 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3890 RTE_PTYPE_INNER_L4_NONFRAG,
3891 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3892 RTE_PTYPE_TUNNEL_IP |
3893 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3894 RTE_PTYPE_INNER_L4_UDP,
3895 /* [105] reserved */
3896 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3897 RTE_PTYPE_TUNNEL_IP |
3898 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3899 RTE_PTYPE_INNER_L4_TCP,
3900 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3901 RTE_PTYPE_TUNNEL_IP |
3902 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3903 RTE_PTYPE_INNER_L4_SCTP,
3904 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3905 RTE_PTYPE_TUNNEL_IP |
3906 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3907 RTE_PTYPE_INNER_L4_ICMP,
3909 /* IPv6 --> GRE/Teredo/VXLAN */
3910 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3911 RTE_PTYPE_TUNNEL_GRENAT,
3913 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3914 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3915 RTE_PTYPE_TUNNEL_GRENAT |
3916 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3917 RTE_PTYPE_INNER_L4_FRAG,
3918 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3919 RTE_PTYPE_TUNNEL_GRENAT |
3920 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3921 RTE_PTYPE_INNER_L4_NONFRAG,
3922 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3923 RTE_PTYPE_TUNNEL_GRENAT |
3924 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3925 RTE_PTYPE_INNER_L4_UDP,
3926 /* [113] reserved */
3927 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3928 RTE_PTYPE_TUNNEL_GRENAT |
3929 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3930 RTE_PTYPE_INNER_L4_TCP,
3931 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3932 RTE_PTYPE_TUNNEL_GRENAT |
3933 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3934 RTE_PTYPE_INNER_L4_SCTP,
3935 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3936 RTE_PTYPE_TUNNEL_GRENAT |
3937 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3938 RTE_PTYPE_INNER_L4_ICMP,
3940 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3941 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3942 RTE_PTYPE_TUNNEL_GRENAT |
3943 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3944 RTE_PTYPE_INNER_L4_FRAG,
3945 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3946 RTE_PTYPE_TUNNEL_GRENAT |
3947 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3948 RTE_PTYPE_INNER_L4_NONFRAG,
3949 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3950 RTE_PTYPE_TUNNEL_GRENAT |
3951 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3952 RTE_PTYPE_INNER_L4_UDP,
3953 /* [120] reserved */
3954 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3955 RTE_PTYPE_TUNNEL_GRENAT |
3956 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3957 RTE_PTYPE_INNER_L4_TCP,
3958 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3959 RTE_PTYPE_TUNNEL_GRENAT |
3960 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3961 RTE_PTYPE_INNER_L4_SCTP,
3962 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3963 RTE_PTYPE_TUNNEL_GRENAT |
3964 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3965 RTE_PTYPE_INNER_L4_ICMP,
3967 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3968 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3969 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3971 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3972 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3973 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3974 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3975 RTE_PTYPE_INNER_L4_FRAG,
3976 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3977 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3978 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3979 RTE_PTYPE_INNER_L4_NONFRAG,
3980 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3981 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3982 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3983 RTE_PTYPE_INNER_L4_UDP,
3984 /* [128] reserved */
3985 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3986 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3987 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3988 RTE_PTYPE_INNER_L4_TCP,
3989 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3990 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3991 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3992 RTE_PTYPE_INNER_L4_SCTP,
3993 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3994 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3995 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3996 RTE_PTYPE_INNER_L4_ICMP,
3998 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3999 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4000 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4001 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4002 RTE_PTYPE_INNER_L4_FRAG,
4003 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4004 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4005 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4006 RTE_PTYPE_INNER_L4_NONFRAG,
4007 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4008 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4009 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4010 RTE_PTYPE_INNER_L4_UDP,
4011 /* [135] reserved */
4012 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4013 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4014 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4015 RTE_PTYPE_INNER_L4_TCP,
4016 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4017 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4018 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4019 RTE_PTYPE_INNER_L4_SCTP,
4020 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4021 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
4022 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4023 RTE_PTYPE_INNER_L4_ICMP,
4024 /* [139] - [299] reserved */
4027 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
4028 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
4030 /* PPPoE --> IPv4 */
4031 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
4032 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4034 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
4035 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4036 RTE_PTYPE_L4_NONFRAG,
4037 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
4038 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4040 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
4041 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4043 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
4044 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4046 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
4047 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4050 /* PPPoE --> IPv6 */
4051 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
4052 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4054 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
4055 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4056 RTE_PTYPE_L4_NONFRAG,
4057 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
4058 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4060 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
4061 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4063 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
4064 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4066 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
4067 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4069 /* [314] - [324] reserved */
4071 /* IPv4/IPv6 --> GTPC/GTPU */
4072 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4073 RTE_PTYPE_TUNNEL_GTPC,
4074 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4075 RTE_PTYPE_TUNNEL_GTPC,
4076 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4077 RTE_PTYPE_TUNNEL_GTPC,
4078 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4079 RTE_PTYPE_TUNNEL_GTPC,
4080 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4081 RTE_PTYPE_TUNNEL_GTPU,
4082 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4083 RTE_PTYPE_TUNNEL_GTPU,
4085 /* IPv4 --> GTPU --> IPv4 */
4086 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4087 RTE_PTYPE_TUNNEL_GTPU |
4088 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4089 RTE_PTYPE_INNER_L4_FRAG,
4090 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4091 RTE_PTYPE_TUNNEL_GTPU |
4092 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4093 RTE_PTYPE_INNER_L4_NONFRAG,
4094 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4095 RTE_PTYPE_TUNNEL_GTPU |
4096 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4097 RTE_PTYPE_INNER_L4_UDP,
4098 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4099 RTE_PTYPE_TUNNEL_GTPU |
4100 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4101 RTE_PTYPE_INNER_L4_TCP,
4102 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4103 RTE_PTYPE_TUNNEL_GTPU |
4104 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4105 RTE_PTYPE_INNER_L4_ICMP,
4107 /* IPv6 --> GTPU --> IPv4 */
4108 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4109 RTE_PTYPE_TUNNEL_GTPU |
4110 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4111 RTE_PTYPE_INNER_L4_FRAG,
4112 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4113 RTE_PTYPE_TUNNEL_GTPU |
4114 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4115 RTE_PTYPE_INNER_L4_NONFRAG,
4116 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4117 RTE_PTYPE_TUNNEL_GTPU |
4118 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4119 RTE_PTYPE_INNER_L4_UDP,
4120 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4121 RTE_PTYPE_TUNNEL_GTPU |
4122 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4123 RTE_PTYPE_INNER_L4_TCP,
4124 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4125 RTE_PTYPE_TUNNEL_GTPU |
4126 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4127 RTE_PTYPE_INNER_L4_ICMP,
4129 /* IPv4 --> GTPU --> IPv6 */
4130 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4131 RTE_PTYPE_TUNNEL_GTPU |
4132 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4133 RTE_PTYPE_INNER_L4_FRAG,
4134 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4135 RTE_PTYPE_TUNNEL_GTPU |
4136 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4137 RTE_PTYPE_INNER_L4_NONFRAG,
4138 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4139 RTE_PTYPE_TUNNEL_GTPU |
4140 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4141 RTE_PTYPE_INNER_L4_UDP,
4142 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4143 RTE_PTYPE_TUNNEL_GTPU |
4144 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4145 RTE_PTYPE_INNER_L4_TCP,
4146 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4147 RTE_PTYPE_TUNNEL_GTPU |
4148 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4149 RTE_PTYPE_INNER_L4_ICMP,
4151 /* IPv6 --> GTPU --> IPv6 */
4152 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4153 RTE_PTYPE_TUNNEL_GTPU |
4154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4155 RTE_PTYPE_INNER_L4_FRAG,
4156 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4157 RTE_PTYPE_TUNNEL_GTPU |
4158 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4159 RTE_PTYPE_INNER_L4_NONFRAG,
4160 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4161 RTE_PTYPE_TUNNEL_GTPU |
4162 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4163 RTE_PTYPE_INNER_L4_UDP,
4164 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4165 RTE_PTYPE_TUNNEL_GTPU |
4166 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4167 RTE_PTYPE_INNER_L4_TCP,
4168 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4169 RTE_PTYPE_TUNNEL_GTPU |
4170 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4171 RTE_PTYPE_INNER_L4_ICMP,
4173 /* IPv4 --> UDP ECPRI */
4174 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4176 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4178 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4180 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4182 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4184 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4186 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4188 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4190 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4192 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4195 /* IPV6 --> UDP ECPRI */
4196 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4198 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4200 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4202 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4204 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4206 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4208 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4210 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4212 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4214 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4216 /* All others reserved */
4219 return type_table[ptype];
4223 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4225 struct ice_adapter *ad =
4226 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4229 for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4230 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4233 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4234 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4235 (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4236 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4237 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4239 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S 4
4240 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M \
4241 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4242 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S 5
4243 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M \
4244 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4247 * check the programming status descriptor in rx queue.
4248 * done after Programming Flow Director is programmed on
4252 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4254 volatile union ice_32byte_rx_desc *rxdp;
4261 rxdp = (volatile union ice_32byte_rx_desc *)
4262 (&rxq->rx_ring[rxq->rx_tail]);
4263 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4264 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4265 >> ICE_RXD_QW1_STATUS_S;
4267 if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4269 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4270 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4271 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4272 ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4274 if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4275 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4276 else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4277 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4281 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4282 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4284 PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4288 rxdp->wb.qword1.status_error_len = 0;
4290 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4292 if (rxq->rx_tail == 0)
4293 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4295 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4301 #define ICE_FDIR_MAX_WAIT_US 10000
4304 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4306 struct ice_tx_queue *txq = pf->fdir.txq;
4307 struct ice_rx_queue *rxq = pf->fdir.rxq;
4308 volatile struct ice_fltr_desc *fdirdp;
4309 volatile struct ice_tx_desc *txdp;
4313 fdirdp = (volatile struct ice_fltr_desc *)
4314 (&txq->tx_ring[txq->tx_tail]);
4315 fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4316 fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4318 txdp = &txq->tx_ring[txq->tx_tail + 1];
4319 txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4320 td_cmd = ICE_TX_DESC_CMD_EOP |
4321 ICE_TX_DESC_CMD_RS |
4322 ICE_TX_DESC_CMD_DUMMY;
4324 txdp->cmd_type_offset_bsz =
4325 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4328 if (txq->tx_tail >= txq->nb_tx_desc)
4330 /* Update the tx tail register */
4331 ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4332 for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4333 if ((txdp->cmd_type_offset_bsz &
4334 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4335 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4339 if (i >= ICE_FDIR_MAX_WAIT_US) {
4341 "Failed to program FDIR filter: time out to get DD on tx queue.");
4345 for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4348 ret = ice_check_fdir_programming_status(rxq);
4356 "Failed to program FDIR filter: programming status reported.");