1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <rte_ethdev_driver.h>
10 #define ICE_TX_CKSUM_OFFLOAD_MASK ( \
14 PKT_TX_OUTER_IP_CKSUM)
17 ice_rxdid_to_proto_xtr_type(uint8_t rxdid)
19 static uint8_t xtr_map[] = {
20 [ICE_RXDID_COMMS_AUX_VLAN] = PROTO_XTR_VLAN,
21 [ICE_RXDID_COMMS_AUX_IPV4] = PROTO_XTR_IPV4,
22 [ICE_RXDID_COMMS_AUX_IPV6] = PROTO_XTR_IPV6,
23 [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = PROTO_XTR_IPV6_FLOW,
24 [ICE_RXDID_COMMS_AUX_TCP] = PROTO_XTR_TCP,
27 return rxdid < RTE_DIM(xtr_map) ? xtr_map[rxdid] : PROTO_XTR_NONE;
31 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
33 static uint8_t rxdid_map[] = {
34 [PROTO_XTR_NONE] = ICE_RXDID_COMMS_GENERIC,
35 [PROTO_XTR_VLAN] = ICE_RXDID_COMMS_AUX_VLAN,
36 [PROTO_XTR_IPV4] = ICE_RXDID_COMMS_AUX_IPV4,
37 [PROTO_XTR_IPV6] = ICE_RXDID_COMMS_AUX_IPV6,
38 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
39 [PROTO_XTR_TCP] = ICE_RXDID_COMMS_AUX_TCP,
42 return xtr_type < RTE_DIM(rxdid_map) ?
43 rxdid_map[xtr_type] : ICE_RXDID_COMMS_GENERIC;
46 static enum ice_status
47 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
49 struct ice_vsi *vsi = rxq->vsi;
50 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
51 struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
52 struct ice_rlan_ctx rx_ctx;
54 uint16_t buf_size, len;
55 struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
56 uint32_t rxdid = ICE_RXDID_COMMS_GENERIC;
59 /* Set buffer size as the head split is disabled. */
60 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
61 RTE_PKTMBUF_HEADROOM);
63 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
64 len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
65 rxq->max_pkt_len = RTE_MIN(len,
66 dev->data->dev_conf.rxmode.max_rx_pkt_len);
68 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
69 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
70 rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
71 PMD_DRV_LOG(ERR, "maximum packet length must "
72 "be larger than %u and smaller than %u,"
73 "as jumbo frame is enabled",
74 (uint32_t)RTE_ETHER_MAX_LEN,
75 (uint32_t)ICE_FRAME_SIZE_MAX);
79 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
80 rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
81 PMD_DRV_LOG(ERR, "maximum packet length must be "
82 "larger than %u and smaller than %u, "
83 "as jumbo frame is disabled",
84 (uint32_t)RTE_ETHER_MIN_LEN,
85 (uint32_t)RTE_ETHER_MAX_LEN);
90 memset(&rx_ctx, 0, sizeof(rx_ctx));
92 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
93 rx_ctx.qlen = rxq->nb_rx_desc;
94 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
95 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
96 rx_ctx.dtype = 0; /* No Header Split mode */
97 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
98 rx_ctx.dsize = 1; /* 32B descriptors */
100 rx_ctx.rxmax = rxq->max_pkt_len;
101 /* TPH: Transaction Layer Packet (TLP) processing hints */
102 rx_ctx.tphrdesc_ena = 1;
103 rx_ctx.tphwdesc_ena = 1;
104 rx_ctx.tphdata_ena = 1;
105 rx_ctx.tphhead_ena = 1;
106 /* Low Receive Queue Threshold defined in 64 descriptors units.
107 * When the number of free descriptors goes below the lrxqthresh,
108 * an immediate interrupt is triggered.
110 rx_ctx.lrxqthresh = 2;
111 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
114 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
116 rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
118 PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
119 rxq->port_id, rxq->queue_id, rxdid);
121 /* Enable Flexible Descriptors in the queue context which
122 * allows this driver to select a specific receive descriptor format
124 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
125 QRXFLXP_CNTXT_RXDID_IDX_M;
127 /* increasing context priority to pick up profile ID;
128 * default is 0x01; setting to 0x03 to ensure profile
129 * is programming if prev context is of same priority
131 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
132 QRXFLXP_CNTXT_RXDID_PRIO_M;
134 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
136 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
138 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
142 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
144 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
149 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
150 RTE_PKTMBUF_HEADROOM);
152 /* Check if scattered RX needs to be used. */
153 if (rxq->max_pkt_len > buf_size)
154 dev->data->scattered_rx = 1;
156 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
158 /* Init the Rx tail register*/
159 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
164 /* Allocate mbufs for all descriptors in rx queue */
166 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
168 struct ice_rx_entry *rxe = rxq->sw_ring;
172 for (i = 0; i < rxq->nb_rx_desc; i++) {
173 volatile union ice_rx_flex_desc *rxd;
174 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
176 if (unlikely(!mbuf)) {
177 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
181 rte_mbuf_refcnt_set(mbuf, 1);
183 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
185 mbuf->port = rxq->port_id;
188 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
190 rxd = &rxq->rx_ring[i];
191 rxd->read.pkt_addr = dma_addr;
192 rxd->read.hdr_addr = 0;
193 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
203 /* Free all mbufs for descriptors in rx queue */
205 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
209 if (!rxq || !rxq->sw_ring) {
210 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
214 for (i = 0; i < rxq->nb_rx_desc; i++) {
215 if (rxq->sw_ring[i].mbuf) {
216 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
217 rxq->sw_ring[i].mbuf = NULL;
220 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
221 if (rxq->rx_nb_avail == 0)
223 for (i = 0; i < rxq->rx_nb_avail; i++) {
224 struct rte_mbuf *mbuf;
226 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
227 rte_pktmbuf_free_seg(mbuf);
229 rxq->rx_nb_avail = 0;
230 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
234 ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
236 rxq->rx_rel_mbufs(rxq);
239 /* turn on or off rx queue
240 * @q_idx: queue index in pf scope
241 * @on: turn on or off the queue
244 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
249 /* QRX_CTRL = QRX_ENA */
250 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
253 if (reg & QRX_CTRL_QENA_STAT_M)
254 return 0; /* Already on, skip */
255 reg |= QRX_CTRL_QENA_REQ_M;
257 if (!(reg & QRX_CTRL_QENA_STAT_M))
258 return 0; /* Already off, skip */
259 reg &= ~QRX_CTRL_QENA_REQ_M;
262 /* Write the register */
263 ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
264 /* Check the result. It is said that QENA_STAT
265 * follows the QENA_REQ not more than 10 use.
266 * TODO: need to change the wait counter later
268 for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
269 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
270 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
272 if ((reg & QRX_CTRL_QENA_REQ_M) &&
273 (reg & QRX_CTRL_QENA_STAT_M))
276 if (!(reg & QRX_CTRL_QENA_REQ_M) &&
277 !(reg & QRX_CTRL_QENA_STAT_M))
282 /* Check if it is timeout */
283 if (j >= ICE_CHK_Q_ENA_COUNT) {
284 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
285 (on ? "enable" : "disable"), q_idx);
293 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
294 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
296 ice_check_rx_burst_bulk_alloc_preconditions
297 (__rte_unused struct ice_rx_queue *rxq)
302 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
303 if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
304 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
305 "rxq->rx_free_thresh=%d, "
306 "ICE_RX_MAX_BURST=%d",
307 rxq->rx_free_thresh, ICE_RX_MAX_BURST);
309 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
310 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
311 "rxq->rx_free_thresh=%d, "
312 "rxq->nb_rx_desc=%d",
313 rxq->rx_free_thresh, rxq->nb_rx_desc);
315 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
316 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
317 "rxq->nb_rx_desc=%d, "
318 "rxq->rx_free_thresh=%d",
319 rxq->nb_rx_desc, rxq->rx_free_thresh);
329 /* reset fields in ice_rx_queue back to default */
331 ice_reset_rx_queue(struct ice_rx_queue *rxq)
337 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
341 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
342 if (ice_check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
343 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
345 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
346 len = rxq->nb_rx_desc;
348 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
349 ((volatile char *)rxq->rx_ring)[i] = 0;
351 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
352 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
353 for (i = 0; i < ICE_RX_MAX_BURST; ++i)
354 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
356 rxq->rx_nb_avail = 0;
357 rxq->rx_next_avail = 0;
358 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
359 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
363 rxq->pkt_first_seg = NULL;
364 rxq->pkt_last_seg = NULL;
366 rxq->rxrearm_start = 0;
371 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
373 struct ice_rx_queue *rxq;
375 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
377 PMD_INIT_FUNC_TRACE();
379 if (rx_queue_id >= dev->data->nb_rx_queues) {
380 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
381 rx_queue_id, dev->data->nb_rx_queues);
385 rxq = dev->data->rx_queues[rx_queue_id];
386 if (!rxq || !rxq->q_set) {
387 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
392 err = ice_program_hw_rx_queue(rxq);
394 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
399 err = ice_alloc_rx_queue_mbufs(rxq);
401 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
405 /* Init the RX tail register. */
406 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
408 err = ice_switch_rx_queue(hw, rxq->reg_idx, TRUE);
410 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
413 ice_rx_queue_release_mbufs(rxq);
414 ice_reset_rx_queue(rxq);
418 dev->data->rx_queue_state[rx_queue_id] =
419 RTE_ETH_QUEUE_STATE_STARTED;
425 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
427 struct ice_rx_queue *rxq;
429 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
431 if (rx_queue_id < dev->data->nb_rx_queues) {
432 rxq = dev->data->rx_queues[rx_queue_id];
434 err = ice_switch_rx_queue(hw, rxq->reg_idx, FALSE);
436 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
440 ice_rx_queue_release_mbufs(rxq);
441 ice_reset_rx_queue(rxq);
442 dev->data->rx_queue_state[rx_queue_id] =
443 RTE_ETH_QUEUE_STATE_STOPPED;
450 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
452 struct ice_tx_queue *txq;
456 struct ice_aqc_add_tx_qgrp txq_elem;
457 struct ice_tlan_ctx tx_ctx;
459 PMD_INIT_FUNC_TRACE();
461 if (tx_queue_id >= dev->data->nb_tx_queues) {
462 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
463 tx_queue_id, dev->data->nb_tx_queues);
467 txq = dev->data->tx_queues[tx_queue_id];
468 if (!txq || !txq->q_set) {
469 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
475 hw = ICE_VSI_TO_HW(vsi);
477 memset(&txq_elem, 0, sizeof(txq_elem));
478 memset(&tx_ctx, 0, sizeof(tx_ctx));
479 txq_elem.num_txqs = 1;
480 txq_elem.txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
482 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
483 tx_ctx.qlen = txq->nb_tx_desc;
484 tx_ctx.pf_num = hw->pf_id;
485 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
486 tx_ctx.src_vsi = vsi->vsi_id;
487 tx_ctx.port_num = hw->port_info->lport;
488 tx_ctx.tso_ena = 1; /* tso enable */
489 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
490 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
492 ice_set_ctx((uint8_t *)&tx_ctx, txq_elem.txqs[0].txq_ctx,
495 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
497 /* Init the Tx tail register*/
498 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
500 /* Fix me, we assume TC always 0 here */
501 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
502 &txq_elem, sizeof(txq_elem), NULL);
504 PMD_DRV_LOG(ERR, "Failed to add lan txq");
507 /* store the schedule node id */
508 txq->q_teid = txq_elem.txqs[0].q_teid;
510 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
514 /* Free all mbufs for descriptors in tx queue */
516 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
520 if (!txq || !txq->sw_ring) {
521 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
525 for (i = 0; i < txq->nb_tx_desc; i++) {
526 if (txq->sw_ring[i].mbuf) {
527 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
528 txq->sw_ring[i].mbuf = NULL;
533 ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
535 txq->tx_rel_mbufs(txq);
539 ice_reset_tx_queue(struct ice_tx_queue *txq)
541 struct ice_tx_entry *txe;
542 uint16_t i, prev, size;
545 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
550 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
551 for (i = 0; i < size; i++)
552 ((volatile char *)txq->tx_ring)[i] = 0;
554 prev = (uint16_t)(txq->nb_tx_desc - 1);
555 for (i = 0; i < txq->nb_tx_desc; i++) {
556 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
558 txd->cmd_type_offset_bsz =
559 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
562 txe[prev].next_id = i;
566 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
567 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
572 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
573 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
577 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
579 struct ice_tx_queue *txq;
580 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
581 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
582 struct ice_vsi *vsi = pf->main_vsi;
583 enum ice_status status;
586 uint16_t q_handle = tx_queue_id;
588 if (tx_queue_id >= dev->data->nb_tx_queues) {
589 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
590 tx_queue_id, dev->data->nb_tx_queues);
594 txq = dev->data->tx_queues[tx_queue_id];
596 PMD_DRV_LOG(ERR, "TX queue %u is not available",
601 q_ids[0] = txq->reg_idx;
602 q_teids[0] = txq->q_teid;
604 /* Fix me, we assume TC always 0 here */
605 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
606 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
607 if (status != ICE_SUCCESS) {
608 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
612 ice_tx_queue_release_mbufs(txq);
613 ice_reset_tx_queue(txq);
614 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
620 ice_rx_queue_setup(struct rte_eth_dev *dev,
623 unsigned int socket_id,
624 const struct rte_eth_rxconf *rx_conf,
625 struct rte_mempool *mp)
627 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
628 struct ice_adapter *ad =
629 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
630 struct ice_vsi *vsi = pf->main_vsi;
631 struct ice_rx_queue *rxq;
632 const struct rte_memzone *rz;
635 int use_def_burst_func = 1;
637 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
638 nb_desc > ICE_MAX_RING_DESC ||
639 nb_desc < ICE_MIN_RING_DESC) {
640 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
645 /* Free memory if needed */
646 if (dev->data->rx_queues[queue_idx]) {
647 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
648 dev->data->rx_queues[queue_idx] = NULL;
651 /* Allocate the rx queue data structure */
652 rxq = rte_zmalloc_socket(NULL,
653 sizeof(struct ice_rx_queue),
657 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
658 "rx queue data structure");
662 rxq->nb_rx_desc = nb_desc;
663 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
664 rxq->queue_id = queue_idx;
666 rxq->reg_idx = vsi->base_queue + queue_idx;
667 rxq->port_id = dev->data->port_id;
668 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
669 rxq->crc_len = RTE_ETHER_CRC_LEN;
673 rxq->drop_en = rx_conf->rx_drop_en;
675 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
676 rxq->proto_xtr = pf->proto_xtr != NULL ?
677 pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
679 /* Allocate the maximun number of RX ring hardware descriptor. */
680 len = ICE_MAX_RING_DESC;
682 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
684 * Allocating a little more memory because vectorized/bulk_alloc Rx
685 * functions doesn't check boundaries each time.
687 len += ICE_RX_MAX_BURST;
690 /* Allocate the maximum number of RX ring hardware descriptor. */
691 ring_size = sizeof(union ice_rx_flex_desc) * len;
692 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
693 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
694 ring_size, ICE_RING_BASE_ALIGN,
697 ice_rx_queue_release(rxq);
698 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
702 /* Zero all the descriptors in the ring. */
703 memset(rz->addr, 0, ring_size);
705 rxq->rx_ring_dma = rz->iova;
706 rxq->rx_ring = rz->addr;
708 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
709 len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
714 /* Allocate the software ring. */
715 rxq->sw_ring = rte_zmalloc_socket(NULL,
716 sizeof(struct ice_rx_entry) * len,
720 ice_rx_queue_release(rxq);
721 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
725 ice_reset_rx_queue(rxq);
727 dev->data->rx_queues[queue_idx] = rxq;
728 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
730 use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
732 if (!use_def_burst_func) {
733 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
734 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
735 "satisfied. Rx Burst Bulk Alloc function will be "
736 "used on port=%d, queue=%d.",
737 rxq->port_id, rxq->queue_id);
738 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
740 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
741 "not satisfied, Scattered Rx is requested, "
742 "or RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC is "
743 "not enabled on port=%d, queue=%d.",
744 rxq->port_id, rxq->queue_id);
745 ad->rx_bulk_alloc_allowed = false;
752 ice_rx_queue_release(void *rxq)
754 struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
757 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
761 ice_rx_queue_release_mbufs(q);
762 rte_free(q->sw_ring);
767 ice_tx_queue_setup(struct rte_eth_dev *dev,
770 unsigned int socket_id,
771 const struct rte_eth_txconf *tx_conf)
773 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
774 struct ice_vsi *vsi = pf->main_vsi;
775 struct ice_tx_queue *txq;
776 const struct rte_memzone *tz;
778 uint16_t tx_rs_thresh, tx_free_thresh;
781 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
783 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
784 nb_desc > ICE_MAX_RING_DESC ||
785 nb_desc < ICE_MIN_RING_DESC) {
786 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
792 * The following two parameters control the setting of the RS bit on
793 * transmit descriptors. TX descriptors will have their RS bit set
794 * after txq->tx_rs_thresh descriptors have been used. The TX
795 * descriptor ring will be cleaned after txq->tx_free_thresh
796 * descriptors are used or if the number of descriptors required to
797 * transmit a packet is greater than the number of free TX descriptors.
799 * The following constraints must be satisfied:
800 * - tx_rs_thresh must be greater than 0.
801 * - tx_rs_thresh must be less than the size of the ring minus 2.
802 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
803 * - tx_rs_thresh must be a divisor of the ring size.
804 * - tx_free_thresh must be greater than 0.
805 * - tx_free_thresh must be less than the size of the ring minus 3.
806 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
808 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
809 * race condition, hence the maximum threshold constraints. When set
810 * to zero use default values.
812 tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
813 tx_conf->tx_free_thresh :
814 ICE_DEFAULT_TX_FREE_THRESH);
815 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
817 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
818 nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
819 if (tx_conf->tx_rs_thresh)
820 tx_rs_thresh = tx_conf->tx_rs_thresh;
821 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
822 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
823 "exceed nb_desc. (tx_rs_thresh=%u "
824 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
825 (unsigned int)tx_rs_thresh,
826 (unsigned int)tx_free_thresh,
827 (unsigned int)nb_desc,
828 (int)dev->data->port_id,
832 if (tx_rs_thresh >= (nb_desc - 2)) {
833 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
834 "number of TX descriptors minus 2. "
835 "(tx_rs_thresh=%u port=%d queue=%d)",
836 (unsigned int)tx_rs_thresh,
837 (int)dev->data->port_id,
841 if (tx_free_thresh >= (nb_desc - 3)) {
842 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
843 "tx_free_thresh must be less than the "
844 "number of TX descriptors minus 3. "
845 "(tx_free_thresh=%u port=%d queue=%d)",
846 (unsigned int)tx_free_thresh,
847 (int)dev->data->port_id,
851 if (tx_rs_thresh > tx_free_thresh) {
852 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
853 "equal to tx_free_thresh. (tx_free_thresh=%u"
854 " tx_rs_thresh=%u port=%d queue=%d)",
855 (unsigned int)tx_free_thresh,
856 (unsigned int)tx_rs_thresh,
857 (int)dev->data->port_id,
861 if ((nb_desc % tx_rs_thresh) != 0) {
862 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
863 "number of TX descriptors. (tx_rs_thresh=%u"
864 " port=%d queue=%d)",
865 (unsigned int)tx_rs_thresh,
866 (int)dev->data->port_id,
870 if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
871 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
872 "tx_rs_thresh is greater than 1. "
873 "(tx_rs_thresh=%u port=%d queue=%d)",
874 (unsigned int)tx_rs_thresh,
875 (int)dev->data->port_id,
880 /* Free memory if needed. */
881 if (dev->data->tx_queues[queue_idx]) {
882 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
883 dev->data->tx_queues[queue_idx] = NULL;
886 /* Allocate the TX queue data structure. */
887 txq = rte_zmalloc_socket(NULL,
888 sizeof(struct ice_tx_queue),
892 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
893 "tx queue structure");
897 /* Allocate TX hardware ring descriptors. */
898 ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
899 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
900 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
901 ring_size, ICE_RING_BASE_ALIGN,
904 ice_tx_queue_release(txq);
905 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
909 txq->nb_tx_desc = nb_desc;
910 txq->tx_rs_thresh = tx_rs_thresh;
911 txq->tx_free_thresh = tx_free_thresh;
912 txq->pthresh = tx_conf->tx_thresh.pthresh;
913 txq->hthresh = tx_conf->tx_thresh.hthresh;
914 txq->wthresh = tx_conf->tx_thresh.wthresh;
915 txq->queue_id = queue_idx;
917 txq->reg_idx = vsi->base_queue + queue_idx;
918 txq->port_id = dev->data->port_id;
919 txq->offloads = offloads;
921 txq->tx_deferred_start = tx_conf->tx_deferred_start;
923 txq->tx_ring_dma = tz->iova;
924 txq->tx_ring = tz->addr;
926 /* Allocate software ring */
928 rte_zmalloc_socket(NULL,
929 sizeof(struct ice_tx_entry) * nb_desc,
933 ice_tx_queue_release(txq);
934 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
938 ice_reset_tx_queue(txq);
940 dev->data->tx_queues[queue_idx] = txq;
941 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
942 ice_set_tx_function_flag(dev, txq);
948 ice_tx_queue_release(void *txq)
950 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
953 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
957 ice_tx_queue_release_mbufs(q);
958 rte_free(q->sw_ring);
963 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
964 struct rte_eth_rxq_info *qinfo)
966 struct ice_rx_queue *rxq;
968 rxq = dev->data->rx_queues[queue_id];
971 qinfo->scattered_rx = dev->data->scattered_rx;
972 qinfo->nb_desc = rxq->nb_rx_desc;
974 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
975 qinfo->conf.rx_drop_en = rxq->drop_en;
976 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
980 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
981 struct rte_eth_txq_info *qinfo)
983 struct ice_tx_queue *txq;
985 txq = dev->data->tx_queues[queue_id];
987 qinfo->nb_desc = txq->nb_tx_desc;
989 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
990 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
991 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
993 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
994 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
995 qinfo->conf.offloads = txq->offloads;
996 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1000 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1002 #define ICE_RXQ_SCAN_INTERVAL 4
1003 volatile union ice_rx_flex_desc *rxdp;
1004 struct ice_rx_queue *rxq;
1007 rxq = dev->data->rx_queues[rx_queue_id];
1008 rxdp = &rxq->rx_ring[rxq->rx_tail];
1009 while ((desc < rxq->nb_rx_desc) &&
1010 rte_le_to_cpu_16(rxdp->wb.status_error0) &
1011 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1013 * Check the DD bit of a rx descriptor of each 4 in a group,
1014 * to avoid checking too frequently and downgrading performance
1017 desc += ICE_RXQ_SCAN_INTERVAL;
1018 rxdp += ICE_RXQ_SCAN_INTERVAL;
1019 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1020 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1021 desc - rxq->nb_rx_desc]);
1027 #define ICE_RX_FLEX_ERR0_BITS \
1028 ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) | \
1029 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1030 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1031 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1032 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1033 (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1035 /* Rx L3/L4 checksum */
1036 static inline uint64_t
1037 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1041 /* check if HW has decoded the packet and checksum */
1042 if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1045 if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1046 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1050 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1051 flags |= PKT_RX_IP_CKSUM_BAD;
1053 flags |= PKT_RX_IP_CKSUM_GOOD;
1055 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1056 flags |= PKT_RX_L4_CKSUM_BAD;
1058 flags |= PKT_RX_L4_CKSUM_GOOD;
1060 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1061 flags |= PKT_RX_EIP_CKSUM_BAD;
1067 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1069 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1070 (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1071 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1073 rte_le_to_cpu_16(rxdp->wb.l2tag1);
1074 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1075 rte_le_to_cpu_16(rxdp->wb.l2tag1));
1080 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1081 if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1082 (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1083 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1084 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1085 mb->vlan_tci_outer = mb->vlan_tci;
1086 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1087 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1088 rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1089 rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1091 mb->vlan_tci_outer = 0;
1094 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1095 mb->vlan_tci, mb->vlan_tci_outer);
1098 #define ICE_RX_PROTO_XTR_VALID \
1099 ((1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) | \
1100 (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1103 ice_rxd_to_pkt_fields(struct rte_mbuf *mb,
1104 volatile union ice_rx_flex_desc *rxdp)
1106 volatile struct ice_32b_rx_flex_desc_comms *desc =
1107 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
1110 stat_err = rte_le_to_cpu_16(desc->status_error0);
1111 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
1112 mb->ol_flags |= PKT_RX_RSS_HASH;
1113 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
1116 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1117 init_proto_xtr_flds(mb);
1119 stat_err = rte_le_to_cpu_16(desc->status_error1);
1120 if (stat_err & ICE_RX_PROTO_XTR_VALID) {
1121 struct proto_xtr_flds *xtr = get_proto_xtr_flds(mb);
1123 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
1125 rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
1127 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1129 rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
1131 xtr->type = ice_rxdid_to_proto_xtr_type(desc->rxdid);
1132 xtr->magic = PROTO_XTR_MAGIC_ID;
1137 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1138 #define ICE_LOOK_AHEAD 8
1139 #if (ICE_LOOK_AHEAD != 8)
1140 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1143 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1145 volatile union ice_rx_flex_desc *rxdp;
1146 struct ice_rx_entry *rxep;
1147 struct rte_mbuf *mb;
1150 int32_t s[ICE_LOOK_AHEAD], nb_dd;
1151 int32_t i, j, nb_rx = 0;
1152 uint64_t pkt_flags = 0;
1153 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1155 rxdp = &rxq->rx_ring[rxq->rx_tail];
1156 rxep = &rxq->sw_ring[rxq->rx_tail];
1158 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1160 /* Make sure there is at least 1 packet to receive */
1161 if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1165 * Scan LOOK_AHEAD descriptors at a time to determine which
1166 * descriptors reference packets that are ready to be received.
1168 for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1169 rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1170 /* Read desc statuses backwards to avoid race condition */
1171 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1172 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1176 /* Compute how many status bits were set */
1177 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1178 nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1182 /* Translate descriptor info to mbuf parameters */
1183 for (j = 0; j < nb_dd; j++) {
1185 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1186 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1187 mb->data_len = pkt_len;
1188 mb->pkt_len = pkt_len;
1190 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1191 pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1192 mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1193 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1194 ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1195 ice_rxd_to_pkt_fields(mb, &rxdp[j]);
1197 mb->ol_flags |= pkt_flags;
1200 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1201 rxq->rx_stage[i + j] = rxep[j].mbuf;
1203 if (nb_dd != ICE_LOOK_AHEAD)
1207 /* Clear software ring entries */
1208 for (i = 0; i < nb_rx; i++)
1209 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1211 PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1212 "port_id=%u, queue_id=%u, nb_rx=%d",
1213 rxq->port_id, rxq->queue_id, nb_rx);
1218 static inline uint16_t
1219 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1220 struct rte_mbuf **rx_pkts,
1224 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1226 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1228 for (i = 0; i < nb_pkts; i++)
1229 rx_pkts[i] = stage[i];
1231 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1232 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1238 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1240 volatile union ice_rx_flex_desc *rxdp;
1241 struct ice_rx_entry *rxep;
1242 struct rte_mbuf *mb;
1243 uint16_t alloc_idx, i;
1247 /* Allocate buffers in bulk */
1248 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1249 (rxq->rx_free_thresh - 1));
1250 rxep = &rxq->sw_ring[alloc_idx];
1251 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1252 rxq->rx_free_thresh);
1253 if (unlikely(diag != 0)) {
1254 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1258 rxdp = &rxq->rx_ring[alloc_idx];
1259 for (i = 0; i < rxq->rx_free_thresh; i++) {
1260 if (likely(i < (rxq->rx_free_thresh - 1)))
1261 /* Prefetch next mbuf */
1262 rte_prefetch0(rxep[i + 1].mbuf);
1265 rte_mbuf_refcnt_set(mb, 1);
1267 mb->data_off = RTE_PKTMBUF_HEADROOM;
1269 mb->port = rxq->port_id;
1270 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1271 rxdp[i].read.hdr_addr = 0;
1272 rxdp[i].read.pkt_addr = dma_addr;
1275 /* Update rx tail regsiter */
1276 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1278 rxq->rx_free_trigger =
1279 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1280 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1281 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1286 static inline uint16_t
1287 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1289 struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1291 struct rte_eth_dev *dev;
1296 if (rxq->rx_nb_avail)
1297 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1299 nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1300 rxq->rx_next_avail = 0;
1301 rxq->rx_nb_avail = nb_rx;
1302 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1304 if (rxq->rx_tail > rxq->rx_free_trigger) {
1305 if (ice_rx_alloc_bufs(rxq) != 0) {
1308 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1309 dev->data->rx_mbuf_alloc_failed +=
1310 rxq->rx_free_thresh;
1311 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1312 "port_id=%u, queue_id=%u",
1313 rxq->port_id, rxq->queue_id);
1314 rxq->rx_nb_avail = 0;
1315 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1316 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1317 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1323 if (rxq->rx_tail >= rxq->nb_rx_desc)
1326 if (rxq->rx_nb_avail)
1327 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1333 ice_recv_pkts_bulk_alloc(void *rx_queue,
1334 struct rte_mbuf **rx_pkts,
1341 if (unlikely(nb_pkts == 0))
1344 if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1345 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1348 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1349 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1350 nb_rx = (uint16_t)(nb_rx + count);
1351 nb_pkts = (uint16_t)(nb_pkts - count);
1360 ice_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
1361 struct rte_mbuf __rte_unused **rx_pkts,
1362 uint16_t __rte_unused nb_pkts)
1366 #endif /* RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC */
1369 ice_recv_scattered_pkts(void *rx_queue,
1370 struct rte_mbuf **rx_pkts,
1373 struct ice_rx_queue *rxq = rx_queue;
1374 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1375 volatile union ice_rx_flex_desc *rxdp;
1376 union ice_rx_flex_desc rxd;
1377 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1378 struct ice_rx_entry *rxe;
1379 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1380 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1381 struct rte_mbuf *nmb; /* new allocated mbuf */
1382 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1383 uint16_t rx_id = rxq->rx_tail;
1385 uint16_t nb_hold = 0;
1386 uint16_t rx_packet_len;
1387 uint16_t rx_stat_err0;
1390 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1391 struct rte_eth_dev *dev;
1393 while (nb_rx < nb_pkts) {
1394 rxdp = &rx_ring[rx_id];
1395 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1397 /* Check the DD bit first */
1398 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1402 nmb = rte_mbuf_raw_alloc(rxq->mp);
1403 if (unlikely(!nmb)) {
1404 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1405 dev->data->rx_mbuf_alloc_failed++;
1408 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1411 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1413 if (unlikely(rx_id == rxq->nb_rx_desc))
1416 /* Prefetch next mbuf */
1417 rte_prefetch0(sw_ring[rx_id].mbuf);
1420 * When next RX descriptor is on a cache line boundary,
1421 * prefetch the next 4 RX descriptors and next 8 pointers
1424 if ((rx_id & 0x3) == 0) {
1425 rte_prefetch0(&rx_ring[rx_id]);
1426 rte_prefetch0(&sw_ring[rx_id]);
1432 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1434 /* Set data buffer address and data length of the mbuf */
1435 rxdp->read.hdr_addr = 0;
1436 rxdp->read.pkt_addr = dma_addr;
1437 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1438 ICE_RX_FLX_DESC_PKT_LEN_M;
1439 rxm->data_len = rx_packet_len;
1440 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1443 * If this is the first buffer of the received packet, set the
1444 * pointer to the first mbuf of the packet and initialize its
1445 * context. Otherwise, update the total length and the number
1446 * of segments of the current scattered packet, and update the
1447 * pointer to the last mbuf of the current packet.
1451 first_seg->nb_segs = 1;
1452 first_seg->pkt_len = rx_packet_len;
1454 first_seg->pkt_len =
1455 (uint16_t)(first_seg->pkt_len +
1457 first_seg->nb_segs++;
1458 last_seg->next = rxm;
1462 * If this is not the last buffer of the received packet,
1463 * update the pointer to the last mbuf of the current scattered
1464 * packet and continue to parse the RX ring.
1466 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1472 * This is the last buffer of the received packet. If the CRC
1473 * is not stripped by the hardware:
1474 * - Subtract the CRC length from the total packet length.
1475 * - If the last buffer only contains the whole CRC or a part
1476 * of it, free the mbuf associated to the last buffer. If part
1477 * of the CRC is also contained in the previous mbuf, subtract
1478 * the length of that CRC part from the data length of the
1482 if (unlikely(rxq->crc_len > 0)) {
1483 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1484 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1485 rte_pktmbuf_free_seg(rxm);
1486 first_seg->nb_segs--;
1487 last_seg->data_len =
1488 (uint16_t)(last_seg->data_len -
1489 (RTE_ETHER_CRC_LEN - rx_packet_len));
1490 last_seg->next = NULL;
1492 rxm->data_len = (uint16_t)(rx_packet_len -
1496 first_seg->port = rxq->port_id;
1497 first_seg->ol_flags = 0;
1498 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1499 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1500 ice_rxd_to_vlan_tci(first_seg, &rxd);
1501 ice_rxd_to_pkt_fields(first_seg, &rxd);
1502 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1503 first_seg->ol_flags |= pkt_flags;
1504 /* Prefetch data of first segment, if configured to do so. */
1505 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1506 first_seg->data_off));
1507 rx_pkts[nb_rx++] = first_seg;
1511 /* Record index of the next RX descriptor to probe. */
1512 rxq->rx_tail = rx_id;
1513 rxq->pkt_first_seg = first_seg;
1514 rxq->pkt_last_seg = last_seg;
1517 * If the number of free RX descriptors is greater than the RX free
1518 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1519 * register. Update the RDT with the value of the last processed RX
1520 * descriptor minus 1, to guarantee that the RDT register is never
1521 * equal to the RDH register, which creates a "full" ring situtation
1522 * from the hardware point of view.
1524 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1525 if (nb_hold > rxq->rx_free_thresh) {
1526 rx_id = (uint16_t)(rx_id == 0 ?
1527 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1528 /* write TAIL register */
1529 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1532 rxq->nb_rx_hold = nb_hold;
1534 /* return received packet in the burst */
1539 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1541 static const uint32_t ptypes[] = {
1542 /* refers to ice_get_default_pkt_type() */
1544 RTE_PTYPE_L2_ETHER_LLDP,
1545 RTE_PTYPE_L2_ETHER_ARP,
1546 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1547 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1550 RTE_PTYPE_L4_NONFRAG,
1554 RTE_PTYPE_TUNNEL_GRENAT,
1555 RTE_PTYPE_TUNNEL_IP,
1556 RTE_PTYPE_INNER_L2_ETHER,
1557 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1558 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1559 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1560 RTE_PTYPE_INNER_L4_FRAG,
1561 RTE_PTYPE_INNER_L4_ICMP,
1562 RTE_PTYPE_INNER_L4_NONFRAG,
1563 RTE_PTYPE_INNER_L4_SCTP,
1564 RTE_PTYPE_INNER_L4_TCP,
1565 RTE_PTYPE_INNER_L4_UDP,
1566 RTE_PTYPE_TUNNEL_GTPC,
1567 RTE_PTYPE_TUNNEL_GTPU,
1571 if (dev->rx_pkt_burst == ice_recv_pkts ||
1572 #ifdef RTE_LIBRTE_ICE_RX_ALLOW_BULK_ALLOC
1573 dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1575 dev->rx_pkt_burst == ice_recv_scattered_pkts)
1579 if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1580 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1581 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1582 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1590 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1592 volatile union ice_rx_flex_desc *rxdp;
1593 struct ice_rx_queue *rxq = rx_queue;
1596 if (unlikely(offset >= rxq->nb_rx_desc))
1599 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1600 return RTE_ETH_RX_DESC_UNAVAIL;
1602 desc = rxq->rx_tail + offset;
1603 if (desc >= rxq->nb_rx_desc)
1604 desc -= rxq->nb_rx_desc;
1606 rxdp = &rxq->rx_ring[desc];
1607 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1608 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1609 return RTE_ETH_RX_DESC_DONE;
1611 return RTE_ETH_RX_DESC_AVAIL;
1615 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1617 struct ice_tx_queue *txq = tx_queue;
1618 volatile uint64_t *status;
1619 uint64_t mask, expect;
1622 if (unlikely(offset >= txq->nb_tx_desc))
1625 desc = txq->tx_tail + offset;
1626 /* go to next desc that has the RS bit */
1627 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1629 if (desc >= txq->nb_tx_desc) {
1630 desc -= txq->nb_tx_desc;
1631 if (desc >= txq->nb_tx_desc)
1632 desc -= txq->nb_tx_desc;
1635 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1636 mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1637 expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1638 ICE_TXD_QW1_DTYPE_S);
1639 if ((*status & mask) == expect)
1640 return RTE_ETH_TX_DESC_DONE;
1642 return RTE_ETH_TX_DESC_FULL;
1646 ice_clear_queues(struct rte_eth_dev *dev)
1650 PMD_INIT_FUNC_TRACE();
1652 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1653 ice_tx_queue_release_mbufs(dev->data->tx_queues[i]);
1654 ice_reset_tx_queue(dev->data->tx_queues[i]);
1657 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1658 ice_rx_queue_release_mbufs(dev->data->rx_queues[i]);
1659 ice_reset_rx_queue(dev->data->rx_queues[i]);
1664 ice_free_queues(struct rte_eth_dev *dev)
1668 PMD_INIT_FUNC_TRACE();
1670 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1671 if (!dev->data->rx_queues[i])
1673 ice_rx_queue_release(dev->data->rx_queues[i]);
1674 dev->data->rx_queues[i] = NULL;
1676 dev->data->nb_rx_queues = 0;
1678 for (i = 0; i < dev->data->nb_tx_queues; i++) {
1679 if (!dev->data->tx_queues[i])
1681 ice_tx_queue_release(dev->data->tx_queues[i]);
1682 dev->data->tx_queues[i] = NULL;
1684 dev->data->nb_tx_queues = 0;
1688 ice_recv_pkts(void *rx_queue,
1689 struct rte_mbuf **rx_pkts,
1692 struct ice_rx_queue *rxq = rx_queue;
1693 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1694 volatile union ice_rx_flex_desc *rxdp;
1695 union ice_rx_flex_desc rxd;
1696 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1697 struct ice_rx_entry *rxe;
1698 struct rte_mbuf *nmb; /* new allocated mbuf */
1699 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1700 uint16_t rx_id = rxq->rx_tail;
1702 uint16_t nb_hold = 0;
1703 uint16_t rx_packet_len;
1704 uint16_t rx_stat_err0;
1707 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1708 struct rte_eth_dev *dev;
1710 while (nb_rx < nb_pkts) {
1711 rxdp = &rx_ring[rx_id];
1712 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1714 /* Check the DD bit first */
1715 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1719 nmb = rte_mbuf_raw_alloc(rxq->mp);
1720 if (unlikely(!nmb)) {
1721 dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1722 dev->data->rx_mbuf_alloc_failed++;
1725 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1728 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1730 if (unlikely(rx_id == rxq->nb_rx_desc))
1735 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1738 * fill the read format of descriptor with physic address in
1739 * new allocated mbuf: nmb
1741 rxdp->read.hdr_addr = 0;
1742 rxdp->read.pkt_addr = dma_addr;
1744 /* calculate rx_packet_len of the received pkt */
1745 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1746 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1748 /* fill old mbuf with received descriptor: rxd */
1749 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1750 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1753 rxm->pkt_len = rx_packet_len;
1754 rxm->data_len = rx_packet_len;
1755 rxm->port = rxq->port_id;
1756 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1757 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1758 ice_rxd_to_vlan_tci(rxm, &rxd);
1759 ice_rxd_to_pkt_fields(rxm, &rxd);
1760 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1761 rxm->ol_flags |= pkt_flags;
1762 /* copy old mbuf to rx_pkts */
1763 rx_pkts[nb_rx++] = rxm;
1765 rxq->rx_tail = rx_id;
1767 * If the number of free RX descriptors is greater than the RX free
1768 * threshold of the queue, advance the receive tail register of queue.
1769 * Update that register with the value of the last processed RX
1770 * descriptor minus 1.
1772 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1773 if (nb_hold > rxq->rx_free_thresh) {
1774 rx_id = (uint16_t)(rx_id == 0 ?
1775 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1776 /* write TAIL register */
1777 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1780 rxq->nb_rx_hold = nb_hold;
1782 /* return received packet in the burst */
1787 ice_parse_tunneling_params(uint64_t ol_flags,
1788 union ice_tx_offload tx_offload,
1789 uint32_t *cd_tunneling)
1791 /* EIPT: External (outer) IP header type */
1792 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
1793 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
1794 else if (ol_flags & PKT_TX_OUTER_IPV4)
1795 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
1796 else if (ol_flags & PKT_TX_OUTER_IPV6)
1797 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
1799 /* EIPLEN: External (outer) IP header length, in DWords */
1800 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
1801 ICE_TXD_CTX_QW0_EIPLEN_S;
1803 /* L4TUNT: L4 Tunneling Type */
1804 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
1805 case PKT_TX_TUNNEL_IPIP:
1806 /* for non UDP / GRE tunneling, set to 00b */
1808 case PKT_TX_TUNNEL_VXLAN:
1809 case PKT_TX_TUNNEL_GENEVE:
1810 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
1812 case PKT_TX_TUNNEL_GRE:
1813 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
1816 PMD_TX_LOG(ERR, "Tunnel type not supported");
1820 /* L4TUNLEN: L4 Tunneling Length, in Words
1822 * We depend on app to set rte_mbuf.l2_len correctly.
1823 * For IP in GRE it should be set to the length of the GRE
1825 * For MAC in GRE or MAC in UDP it should be set to the length
1826 * of the GRE or UDP headers plus the inner MAC up to including
1827 * its last Ethertype.
1828 * If MPLS labels exists, it should include them as well.
1830 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
1831 ICE_TXD_CTX_QW0_NATLEN_S;
1833 if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
1834 (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
1835 (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
1836 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
1840 ice_txd_enable_checksum(uint64_t ol_flags,
1842 uint32_t *td_offset,
1843 union ice_tx_offload tx_offload)
1846 if (ol_flags & PKT_TX_TUNNEL_MASK)
1847 *td_offset |= (tx_offload.outer_l2_len >> 1)
1848 << ICE_TX_DESC_LEN_MACLEN_S;
1850 *td_offset |= (tx_offload.l2_len >> 1)
1851 << ICE_TX_DESC_LEN_MACLEN_S;
1853 /* Enable L3 checksum offloads */
1854 if (ol_flags & PKT_TX_IP_CKSUM) {
1855 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
1856 *td_offset |= (tx_offload.l3_len >> 2) <<
1857 ICE_TX_DESC_LEN_IPLEN_S;
1858 } else if (ol_flags & PKT_TX_IPV4) {
1859 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
1860 *td_offset |= (tx_offload.l3_len >> 2) <<
1861 ICE_TX_DESC_LEN_IPLEN_S;
1862 } else if (ol_flags & PKT_TX_IPV6) {
1863 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
1864 *td_offset |= (tx_offload.l3_len >> 2) <<
1865 ICE_TX_DESC_LEN_IPLEN_S;
1868 if (ol_flags & PKT_TX_TCP_SEG) {
1869 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1870 *td_offset |= (tx_offload.l4_len >> 2) <<
1871 ICE_TX_DESC_LEN_L4_LEN_S;
1875 /* Enable L4 checksum offloads */
1876 switch (ol_flags & PKT_TX_L4_MASK) {
1877 case PKT_TX_TCP_CKSUM:
1878 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
1879 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
1880 ICE_TX_DESC_LEN_L4_LEN_S;
1882 case PKT_TX_SCTP_CKSUM:
1883 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
1884 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
1885 ICE_TX_DESC_LEN_L4_LEN_S;
1887 case PKT_TX_UDP_CKSUM:
1888 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
1889 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
1890 ICE_TX_DESC_LEN_L4_LEN_S;
1898 ice_xmit_cleanup(struct ice_tx_queue *txq)
1900 struct ice_tx_entry *sw_ring = txq->sw_ring;
1901 volatile struct ice_tx_desc *txd = txq->tx_ring;
1902 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1903 uint16_t nb_tx_desc = txq->nb_tx_desc;
1904 uint16_t desc_to_clean_to;
1905 uint16_t nb_tx_to_clean;
1907 /* Determine the last descriptor needing to be cleaned */
1908 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
1909 if (desc_to_clean_to >= nb_tx_desc)
1910 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1912 /* Check to make sure the last descriptor to clean is done */
1913 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1914 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
1915 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
1916 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1917 "(port=%d queue=%d) value=0x%"PRIx64"\n",
1919 txq->port_id, txq->queue_id,
1920 txd[desc_to_clean_to].cmd_type_offset_bsz);
1921 /* Failed to clean any descriptors */
1925 /* Figure out how many descriptors will be cleaned */
1926 if (last_desc_cleaned > desc_to_clean_to)
1927 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1930 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1933 /* The last descriptor to clean is done, so that means all the
1934 * descriptors from the last descriptor that was cleaned
1935 * up to the last descriptor with the RS bit set
1936 * are done. Only reset the threshold descriptor.
1938 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1940 /* Update the txq to reflect the last descriptor that was cleaned */
1941 txq->last_desc_cleaned = desc_to_clean_to;
1942 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
1947 /* Construct the tx flags */
1948 static inline uint64_t
1949 ice_build_ctob(uint32_t td_cmd,
1954 return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
1955 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
1956 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
1957 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
1958 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
1961 /* Check if the context descriptor is needed for TX offloading */
1962 static inline uint16_t
1963 ice_calc_context_desc(uint64_t flags)
1965 static uint64_t mask = PKT_TX_TCP_SEG |
1967 PKT_TX_OUTER_IP_CKSUM |
1970 return (flags & mask) ? 1 : 0;
1973 /* set ice TSO context descriptor */
1974 static inline uint64_t
1975 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
1977 uint64_t ctx_desc = 0;
1978 uint32_t cd_cmd, hdr_len, cd_tso_len;
1980 if (!tx_offload.l4_len) {
1981 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1985 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
1986 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
1987 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
1989 cd_cmd = ICE_TX_CTX_DESC_TSO;
1990 cd_tso_len = mbuf->pkt_len - hdr_len;
1991 ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
1992 ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
1993 ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
1999 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2001 struct ice_tx_queue *txq;
2002 volatile struct ice_tx_desc *tx_ring;
2003 volatile struct ice_tx_desc *txd;
2004 struct ice_tx_entry *sw_ring;
2005 struct ice_tx_entry *txe, *txn;
2006 struct rte_mbuf *tx_pkt;
2007 struct rte_mbuf *m_seg;
2008 uint32_t cd_tunneling_params;
2013 uint32_t td_cmd = 0;
2014 uint32_t td_offset = 0;
2015 uint32_t td_tag = 0;
2017 uint64_t buf_dma_addr;
2019 union ice_tx_offload tx_offload = {0};
2022 sw_ring = txq->sw_ring;
2023 tx_ring = txq->tx_ring;
2024 tx_id = txq->tx_tail;
2025 txe = &sw_ring[tx_id];
2027 /* Check if the descriptor ring needs to be cleaned. */
2028 if (txq->nb_tx_free < txq->tx_free_thresh)
2029 ice_xmit_cleanup(txq);
2031 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2032 tx_pkt = *tx_pkts++;
2035 ol_flags = tx_pkt->ol_flags;
2036 tx_offload.l2_len = tx_pkt->l2_len;
2037 tx_offload.l3_len = tx_pkt->l3_len;
2038 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2039 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2040 tx_offload.l4_len = tx_pkt->l4_len;
2041 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2042 /* Calculate the number of context descriptors needed. */
2043 nb_ctx = ice_calc_context_desc(ol_flags);
2045 /* The number of descriptors that must be allocated for
2046 * a packet equals to the number of the segments of that
2047 * packet plus the number of context descriptor if needed.
2049 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2050 tx_last = (uint16_t)(tx_id + nb_used - 1);
2053 if (tx_last >= txq->nb_tx_desc)
2054 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2056 if (nb_used > txq->nb_tx_free) {
2057 if (ice_xmit_cleanup(txq) != 0) {
2062 if (unlikely(nb_used > txq->tx_rs_thresh)) {
2063 while (nb_used > txq->nb_tx_free) {
2064 if (ice_xmit_cleanup(txq) != 0) {
2073 /* Descriptor based VLAN insertion */
2074 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2075 td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2076 td_tag = tx_pkt->vlan_tci;
2079 /* Fill in tunneling parameters if necessary */
2080 cd_tunneling_params = 0;
2081 if (ol_flags & PKT_TX_TUNNEL_MASK)
2082 ice_parse_tunneling_params(ol_flags, tx_offload,
2083 &cd_tunneling_params);
2085 /* Enable checksum offloading */
2086 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK) {
2087 ice_txd_enable_checksum(ol_flags, &td_cmd,
2088 &td_offset, tx_offload);
2092 /* Setup TX context descriptor if required */
2093 volatile struct ice_tx_ctx_desc *ctx_txd =
2094 (volatile struct ice_tx_ctx_desc *)
2096 uint16_t cd_l2tag2 = 0;
2097 uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2099 txn = &sw_ring[txe->next_id];
2100 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2102 rte_pktmbuf_free_seg(txe->mbuf);
2106 if (ol_flags & PKT_TX_TCP_SEG)
2107 cd_type_cmd_tso_mss |=
2108 ice_set_tso_ctx(tx_pkt, tx_offload);
2110 ctx_txd->tunneling_params =
2111 rte_cpu_to_le_32(cd_tunneling_params);
2113 /* TX context descriptor based double VLAN insert */
2114 if (ol_flags & PKT_TX_QINQ) {
2115 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2116 cd_type_cmd_tso_mss |=
2117 ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2118 ICE_TXD_CTX_QW1_CMD_S);
2120 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2122 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2124 txe->last_id = tx_last;
2125 tx_id = txe->next_id;
2131 txd = &tx_ring[tx_id];
2132 txn = &sw_ring[txe->next_id];
2135 rte_pktmbuf_free_seg(txe->mbuf);
2138 /* Setup TX Descriptor */
2139 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2140 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2141 txd->cmd_type_offset_bsz =
2142 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2143 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2144 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2145 ((uint64_t)m_seg->data_len <<
2146 ICE_TXD_QW1_TX_BUF_SZ_S) |
2147 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2149 txe->last_id = tx_last;
2150 tx_id = txe->next_id;
2152 m_seg = m_seg->next;
2155 /* fill the last descriptor with End of Packet (EOP) bit */
2156 td_cmd |= ICE_TX_DESC_CMD_EOP;
2157 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2158 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2160 /* set RS bit on the last descriptor of one packet */
2161 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2162 PMD_TX_FREE_LOG(DEBUG,
2163 "Setting RS bit on TXD id="
2164 "%4u (port=%d queue=%d)",
2165 tx_last, txq->port_id, txq->queue_id);
2167 td_cmd |= ICE_TX_DESC_CMD_RS;
2169 /* Update txq RS bit counters */
2170 txq->nb_tx_used = 0;
2172 txd->cmd_type_offset_bsz |=
2173 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2177 /* update Tail register */
2178 ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2179 txq->tx_tail = tx_id;
2184 static inline int __attribute__((always_inline))
2185 ice_tx_free_bufs(struct ice_tx_queue *txq)
2187 struct ice_tx_entry *txep;
2190 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2191 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2192 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2195 txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2197 for (i = 0; i < txq->tx_rs_thresh; i++)
2198 rte_prefetch0((txep + i)->mbuf);
2200 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2201 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2202 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2206 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2207 rte_pktmbuf_free_seg(txep->mbuf);
2212 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2213 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2214 if (txq->tx_next_dd >= txq->nb_tx_desc)
2215 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2217 return txq->tx_rs_thresh;
2220 /* Populate 4 descriptors with data from 4 mbufs */
2222 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2227 for (i = 0; i < 4; i++, txdp++, pkts++) {
2228 dma_addr = rte_mbuf_data_iova(*pkts);
2229 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2230 txdp->cmd_type_offset_bsz =
2231 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2232 (*pkts)->data_len, 0);
2236 /* Populate 1 descriptor with data from 1 mbuf */
2238 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2242 dma_addr = rte_mbuf_data_iova(*pkts);
2243 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2244 txdp->cmd_type_offset_bsz =
2245 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2246 (*pkts)->data_len, 0);
2250 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2253 volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2254 struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2255 const int N_PER_LOOP = 4;
2256 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2257 int mainpart, leftover;
2261 * Process most of the packets in chunks of N pkts. Any
2262 * leftover packets will get processed one at a time.
2264 mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2265 leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2266 for (i = 0; i < mainpart; i += N_PER_LOOP) {
2267 /* Copy N mbuf pointers to the S/W ring */
2268 for (j = 0; j < N_PER_LOOP; ++j)
2269 (txep + i + j)->mbuf = *(pkts + i + j);
2270 tx4(txdp + i, pkts + i);
2273 if (unlikely(leftover > 0)) {
2274 for (i = 0; i < leftover; ++i) {
2275 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2276 tx1(txdp + mainpart + i, pkts + mainpart + i);
2281 static inline uint16_t
2282 tx_xmit_pkts(struct ice_tx_queue *txq,
2283 struct rte_mbuf **tx_pkts,
2286 volatile struct ice_tx_desc *txr = txq->tx_ring;
2290 * Begin scanning the H/W ring for done descriptors when the number
2291 * of available descriptors drops below tx_free_thresh. For each done
2292 * descriptor, free the associated buffer.
2294 if (txq->nb_tx_free < txq->tx_free_thresh)
2295 ice_tx_free_bufs(txq);
2297 /* Use available descriptor only */
2298 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2299 if (unlikely(!nb_pkts))
2302 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2303 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2304 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2305 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2306 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2307 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2309 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2313 /* Fill hardware descriptor ring with mbuf data */
2314 ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2315 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2317 /* Determin if RS bit needs to be set */
2318 if (txq->tx_tail > txq->tx_next_rs) {
2319 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2320 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2323 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2324 if (txq->tx_next_rs >= txq->nb_tx_desc)
2325 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2328 if (txq->tx_tail >= txq->nb_tx_desc)
2331 /* Update the tx tail register */
2332 ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2338 ice_xmit_pkts_simple(void *tx_queue,
2339 struct rte_mbuf **tx_pkts,
2344 if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2345 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2349 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2352 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2353 &tx_pkts[nb_tx], num);
2354 nb_tx = (uint16_t)(nb_tx + ret);
2355 nb_pkts = (uint16_t)(nb_pkts - ret);
2363 void __attribute__((cold))
2364 ice_set_rx_function(struct rte_eth_dev *dev)
2366 PMD_INIT_FUNC_TRACE();
2367 struct ice_adapter *ad =
2368 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2370 struct ice_rx_queue *rxq;
2372 bool use_avx2 = false;
2374 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2375 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
2376 ad->rx_vec_allowed = true;
2377 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2378 rxq = dev->data->rx_queues[i];
2379 if (rxq && ice_rxq_vec_setup(rxq)) {
2380 ad->rx_vec_allowed = false;
2385 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2386 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2390 ad->rx_vec_allowed = false;
2394 if (ad->rx_vec_allowed) {
2395 if (dev->data->scattered_rx) {
2397 "Using %sVector Scattered Rx (port %d).",
2398 use_avx2 ? "avx2 " : "",
2399 dev->data->port_id);
2400 dev->rx_pkt_burst = use_avx2 ?
2401 ice_recv_scattered_pkts_vec_avx2 :
2402 ice_recv_scattered_pkts_vec;
2404 PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2405 use_avx2 ? "avx2 " : "",
2406 dev->data->port_id);
2407 dev->rx_pkt_burst = use_avx2 ?
2408 ice_recv_pkts_vec_avx2 :
2416 if (dev->data->scattered_rx) {
2417 /* Set the non-LRO scattered function */
2419 "Using a Scattered function on port %d.",
2420 dev->data->port_id);
2421 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2422 } else if (ad->rx_bulk_alloc_allowed) {
2424 "Rx Burst Bulk Alloc Preconditions are "
2425 "satisfied. Rx Burst Bulk Alloc function "
2426 "will be used on port %d.",
2427 dev->data->port_id);
2428 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2431 "Rx Burst Bulk Alloc Preconditions are not "
2432 "satisfied, Normal Rx will be used on port %d.",
2433 dev->data->port_id);
2434 dev->rx_pkt_burst = ice_recv_pkts;
2439 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2440 struct rte_eth_burst_mode *mode)
2442 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
2445 if (pkt_burst == ice_recv_scattered_pkts)
2446 options = RTE_ETH_BURST_SCALAR | RTE_ETH_BURST_SCATTERED;
2447 else if (pkt_burst == ice_recv_pkts_bulk_alloc)
2448 options = RTE_ETH_BURST_SCALAR | RTE_ETH_BURST_BULK_ALLOC;
2449 else if (pkt_burst == ice_recv_pkts)
2450 options = RTE_ETH_BURST_SCALAR;
2452 else if (pkt_burst == ice_recv_scattered_pkts_vec_avx2)
2453 options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_AVX2 |
2454 RTE_ETH_BURST_SCATTERED;
2455 else if (pkt_burst == ice_recv_pkts_vec_avx2)
2456 options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_AVX2;
2457 else if (pkt_burst == ice_recv_scattered_pkts_vec)
2458 options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_SSE |
2459 RTE_ETH_BURST_SCATTERED;
2460 else if (pkt_burst == ice_recv_pkts_vec)
2461 options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_SSE;
2466 mode->options = options;
2468 return options != 0 ? 0 : -EINVAL;
2471 void __attribute__((cold))
2472 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
2474 struct ice_adapter *ad =
2475 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2477 /* Use a simple Tx queue if possible (only fast free is allowed) */
2478 ad->tx_simple_allowed =
2480 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
2481 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
2483 if (ad->tx_simple_allowed)
2484 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
2488 "Simple Tx can NOT be enabled on Tx queue %u.",
2492 /*********************************************************************
2496 **********************************************************************/
2497 /* The default values of TSO MSS */
2498 #define ICE_MIN_TSO_MSS 64
2499 #define ICE_MAX_TSO_MSS 9728
2500 #define ICE_MAX_TSO_FRAME_SIZE 262144
2502 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2509 for (i = 0; i < nb_pkts; i++) {
2511 ol_flags = m->ol_flags;
2513 if (ol_flags & PKT_TX_TCP_SEG &&
2514 (m->tso_segsz < ICE_MIN_TSO_MSS ||
2515 m->tso_segsz > ICE_MAX_TSO_MSS ||
2516 m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
2518 * MSS outside the range are considered malicious
2524 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2525 ret = rte_validate_tx_offload(m);
2531 ret = rte_net_intel_cksum_prepare(m);
2540 void __attribute__((cold))
2541 ice_set_tx_function(struct rte_eth_dev *dev)
2543 struct ice_adapter *ad =
2544 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2546 struct ice_tx_queue *txq;
2548 bool use_avx2 = false;
2550 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2551 if (!ice_tx_vec_dev_check(dev)) {
2552 ad->tx_vec_allowed = true;
2553 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2554 txq = dev->data->tx_queues[i];
2555 if (txq && ice_txq_vec_setup(txq)) {
2556 ad->tx_vec_allowed = false;
2561 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2562 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2566 ad->tx_vec_allowed = false;
2570 if (ad->tx_vec_allowed) {
2571 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2572 use_avx2 ? "avx2 " : "",
2573 dev->data->port_id);
2574 dev->tx_pkt_burst = use_avx2 ?
2575 ice_xmit_pkts_vec_avx2 :
2577 dev->tx_pkt_prepare = NULL;
2583 if (ad->tx_simple_allowed) {
2584 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2585 dev->tx_pkt_burst = ice_xmit_pkts_simple;
2586 dev->tx_pkt_prepare = NULL;
2588 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
2589 dev->tx_pkt_burst = ice_xmit_pkts;
2590 dev->tx_pkt_prepare = ice_prep_pkts;
2595 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
2596 struct rte_eth_burst_mode *mode)
2598 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
2601 if (pkt_burst == ice_xmit_pkts_simple)
2602 options = RTE_ETH_BURST_SCALAR | RTE_ETH_BURST_SIMPLE;
2603 else if (pkt_burst == ice_xmit_pkts)
2604 options = RTE_ETH_BURST_SCALAR;
2606 else if (pkt_burst == ice_xmit_pkts_vec_avx2)
2607 options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_AVX2;
2608 else if (pkt_burst == ice_xmit_pkts_vec)
2609 options = RTE_ETH_BURST_VECTOR | RTE_ETH_BURST_SSE;
2614 mode->options = options;
2616 return options != 0 ? 0 : -EINVAL;
2619 /* For each value it means, datasheet of hardware can tell more details
2621 * @note: fix ice_dev_supported_ptypes_get() if any change here.
2623 static inline uint32_t
2624 ice_get_default_pkt_type(uint16_t ptype)
2626 static const uint32_t type_table[ICE_MAX_PKT_TYPE]
2627 __rte_cache_aligned = {
2630 [1] = RTE_PTYPE_L2_ETHER,
2631 /* [2] - [5] reserved */
2632 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2633 /* [7] - [10] reserved */
2634 [11] = RTE_PTYPE_L2_ETHER_ARP,
2635 /* [12] - [21] reserved */
2637 /* Non tunneled IPv4 */
2638 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2640 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2641 RTE_PTYPE_L4_NONFRAG,
2642 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2645 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2647 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2649 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2653 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2654 RTE_PTYPE_TUNNEL_IP |
2655 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2656 RTE_PTYPE_INNER_L4_FRAG,
2657 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2658 RTE_PTYPE_TUNNEL_IP |
2659 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2660 RTE_PTYPE_INNER_L4_NONFRAG,
2661 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2662 RTE_PTYPE_TUNNEL_IP |
2663 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2664 RTE_PTYPE_INNER_L4_UDP,
2666 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2667 RTE_PTYPE_TUNNEL_IP |
2668 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2669 RTE_PTYPE_INNER_L4_TCP,
2670 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2671 RTE_PTYPE_TUNNEL_IP |
2672 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2673 RTE_PTYPE_INNER_L4_SCTP,
2674 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2675 RTE_PTYPE_TUNNEL_IP |
2676 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2677 RTE_PTYPE_INNER_L4_ICMP,
2680 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2681 RTE_PTYPE_TUNNEL_IP |
2682 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2683 RTE_PTYPE_INNER_L4_FRAG,
2684 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2685 RTE_PTYPE_TUNNEL_IP |
2686 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2687 RTE_PTYPE_INNER_L4_NONFRAG,
2688 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2689 RTE_PTYPE_TUNNEL_IP |
2690 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2691 RTE_PTYPE_INNER_L4_UDP,
2693 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2694 RTE_PTYPE_TUNNEL_IP |
2695 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2696 RTE_PTYPE_INNER_L4_TCP,
2697 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2698 RTE_PTYPE_TUNNEL_IP |
2699 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2700 RTE_PTYPE_INNER_L4_SCTP,
2701 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2702 RTE_PTYPE_TUNNEL_IP |
2703 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2704 RTE_PTYPE_INNER_L4_ICMP,
2706 /* IPv4 --> GRE/Teredo/VXLAN */
2707 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2708 RTE_PTYPE_TUNNEL_GRENAT,
2710 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2711 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2712 RTE_PTYPE_TUNNEL_GRENAT |
2713 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2714 RTE_PTYPE_INNER_L4_FRAG,
2715 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2716 RTE_PTYPE_TUNNEL_GRENAT |
2717 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2718 RTE_PTYPE_INNER_L4_NONFRAG,
2719 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2720 RTE_PTYPE_TUNNEL_GRENAT |
2721 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2722 RTE_PTYPE_INNER_L4_UDP,
2724 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2725 RTE_PTYPE_TUNNEL_GRENAT |
2726 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2727 RTE_PTYPE_INNER_L4_TCP,
2728 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2729 RTE_PTYPE_TUNNEL_GRENAT |
2730 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2731 RTE_PTYPE_INNER_L4_SCTP,
2732 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2733 RTE_PTYPE_TUNNEL_GRENAT |
2734 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2735 RTE_PTYPE_INNER_L4_ICMP,
2737 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2738 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2739 RTE_PTYPE_TUNNEL_GRENAT |
2740 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2741 RTE_PTYPE_INNER_L4_FRAG,
2742 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2743 RTE_PTYPE_TUNNEL_GRENAT |
2744 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2745 RTE_PTYPE_INNER_L4_NONFRAG,
2746 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2747 RTE_PTYPE_TUNNEL_GRENAT |
2748 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2749 RTE_PTYPE_INNER_L4_UDP,
2751 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2752 RTE_PTYPE_TUNNEL_GRENAT |
2753 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2754 RTE_PTYPE_INNER_L4_TCP,
2755 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2756 RTE_PTYPE_TUNNEL_GRENAT |
2757 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2758 RTE_PTYPE_INNER_L4_SCTP,
2759 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2760 RTE_PTYPE_TUNNEL_GRENAT |
2761 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2762 RTE_PTYPE_INNER_L4_ICMP,
2764 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2765 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2766 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2768 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2769 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2770 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2771 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2772 RTE_PTYPE_INNER_L4_FRAG,
2773 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2774 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2775 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2776 RTE_PTYPE_INNER_L4_NONFRAG,
2777 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2778 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2779 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2780 RTE_PTYPE_INNER_L4_UDP,
2782 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2783 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2784 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2785 RTE_PTYPE_INNER_L4_TCP,
2786 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2787 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2788 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2789 RTE_PTYPE_INNER_L4_SCTP,
2790 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2791 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2792 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2793 RTE_PTYPE_INNER_L4_ICMP,
2795 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2796 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2797 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2798 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2799 RTE_PTYPE_INNER_L4_FRAG,
2800 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2801 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2802 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2803 RTE_PTYPE_INNER_L4_NONFRAG,
2804 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2805 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2806 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2807 RTE_PTYPE_INNER_L4_UDP,
2809 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2810 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2811 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2812 RTE_PTYPE_INNER_L4_TCP,
2813 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2814 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2815 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2816 RTE_PTYPE_INNER_L4_SCTP,
2817 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2818 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2819 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2820 RTE_PTYPE_INNER_L4_ICMP,
2822 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
2823 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2824 RTE_PTYPE_TUNNEL_GRENAT |
2825 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2827 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
2828 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2829 RTE_PTYPE_TUNNEL_GRENAT |
2830 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2831 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2832 RTE_PTYPE_INNER_L4_FRAG,
2833 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2834 RTE_PTYPE_TUNNEL_GRENAT |
2835 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2836 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2837 RTE_PTYPE_INNER_L4_NONFRAG,
2838 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2839 RTE_PTYPE_TUNNEL_GRENAT |
2840 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2841 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2842 RTE_PTYPE_INNER_L4_UDP,
2844 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2845 RTE_PTYPE_TUNNEL_GRENAT |
2846 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2847 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2848 RTE_PTYPE_INNER_L4_TCP,
2849 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2850 RTE_PTYPE_TUNNEL_GRENAT |
2851 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2852 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2853 RTE_PTYPE_INNER_L4_SCTP,
2854 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2855 RTE_PTYPE_TUNNEL_GRENAT |
2856 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2857 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2858 RTE_PTYPE_INNER_L4_ICMP,
2860 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
2861 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2862 RTE_PTYPE_TUNNEL_GRENAT |
2863 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2864 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2865 RTE_PTYPE_INNER_L4_FRAG,
2866 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2867 RTE_PTYPE_TUNNEL_GRENAT |
2868 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2869 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2870 RTE_PTYPE_INNER_L4_NONFRAG,
2871 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2872 RTE_PTYPE_TUNNEL_GRENAT |
2873 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2874 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2875 RTE_PTYPE_INNER_L4_UDP,
2877 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2878 RTE_PTYPE_TUNNEL_GRENAT |
2879 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2880 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2881 RTE_PTYPE_INNER_L4_TCP,
2882 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2883 RTE_PTYPE_TUNNEL_GRENAT |
2884 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2885 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2886 RTE_PTYPE_INNER_L4_SCTP,
2887 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2888 RTE_PTYPE_TUNNEL_GRENAT |
2889 RTE_PTYPE_INNER_L2_ETHER_VLAN |
2890 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2891 RTE_PTYPE_INNER_L4_ICMP,
2893 /* Non tunneled IPv6 */
2894 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2896 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2897 RTE_PTYPE_L4_NONFRAG,
2898 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2901 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2903 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2905 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2909 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2910 RTE_PTYPE_TUNNEL_IP |
2911 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2912 RTE_PTYPE_INNER_L4_FRAG,
2913 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2914 RTE_PTYPE_TUNNEL_IP |
2915 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2916 RTE_PTYPE_INNER_L4_NONFRAG,
2917 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2918 RTE_PTYPE_TUNNEL_IP |
2919 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2920 RTE_PTYPE_INNER_L4_UDP,
2922 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2923 RTE_PTYPE_TUNNEL_IP |
2924 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2925 RTE_PTYPE_INNER_L4_TCP,
2926 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2927 RTE_PTYPE_TUNNEL_IP |
2928 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2929 RTE_PTYPE_INNER_L4_SCTP,
2930 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2931 RTE_PTYPE_TUNNEL_IP |
2932 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2933 RTE_PTYPE_INNER_L4_ICMP,
2936 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2937 RTE_PTYPE_TUNNEL_IP |
2938 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2939 RTE_PTYPE_INNER_L4_FRAG,
2940 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2941 RTE_PTYPE_TUNNEL_IP |
2942 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2943 RTE_PTYPE_INNER_L4_NONFRAG,
2944 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2945 RTE_PTYPE_TUNNEL_IP |
2946 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2947 RTE_PTYPE_INNER_L4_UDP,
2948 /* [105] reserved */
2949 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2950 RTE_PTYPE_TUNNEL_IP |
2951 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2952 RTE_PTYPE_INNER_L4_TCP,
2953 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2954 RTE_PTYPE_TUNNEL_IP |
2955 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2956 RTE_PTYPE_INNER_L4_SCTP,
2957 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2958 RTE_PTYPE_TUNNEL_IP |
2959 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2960 RTE_PTYPE_INNER_L4_ICMP,
2962 /* IPv6 --> GRE/Teredo/VXLAN */
2963 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2964 RTE_PTYPE_TUNNEL_GRENAT,
2966 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2967 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2968 RTE_PTYPE_TUNNEL_GRENAT |
2969 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2970 RTE_PTYPE_INNER_L4_FRAG,
2971 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2972 RTE_PTYPE_TUNNEL_GRENAT |
2973 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2974 RTE_PTYPE_INNER_L4_NONFRAG,
2975 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2976 RTE_PTYPE_TUNNEL_GRENAT |
2977 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2978 RTE_PTYPE_INNER_L4_UDP,
2979 /* [113] reserved */
2980 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2981 RTE_PTYPE_TUNNEL_GRENAT |
2982 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2983 RTE_PTYPE_INNER_L4_TCP,
2984 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2985 RTE_PTYPE_TUNNEL_GRENAT |
2986 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2987 RTE_PTYPE_INNER_L4_SCTP,
2988 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2989 RTE_PTYPE_TUNNEL_GRENAT |
2990 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2991 RTE_PTYPE_INNER_L4_ICMP,
2993 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2994 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2995 RTE_PTYPE_TUNNEL_GRENAT |
2996 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2997 RTE_PTYPE_INNER_L4_FRAG,
2998 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2999 RTE_PTYPE_TUNNEL_GRENAT |
3000 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3001 RTE_PTYPE_INNER_L4_NONFRAG,
3002 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3003 RTE_PTYPE_TUNNEL_GRENAT |
3004 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3005 RTE_PTYPE_INNER_L4_UDP,
3006 /* [120] reserved */
3007 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3008 RTE_PTYPE_TUNNEL_GRENAT |
3009 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3010 RTE_PTYPE_INNER_L4_TCP,
3011 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3012 RTE_PTYPE_TUNNEL_GRENAT |
3013 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3014 RTE_PTYPE_INNER_L4_SCTP,
3015 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3016 RTE_PTYPE_TUNNEL_GRENAT |
3017 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3018 RTE_PTYPE_INNER_L4_ICMP,
3020 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3021 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3022 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3024 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3025 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3026 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3027 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3028 RTE_PTYPE_INNER_L4_FRAG,
3029 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3030 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3031 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3032 RTE_PTYPE_INNER_L4_NONFRAG,
3033 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3034 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3035 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3036 RTE_PTYPE_INNER_L4_UDP,
3037 /* [128] reserved */
3038 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3039 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3040 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3041 RTE_PTYPE_INNER_L4_TCP,
3042 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3043 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3044 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3045 RTE_PTYPE_INNER_L4_SCTP,
3046 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3047 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3048 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3049 RTE_PTYPE_INNER_L4_ICMP,
3051 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3052 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3053 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3054 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3055 RTE_PTYPE_INNER_L4_FRAG,
3056 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3057 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3058 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3059 RTE_PTYPE_INNER_L4_NONFRAG,
3060 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3061 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3062 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3063 RTE_PTYPE_INNER_L4_UDP,
3064 /* [135] reserved */
3065 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3066 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3067 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3068 RTE_PTYPE_INNER_L4_TCP,
3069 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3070 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3071 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3072 RTE_PTYPE_INNER_L4_SCTP,
3073 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3074 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3075 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3076 RTE_PTYPE_INNER_L4_ICMP,
3078 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
3079 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3080 RTE_PTYPE_TUNNEL_GRENAT |
3081 RTE_PTYPE_INNER_L2_ETHER_VLAN,
3083 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
3084 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3085 RTE_PTYPE_TUNNEL_GRENAT |
3086 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3087 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3088 RTE_PTYPE_INNER_L4_FRAG,
3089 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3090 RTE_PTYPE_TUNNEL_GRENAT |
3091 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3092 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3093 RTE_PTYPE_INNER_L4_NONFRAG,
3094 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3095 RTE_PTYPE_TUNNEL_GRENAT |
3096 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3097 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3098 RTE_PTYPE_INNER_L4_UDP,
3099 /* [143] reserved */
3100 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3101 RTE_PTYPE_TUNNEL_GRENAT |
3102 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3103 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3104 RTE_PTYPE_INNER_L4_TCP,
3105 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3106 RTE_PTYPE_TUNNEL_GRENAT |
3107 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3108 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3109 RTE_PTYPE_INNER_L4_SCTP,
3110 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3111 RTE_PTYPE_TUNNEL_GRENAT |
3112 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3113 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3114 RTE_PTYPE_INNER_L4_ICMP,
3116 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
3117 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3118 RTE_PTYPE_TUNNEL_GRENAT |
3119 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3120 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3121 RTE_PTYPE_INNER_L4_FRAG,
3122 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3123 RTE_PTYPE_TUNNEL_GRENAT |
3124 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3125 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3126 RTE_PTYPE_INNER_L4_NONFRAG,
3127 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3128 RTE_PTYPE_TUNNEL_GRENAT |
3129 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3130 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3131 RTE_PTYPE_INNER_L4_UDP,
3132 /* [150] reserved */
3133 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3134 RTE_PTYPE_TUNNEL_GRENAT |
3135 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3136 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3137 RTE_PTYPE_INNER_L4_TCP,
3138 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3139 RTE_PTYPE_TUNNEL_GRENAT |
3140 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3141 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3142 RTE_PTYPE_INNER_L4_SCTP,
3143 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3144 RTE_PTYPE_TUNNEL_GRENAT |
3145 RTE_PTYPE_INNER_L2_ETHER_VLAN |
3146 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3147 RTE_PTYPE_INNER_L4_ICMP,
3148 /* [154] - [255] reserved */
3149 [256] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3150 RTE_PTYPE_TUNNEL_GTPC,
3151 [257] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3152 RTE_PTYPE_TUNNEL_GTPC,
3153 [258] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3154 RTE_PTYPE_TUNNEL_GTPU,
3155 [259] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3156 RTE_PTYPE_TUNNEL_GTPU,
3157 /* [260] - [263] reserved */
3158 [264] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3159 RTE_PTYPE_TUNNEL_GTPC,
3160 [265] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3161 RTE_PTYPE_TUNNEL_GTPC,
3162 [266] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3163 RTE_PTYPE_TUNNEL_GTPU,
3164 [267] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3165 RTE_PTYPE_TUNNEL_GTPU,
3167 /* All others reserved */
3170 return type_table[ptype];
3173 void __attribute__((cold))
3174 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3176 struct ice_adapter *ad =
3177 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3180 for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3181 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);