drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "rte_pmd_ice.h"
   9 #include "ice_rxtx.h"
  10
  11 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  12                 PKT_TX_IP_CKSUM |                \
  13                 PKT_TX_L4_MASK |                 \
  14                 PKT_TX_TCP_SEG |                 \
  15                 PKT_TX_OUTER_IP_CKSUM)
  16
  17 /* Offset of mbuf dynamic field for protocol extraction data */
  18 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  19
  20 /* Mask of mbuf dynamic flags for protocol extraction type */
  21 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  22 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  27
  28 static inline uint64_t
  29 ice_rxdid_to_proto_xtr_ol_flag(uint8_t rxdid, bool *chk_valid)
  30 {
  31         static struct {
  32                 uint64_t *ol_flag;
  33                 bool chk_valid;
  34         } ol_flag_map[] = {
  35                 [ICE_RXDID_COMMS_AUX_VLAN] = {
  36                         &rte_net_ice_dynflag_proto_xtr_vlan_mask, true },
  37                 [ICE_RXDID_COMMS_AUX_IPV4] = {
  38                         &rte_net_ice_dynflag_proto_xtr_ipv4_mask, true },
  39                 [ICE_RXDID_COMMS_AUX_IPV6] = {
  40                         &rte_net_ice_dynflag_proto_xtr_ipv6_mask, true },
  41                 [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = {
  42                         &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask, true },
  43                 [ICE_RXDID_COMMS_AUX_TCP] = {
  44                         &rte_net_ice_dynflag_proto_xtr_tcp_mask, true },
  45                 [ICE_RXDID_COMMS_AUX_IP_OFFSET] = {
  46                         &rte_net_ice_dynflag_proto_xtr_ip_offset_mask, false },
  47         };
  48         uint64_t *ol_flag;
  49
  50         if (rxdid < RTE_DIM(ol_flag_map)) {
  51                 ol_flag = ol_flag_map[rxdid].ol_flag;
  52                 if (!ol_flag)
  53                         return 0ULL;
  54
  55                 *chk_valid = ol_flag_map[rxdid].chk_valid;
  56                 return *ol_flag;
  57         }
  58
  59         return 0ULL;
  60 }
  61
  62 static inline uint8_t
  63 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  64 {
  65         static uint8_t rxdid_map[] = {
  66                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_GENERIC,
  67                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  68                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  69                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  70                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  71                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  72                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  73         };
  74
  75         return xtr_type < RTE_DIM(rxdid_map) ?
  76                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_GENERIC;
  77 }
  78
  79 static enum ice_status
  80 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  81 {
  82         struct ice_vsi *vsi = rxq->vsi;
  83         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  84         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  85         struct ice_rlan_ctx rx_ctx;
  86         enum ice_status err;
  87         uint16_t buf_size, len;
  88         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  89         uint32_t rxdid = ICE_RXDID_COMMS_GENERIC;
  90         uint32_t regval;
  91
  92         /* Set buffer size as the head split is disabled. */
  93         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  94                               RTE_PKTMBUF_HEADROOM);
  95         rxq->rx_hdr_len = 0;
  96         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  97         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  98         rxq->max_pkt_len = RTE_MIN(len,
  99                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
 100
 101         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 102                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
 103                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 104                         PMD_DRV_LOG(ERR, "maximum packet length must "
 105                                     "be larger than %u and smaller than %u,"
 106                                     "as jumbo frame is enabled",
 107                                     (uint32_t)RTE_ETHER_MAX_LEN,
 108                                     (uint32_t)ICE_FRAME_SIZE_MAX);
 109                         return -EINVAL;
 110                 }
 111         } else {
 112                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
 113                     rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
 114                         PMD_DRV_LOG(ERR, "maximum packet length must be "
 115                                     "larger than %u and smaller than %u, "
 116                                     "as jumbo frame is disabled",
 117                                     (uint32_t)RTE_ETHER_MIN_LEN,
 118                                     (uint32_t)RTE_ETHER_MAX_LEN);
 119                         return -EINVAL;
 120                 }
 121         }
 122
 123         memset(&rx_ctx, 0, sizeof(rx_ctx));
 124
 125         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 126         rx_ctx.qlen = rxq->nb_rx_desc;
 127         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 128         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 129         rx_ctx.dtype = 0; /* No Header Split mode */
 130 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 131         rx_ctx.dsize = 1; /* 32B descriptors */
 132 #endif
 133         rx_ctx.rxmax = rxq->max_pkt_len;
 134         /* TPH: Transaction Layer Packet (TLP) processing hints */
 135         rx_ctx.tphrdesc_ena = 1;
 136         rx_ctx.tphwdesc_ena = 1;
 137         rx_ctx.tphdata_ena = 1;
 138         rx_ctx.tphhead_ena = 1;
 139         /* Low Receive Queue Threshold defined in 64 descriptors units.
 140          * When the number of free descriptors goes below the lrxqthresh,
 141          * an immediate interrupt is triggered.
 142          */
 143         rx_ctx.lrxqthresh = 2;
 144         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 145         rx_ctx.l2tsel = 1;
 146         rx_ctx.showiv = 0;
 147         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 148
 149         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 150
 151         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 152                     rxq->port_id, rxq->queue_id, rxdid);
 153
 154         /* Enable Flexible Descriptors in the queue context which
 155          * allows this driver to select a specific receive descriptor format
 156          */
 157         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 158                 QRXFLXP_CNTXT_RXDID_IDX_M;
 159
 160         /* increasing context priority to pick up profile ID;
 161          * default is 0x01; setting to 0x03 to ensure profile
 162          * is programming if prev context is of same priority
 163          */
 164         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 165                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 166
 167         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 168
 169         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 170         if (err) {
 171                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 172                             rxq->queue_id);
 173                 return -EINVAL;
 174         }
 175         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 176         if (err) {
 177                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 178                             rxq->queue_id);
 179                 return -EINVAL;
 180         }
 181
 182         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 183                               RTE_PKTMBUF_HEADROOM);
 184
 185         /* Check if scattered RX needs to be used. */
 186         if (rxq->max_pkt_len > buf_size)
 187                 dev->data->scattered_rx = 1;
 188
 189         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 190
 191         /* Init the Rx tail register*/
 192         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 193
 194         return 0;
 195 }
 196
 197 /* Allocate mbufs for all descriptors in rx queue */
 198 static int
 199 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 200 {
 201         struct ice_rx_entry *rxe = rxq->sw_ring;
 202         uint64_t dma_addr;
 203         uint16_t i;
 204
 205         for (i = 0; i < rxq->nb_rx_desc; i++) {
 206                 volatile union ice_rx_flex_desc *rxd;
 207                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 208
 209                 if (unlikely(!mbuf)) {
 210                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 211                         return -ENOMEM;
 212                 }
 213
 214                 rte_mbuf_refcnt_set(mbuf, 1);
 215                 mbuf->next = NULL;
 216                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 217                 mbuf->nb_segs = 1;
 218                 mbuf->port = rxq->port_id;
 219
 220                 dma_addr =
 221                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 222
 223                 rxd = &rxq->rx_ring[i];
 224                 rxd->read.pkt_addr = dma_addr;
 225                 rxd->read.hdr_addr = 0;
 226 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 227                 rxd->read.rsvd1 = 0;
 228                 rxd->read.rsvd2 = 0;
 229 #endif
 230                 rxe[i].mbuf = mbuf;
 231         }
 232
 233         return 0;
 234 }
 235
 236 /* Free all mbufs for descriptors in rx queue */
 237 static void
 238 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 239 {
 240         uint16_t i;
 241
 242         if (!rxq || !rxq->sw_ring) {
 243                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 244                 return;
 245         }
 246
 247         for (i = 0; i < rxq->nb_rx_desc; i++) {
 248                 if (rxq->sw_ring[i].mbuf) {
 249                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 250                         rxq->sw_ring[i].mbuf = NULL;
 251                 }
 252         }
 253         if (rxq->rx_nb_avail == 0)
 254                 return;
 255         for (i = 0; i < rxq->rx_nb_avail; i++)
 256                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 257
 258         rxq->rx_nb_avail = 0;
 259 }
 260
 261 /* turn on or off rx queue
 262  * @q_idx: queue index in pf scope
 263  * @on: turn on or off the queue
 264  */
 265 static int
 266 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 267 {
 268         uint32_t reg;
 269         uint16_t j;
 270
 271         /* QRX_CTRL = QRX_ENA */
 272         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 273
 274         if (on) {
 275                 if (reg & QRX_CTRL_QENA_STAT_M)
 276                         return 0; /* Already on, skip */
 277                 reg |= QRX_CTRL_QENA_REQ_M;
 278         } else {
 279                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 280                         return 0; /* Already off, skip */
 281                 reg &= ~QRX_CTRL_QENA_REQ_M;
 282         }
 283
 284         /* Write the register */
 285         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 286         /* Check the result. It is said that QENA_STAT
 287          * follows the QENA_REQ not more than 10 use.
 288          * TODO: need to change the wait counter later
 289          */
 290         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 291                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 292                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 293                 if (on) {
 294                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 295                             (reg & QRX_CTRL_QENA_STAT_M))
 296                                 break;
 297                 } else {
 298                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 299                             !(reg & QRX_CTRL_QENA_STAT_M))
 300                                 break;
 301                 }
 302         }
 303
 304         /* Check if it is timeout */
 305         if (j >= ICE_CHK_Q_ENA_COUNT) {
 306                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 307                             (on ? "enable" : "disable"), q_idx);
 308                 return -ETIMEDOUT;
 309         }
 310
 311         return 0;
 312 }
 313
 314 static inline int
 315 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 316 {
 317         int ret = 0;
 318
 319         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 320                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 321                              "rxq->rx_free_thresh=%d, "
 322                              "ICE_RX_MAX_BURST=%d",
 323                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 324                 ret = -EINVAL;
 325         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 326                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 327                              "rxq->rx_free_thresh=%d, "
 328                              "rxq->nb_rx_desc=%d",
 329                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 330                 ret = -EINVAL;
 331         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 332                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 333                              "rxq->nb_rx_desc=%d, "
 334                              "rxq->rx_free_thresh=%d",
 335                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 336                 ret = -EINVAL;
 337         }
 338
 339         return ret;
 340 }
 341
 342 /* reset fields in ice_rx_queue back to default */
 343 static void
 344 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 345 {
 346         unsigned int i;
 347         uint16_t len;
 348
 349         if (!rxq) {
 350                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 351                 return;
 352         }
 353
 354         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 355
 356         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 357                 ((volatile char *)rxq->rx_ring)[i] = 0;
 358
 359         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 360         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 361                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 362
 363         rxq->rx_nb_avail = 0;
 364         rxq->rx_next_avail = 0;
 365         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 366
 367         rxq->rx_tail = 0;
 368         rxq->nb_rx_hold = 0;
 369         rxq->pkt_first_seg = NULL;
 370         rxq->pkt_last_seg = NULL;
 371
 372         rxq->rxrearm_start = 0;
 373         rxq->rxrearm_nb = 0;
 374 }
 375
 376 int
 377 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 378 {
 379         struct ice_rx_queue *rxq;
 380         int err;
 381         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 382
 383         PMD_INIT_FUNC_TRACE();
 384
 385         if (rx_queue_id >= dev->data->nb_rx_queues) {
 386                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 387                             rx_queue_id, dev->data->nb_rx_queues);
 388                 return -EINVAL;
 389         }
 390
 391         rxq = dev->data->rx_queues[rx_queue_id];
 392         if (!rxq || !rxq->q_set) {
 393                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 394                             rx_queue_id);
 395                 return -EINVAL;
 396         }
 397
 398         err = ice_program_hw_rx_queue(rxq);
 399         if (err) {
 400                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 401                             rx_queue_id);
 402                 return -EIO;
 403         }
 404
 405         err = ice_alloc_rx_queue_mbufs(rxq);
 406         if (err) {
 407                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 408                 return -ENOMEM;
 409         }
 410
 411         /* Init the RX tail register. */
 412         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 413
 414         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 415         if (err) {
 416                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 417                             rx_queue_id);
 418
 419                 rxq->rx_rel_mbufs(rxq);
 420                 ice_reset_rx_queue(rxq);
 421                 return -EINVAL;
 422         }
 423
 424         dev->data->rx_queue_state[rx_queue_id] =
 425                 RTE_ETH_QUEUE_STATE_STARTED;
 426
 427         return 0;
 428 }
 429
 430 int
 431 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 432 {
 433         struct ice_rx_queue *rxq;
 434         int err;
 435         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 436
 437         if (rx_queue_id < dev->data->nb_rx_queues) {
 438                 rxq = dev->data->rx_queues[rx_queue_id];
 439
 440                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 441                 if (err) {
 442                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 443                                     rx_queue_id);
 444                         return -EINVAL;
 445                 }
 446                 rxq->rx_rel_mbufs(rxq);
 447                 ice_reset_rx_queue(rxq);
 448                 dev->data->rx_queue_state[rx_queue_id] =
 449                         RTE_ETH_QUEUE_STATE_STOPPED;
 450         }
 451
 452         return 0;
 453 }
 454
 455 int
 456 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 457 {
 458         struct ice_tx_queue *txq;
 459         int err;
 460         struct ice_vsi *vsi;
 461         struct ice_hw *hw;
 462         struct ice_aqc_add_tx_qgrp *txq_elem;
 463         struct ice_tlan_ctx tx_ctx;
 464         int buf_len;
 465
 466         PMD_INIT_FUNC_TRACE();
 467
 468         if (tx_queue_id >= dev->data->nb_tx_queues) {
 469                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 470                             tx_queue_id, dev->data->nb_tx_queues);
 471                 return -EINVAL;
 472         }
 473
 474         txq = dev->data->tx_queues[tx_queue_id];
 475         if (!txq || !txq->q_set) {
 476                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 477                             tx_queue_id);
 478                 return -EINVAL;
 479         }
 480
 481         buf_len = ice_struct_size(txq_elem, txqs, 1);
 482         txq_elem = ice_malloc(hw, buf_len);
 483         if (!txq_elem)
 484                 return -ENOMEM;
 485
 486         vsi = txq->vsi;
 487         hw = ICE_VSI_TO_HW(vsi);
 488
 489         memset(&tx_ctx, 0, sizeof(tx_ctx));
 490         txq_elem->num_txqs = 1;
 491         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 492
 493         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 494         tx_ctx.qlen = txq->nb_tx_desc;
 495         tx_ctx.pf_num = hw->pf_id;
 496         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 497         tx_ctx.src_vsi = vsi->vsi_id;
 498         tx_ctx.port_num = hw->port_info->lport;
 499         tx_ctx.tso_ena = 1; /* tso enable */
 500         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 501         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 502
 503         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 504                     ice_tlan_ctx_info);
 505
 506         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 507
 508         /* Init the Tx tail register*/
 509         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 510
 511         /* Fix me, we assume TC always 0 here */
 512         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 513                         txq_elem, buf_len, NULL);
 514         if (err) {
 515                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 516                 rte_free(txq_elem);
 517                 return -EIO;
 518         }
 519         /* store the schedule node id */
 520         txq->q_teid = txq_elem->txqs[0].q_teid;
 521
 522         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 523
 524         rte_free(txq_elem);
 525         return 0;
 526 }
 527
 528 static enum ice_status
 529 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 530 {
 531         struct ice_vsi *vsi = rxq->vsi;
 532         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 533         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 534         struct ice_rlan_ctx rx_ctx;
 535         enum ice_status err;
 536         uint32_t regval;
 537
 538         rxq->rx_hdr_len = 0;
 539         rxq->rx_buf_len = 1024;
 540
 541         memset(&rx_ctx, 0, sizeof(rx_ctx));
 542
 543         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 544         rx_ctx.qlen = rxq->nb_rx_desc;
 545         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 546         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 547         rx_ctx.dtype = 0; /* No Header Split mode */
 548         rx_ctx.dsize = 1; /* 32B descriptors */
 549         rx_ctx.rxmax = RTE_ETHER_MAX_LEN;
 550         /* TPH: Transaction Layer Packet (TLP) processing hints */
 551         rx_ctx.tphrdesc_ena = 1;
 552         rx_ctx.tphwdesc_ena = 1;
 553         rx_ctx.tphdata_ena = 1;
 554         rx_ctx.tphhead_ena = 1;
 555         /* Low Receive Queue Threshold defined in 64 descriptors units.
 556          * When the number of free descriptors goes below the lrxqthresh,
 557          * an immediate interrupt is triggered.
 558          */
 559         rx_ctx.lrxqthresh = 2;
 560         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 561         rx_ctx.l2tsel = 1;
 562         rx_ctx.showiv = 0;
 563         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 564
 565         /* Enable Flexible Descriptors in the queue context which
 566          * allows this driver to select a specific receive descriptor format
 567          */
 568         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 569                 QRXFLXP_CNTXT_RXDID_IDX_M;
 570
 571         /* increasing context priority to pick up profile ID;
 572          * default is 0x01; setting to 0x03 to ensure profile
 573          * is programming if prev context is of same priority
 574          */
 575         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 576                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 577
 578         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 579
 580         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 581         if (err) {
 582                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 583                             rxq->queue_id);
 584                 return -EINVAL;
 585         }
 586         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 587         if (err) {
 588                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 589                             rxq->queue_id);
 590                 return -EINVAL;
 591         }
 592
 593         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 594
 595         /* Init the Rx tail register*/
 596         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 597
 598         return 0;
 599 }
 600
 601 int
 602 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 603 {
 604         struct ice_rx_queue *rxq;
 605         int err;
 606         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 607         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 608
 609         PMD_INIT_FUNC_TRACE();
 610
 611         rxq = pf->fdir.rxq;
 612         if (!rxq || !rxq->q_set) {
 613                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 614                             rx_queue_id);
 615                 return -EINVAL;
 616         }
 617
 618         err = ice_fdir_program_hw_rx_queue(rxq);
 619         if (err) {
 620                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 621                             rx_queue_id);
 622                 return -EIO;
 623         }
 624
 625         /* Init the RX tail register. */
 626         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 627
 628         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 629         if (err) {
 630                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 631                             rx_queue_id);
 632
 633                 ice_reset_rx_queue(rxq);
 634                 return -EINVAL;
 635         }
 636
 637         return 0;
 638 }
 639
 640 int
 641 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 642 {
 643         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 644         struct ice_tx_queue *txq;
 645         int err;
 646         struct ice_vsi *vsi;
 647         struct ice_hw *hw;
 648         struct ice_aqc_add_tx_qgrp *txq_elem;
 649         struct ice_tlan_ctx tx_ctx;
 650         int buf_len;
 651
 652         PMD_INIT_FUNC_TRACE();
 653
 654         txq = pf->fdir.txq;
 655         if (!txq || !txq->q_set) {
 656                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 657                             tx_queue_id);
 658                 return -EINVAL;
 659         }
 660
 661         buf_len = ice_struct_size(txq_elem, txqs, 1);
 662         txq_elem = ice_malloc(hw, buf_len);
 663         if (!txq_elem)
 664                 return -ENOMEM;
 665
 666         vsi = txq->vsi;
 667         hw = ICE_VSI_TO_HW(vsi);
 668
 669         memset(&tx_ctx, 0, sizeof(tx_ctx));
 670         txq_elem->num_txqs = 1;
 671         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 672
 673         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 674         tx_ctx.qlen = txq->nb_tx_desc;
 675         tx_ctx.pf_num = hw->pf_id;
 676         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 677         tx_ctx.src_vsi = vsi->vsi_id;
 678         tx_ctx.port_num = hw->port_info->lport;
 679         tx_ctx.tso_ena = 1; /* tso enable */
 680         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 681         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 682
 683         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 684                     ice_tlan_ctx_info);
 685
 686         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 687
 688         /* Init the Tx tail register*/
 689         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 690
 691         /* Fix me, we assume TC always 0 here */
 692         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 693                               txq_elem, buf_len, NULL);
 694         if (err) {
 695                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 696                 rte_free(txq_elem);
 697                 return -EIO;
 698         }
 699         /* store the schedule node id */
 700         txq->q_teid = txq_elem->txqs[0].q_teid;
 701
 702         rte_free(txq_elem);
 703         return 0;
 704 }
 705
 706 /* Free all mbufs for descriptors in tx queue */
 707 static void
 708 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 709 {
 710         uint16_t i;
 711
 712         if (!txq || !txq->sw_ring) {
 713                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 714                 return;
 715         }
 716
 717         for (i = 0; i < txq->nb_tx_desc; i++) {
 718                 if (txq->sw_ring[i].mbuf) {
 719                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 720                         txq->sw_ring[i].mbuf = NULL;
 721                 }
 722         }
 723 }
 724
 725 static void
 726 ice_reset_tx_queue(struct ice_tx_queue *txq)
 727 {
 728         struct ice_tx_entry *txe;
 729         uint16_t i, prev, size;
 730
 731         if (!txq) {
 732                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 733                 return;
 734         }
 735
 736         txe = txq->sw_ring;
 737         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 738         for (i = 0; i < size; i++)
 739                 ((volatile char *)txq->tx_ring)[i] = 0;
 740
 741         prev = (uint16_t)(txq->nb_tx_desc - 1);
 742         for (i = 0; i < txq->nb_tx_desc; i++) {
 743                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 744
 745                 txd->cmd_type_offset_bsz =
 746                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 747                 txe[i].mbuf =  NULL;
 748                 txe[i].last_id = i;
 749                 txe[prev].next_id = i;
 750                 prev = i;
 751         }
 752
 753         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 754         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 755
 756         txq->tx_tail = 0;
 757         txq->nb_tx_used = 0;
 758
 759         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 760         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 761 }
 762
 763 int
 764 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 765 {
 766         struct ice_tx_queue *txq;
 767         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 768         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 769         struct ice_vsi *vsi = pf->main_vsi;
 770         enum ice_status status;
 771         uint16_t q_ids[1];
 772         uint32_t q_teids[1];
 773         uint16_t q_handle = tx_queue_id;
 774
 775         if (tx_queue_id >= dev->data->nb_tx_queues) {
 776                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 777                             tx_queue_id, dev->data->nb_tx_queues);
 778                 return -EINVAL;
 779         }
 780
 781         txq = dev->data->tx_queues[tx_queue_id];
 782         if (!txq) {
 783                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 784                             tx_queue_id);
 785                 return -EINVAL;
 786         }
 787
 788         q_ids[0] = txq->reg_idx;
 789         q_teids[0] = txq->q_teid;
 790
 791         /* Fix me, we assume TC always 0 here */
 792         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 793                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 794         if (status != ICE_SUCCESS) {
 795                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 796                 return -EINVAL;
 797         }
 798
 799         txq->tx_rel_mbufs(txq);
 800         ice_reset_tx_queue(txq);
 801         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 802
 803         return 0;
 804 }
 805
 806 int
 807 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 808 {
 809         struct ice_rx_queue *rxq;
 810         int err;
 811         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 812         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 813
 814         rxq = pf->fdir.rxq;
 815
 816         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 817         if (err) {
 818                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
 819                             rx_queue_id);
 820                 return -EINVAL;
 821         }
 822         rxq->rx_rel_mbufs(rxq);
 823
 824         return 0;
 825 }
 826
 827 int
 828 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 829 {
 830         struct ice_tx_queue *txq;
 831         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 832         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 833         struct ice_vsi *vsi = pf->main_vsi;
 834         enum ice_status status;
 835         uint16_t q_ids[1];
 836         uint32_t q_teids[1];
 837         uint16_t q_handle = tx_queue_id;
 838
 839         txq = pf->fdir.txq;
 840         if (!txq) {
 841                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 842                             tx_queue_id);
 843                 return -EINVAL;
 844         }
 845         vsi = txq->vsi;
 846
 847         q_ids[0] = txq->reg_idx;
 848         q_teids[0] = txq->q_teid;
 849
 850         /* Fix me, we assume TC always 0 here */
 851         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 852                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 853         if (status != ICE_SUCCESS) {
 854                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 855                 return -EINVAL;
 856         }
 857
 858         txq->tx_rel_mbufs(txq);
 859
 860         return 0;
 861 }
 862
 863 int
 864 ice_rx_queue_setup(struct rte_eth_dev *dev,
 865                    uint16_t queue_idx,
 866                    uint16_t nb_desc,
 867                    unsigned int socket_id,
 868                    const struct rte_eth_rxconf *rx_conf,
 869                    struct rte_mempool *mp)
 870 {
 871         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 872         struct ice_adapter *ad =
 873                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 874         struct ice_vsi *vsi = pf->main_vsi;
 875         struct ice_rx_queue *rxq;
 876         const struct rte_memzone *rz;
 877         uint32_t ring_size;
 878         uint16_t len;
 879         int use_def_burst_func = 1;
 880
 881         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 882             nb_desc > ICE_MAX_RING_DESC ||
 883             nb_desc < ICE_MIN_RING_DESC) {
 884                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 885                              "invalid", nb_desc);
 886                 return -EINVAL;
 887         }
 888
 889         /* Free memory if needed */
 890         if (dev->data->rx_queues[queue_idx]) {
 891                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 892                 dev->data->rx_queues[queue_idx] = NULL;
 893         }
 894
 895         /* Allocate the rx queue data structure */
 896         rxq = rte_zmalloc_socket(NULL,
 897                                  sizeof(struct ice_rx_queue),
 898                                  RTE_CACHE_LINE_SIZE,
 899                                  socket_id);
 900         if (!rxq) {
 901                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 902                              "rx queue data structure");
 903                 return -ENOMEM;
 904         }
 905         rxq->mp = mp;
 906         rxq->nb_rx_desc = nb_desc;
 907         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 908         rxq->queue_id = queue_idx;
 909
 910         rxq->reg_idx = vsi->base_queue + queue_idx;
 911         rxq->port_id = dev->data->port_id;
 912         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 913                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 914         else
 915                 rxq->crc_len = 0;
 916
 917         rxq->drop_en = rx_conf->rx_drop_en;
 918         rxq->vsi = vsi;
 919         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 920         rxq->proto_xtr = pf->proto_xtr != NULL ?
 921                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
 922
 923         /* Allocate the maximun number of RX ring hardware descriptor. */
 924         len = ICE_MAX_RING_DESC;
 925
 926         /**
 927          * Allocating a little more memory because vectorized/bulk_alloc Rx
 928          * functions doesn't check boundaries each time.
 929          */
 930         len += ICE_RX_MAX_BURST;
 931
 932         /* Allocate the maximum number of RX ring hardware descriptor. */
 933         ring_size = sizeof(union ice_rx_flex_desc) * len;
 934         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 935         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 936                                       ring_size, ICE_RING_BASE_ALIGN,
 937                                       socket_id);
 938         if (!rz) {
 939                 ice_rx_queue_release(rxq);
 940                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 941                 return -ENOMEM;
 942         }
 943
 944         /* Zero all the descriptors in the ring. */
 945         memset(rz->addr, 0, ring_size);
 946
 947         rxq->rx_ring_dma = rz->iova;
 948         rxq->rx_ring = rz->addr;
 949
 950         /* always reserve more for bulk alloc */
 951         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 952
 953         /* Allocate the software ring. */
 954         rxq->sw_ring = rte_zmalloc_socket(NULL,
 955                                           sizeof(struct ice_rx_entry) * len,
 956                                           RTE_CACHE_LINE_SIZE,
 957                                           socket_id);
 958         if (!rxq->sw_ring) {
 959                 ice_rx_queue_release(rxq);
 960                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 961                 return -ENOMEM;
 962         }
 963
 964         ice_reset_rx_queue(rxq);
 965         rxq->q_set = true;
 966         dev->data->rx_queues[queue_idx] = rxq;
 967         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
 968
 969         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 970
 971         if (!use_def_burst_func) {
 972                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 973                              "satisfied. Rx Burst Bulk Alloc function will be "
 974                              "used on port=%d, queue=%d.",
 975                              rxq->port_id, rxq->queue_id);
 976         } else {
 977                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 978                              "not satisfied, Scattered Rx is requested. "
 979                              "on port=%d, queue=%d.",
 980                              rxq->port_id, rxq->queue_id);
 981                 ad->rx_bulk_alloc_allowed = false;
 982         }
 983
 984         return 0;
 985 }
 986
 987 void
 988 ice_rx_queue_release(void *rxq)
 989 {
 990         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
 991
 992         if (!q) {
 993                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 994                 return;
 995         }
 996
 997         q->rx_rel_mbufs(q);
 998         rte_free(q->sw_ring);
 999         rte_free(q);
1000 }
1001
1002 int
1003 ice_tx_queue_setup(struct rte_eth_dev *dev,
1004                    uint16_t queue_idx,
1005                    uint16_t nb_desc,
1006                    unsigned int socket_id,
1007                    const struct rte_eth_txconf *tx_conf)
1008 {
1009         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1010         struct ice_vsi *vsi = pf->main_vsi;
1011         struct ice_tx_queue *txq;
1012         const struct rte_memzone *tz;
1013         uint32_t ring_size;
1014         uint16_t tx_rs_thresh, tx_free_thresh;
1015         uint64_t offloads;
1016
1017         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1018
1019         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1020             nb_desc > ICE_MAX_RING_DESC ||
1021             nb_desc < ICE_MIN_RING_DESC) {
1022                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1023                              "invalid", nb_desc);
1024                 return -EINVAL;
1025         }
1026
1027         /**
1028          * The following two parameters control the setting of the RS bit on
1029          * transmit descriptors. TX descriptors will have their RS bit set
1030          * after txq->tx_rs_thresh descriptors have been used. The TX
1031          * descriptor ring will be cleaned after txq->tx_free_thresh
1032          * descriptors are used or if the number of descriptors required to
1033          * transmit a packet is greater than the number of free TX descriptors.
1034          *
1035          * The following constraints must be satisfied:
1036          *  - tx_rs_thresh must be greater than 0.
1037          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1038          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1039          *  - tx_rs_thresh must be a divisor of the ring size.
1040          *  - tx_free_thresh must be greater than 0.
1041          *  - tx_free_thresh must be less than the size of the ring minus 3.
1042          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1043          *
1044          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1045          * race condition, hence the maximum threshold constraints. When set
1046          * to zero use default values.
1047          */
1048         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1049                                     tx_conf->tx_free_thresh :
1050                                     ICE_DEFAULT_TX_FREE_THRESH);
1051         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1052         tx_rs_thresh =
1053                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1054                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1055         if (tx_conf->tx_rs_thresh)
1056                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1057         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1058                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1059                                 "exceed nb_desc. (tx_rs_thresh=%u "
1060                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1061                                 (unsigned int)tx_rs_thresh,
1062                                 (unsigned int)tx_free_thresh,
1063                                 (unsigned int)nb_desc,
1064                                 (int)dev->data->port_id,
1065                                 (int)queue_idx);
1066                 return -EINVAL;
1067         }
1068         if (tx_rs_thresh >= (nb_desc - 2)) {
1069                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1070                              "number of TX descriptors minus 2. "
1071                              "(tx_rs_thresh=%u port=%d queue=%d)",
1072                              (unsigned int)tx_rs_thresh,
1073                              (int)dev->data->port_id,
1074                              (int)queue_idx);
1075                 return -EINVAL;
1076         }
1077         if (tx_free_thresh >= (nb_desc - 3)) {
1078                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1079                              "tx_free_thresh must be less than the "
1080                              "number of TX descriptors minus 3. "
1081                              "(tx_free_thresh=%u port=%d queue=%d)",
1082                              (unsigned int)tx_free_thresh,
1083                              (int)dev->data->port_id,
1084                              (int)queue_idx);
1085                 return -EINVAL;
1086         }
1087         if (tx_rs_thresh > tx_free_thresh) {
1088                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1089                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1090                              " tx_rs_thresh=%u port=%d queue=%d)",
1091                              (unsigned int)tx_free_thresh,
1092                              (unsigned int)tx_rs_thresh,
1093                              (int)dev->data->port_id,
1094                              (int)queue_idx);
1095                 return -EINVAL;
1096         }
1097         if ((nb_desc % tx_rs_thresh) != 0) {
1098                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1099                              "number of TX descriptors. (tx_rs_thresh=%u"
1100                              " port=%d queue=%d)",
1101                              (unsigned int)tx_rs_thresh,
1102                              (int)dev->data->port_id,
1103                              (int)queue_idx);
1104                 return -EINVAL;
1105         }
1106         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1107                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1108                              "tx_rs_thresh is greater than 1. "
1109                              "(tx_rs_thresh=%u port=%d queue=%d)",
1110                              (unsigned int)tx_rs_thresh,
1111                              (int)dev->data->port_id,
1112                              (int)queue_idx);
1113                 return -EINVAL;
1114         }
1115
1116         /* Free memory if needed. */
1117         if (dev->data->tx_queues[queue_idx]) {
1118                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1119                 dev->data->tx_queues[queue_idx] = NULL;
1120         }
1121
1122         /* Allocate the TX queue data structure. */
1123         txq = rte_zmalloc_socket(NULL,
1124                                  sizeof(struct ice_tx_queue),
1125                                  RTE_CACHE_LINE_SIZE,
1126                                  socket_id);
1127         if (!txq) {
1128                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1129                              "tx queue structure");
1130                 return -ENOMEM;
1131         }
1132
1133         /* Allocate TX hardware ring descriptors. */
1134         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1135         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1136         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1137                                       ring_size, ICE_RING_BASE_ALIGN,
1138                                       socket_id);
1139         if (!tz) {
1140                 ice_tx_queue_release(txq);
1141                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1142                 return -ENOMEM;
1143         }
1144
1145         txq->nb_tx_desc = nb_desc;
1146         txq->tx_rs_thresh = tx_rs_thresh;
1147         txq->tx_free_thresh = tx_free_thresh;
1148         txq->pthresh = tx_conf->tx_thresh.pthresh;
1149         txq->hthresh = tx_conf->tx_thresh.hthresh;
1150         txq->wthresh = tx_conf->tx_thresh.wthresh;
1151         txq->queue_id = queue_idx;
1152
1153         txq->reg_idx = vsi->base_queue + queue_idx;
1154         txq->port_id = dev->data->port_id;
1155         txq->offloads = offloads;
1156         txq->vsi = vsi;
1157         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1158
1159         txq->tx_ring_dma = tz->iova;
1160         txq->tx_ring = tz->addr;
1161
1162         /* Allocate software ring */
1163         txq->sw_ring =
1164                 rte_zmalloc_socket(NULL,
1165                                    sizeof(struct ice_tx_entry) * nb_desc,
1166                                    RTE_CACHE_LINE_SIZE,
1167                                    socket_id);
1168         if (!txq->sw_ring) {
1169                 ice_tx_queue_release(txq);
1170                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1171                 return -ENOMEM;
1172         }
1173
1174         ice_reset_tx_queue(txq);
1175         txq->q_set = true;
1176         dev->data->tx_queues[queue_idx] = txq;
1177         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1178         ice_set_tx_function_flag(dev, txq);
1179
1180         return 0;
1181 }
1182
1183 void
1184 ice_tx_queue_release(void *txq)
1185 {
1186         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1187
1188         if (!q) {
1189                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1190                 return;
1191         }
1192
1193         q->tx_rel_mbufs(q);
1194         rte_free(q->sw_ring);
1195         rte_free(q);
1196 }
1197
1198 void
1199 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1200                  struct rte_eth_rxq_info *qinfo)
1201 {
1202         struct ice_rx_queue *rxq;
1203
1204         rxq = dev->data->rx_queues[queue_id];
1205
1206         qinfo->mp = rxq->mp;
1207         qinfo->scattered_rx = dev->data->scattered_rx;
1208         qinfo->nb_desc = rxq->nb_rx_desc;
1209
1210         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1211         qinfo->conf.rx_drop_en = rxq->drop_en;
1212         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1213 }
1214
1215 void
1216 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1217                  struct rte_eth_txq_info *qinfo)
1218 {
1219         struct ice_tx_queue *txq;
1220
1221         txq = dev->data->tx_queues[queue_id];
1222
1223         qinfo->nb_desc = txq->nb_tx_desc;
1224
1225         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1226         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1227         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1228
1229         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1230         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1231         qinfo->conf.offloads = txq->offloads;
1232         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1233 }
1234
1235 uint32_t
1236 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1237 {
1238 #define ICE_RXQ_SCAN_INTERVAL 4
1239         volatile union ice_rx_flex_desc *rxdp;
1240         struct ice_rx_queue *rxq;
1241         uint16_t desc = 0;
1242
1243         rxq = dev->data->rx_queues[rx_queue_id];
1244         rxdp = &rxq->rx_ring[rxq->rx_tail];
1245         while ((desc < rxq->nb_rx_desc) &&
1246                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1247                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1248                 /**
1249                  * Check the DD bit of a rx descriptor of each 4 in a group,
1250                  * to avoid checking too frequently and downgrading performance
1251                  * too much.
1252                  */
1253                 desc += ICE_RXQ_SCAN_INTERVAL;
1254                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1255                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1256                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1257                                  desc - rxq->nb_rx_desc]);
1258         }
1259
1260         return desc;
1261 }
1262
1263 #define ICE_RX_FLEX_ERR0_BITS   \
1264         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1265          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1266          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1267          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1268          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1269          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1270
1271 /* Rx L3/L4 checksum */
1272 static inline uint64_t
1273 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1274 {
1275         uint64_t flags = 0;
1276
1277         /* check if HW has decoded the packet and checksum */
1278         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1279                 return 0;
1280
1281         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1282                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1283                 return flags;
1284         }
1285
1286         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1287                 flags |= PKT_RX_IP_CKSUM_BAD;
1288         else
1289                 flags |= PKT_RX_IP_CKSUM_GOOD;
1290
1291         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1292                 flags |= PKT_RX_L4_CKSUM_BAD;
1293         else
1294                 flags |= PKT_RX_L4_CKSUM_GOOD;
1295
1296         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1297                 flags |= PKT_RX_EIP_CKSUM_BAD;
1298
1299         return flags;
1300 }
1301
1302 static inline void
1303 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1304 {
1305         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1306             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1307                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1308                 mb->vlan_tci =
1309                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1310                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1311                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1312         } else {
1313                 mb->vlan_tci = 0;
1314         }
1315
1316 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1317         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1318             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1319                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1320                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1321                 mb->vlan_tci_outer = mb->vlan_tci;
1322                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1323                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1324                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1325                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1326         } else {
1327                 mb->vlan_tci_outer = 0;
1328         }
1329 #endif
1330         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1331                    mb->vlan_tci, mb->vlan_tci_outer);
1332 }
1333
1334 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1335 #define ICE_RX_PROTO_XTR_VALID \
1336         ((1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) | \
1337          (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1338
1339 static void
1340 ice_rxd_to_proto_xtr(struct rte_mbuf *mb,
1341                      volatile struct ice_32b_rx_flex_desc_comms *desc)
1342 {
1343         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error1);
1344         uint32_t metadata = 0;
1345         uint64_t ol_flag;
1346         bool chk_valid;
1347
1348         ol_flag = ice_rxdid_to_proto_xtr_ol_flag(desc->rxdid, &chk_valid);
1349         if (unlikely(!ol_flag))
1350                 return;
1351
1352         if (chk_valid) {
1353                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
1354                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
1355
1356                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1357                         metadata |=
1358                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
1359         } else {
1360                 if (rte_le_to_cpu_16(desc->flex_ts.flex.aux0) != 0xFFFF)
1361                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
1362                 else if (rte_le_to_cpu_16(desc->flex_ts.flex.aux1) != 0xFFFF)
1363                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
1364         }
1365
1366         if (!metadata)
1367                 return;
1368
1369         mb->ol_flags |= ol_flag;
1370
1371         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
1372 }
1373 #endif
1374
1375 static inline void
1376 ice_rxd_to_pkt_fields(struct rte_mbuf *mb,
1377                       volatile union ice_rx_flex_desc *rxdp)
1378 {
1379         volatile struct ice_32b_rx_flex_desc_comms *desc =
1380                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
1381         uint16_t stat_err;
1382
1383         stat_err = rte_le_to_cpu_16(desc->status_error0);
1384         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
1385                 mb->ol_flags |= PKT_RX_RSS_HASH;
1386                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
1387         }
1388
1389 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1390         if (desc->flow_id != 0xFFFFFFFF) {
1391                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1392                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
1393         }
1394
1395         if (unlikely(rte_net_ice_dynf_proto_xtr_metadata_avail()))
1396                 ice_rxd_to_proto_xtr(mb, desc);
1397 #endif
1398 }
1399
1400 #define ICE_LOOK_AHEAD 8
1401 #if (ICE_LOOK_AHEAD != 8)
1402 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1403 #endif
1404 static inline int
1405 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1406 {
1407         volatile union ice_rx_flex_desc *rxdp;
1408         struct ice_rx_entry *rxep;
1409         struct rte_mbuf *mb;
1410         uint16_t stat_err0;
1411         uint16_t pkt_len;
1412         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1413         int32_t i, j, nb_rx = 0;
1414         uint64_t pkt_flags = 0;
1415         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1416
1417         rxdp = &rxq->rx_ring[rxq->rx_tail];
1418         rxep = &rxq->sw_ring[rxq->rx_tail];
1419
1420         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1421
1422         /* Make sure there is at least 1 packet to receive */
1423         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1424                 return 0;
1425
1426         /**
1427          * Scan LOOK_AHEAD descriptors at a time to determine which
1428          * descriptors reference packets that are ready to be received.
1429          */
1430         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1431              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1432                 /* Read desc statuses backwards to avoid race condition */
1433                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1434                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1435
1436                 rte_smp_rmb();
1437
1438                 /* Compute how many status bits were set */
1439                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1440                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1441
1442                 nb_rx += nb_dd;
1443
1444                 /* Translate descriptor info to mbuf parameters */
1445                 for (j = 0; j < nb_dd; j++) {
1446                         mb = rxep[j].mbuf;
1447                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1448                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1449                         mb->data_len = pkt_len;
1450                         mb->pkt_len = pkt_len;
1451                         mb->ol_flags = 0;
1452                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1453                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1454                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1455                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1456                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1457                         ice_rxd_to_pkt_fields(mb, &rxdp[j]);
1458
1459                         mb->ol_flags |= pkt_flags;
1460                 }
1461
1462                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1463                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1464
1465                 if (nb_dd != ICE_LOOK_AHEAD)
1466                         break;
1467         }
1468
1469         /* Clear software ring entries */
1470         for (i = 0; i < nb_rx; i++)
1471                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1472
1473         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1474                    "port_id=%u, queue_id=%u, nb_rx=%d",
1475                    rxq->port_id, rxq->queue_id, nb_rx);
1476
1477         return nb_rx;
1478 }
1479
1480 static inline uint16_t
1481 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1482                        struct rte_mbuf **rx_pkts,
1483                        uint16_t nb_pkts)
1484 {
1485         uint16_t i;
1486         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1487
1488         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1489
1490         for (i = 0; i < nb_pkts; i++)
1491                 rx_pkts[i] = stage[i];
1492
1493         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1494         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1495
1496         return nb_pkts;
1497 }
1498
1499 static inline int
1500 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1501 {
1502         volatile union ice_rx_flex_desc *rxdp;
1503         struct ice_rx_entry *rxep;
1504         struct rte_mbuf *mb;
1505         uint16_t alloc_idx, i;
1506         uint64_t dma_addr;
1507         int diag;
1508
1509         /* Allocate buffers in bulk */
1510         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1511                                (rxq->rx_free_thresh - 1));
1512         rxep = &rxq->sw_ring[alloc_idx];
1513         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1514                                     rxq->rx_free_thresh);
1515         if (unlikely(diag != 0)) {
1516                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1517                 return -ENOMEM;
1518         }
1519
1520         rxdp = &rxq->rx_ring[alloc_idx];
1521         for (i = 0; i < rxq->rx_free_thresh; i++) {
1522                 if (likely(i < (rxq->rx_free_thresh - 1)))
1523                         /* Prefetch next mbuf */
1524                         rte_prefetch0(rxep[i + 1].mbuf);
1525
1526                 mb = rxep[i].mbuf;
1527                 rte_mbuf_refcnt_set(mb, 1);
1528                 mb->next = NULL;
1529                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1530                 mb->nb_segs = 1;
1531                 mb->port = rxq->port_id;
1532                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1533                 rxdp[i].read.hdr_addr = 0;
1534                 rxdp[i].read.pkt_addr = dma_addr;
1535         }
1536
1537         /* Update rx tail regsiter */
1538         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1539
1540         rxq->rx_free_trigger =
1541                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1542         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1543                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1544
1545         return 0;
1546 }
1547
1548 static inline uint16_t
1549 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1550 {
1551         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1552         uint16_t nb_rx = 0;
1553         struct rte_eth_dev *dev;
1554
1555         if (!nb_pkts)
1556                 return 0;
1557
1558         if (rxq->rx_nb_avail)
1559                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1560
1561         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1562         rxq->rx_next_avail = 0;
1563         rxq->rx_nb_avail = nb_rx;
1564         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1565
1566         if (rxq->rx_tail > rxq->rx_free_trigger) {
1567                 if (ice_rx_alloc_bufs(rxq) != 0) {
1568                         uint16_t i, j;
1569
1570                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1571                         dev->data->rx_mbuf_alloc_failed +=
1572                                 rxq->rx_free_thresh;
1573                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1574                                    "port_id=%u, queue_id=%u",
1575                                    rxq->port_id, rxq->queue_id);
1576                         rxq->rx_nb_avail = 0;
1577                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1578                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1579                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1580
1581                         return 0;
1582                 }
1583         }
1584
1585         if (rxq->rx_tail >= rxq->nb_rx_desc)
1586                 rxq->rx_tail = 0;
1587
1588         if (rxq->rx_nb_avail)
1589                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1590
1591         return 0;
1592 }
1593
1594 static uint16_t
1595 ice_recv_pkts_bulk_alloc(void *rx_queue,
1596                          struct rte_mbuf **rx_pkts,
1597                          uint16_t nb_pkts)
1598 {
1599         uint16_t nb_rx = 0;
1600         uint16_t n;
1601         uint16_t count;
1602
1603         if (unlikely(nb_pkts == 0))
1604                 return nb_rx;
1605
1606         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1607                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1608
1609         while (nb_pkts) {
1610                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1611                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1612                 nb_rx = (uint16_t)(nb_rx + count);
1613                 nb_pkts = (uint16_t)(nb_pkts - count);
1614                 if (count < n)
1615                         break;
1616         }
1617
1618         return nb_rx;
1619 }
1620
1621 static uint16_t
1622 ice_recv_scattered_pkts(void *rx_queue,
1623                         struct rte_mbuf **rx_pkts,
1624                         uint16_t nb_pkts)
1625 {
1626         struct ice_rx_queue *rxq = rx_queue;
1627         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1628         volatile union ice_rx_flex_desc *rxdp;
1629         union ice_rx_flex_desc rxd;
1630         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1631         struct ice_rx_entry *rxe;
1632         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1633         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1634         struct rte_mbuf *nmb; /* new allocated mbuf */
1635         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1636         uint16_t rx_id = rxq->rx_tail;
1637         uint16_t nb_rx = 0;
1638         uint16_t nb_hold = 0;
1639         uint16_t rx_packet_len;
1640         uint16_t rx_stat_err0;
1641         uint64_t dma_addr;
1642         uint64_t pkt_flags;
1643         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1644         struct rte_eth_dev *dev;
1645
1646         while (nb_rx < nb_pkts) {
1647                 rxdp = &rx_ring[rx_id];
1648                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1649
1650                 /* Check the DD bit first */
1651                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1652                         break;
1653
1654                 /* allocate mbuf */
1655                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1656                 if (unlikely(!nmb)) {
1657                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1658                         dev->data->rx_mbuf_alloc_failed++;
1659                         break;
1660                 }
1661                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1662
1663                 nb_hold++;
1664                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1665                 rx_id++;
1666                 if (unlikely(rx_id == rxq->nb_rx_desc))
1667                         rx_id = 0;
1668
1669                 /* Prefetch next mbuf */
1670                 rte_prefetch0(sw_ring[rx_id].mbuf);
1671
1672                 /**
1673                  * When next RX descriptor is on a cache line boundary,
1674                  * prefetch the next 4 RX descriptors and next 8 pointers
1675                  * to mbufs.
1676                  */
1677                 if ((rx_id & 0x3) == 0) {
1678                         rte_prefetch0(&rx_ring[rx_id]);
1679                         rte_prefetch0(&sw_ring[rx_id]);
1680                 }
1681
1682                 rxm = rxe->mbuf;
1683                 rxe->mbuf = nmb;
1684                 dma_addr =
1685                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1686
1687                 /* Set data buffer address and data length of the mbuf */
1688                 rxdp->read.hdr_addr = 0;
1689                 rxdp->read.pkt_addr = dma_addr;
1690                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1691                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1692                 rxm->data_len = rx_packet_len;
1693                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1694
1695                 /**
1696                  * If this is the first buffer of the received packet, set the
1697                  * pointer to the first mbuf of the packet and initialize its
1698                  * context. Otherwise, update the total length and the number
1699                  * of segments of the current scattered packet, and update the
1700                  * pointer to the last mbuf of the current packet.
1701                  */
1702                 if (!first_seg) {
1703                         first_seg = rxm;
1704                         first_seg->nb_segs = 1;
1705                         first_seg->pkt_len = rx_packet_len;
1706                 } else {
1707                         first_seg->pkt_len =
1708                                 (uint16_t)(first_seg->pkt_len +
1709                                            rx_packet_len);
1710                         first_seg->nb_segs++;
1711                         last_seg->next = rxm;
1712                 }
1713
1714                 /**
1715                  * If this is not the last buffer of the received packet,
1716                  * update the pointer to the last mbuf of the current scattered
1717                  * packet and continue to parse the RX ring.
1718                  */
1719                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1720                         last_seg = rxm;
1721                         continue;
1722                 }
1723
1724                 /**
1725                  * This is the last buffer of the received packet. If the CRC
1726                  * is not stripped by the hardware:
1727                  *  - Subtract the CRC length from the total packet length.
1728                  *  - If the last buffer only contains the whole CRC or a part
1729                  *  of it, free the mbuf associated to the last buffer. If part
1730                  *  of the CRC is also contained in the previous mbuf, subtract
1731                  *  the length of that CRC part from the data length of the
1732                  *  previous mbuf.
1733                  */
1734                 rxm->next = NULL;
1735                 if (unlikely(rxq->crc_len > 0)) {
1736                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1737                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1738                                 rte_pktmbuf_free_seg(rxm);
1739                                 first_seg->nb_segs--;
1740                                 last_seg->data_len =
1741                                         (uint16_t)(last_seg->data_len -
1742                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1743                                 last_seg->next = NULL;
1744                         } else
1745                                 rxm->data_len = (uint16_t)(rx_packet_len -
1746                                                            RTE_ETHER_CRC_LEN);
1747                 }
1748
1749                 first_seg->port = rxq->port_id;
1750                 first_seg->ol_flags = 0;
1751                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1752                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1753                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1754                 ice_rxd_to_pkt_fields(first_seg, &rxd);
1755                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1756                 first_seg->ol_flags |= pkt_flags;
1757                 /* Prefetch data of first segment, if configured to do so. */
1758                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1759                                           first_seg->data_off));
1760                 rx_pkts[nb_rx++] = first_seg;
1761                 first_seg = NULL;
1762         }
1763
1764         /* Record index of the next RX descriptor to probe. */
1765         rxq->rx_tail = rx_id;
1766         rxq->pkt_first_seg = first_seg;
1767         rxq->pkt_last_seg = last_seg;
1768
1769         /**
1770          * If the number of free RX descriptors is greater than the RX free
1771          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1772          * register. Update the RDT with the value of the last processed RX
1773          * descriptor minus 1, to guarantee that the RDT register is never
1774          * equal to the RDH register, which creates a "full" ring situtation
1775          * from the hardware point of view.
1776          */
1777         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1778         if (nb_hold > rxq->rx_free_thresh) {
1779                 rx_id = (uint16_t)(rx_id == 0 ?
1780                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1781                 /* write TAIL register */
1782                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1783                 nb_hold = 0;
1784         }
1785         rxq->nb_rx_hold = nb_hold;
1786
1787         /* return received packet in the burst */
1788         return nb_rx;
1789 }
1790
1791 const uint32_t *
1792 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1793 {
1794         struct ice_adapter *ad =
1795                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1796         const uint32_t *ptypes;
1797
1798         static const uint32_t ptypes_os[] = {
1799                 /* refers to ice_get_default_pkt_type() */
1800                 RTE_PTYPE_L2_ETHER,
1801                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1802                 RTE_PTYPE_L2_ETHER_LLDP,
1803                 RTE_PTYPE_L2_ETHER_ARP,
1804                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1805                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1806                 RTE_PTYPE_L4_FRAG,
1807                 RTE_PTYPE_L4_ICMP,
1808                 RTE_PTYPE_L4_NONFRAG,
1809                 RTE_PTYPE_L4_SCTP,
1810                 RTE_PTYPE_L4_TCP,
1811                 RTE_PTYPE_L4_UDP,
1812                 RTE_PTYPE_TUNNEL_GRENAT,
1813                 RTE_PTYPE_TUNNEL_IP,
1814                 RTE_PTYPE_INNER_L2_ETHER,
1815                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1816                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1817                 RTE_PTYPE_INNER_L4_FRAG,
1818                 RTE_PTYPE_INNER_L4_ICMP,
1819                 RTE_PTYPE_INNER_L4_NONFRAG,
1820                 RTE_PTYPE_INNER_L4_SCTP,
1821                 RTE_PTYPE_INNER_L4_TCP,
1822                 RTE_PTYPE_INNER_L4_UDP,
1823                 RTE_PTYPE_UNKNOWN
1824         };
1825
1826         static const uint32_t ptypes_comms[] = {
1827                 /* refers to ice_get_default_pkt_type() */
1828                 RTE_PTYPE_L2_ETHER,
1829                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1830                 RTE_PTYPE_L2_ETHER_LLDP,
1831                 RTE_PTYPE_L2_ETHER_ARP,
1832                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1833                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1834                 RTE_PTYPE_L4_FRAG,
1835                 RTE_PTYPE_L4_ICMP,
1836                 RTE_PTYPE_L4_NONFRAG,
1837                 RTE_PTYPE_L4_SCTP,
1838                 RTE_PTYPE_L4_TCP,
1839                 RTE_PTYPE_L4_UDP,
1840                 RTE_PTYPE_TUNNEL_GRENAT,
1841                 RTE_PTYPE_TUNNEL_IP,
1842                 RTE_PTYPE_INNER_L2_ETHER,
1843                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1844                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1845                 RTE_PTYPE_INNER_L4_FRAG,
1846                 RTE_PTYPE_INNER_L4_ICMP,
1847                 RTE_PTYPE_INNER_L4_NONFRAG,
1848                 RTE_PTYPE_INNER_L4_SCTP,
1849                 RTE_PTYPE_INNER_L4_TCP,
1850                 RTE_PTYPE_INNER_L4_UDP,
1851                 RTE_PTYPE_TUNNEL_GTPC,
1852                 RTE_PTYPE_TUNNEL_GTPU,
1853                 RTE_PTYPE_L2_ETHER_PPPOE,
1854                 RTE_PTYPE_UNKNOWN
1855         };
1856
1857         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
1858                 ptypes = ptypes_comms;
1859         else
1860                 ptypes = ptypes_os;
1861
1862         if (dev->rx_pkt_burst == ice_recv_pkts ||
1863             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1864             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1865                 return ptypes;
1866
1867 #ifdef RTE_ARCH_X86
1868         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1869             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1870             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1871             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1872                 return ptypes;
1873 #endif
1874
1875         return NULL;
1876 }
1877
1878 int
1879 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1880 {
1881         volatile union ice_rx_flex_desc *rxdp;
1882         struct ice_rx_queue *rxq = rx_queue;
1883         uint32_t desc;
1884
1885         if (unlikely(offset >= rxq->nb_rx_desc))
1886                 return -EINVAL;
1887
1888         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1889                 return RTE_ETH_RX_DESC_UNAVAIL;
1890
1891         desc = rxq->rx_tail + offset;
1892         if (desc >= rxq->nb_rx_desc)
1893                 desc -= rxq->nb_rx_desc;
1894
1895         rxdp = &rxq->rx_ring[desc];
1896         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1897             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1898                 return RTE_ETH_RX_DESC_DONE;
1899
1900         return RTE_ETH_RX_DESC_AVAIL;
1901 }
1902
1903 int
1904 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1905 {
1906         struct ice_tx_queue *txq = tx_queue;
1907         volatile uint64_t *status;
1908         uint64_t mask, expect;
1909         uint32_t desc;
1910
1911         if (unlikely(offset >= txq->nb_tx_desc))
1912                 return -EINVAL;
1913
1914         desc = txq->tx_tail + offset;
1915         /* go to next desc that has the RS bit */
1916         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1917                 txq->tx_rs_thresh;
1918         if (desc >= txq->nb_tx_desc) {
1919                 desc -= txq->nb_tx_desc;
1920                 if (desc >= txq->nb_tx_desc)
1921                         desc -= txq->nb_tx_desc;
1922         }
1923
1924         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1925         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1926         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1927                                   ICE_TXD_QW1_DTYPE_S);
1928         if ((*status & mask) == expect)
1929                 return RTE_ETH_TX_DESC_DONE;
1930
1931         return RTE_ETH_TX_DESC_FULL;
1932 }
1933
1934 void
1935 ice_free_queues(struct rte_eth_dev *dev)
1936 {
1937         uint16_t i;
1938
1939         PMD_INIT_FUNC_TRACE();
1940
1941         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1942                 if (!dev->data->rx_queues[i])
1943                         continue;
1944                 ice_rx_queue_release(dev->data->rx_queues[i]);
1945                 dev->data->rx_queues[i] = NULL;
1946                 rte_eth_dma_zone_free(dev, "rx_ring", i);
1947         }
1948         dev->data->nb_rx_queues = 0;
1949
1950         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1951                 if (!dev->data->tx_queues[i])
1952                         continue;
1953                 ice_tx_queue_release(dev->data->tx_queues[i]);
1954                 dev->data->tx_queues[i] = NULL;
1955                 rte_eth_dma_zone_free(dev, "tx_ring", i);
1956         }
1957         dev->data->nb_tx_queues = 0;
1958 }
1959
1960 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
1961 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
1962
1963 int
1964 ice_fdir_setup_tx_resources(struct ice_pf *pf)
1965 {
1966         struct ice_tx_queue *txq;
1967         const struct rte_memzone *tz = NULL;
1968         uint32_t ring_size;
1969         struct rte_eth_dev *dev;
1970
1971         if (!pf) {
1972                 PMD_DRV_LOG(ERR, "PF is not available");
1973                 return -EINVAL;
1974         }
1975
1976         dev = pf->adapter->eth_dev;
1977
1978         /* Allocate the TX queue data structure. */
1979         txq = rte_zmalloc_socket("ice fdir tx queue",
1980                                  sizeof(struct ice_tx_queue),
1981                                  RTE_CACHE_LINE_SIZE,
1982                                  SOCKET_ID_ANY);
1983         if (!txq) {
1984                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1985                             "tx queue structure.");
1986                 return -ENOMEM;
1987         }
1988
1989         /* Allocate TX hardware ring descriptors. */
1990         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
1991         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1992
1993         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
1994                                       ICE_FDIR_QUEUE_ID, ring_size,
1995                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
1996         if (!tz) {
1997                 ice_tx_queue_release(txq);
1998                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
1999                 return -ENOMEM;
2000         }
2001
2002         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2003         txq->queue_id = ICE_FDIR_QUEUE_ID;
2004         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2005         txq->vsi = pf->fdir.fdir_vsi;
2006
2007         txq->tx_ring_dma = tz->iova;
2008         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2009         /*
2010          * don't need to allocate software ring and reset for the fdir
2011          * program queue just set the queue has been configured.
2012          */
2013         txq->q_set = true;
2014         pf->fdir.txq = txq;
2015
2016         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2017
2018         return ICE_SUCCESS;
2019 }
2020
2021 int
2022 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2023 {
2024         struct ice_rx_queue *rxq;
2025         const struct rte_memzone *rz = NULL;
2026         uint32_t ring_size;
2027         struct rte_eth_dev *dev;
2028
2029         if (!pf) {
2030                 PMD_DRV_LOG(ERR, "PF is not available");
2031                 return -EINVAL;
2032         }
2033
2034         dev = pf->adapter->eth_dev;
2035
2036         /* Allocate the RX queue data structure. */
2037         rxq = rte_zmalloc_socket("ice fdir rx queue",
2038                                  sizeof(struct ice_rx_queue),
2039                                  RTE_CACHE_LINE_SIZE,
2040                                  SOCKET_ID_ANY);
2041         if (!rxq) {
2042                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2043                             "rx queue structure.");
2044                 return -ENOMEM;
2045         }
2046
2047         /* Allocate RX hardware ring descriptors. */
2048         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2049         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2050
2051         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2052                                       ICE_FDIR_QUEUE_ID, ring_size,
2053                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2054         if (!rz) {
2055                 ice_rx_queue_release(rxq);
2056                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2057                 return -ENOMEM;
2058         }
2059
2060         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2061         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2062         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2063         rxq->vsi = pf->fdir.fdir_vsi;
2064
2065         rxq->rx_ring_dma = rz->iova;
2066         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2067                sizeof(union ice_32byte_rx_desc));
2068         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2069
2070         /*
2071          * Don't need to allocate software ring and reset for the fdir
2072          * rx queue, just set the queue has been configured.
2073          */
2074         rxq->q_set = true;
2075         pf->fdir.rxq = rxq;
2076
2077         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2078
2079         return ICE_SUCCESS;
2080 }
2081
2082 uint16_t
2083 ice_recv_pkts(void *rx_queue,
2084               struct rte_mbuf **rx_pkts,
2085               uint16_t nb_pkts)
2086 {
2087         struct ice_rx_queue *rxq = rx_queue;
2088         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2089         volatile union ice_rx_flex_desc *rxdp;
2090         union ice_rx_flex_desc rxd;
2091         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2092         struct ice_rx_entry *rxe;
2093         struct rte_mbuf *nmb; /* new allocated mbuf */
2094         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2095         uint16_t rx_id = rxq->rx_tail;
2096         uint16_t nb_rx = 0;
2097         uint16_t nb_hold = 0;
2098         uint16_t rx_packet_len;
2099         uint16_t rx_stat_err0;
2100         uint64_t dma_addr;
2101         uint64_t pkt_flags;
2102         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2103         struct rte_eth_dev *dev;
2104
2105         while (nb_rx < nb_pkts) {
2106                 rxdp = &rx_ring[rx_id];
2107                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2108
2109                 /* Check the DD bit first */
2110                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2111                         break;
2112
2113                 /* allocate mbuf */
2114                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2115                 if (unlikely(!nmb)) {
2116                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
2117                         dev->data->rx_mbuf_alloc_failed++;
2118                         break;
2119                 }
2120                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2121
2122                 nb_hold++;
2123                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2124                 rx_id++;
2125                 if (unlikely(rx_id == rxq->nb_rx_desc))
2126                         rx_id = 0;
2127                 rxm = rxe->mbuf;
2128                 rxe->mbuf = nmb;
2129                 dma_addr =
2130                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2131
2132                 /**
2133                  * fill the read format of descriptor with physic address in
2134                  * new allocated mbuf: nmb
2135                  */
2136                 rxdp->read.hdr_addr = 0;
2137                 rxdp->read.pkt_addr = dma_addr;
2138
2139                 /* calculate rx_packet_len of the received pkt */
2140                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2141                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2142
2143                 /* fill old mbuf with received descriptor: rxd */
2144                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2145                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2146                 rxm->nb_segs = 1;
2147                 rxm->next = NULL;
2148                 rxm->pkt_len = rx_packet_len;
2149                 rxm->data_len = rx_packet_len;
2150                 rxm->port = rxq->port_id;
2151                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2152                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2153                 ice_rxd_to_vlan_tci(rxm, &rxd);
2154                 ice_rxd_to_pkt_fields(rxm, &rxd);
2155                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2156                 rxm->ol_flags |= pkt_flags;
2157                 /* copy old mbuf to rx_pkts */
2158                 rx_pkts[nb_rx++] = rxm;
2159         }
2160         rxq->rx_tail = rx_id;
2161         /**
2162          * If the number of free RX descriptors is greater than the RX free
2163          * threshold of the queue, advance the receive tail register of queue.
2164          * Update that register with the value of the last processed RX
2165          * descriptor minus 1.
2166          */
2167         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2168         if (nb_hold > rxq->rx_free_thresh) {
2169                 rx_id = (uint16_t)(rx_id == 0 ?
2170                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2171                 /* write TAIL register */
2172                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
2173                 nb_hold = 0;
2174         }
2175         rxq->nb_rx_hold = nb_hold;
2176
2177         /* return received packet in the burst */
2178         return nb_rx;
2179 }
2180
2181 static inline void
2182 ice_parse_tunneling_params(uint64_t ol_flags,
2183                             union ice_tx_offload tx_offload,
2184                             uint32_t *cd_tunneling)
2185 {
2186         /* EIPT: External (outer) IP header type */
2187         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2188                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2189         else if (ol_flags & PKT_TX_OUTER_IPV4)
2190                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2191         else if (ol_flags & PKT_TX_OUTER_IPV6)
2192                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2193
2194         /* EIPLEN: External (outer) IP header length, in DWords */
2195         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2196                 ICE_TXD_CTX_QW0_EIPLEN_S;
2197
2198         /* L4TUNT: L4 Tunneling Type */
2199         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2200         case PKT_TX_TUNNEL_IPIP:
2201                 /* for non UDP / GRE tunneling, set to 00b */
2202                 break;
2203         case PKT_TX_TUNNEL_VXLAN:
2204         case PKT_TX_TUNNEL_GTP:
2205         case PKT_TX_TUNNEL_GENEVE:
2206                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2207                 break;
2208         case PKT_TX_TUNNEL_GRE:
2209                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2210                 break;
2211         default:
2212                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2213                 return;
2214         }
2215
2216         /* L4TUNLEN: L4 Tunneling Length, in Words
2217          *
2218          * We depend on app to set rte_mbuf.l2_len correctly.
2219          * For IP in GRE it should be set to the length of the GRE
2220          * header;
2221          * For MAC in GRE or MAC in UDP it should be set to the length
2222          * of the GRE or UDP headers plus the inner MAC up to including
2223          * its last Ethertype.
2224          * If MPLS labels exists, it should include them as well.
2225          */
2226         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2227                 ICE_TXD_CTX_QW0_NATLEN_S;
2228
2229         if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
2230             (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
2231             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2232                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2233 }
2234
2235 static inline void
2236 ice_txd_enable_checksum(uint64_t ol_flags,
2237                         uint32_t *td_cmd,
2238                         uint32_t *td_offset,
2239                         union ice_tx_offload tx_offload)
2240 {
2241         /* Set MACLEN */
2242         if (ol_flags & PKT_TX_TUNNEL_MASK)
2243                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2244                         << ICE_TX_DESC_LEN_MACLEN_S;
2245         else
2246                 *td_offset |= (tx_offload.l2_len >> 1)
2247                         << ICE_TX_DESC_LEN_MACLEN_S;
2248
2249         /* Enable L3 checksum offloads */
2250         if (ol_flags & PKT_TX_IP_CKSUM) {
2251                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2252                 *td_offset |= (tx_offload.l3_len >> 2) <<
2253                               ICE_TX_DESC_LEN_IPLEN_S;
2254         } else if (ol_flags & PKT_TX_IPV4) {
2255                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2256                 *td_offset |= (tx_offload.l3_len >> 2) <<
2257                               ICE_TX_DESC_LEN_IPLEN_S;
2258         } else if (ol_flags & PKT_TX_IPV6) {
2259                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2260                 *td_offset |= (tx_offload.l3_len >> 2) <<
2261                               ICE_TX_DESC_LEN_IPLEN_S;
2262         }
2263
2264         if (ol_flags & PKT_TX_TCP_SEG) {
2265                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2266                 *td_offset |= (tx_offload.l4_len >> 2) <<
2267                               ICE_TX_DESC_LEN_L4_LEN_S;
2268                 return;
2269         }
2270
2271         /* Enable L4 checksum offloads */
2272         switch (ol_flags & PKT_TX_L4_MASK) {
2273         case PKT_TX_TCP_CKSUM:
2274                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2275                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2276                               ICE_TX_DESC_LEN_L4_LEN_S;
2277                 break;
2278         case PKT_TX_SCTP_CKSUM:
2279                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2280                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2281                               ICE_TX_DESC_LEN_L4_LEN_S;
2282                 break;
2283         case PKT_TX_UDP_CKSUM:
2284                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2285                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2286                               ICE_TX_DESC_LEN_L4_LEN_S;
2287                 break;
2288         default:
2289                 break;
2290         }
2291 }
2292
2293 static inline int
2294 ice_xmit_cleanup(struct ice_tx_queue *txq)
2295 {
2296         struct ice_tx_entry *sw_ring = txq->sw_ring;
2297         volatile struct ice_tx_desc *txd = txq->tx_ring;
2298         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2299         uint16_t nb_tx_desc = txq->nb_tx_desc;
2300         uint16_t desc_to_clean_to;
2301         uint16_t nb_tx_to_clean;
2302
2303         /* Determine the last descriptor needing to be cleaned */
2304         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2305         if (desc_to_clean_to >= nb_tx_desc)
2306                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2307
2308         /* Check to make sure the last descriptor to clean is done */
2309         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2310         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2311             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2312                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
2313                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2314                                 desc_to_clean_to,
2315                                 txq->port_id, txq->queue_id,
2316                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
2317                 /* Failed to clean any descriptors */
2318                 return -1;
2319         }
2320
2321         /* Figure out how many descriptors will be cleaned */
2322         if (last_desc_cleaned > desc_to_clean_to)
2323                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2324                                             desc_to_clean_to);
2325         else
2326                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2327                                             last_desc_cleaned);
2328
2329         /* The last descriptor to clean is done, so that means all the
2330          * descriptors from the last descriptor that was cleaned
2331          * up to the last descriptor with the RS bit set
2332          * are done. Only reset the threshold descriptor.
2333          */
2334         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2335
2336         /* Update the txq to reflect the last descriptor that was cleaned */
2337         txq->last_desc_cleaned = desc_to_clean_to;
2338         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2339
2340         return 0;
2341 }
2342
2343 /* Construct the tx flags */
2344 static inline uint64_t
2345 ice_build_ctob(uint32_t td_cmd,
2346                uint32_t td_offset,
2347                uint16_t size,
2348                uint32_t td_tag)
2349 {
2350         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2351                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2352                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2353                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2354                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2355 }
2356
2357 /* Check if the context descriptor is needed for TX offloading */
2358 static inline uint16_t
2359 ice_calc_context_desc(uint64_t flags)
2360 {
2361         static uint64_t mask = PKT_TX_TCP_SEG |
2362                 PKT_TX_QINQ |
2363                 PKT_TX_OUTER_IP_CKSUM |
2364                 PKT_TX_TUNNEL_MASK;
2365
2366         return (flags & mask) ? 1 : 0;
2367 }
2368
2369 /* set ice TSO context descriptor */
2370 static inline uint64_t
2371 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2372 {
2373         uint64_t ctx_desc = 0;
2374         uint32_t cd_cmd, hdr_len, cd_tso_len;
2375
2376         if (!tx_offload.l4_len) {
2377                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2378                 return ctx_desc;
2379         }
2380
2381         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2382         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2383                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2384
2385         cd_cmd = ICE_TX_CTX_DESC_TSO;
2386         cd_tso_len = mbuf->pkt_len - hdr_len;
2387         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2388                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2389                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2390
2391         return ctx_desc;
2392 }
2393
2394 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2395 #define ICE_MAX_DATA_PER_TXD \
2396         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2397 /* Calculate the number of TX descriptors needed for each pkt */
2398 static inline uint16_t
2399 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2400 {
2401         struct rte_mbuf *txd = tx_pkt;
2402         uint16_t count = 0;
2403
2404         while (txd != NULL) {
2405                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2406                 txd = txd->next;
2407         }
2408
2409         return count;
2410 }
2411
2412 uint16_t
2413 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2414 {
2415         struct ice_tx_queue *txq;
2416         volatile struct ice_tx_desc *tx_ring;
2417         volatile struct ice_tx_desc *txd;
2418         struct ice_tx_entry *sw_ring;
2419         struct ice_tx_entry *txe, *txn;
2420         struct rte_mbuf *tx_pkt;
2421         struct rte_mbuf *m_seg;
2422         uint32_t cd_tunneling_params;
2423         uint16_t tx_id;
2424         uint16_t nb_tx;
2425         uint16_t nb_used;
2426         uint16_t nb_ctx;
2427         uint32_t td_cmd = 0;
2428         uint32_t td_offset = 0;
2429         uint32_t td_tag = 0;
2430         uint16_t tx_last;
2431         uint16_t slen;
2432         uint64_t buf_dma_addr;
2433         uint64_t ol_flags;
2434         union ice_tx_offload tx_offload = {0};
2435
2436         txq = tx_queue;
2437         sw_ring = txq->sw_ring;
2438         tx_ring = txq->tx_ring;
2439         tx_id = txq->tx_tail;
2440         txe = &sw_ring[tx_id];
2441
2442         /* Check if the descriptor ring needs to be cleaned. */
2443         if (txq->nb_tx_free < txq->tx_free_thresh)
2444                 (void)ice_xmit_cleanup(txq);
2445
2446         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2447                 tx_pkt = *tx_pkts++;
2448
2449                 td_cmd = 0;
2450                 td_tag = 0;
2451                 td_offset = 0;
2452                 ol_flags = tx_pkt->ol_flags;
2453                 tx_offload.l2_len = tx_pkt->l2_len;
2454                 tx_offload.l3_len = tx_pkt->l3_len;
2455                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2456                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2457                 tx_offload.l4_len = tx_pkt->l4_len;
2458                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2459                 /* Calculate the number of context descriptors needed. */
2460                 nb_ctx = ice_calc_context_desc(ol_flags);
2461
2462                 /* The number of descriptors that must be allocated for
2463                  * a packet equals to the number of the segments of that
2464                  * packet plus the number of context descriptor if needed.
2465                  * Recalculate the needed tx descs when TSO enabled in case
2466                  * the mbuf data size exceeds max data size that hw allows
2467                  * per tx desc.
2468                  */
2469                 if (ol_flags & PKT_TX_TCP_SEG)
2470                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2471                                              nb_ctx);
2472                 else
2473                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2474                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2475
2476                 /* Circular ring */
2477                 if (tx_last >= txq->nb_tx_desc)
2478                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2479
2480                 if (nb_used > txq->nb_tx_free) {
2481                         if (ice_xmit_cleanup(txq) != 0) {
2482                                 if (nb_tx == 0)
2483                                         return 0;
2484                                 goto end_of_tx;
2485                         }
2486                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2487                                 while (nb_used > txq->nb_tx_free) {
2488                                         if (ice_xmit_cleanup(txq) != 0) {
2489                                                 if (nb_tx == 0)
2490                                                         return 0;
2491                                                 goto end_of_tx;
2492                                         }
2493                                 }
2494                         }
2495                 }
2496
2497                 /* Descriptor based VLAN insertion */
2498                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2499                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2500                         td_tag = tx_pkt->vlan_tci;
2501                 }
2502
2503                 /* Fill in tunneling parameters if necessary */
2504                 cd_tunneling_params = 0;
2505                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2506                         ice_parse_tunneling_params(ol_flags, tx_offload,
2507                                                    &cd_tunneling_params);
2508
2509                 /* Enable checksum offloading */
2510                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2511                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2512                                                 &td_offset, tx_offload);
2513
2514                 if (nb_ctx) {
2515                         /* Setup TX context descriptor if required */
2516                         volatile struct ice_tx_ctx_desc *ctx_txd =
2517                                 (volatile struct ice_tx_ctx_desc *)
2518                                         &tx_ring[tx_id];
2519                         uint16_t cd_l2tag2 = 0;
2520                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2521
2522                         txn = &sw_ring[txe->next_id];
2523                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2524                         if (txe->mbuf) {
2525                                 rte_pktmbuf_free_seg(txe->mbuf);
2526                                 txe->mbuf = NULL;
2527                         }
2528
2529                         if (ol_flags & PKT_TX_TCP_SEG)
2530                                 cd_type_cmd_tso_mss |=
2531                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2532
2533                         ctx_txd->tunneling_params =
2534                                 rte_cpu_to_le_32(cd_tunneling_params);
2535
2536                         /* TX context descriptor based double VLAN insert */
2537                         if (ol_flags & PKT_TX_QINQ) {
2538                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2539                                 cd_type_cmd_tso_mss |=
2540                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2541                                          ICE_TXD_CTX_QW1_CMD_S);
2542                         }
2543                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2544                         ctx_txd->qw1 =
2545                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2546
2547                         txe->last_id = tx_last;
2548                         tx_id = txe->next_id;
2549                         txe = txn;
2550                 }
2551                 m_seg = tx_pkt;
2552
2553                 do {
2554                         txd = &tx_ring[tx_id];
2555                         txn = &sw_ring[txe->next_id];
2556
2557                         if (txe->mbuf)
2558                                 rte_pktmbuf_free_seg(txe->mbuf);
2559                         txe->mbuf = m_seg;
2560
2561                         /* Setup TX Descriptor */
2562                         slen = m_seg->data_len;
2563                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2564
2565                         while ((ol_flags & PKT_TX_TCP_SEG) &&
2566                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2567                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2568                                 txd->cmd_type_offset_bsz =
2569                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2570                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2571                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2572                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2573                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2574                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2575
2576                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2577                                 slen -= ICE_MAX_DATA_PER_TXD;
2578
2579                                 txe->last_id = tx_last;
2580                                 tx_id = txe->next_id;
2581                                 txe = txn;
2582                                 txd = &tx_ring[tx_id];
2583                                 txn = &sw_ring[txe->next_id];
2584                         }
2585
2586                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2587                         txd->cmd_type_offset_bsz =
2588                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2589                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2590                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2591                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2592                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2593
2594                         txe->last_id = tx_last;
2595                         tx_id = txe->next_id;
2596                         txe = txn;
2597                         m_seg = m_seg->next;
2598                 } while (m_seg);
2599
2600                 /* fill the last descriptor with End of Packet (EOP) bit */
2601                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2602                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2603                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2604
2605                 /* set RS bit on the last descriptor of one packet */
2606                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2607                         PMD_TX_FREE_LOG(DEBUG,
2608                                         "Setting RS bit on TXD id="
2609                                         "%4u (port=%d queue=%d)",
2610                                         tx_last, txq->port_id, txq->queue_id);
2611
2612                         td_cmd |= ICE_TX_DESC_CMD_RS;
2613
2614                         /* Update txq RS bit counters */
2615                         txq->nb_tx_used = 0;
2616                 }
2617                 txd->cmd_type_offset_bsz |=
2618                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2619                                          ICE_TXD_QW1_CMD_S);
2620         }
2621 end_of_tx:
2622         /* update Tail register */
2623         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2624         txq->tx_tail = tx_id;
2625
2626         return nb_tx;
2627 }
2628
2629 static __rte_always_inline int
2630 ice_tx_free_bufs(struct ice_tx_queue *txq)
2631 {
2632         struct ice_tx_entry *txep;
2633         uint16_t i;
2634
2635         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2636              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2637             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2638                 return 0;
2639
2640         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2641
2642         for (i = 0; i < txq->tx_rs_thresh; i++)
2643                 rte_prefetch0((txep + i)->mbuf);
2644
2645         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2646                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2647                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2648                         txep->mbuf = NULL;
2649                 }
2650         } else {
2651                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2652                         rte_pktmbuf_free_seg(txep->mbuf);
2653                         txep->mbuf = NULL;
2654                 }
2655         }
2656
2657         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2658         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2659         if (txq->tx_next_dd >= txq->nb_tx_desc)
2660                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2661
2662         return txq->tx_rs_thresh;
2663 }
2664
2665 static int
2666 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2667                         uint32_t free_cnt)
2668 {
2669         struct ice_tx_entry *swr_ring = txq->sw_ring;
2670         uint16_t i, tx_last, tx_id;
2671         uint16_t nb_tx_free_last;
2672         uint16_t nb_tx_to_clean;
2673         uint32_t pkt_cnt;
2674
2675         /* Start free mbuf from the next of tx_tail */
2676         tx_last = txq->tx_tail;
2677         tx_id  = swr_ring[tx_last].next_id;
2678
2679         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2680                 return 0;
2681
2682         nb_tx_to_clean = txq->nb_tx_free;
2683         nb_tx_free_last = txq->nb_tx_free;
2684         if (!free_cnt)
2685                 free_cnt = txq->nb_tx_desc;
2686
2687         /* Loop through swr_ring to count the amount of
2688          * freeable mubfs and packets.
2689          */
2690         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2691                 for (i = 0; i < nb_tx_to_clean &&
2692                         pkt_cnt < free_cnt &&
2693                         tx_id != tx_last; i++) {
2694                         if (swr_ring[tx_id].mbuf != NULL) {
2695                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2696                                 swr_ring[tx_id].mbuf = NULL;
2697
2698                                 /*
2699                                  * last segment in the packet,
2700                                  * increment packet count
2701                                  */
2702                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2703                         }
2704
2705                         tx_id = swr_ring[tx_id].next_id;
2706                 }
2707
2708                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2709                         txq->nb_tx_free || tx_id == tx_last)
2710                         break;
2711
2712                 if (pkt_cnt < free_cnt) {
2713                         if (ice_xmit_cleanup(txq))
2714                                 break;
2715
2716                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2717                         nb_tx_free_last = txq->nb_tx_free;
2718                 }
2719         }
2720
2721         return (int)pkt_cnt;
2722 }
2723
2724 #ifdef RTE_ARCH_X86
2725 static int
2726 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2727                         uint32_t free_cnt __rte_unused)
2728 {
2729         return -ENOTSUP;
2730 }
2731 #endif
2732
2733 static int
2734 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2735                         uint32_t free_cnt)
2736 {
2737         int i, n, cnt;
2738
2739         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2740                 free_cnt = txq->nb_tx_desc;
2741
2742         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2743
2744         for (i = 0; i < cnt; i += n) {
2745                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2746                         break;
2747
2748                 n = ice_tx_free_bufs(txq);
2749
2750                 if (n == 0)
2751                         break;
2752         }
2753
2754         return i;
2755 }
2756
2757 int
2758 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2759 {
2760         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2761         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2762         struct ice_adapter *ad =
2763                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2764
2765 #ifdef RTE_ARCH_X86
2766         if (ad->tx_vec_allowed)
2767                 return ice_tx_done_cleanup_vec(q, free_cnt);
2768 #endif
2769         if (ad->tx_simple_allowed)
2770                 return ice_tx_done_cleanup_simple(q, free_cnt);
2771         else
2772                 return ice_tx_done_cleanup_full(q, free_cnt);
2773 }
2774
2775 /* Populate 4 descriptors with data from 4 mbufs */
2776 static inline void
2777 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2778 {
2779         uint64_t dma_addr;
2780         uint32_t i;
2781
2782         for (i = 0; i < 4; i++, txdp++, pkts++) {
2783                 dma_addr = rte_mbuf_data_iova(*pkts);
2784                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2785                 txdp->cmd_type_offset_bsz =
2786                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2787                                        (*pkts)->data_len, 0);
2788         }
2789 }
2790
2791 /* Populate 1 descriptor with data from 1 mbuf */
2792 static inline void
2793 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2794 {
2795         uint64_t dma_addr;
2796
2797         dma_addr = rte_mbuf_data_iova(*pkts);
2798         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2799         txdp->cmd_type_offset_bsz =
2800                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2801                                (*pkts)->data_len, 0);
2802 }
2803
2804 static inline void
2805 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2806                     uint16_t nb_pkts)
2807 {
2808         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2809         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2810         const int N_PER_LOOP = 4;
2811         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2812         int mainpart, leftover;
2813         int i, j;
2814
2815         /**
2816          * Process most of the packets in chunks of N pkts.  Any
2817          * leftover packets will get processed one at a time.
2818          */
2819         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2820         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2821         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2822                 /* Copy N mbuf pointers to the S/W ring */
2823                 for (j = 0; j < N_PER_LOOP; ++j)
2824                         (txep + i + j)->mbuf = *(pkts + i + j);
2825                 tx4(txdp + i, pkts + i);
2826         }
2827
2828         if (unlikely(leftover > 0)) {
2829                 for (i = 0; i < leftover; ++i) {
2830                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2831                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2832                 }
2833         }
2834 }
2835
2836 static inline uint16_t
2837 tx_xmit_pkts(struct ice_tx_queue *txq,
2838              struct rte_mbuf **tx_pkts,
2839              uint16_t nb_pkts)
2840 {
2841         volatile struct ice_tx_desc *txr = txq->tx_ring;
2842         uint16_t n = 0;
2843
2844         /**
2845          * Begin scanning the H/W ring for done descriptors when the number
2846          * of available descriptors drops below tx_free_thresh. For each done
2847          * descriptor, free the associated buffer.
2848          */
2849         if (txq->nb_tx_free < txq->tx_free_thresh)
2850                 ice_tx_free_bufs(txq);
2851
2852         /* Use available descriptor only */
2853         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2854         if (unlikely(!nb_pkts))
2855                 return 0;
2856
2857         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2858         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2859                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2860                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2861                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2862                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2863                                          ICE_TXD_QW1_CMD_S);
2864                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2865                 txq->tx_tail = 0;
2866         }
2867
2868         /* Fill hardware descriptor ring with mbuf data */
2869         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2870         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2871
2872         /* Determin if RS bit needs to be set */
2873         if (txq->tx_tail > txq->tx_next_rs) {
2874                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2875                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2876                                          ICE_TXD_QW1_CMD_S);
2877                 txq->tx_next_rs =
2878                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2879                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2880                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2881         }
2882
2883         if (txq->tx_tail >= txq->nb_tx_desc)
2884                 txq->tx_tail = 0;
2885
2886         /* Update the tx tail register */
2887         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2888
2889         return nb_pkts;
2890 }
2891
2892 static uint16_t
2893 ice_xmit_pkts_simple(void *tx_queue,
2894                      struct rte_mbuf **tx_pkts,
2895                      uint16_t nb_pkts)
2896 {
2897         uint16_t nb_tx = 0;
2898
2899         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2900                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2901                                     tx_pkts, nb_pkts);
2902
2903         while (nb_pkts) {
2904                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2905                                                       ICE_TX_MAX_BURST);
2906
2907                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2908                                    &tx_pkts[nb_tx], num);
2909                 nb_tx = (uint16_t)(nb_tx + ret);
2910                 nb_pkts = (uint16_t)(nb_pkts - ret);
2911                 if (ret < num)
2912                         break;
2913         }
2914
2915         return nb_tx;
2916 }
2917
2918 void __rte_cold
2919 ice_set_rx_function(struct rte_eth_dev *dev)
2920 {
2921         PMD_INIT_FUNC_TRACE();
2922         struct ice_adapter *ad =
2923                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2924 #ifdef RTE_ARCH_X86
2925         struct ice_rx_queue *rxq;
2926         int i;
2927         bool use_avx2 = false;
2928
2929         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2930                 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
2931                         ad->rx_vec_allowed = true;
2932                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2933                                 rxq = dev->data->rx_queues[i];
2934                                 if (rxq && ice_rxq_vec_setup(rxq)) {
2935                                         ad->rx_vec_allowed = false;
2936                                         break;
2937                                 }
2938                         }
2939
2940                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2941                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2942                                 use_avx2 = true;
2943
2944                 } else {
2945                         ad->rx_vec_allowed = false;
2946                 }
2947         }
2948
2949         if (ad->rx_vec_allowed) {
2950                 if (dev->data->scattered_rx) {
2951                         PMD_DRV_LOG(DEBUG,
2952                                         "Using %sVector Scattered Rx (port %d).",
2953                                         use_avx2 ? "avx2 " : "",
2954                                         dev->data->port_id);
2955                         dev->rx_pkt_burst = use_avx2 ?
2956                                         ice_recv_scattered_pkts_vec_avx2 :
2957                                         ice_recv_scattered_pkts_vec;
2958                 } else {
2959                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2960                                         use_avx2 ? "avx2 " : "",
2961                                         dev->data->port_id);
2962                         dev->rx_pkt_burst = use_avx2 ?
2963                                                 ice_recv_pkts_vec_avx2 :
2964                                                 ice_recv_pkts_vec;
2965                 }
2966                 return;
2967         }
2968
2969 #endif
2970
2971         if (dev->data->scattered_rx) {
2972                 /* Set the non-LRO scattered function */
2973                 PMD_INIT_LOG(DEBUG,
2974                              "Using a Scattered function on port %d.",
2975                              dev->data->port_id);
2976                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2977         } else if (ad->rx_bulk_alloc_allowed) {
2978                 PMD_INIT_LOG(DEBUG,
2979                              "Rx Burst Bulk Alloc Preconditions are "
2980                              "satisfied. Rx Burst Bulk Alloc function "
2981                              "will be used on port %d.",
2982                              dev->data->port_id);
2983                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2984         } else {
2985                 PMD_INIT_LOG(DEBUG,
2986                              "Rx Burst Bulk Alloc Preconditions are not "
2987                              "satisfied, Normal Rx will be used on port %d.",
2988                              dev->data->port_id);
2989                 dev->rx_pkt_burst = ice_recv_pkts;
2990         }
2991 }
2992
2993 static const struct {
2994         eth_rx_burst_t pkt_burst;
2995         const char *info;
2996 } ice_rx_burst_infos[] = {
2997         { ice_recv_scattered_pkts,          "Scalar Scattered" },
2998         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
2999         { ice_recv_pkts,                    "Scalar" },
3000 #ifdef RTE_ARCH_X86
3001         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3002         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3003         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3004         { ice_recv_pkts_vec,                "Vector SSE" },
3005 #endif
3006 };
3007
3008 int
3009 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3010                       struct rte_eth_burst_mode *mode)
3011 {
3012         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3013         int ret = -EINVAL;
3014         unsigned int i;
3015
3016         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3017                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3018                         snprintf(mode->info, sizeof(mode->info), "%s",
3019                                  ice_rx_burst_infos[i].info);
3020                         ret = 0;
3021                         break;
3022                 }
3023         }
3024
3025         return ret;
3026 }
3027
3028 void __rte_cold
3029 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3030 {
3031         struct ice_adapter *ad =
3032                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3033
3034         /* Use a simple Tx queue if possible (only fast free is allowed) */
3035         ad->tx_simple_allowed =
3036                 (txq->offloads ==
3037                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3038                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3039
3040         if (ad->tx_simple_allowed)
3041                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3042                              txq->queue_id);
3043         else
3044                 PMD_INIT_LOG(DEBUG,
3045                              "Simple Tx can NOT be enabled on Tx queue %u.",
3046                              txq->queue_id);
3047 }
3048
3049 /*********************************************************************
3050  *
3051  *  TX prep functions
3052  *
3053  **********************************************************************/
3054 /* The default values of TSO MSS */
3055 #define ICE_MIN_TSO_MSS            64
3056 #define ICE_MAX_TSO_MSS            9728
3057 #define ICE_MAX_TSO_FRAME_SIZE     262144
3058 uint16_t
3059 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3060               uint16_t nb_pkts)
3061 {
3062         int i, ret;
3063         uint64_t ol_flags;
3064         struct rte_mbuf *m;
3065
3066         for (i = 0; i < nb_pkts; i++) {
3067                 m = tx_pkts[i];
3068                 ol_flags = m->ol_flags;
3069
3070                 if (ol_flags & PKT_TX_TCP_SEG &&
3071                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3072                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3073                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3074                         /**
3075                          * MSS outside the range are considered malicious
3076                          */
3077                         rte_errno = EINVAL;
3078                         return i;
3079                 }
3080
3081 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3082                 ret = rte_validate_tx_offload(m);
3083                 if (ret != 0) {
3084                         rte_errno = -ret;
3085                         return i;
3086                 }
3087 #endif
3088                 ret = rte_net_intel_cksum_prepare(m);
3089                 if (ret != 0) {
3090                         rte_errno = -ret;
3091                         return i;
3092                 }
3093         }
3094         return i;
3095 }
3096
3097 void __rte_cold
3098 ice_set_tx_function(struct rte_eth_dev *dev)
3099 {
3100         struct ice_adapter *ad =
3101                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3102 #ifdef RTE_ARCH_X86
3103         struct ice_tx_queue *txq;
3104         int i;
3105         bool use_avx2 = false;
3106
3107         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3108                 if (!ice_tx_vec_dev_check(dev)) {
3109                         ad->tx_vec_allowed = true;
3110                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3111                                 txq = dev->data->tx_queues[i];
3112                                 if (txq && ice_txq_vec_setup(txq)) {
3113                                         ad->tx_vec_allowed = false;
3114                                         break;
3115                                 }
3116                         }
3117
3118                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3119                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3120                                 use_avx2 = true;
3121
3122                 } else {
3123                         ad->tx_vec_allowed = false;
3124                 }
3125         }
3126
3127         if (ad->tx_vec_allowed) {
3128                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3129                             use_avx2 ? "avx2 " : "",
3130                             dev->data->port_id);
3131                 dev->tx_pkt_burst = use_avx2 ?
3132                                     ice_xmit_pkts_vec_avx2 :
3133                                     ice_xmit_pkts_vec;
3134                 dev->tx_pkt_prepare = NULL;
3135
3136                 return;
3137         }
3138 #endif
3139
3140         if (ad->tx_simple_allowed) {
3141                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3142                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3143                 dev->tx_pkt_prepare = NULL;
3144         } else {
3145                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3146                 dev->tx_pkt_burst = ice_xmit_pkts;
3147                 dev->tx_pkt_prepare = ice_prep_pkts;
3148         }
3149 }
3150
3151 static const struct {
3152         eth_tx_burst_t pkt_burst;
3153         const char *info;
3154 } ice_tx_burst_infos[] = {
3155         { ice_xmit_pkts_simple,   "Scalar Simple" },
3156         { ice_xmit_pkts,          "Scalar" },
3157 #ifdef RTE_ARCH_X86
3158         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3159         { ice_xmit_pkts_vec,      "Vector SSE" },
3160 #endif
3161 };
3162
3163 int
3164 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3165                       struct rte_eth_burst_mode *mode)
3166 {
3167         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3168         int ret = -EINVAL;
3169         unsigned int i;
3170
3171         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3172                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3173                         snprintf(mode->info, sizeof(mode->info), "%s",
3174                                  ice_tx_burst_infos[i].info);
3175                         ret = 0;
3176                         break;
3177                 }
3178         }
3179
3180         return ret;
3181 }
3182
3183 /* For each value it means, datasheet of hardware can tell more details
3184  *
3185  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3186  */
3187 static inline uint32_t
3188 ice_get_default_pkt_type(uint16_t ptype)
3189 {
3190         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3191                 __rte_cache_aligned = {
3192                 /* L2 types */
3193                 /* [0] reserved */
3194                 [1] = RTE_PTYPE_L2_ETHER,
3195                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3196                 /* [3] - [5] reserved */
3197                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3198                 /* [7] - [10] reserved */
3199                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3200                 /* [12] - [21] reserved */
3201
3202                 /* Non tunneled IPv4 */
3203                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3204                        RTE_PTYPE_L4_FRAG,
3205                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3206                        RTE_PTYPE_L4_NONFRAG,
3207                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3208                        RTE_PTYPE_L4_UDP,
3209                 /* [25] reserved */
3210                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3211                        RTE_PTYPE_L4_TCP,
3212                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3213                        RTE_PTYPE_L4_SCTP,
3214                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3215                        RTE_PTYPE_L4_ICMP,
3216
3217                 /* IPv4 --> IPv4 */
3218                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3219                        RTE_PTYPE_TUNNEL_IP |
3220                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3221                        RTE_PTYPE_INNER_L4_FRAG,
3222                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3223                        RTE_PTYPE_TUNNEL_IP |
3224                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3225                        RTE_PTYPE_INNER_L4_NONFRAG,
3226                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3227                        RTE_PTYPE_TUNNEL_IP |
3228                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3229                        RTE_PTYPE_INNER_L4_UDP,
3230                 /* [32] reserved */
3231                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3232                        RTE_PTYPE_TUNNEL_IP |
3233                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3234                        RTE_PTYPE_INNER_L4_TCP,
3235                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3236                        RTE_PTYPE_TUNNEL_IP |
3237                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3238                        RTE_PTYPE_INNER_L4_SCTP,
3239                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3240                        RTE_PTYPE_TUNNEL_IP |
3241                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3242                        RTE_PTYPE_INNER_L4_ICMP,
3243
3244                 /* IPv4 --> IPv6 */
3245                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3246                        RTE_PTYPE_TUNNEL_IP |
3247                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3248                        RTE_PTYPE_INNER_L4_FRAG,
3249                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3250                        RTE_PTYPE_TUNNEL_IP |
3251                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3252                        RTE_PTYPE_INNER_L4_NONFRAG,
3253                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3254                        RTE_PTYPE_TUNNEL_IP |
3255                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3256                        RTE_PTYPE_INNER_L4_UDP,
3257                 /* [39] reserved */
3258                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3259                        RTE_PTYPE_TUNNEL_IP |
3260                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3261                        RTE_PTYPE_INNER_L4_TCP,
3262                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3263                        RTE_PTYPE_TUNNEL_IP |
3264                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3265                        RTE_PTYPE_INNER_L4_SCTP,
3266                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3267                        RTE_PTYPE_TUNNEL_IP |
3268                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3269                        RTE_PTYPE_INNER_L4_ICMP,
3270
3271                 /* IPv4 --> GRE/Teredo/VXLAN */
3272                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3273                        RTE_PTYPE_TUNNEL_GRENAT,
3274
3275                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3276                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3277                        RTE_PTYPE_TUNNEL_GRENAT |
3278                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3279                        RTE_PTYPE_INNER_L4_FRAG,
3280                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3281                        RTE_PTYPE_TUNNEL_GRENAT |
3282                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3283                        RTE_PTYPE_INNER_L4_NONFRAG,
3284                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3285                        RTE_PTYPE_TUNNEL_GRENAT |
3286                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3287                        RTE_PTYPE_INNER_L4_UDP,
3288                 /* [47] reserved */
3289                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3290                        RTE_PTYPE_TUNNEL_GRENAT |
3291                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3292                        RTE_PTYPE_INNER_L4_TCP,
3293                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3294                        RTE_PTYPE_TUNNEL_GRENAT |
3295                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3296                        RTE_PTYPE_INNER_L4_SCTP,
3297                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3298                        RTE_PTYPE_TUNNEL_GRENAT |
3299                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3300                        RTE_PTYPE_INNER_L4_ICMP,
3301
3302                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3303                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3304                        RTE_PTYPE_TUNNEL_GRENAT |
3305                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3306                        RTE_PTYPE_INNER_L4_FRAG,
3307                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3308                        RTE_PTYPE_TUNNEL_GRENAT |
3309                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3310                        RTE_PTYPE_INNER_L4_NONFRAG,
3311                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3312                        RTE_PTYPE_TUNNEL_GRENAT |
3313                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3314                        RTE_PTYPE_INNER_L4_UDP,
3315                 /* [54] reserved */
3316                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3317                        RTE_PTYPE_TUNNEL_GRENAT |
3318                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3319                        RTE_PTYPE_INNER_L4_TCP,
3320                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3321                        RTE_PTYPE_TUNNEL_GRENAT |
3322                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3323                        RTE_PTYPE_INNER_L4_SCTP,
3324                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3325                        RTE_PTYPE_TUNNEL_GRENAT |
3326                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3327                        RTE_PTYPE_INNER_L4_ICMP,
3328
3329                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3330                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3331                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3332
3333                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3334                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3335                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3336                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3337                        RTE_PTYPE_INNER_L4_FRAG,
3338                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3339                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3340                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3341                        RTE_PTYPE_INNER_L4_NONFRAG,
3342                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3343                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3344                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3345                        RTE_PTYPE_INNER_L4_UDP,
3346                 /* [62] reserved */
3347                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3348                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3349                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3350                        RTE_PTYPE_INNER_L4_TCP,
3351                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3352                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3353                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3354                        RTE_PTYPE_INNER_L4_SCTP,
3355                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3356                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3357                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3358                        RTE_PTYPE_INNER_L4_ICMP,
3359
3360                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3361                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3362                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3363                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3364                        RTE_PTYPE_INNER_L4_FRAG,
3365                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3366                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3367                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3368                        RTE_PTYPE_INNER_L4_NONFRAG,
3369                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3370                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3371                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3372                        RTE_PTYPE_INNER_L4_UDP,
3373                 /* [69] reserved */
3374                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3375                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3376                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3377                        RTE_PTYPE_INNER_L4_TCP,
3378                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3379                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3380                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3381                        RTE_PTYPE_INNER_L4_SCTP,
3382                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3383                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3384                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3385                        RTE_PTYPE_INNER_L4_ICMP,
3386                 /* [73] - [87] reserved */
3387
3388                 /* Non tunneled IPv6 */
3389                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3390                        RTE_PTYPE_L4_FRAG,
3391                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3392                        RTE_PTYPE_L4_NONFRAG,
3393                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3394                        RTE_PTYPE_L4_UDP,
3395                 /* [91] reserved */
3396                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3397                        RTE_PTYPE_L4_TCP,
3398                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3399                        RTE_PTYPE_L4_SCTP,
3400                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3401                        RTE_PTYPE_L4_ICMP,
3402
3403                 /* IPv6 --> IPv4 */
3404                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3405                        RTE_PTYPE_TUNNEL_IP |
3406                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3407                        RTE_PTYPE_INNER_L4_FRAG,
3408                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3409                        RTE_PTYPE_TUNNEL_IP |
3410                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3411                        RTE_PTYPE_INNER_L4_NONFRAG,
3412                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3413                        RTE_PTYPE_TUNNEL_IP |
3414                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3415                        RTE_PTYPE_INNER_L4_UDP,
3416                 /* [98] reserved */
3417                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3418                        RTE_PTYPE_TUNNEL_IP |
3419                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3420                        RTE_PTYPE_INNER_L4_TCP,
3421                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3422                         RTE_PTYPE_TUNNEL_IP |
3423                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3424                         RTE_PTYPE_INNER_L4_SCTP,
3425                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3426                         RTE_PTYPE_TUNNEL_IP |
3427                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3428                         RTE_PTYPE_INNER_L4_ICMP,
3429
3430                 /* IPv6 --> IPv6 */
3431                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3432                         RTE_PTYPE_TUNNEL_IP |
3433                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3434                         RTE_PTYPE_INNER_L4_FRAG,
3435                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3436                         RTE_PTYPE_TUNNEL_IP |
3437                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3438                         RTE_PTYPE_INNER_L4_NONFRAG,
3439                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3440                         RTE_PTYPE_TUNNEL_IP |
3441                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3442                         RTE_PTYPE_INNER_L4_UDP,
3443                 /* [105] reserved */
3444                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3445                         RTE_PTYPE_TUNNEL_IP |
3446                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3447                         RTE_PTYPE_INNER_L4_TCP,
3448                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3449                         RTE_PTYPE_TUNNEL_IP |
3450                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3451                         RTE_PTYPE_INNER_L4_SCTP,
3452                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3453                         RTE_PTYPE_TUNNEL_IP |
3454                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3455                         RTE_PTYPE_INNER_L4_ICMP,
3456
3457                 /* IPv6 --> GRE/Teredo/VXLAN */
3458                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3459                         RTE_PTYPE_TUNNEL_GRENAT,
3460
3461                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3462                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3463                         RTE_PTYPE_TUNNEL_GRENAT |
3464                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3465                         RTE_PTYPE_INNER_L4_FRAG,
3466                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3467                         RTE_PTYPE_TUNNEL_GRENAT |
3468                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3469                         RTE_PTYPE_INNER_L4_NONFRAG,
3470                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3471                         RTE_PTYPE_TUNNEL_GRENAT |
3472                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3473                         RTE_PTYPE_INNER_L4_UDP,
3474                 /* [113] reserved */
3475                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3476                         RTE_PTYPE_TUNNEL_GRENAT |
3477                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3478                         RTE_PTYPE_INNER_L4_TCP,
3479                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3480                         RTE_PTYPE_TUNNEL_GRENAT |
3481                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3482                         RTE_PTYPE_INNER_L4_SCTP,
3483                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3484                         RTE_PTYPE_TUNNEL_GRENAT |
3485                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3486                         RTE_PTYPE_INNER_L4_ICMP,
3487
3488                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3489                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3490                         RTE_PTYPE_TUNNEL_GRENAT |
3491                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3492                         RTE_PTYPE_INNER_L4_FRAG,
3493                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3494                         RTE_PTYPE_TUNNEL_GRENAT |
3495                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3496                         RTE_PTYPE_INNER_L4_NONFRAG,
3497                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3498                         RTE_PTYPE_TUNNEL_GRENAT |
3499                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3500                         RTE_PTYPE_INNER_L4_UDP,
3501                 /* [120] reserved */
3502                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3503                         RTE_PTYPE_TUNNEL_GRENAT |
3504                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3505                         RTE_PTYPE_INNER_L4_TCP,
3506                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3507                         RTE_PTYPE_TUNNEL_GRENAT |
3508                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3509                         RTE_PTYPE_INNER_L4_SCTP,
3510                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3511                         RTE_PTYPE_TUNNEL_GRENAT |
3512                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3513                         RTE_PTYPE_INNER_L4_ICMP,
3514
3515                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3516                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3517                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3518
3519                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3520                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3521                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3522                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3523                         RTE_PTYPE_INNER_L4_FRAG,
3524                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3525                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3526                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3527                         RTE_PTYPE_INNER_L4_NONFRAG,
3528                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3529                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3530                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3531                         RTE_PTYPE_INNER_L4_UDP,
3532                 /* [128] reserved */
3533                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3534                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3535                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3536                         RTE_PTYPE_INNER_L4_TCP,
3537                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3538                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3539                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3540                         RTE_PTYPE_INNER_L4_SCTP,
3541                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3542                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3543                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3544                         RTE_PTYPE_INNER_L4_ICMP,
3545
3546                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3547                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3548                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3549                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3550                         RTE_PTYPE_INNER_L4_FRAG,
3551                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3552                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3553                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3554                         RTE_PTYPE_INNER_L4_NONFRAG,
3555                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3556                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3557                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3558                         RTE_PTYPE_INNER_L4_UDP,
3559                 /* [135] reserved */
3560                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3561                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3562                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3563                         RTE_PTYPE_INNER_L4_TCP,
3564                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3565                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3566                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3567                         RTE_PTYPE_INNER_L4_SCTP,
3568                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3569                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3570                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3571                         RTE_PTYPE_INNER_L4_ICMP,
3572                 /* [139] - [299] reserved */
3573
3574                 /* PPPoE */
3575                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3576                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3577
3578                 /* PPPoE --> IPv4 */
3579                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3580                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3581                         RTE_PTYPE_L4_FRAG,
3582                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3583                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3584                         RTE_PTYPE_L4_NONFRAG,
3585                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3586                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3587                         RTE_PTYPE_L4_UDP,
3588                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3589                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3590                         RTE_PTYPE_L4_TCP,
3591                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3592                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3593                         RTE_PTYPE_L4_SCTP,
3594                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3595                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3596                         RTE_PTYPE_L4_ICMP,
3597
3598                 /* PPPoE --> IPv6 */
3599                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3600                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3601                         RTE_PTYPE_L4_FRAG,
3602                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3603                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3604                         RTE_PTYPE_L4_NONFRAG,
3605                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3606                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3607                         RTE_PTYPE_L4_UDP,
3608                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3609                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3610                         RTE_PTYPE_L4_TCP,
3611                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3612                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3613                         RTE_PTYPE_L4_SCTP,
3614                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3615                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3616                         RTE_PTYPE_L4_ICMP,
3617                 /* [314] - [324] reserved */
3618
3619                 /* IPv4/IPv6 --> GTPC/GTPU */
3620                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3621                         RTE_PTYPE_TUNNEL_GTPC,
3622                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3623                         RTE_PTYPE_TUNNEL_GTPC,
3624                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3625                         RTE_PTYPE_TUNNEL_GTPC,
3626                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3627                         RTE_PTYPE_TUNNEL_GTPC,
3628                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3629                         RTE_PTYPE_TUNNEL_GTPU,
3630                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3631                         RTE_PTYPE_TUNNEL_GTPU,
3632
3633                 /* IPv4 --> GTPU --> IPv4 */
3634                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3635                         RTE_PTYPE_TUNNEL_GTPU |
3636                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3637                         RTE_PTYPE_INNER_L4_FRAG,
3638                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3639                         RTE_PTYPE_TUNNEL_GTPU |
3640                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3641                         RTE_PTYPE_INNER_L4_NONFRAG,
3642                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3643                         RTE_PTYPE_TUNNEL_GTPU |
3644                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3645                         RTE_PTYPE_INNER_L4_UDP,
3646                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3647                         RTE_PTYPE_TUNNEL_GTPU |
3648                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3649                         RTE_PTYPE_INNER_L4_TCP,
3650                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3651                         RTE_PTYPE_TUNNEL_GTPU |
3652                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3653                         RTE_PTYPE_INNER_L4_ICMP,
3654
3655                 /* IPv6 --> GTPU --> IPv4 */
3656                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3657                         RTE_PTYPE_TUNNEL_GTPU |
3658                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3659                         RTE_PTYPE_INNER_L4_FRAG,
3660                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3661                         RTE_PTYPE_TUNNEL_GTPU |
3662                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3663                         RTE_PTYPE_INNER_L4_NONFRAG,
3664                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3665                         RTE_PTYPE_TUNNEL_GTPU |
3666                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3667                         RTE_PTYPE_INNER_L4_UDP,
3668                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3669                         RTE_PTYPE_TUNNEL_GTPU |
3670                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3671                         RTE_PTYPE_INNER_L4_TCP,
3672                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3673                         RTE_PTYPE_TUNNEL_GTPU |
3674                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3675                         RTE_PTYPE_INNER_L4_ICMP,
3676
3677                 /* IPv4 --> GTPU --> IPv6 */
3678                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3679                         RTE_PTYPE_TUNNEL_GTPU |
3680                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3681                         RTE_PTYPE_INNER_L4_FRAG,
3682                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3683                         RTE_PTYPE_TUNNEL_GTPU |
3684                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3685                         RTE_PTYPE_INNER_L4_NONFRAG,
3686                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3687                         RTE_PTYPE_TUNNEL_GTPU |
3688                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3689                         RTE_PTYPE_INNER_L4_UDP,
3690                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3691                         RTE_PTYPE_TUNNEL_GTPU |
3692                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3693                         RTE_PTYPE_INNER_L4_TCP,
3694                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3695                         RTE_PTYPE_TUNNEL_GTPU |
3696                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3697                         RTE_PTYPE_INNER_L4_ICMP,
3698
3699                 /* IPv6 --> GTPU --> IPv6 */
3700                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3701                         RTE_PTYPE_TUNNEL_GTPU |
3702                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3703                         RTE_PTYPE_INNER_L4_FRAG,
3704                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3705                         RTE_PTYPE_TUNNEL_GTPU |
3706                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3707                         RTE_PTYPE_INNER_L4_NONFRAG,
3708                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3709                         RTE_PTYPE_TUNNEL_GTPU |
3710                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3711                         RTE_PTYPE_INNER_L4_UDP,
3712                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3713                         RTE_PTYPE_TUNNEL_GTPU |
3714                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3715                         RTE_PTYPE_INNER_L4_TCP,
3716                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3717                         RTE_PTYPE_TUNNEL_GTPU |
3718                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3719                         RTE_PTYPE_INNER_L4_ICMP,
3720                 /* All others reserved */
3721         };
3722
3723         return type_table[ptype];
3724 }
3725
3726 void __rte_cold
3727 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3728 {
3729         struct ice_adapter *ad =
3730                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3731         int i;
3732
3733         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3734                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3735 }
3736
3737 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
3738 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
3739                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
3740 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
3741 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
3742
3743 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
3744 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
3745         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
3746 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
3747 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
3748         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
3749
3750 /*
3751  * check the programming status descriptor in rx queue.
3752  * done after Programming Flow Director is programmed on
3753  * tx queue
3754  */
3755 static inline int
3756 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
3757 {
3758         volatile union ice_32byte_rx_desc *rxdp;
3759         uint64_t qword1;
3760         uint32_t rx_status;
3761         uint32_t error;
3762         uint32_t id;
3763         int ret = -EAGAIN;
3764
3765         rxdp = (volatile union ice_32byte_rx_desc *)
3766                 (&rxq->rx_ring[rxq->rx_tail]);
3767         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
3768         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
3769                         >> ICE_RXD_QW1_STATUS_S;
3770
3771         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
3772                 ret = 0;
3773                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
3774                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
3775                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
3776                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
3777                 if (error) {
3778                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
3779                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
3780                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
3781                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
3782                         ret = -EINVAL;
3783                         goto err;
3784                 }
3785                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
3786                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
3787                 if (error) {
3788                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
3789                         ret = -EINVAL;
3790                 }
3791 err:
3792                 rxdp->wb.qword1.status_error_len = 0;
3793                 rxq->rx_tail++;
3794                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
3795                         rxq->rx_tail = 0;
3796                 if (rxq->rx_tail == 0)
3797                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3798                 else
3799                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
3800         }
3801
3802         return ret;
3803 }
3804
3805 #define ICE_FDIR_MAX_WAIT_US 10000
3806
3807 int
3808 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
3809 {
3810         struct ice_tx_queue *txq = pf->fdir.txq;
3811         struct ice_rx_queue *rxq = pf->fdir.rxq;
3812         volatile struct ice_fltr_desc *fdirdp;
3813         volatile struct ice_tx_desc *txdp;
3814         uint32_t td_cmd;
3815         uint16_t i;
3816
3817         fdirdp = (volatile struct ice_fltr_desc *)
3818                 (&txq->tx_ring[txq->tx_tail]);
3819         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
3820         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
3821
3822         txdp = &txq->tx_ring[txq->tx_tail + 1];
3823         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
3824         td_cmd = ICE_TX_DESC_CMD_EOP |
3825                 ICE_TX_DESC_CMD_RS  |
3826                 ICE_TX_DESC_CMD_DUMMY;
3827
3828         txdp->cmd_type_offset_bsz =
3829                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
3830
3831         txq->tx_tail += 2;
3832         if (txq->tx_tail >= txq->nb_tx_desc)
3833                 txq->tx_tail = 0;
3834         /* Update the tx tail register */
3835         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
3836         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
3837                 if ((txdp->cmd_type_offset_bsz &
3838                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
3839                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
3840                         break;
3841                 rte_delay_us(1);
3842         }
3843         if (i >= ICE_FDIR_MAX_WAIT_US) {
3844                 PMD_DRV_LOG(ERR,
3845                             "Failed to program FDIR filter: time out to get DD on tx queue.");
3846                 return -ETIMEDOUT;
3847         }
3848
3849         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
3850                 int ret;
3851
3852                 ret = ice_check_fdir_programming_status(rxq);
3853                 if (ret == -EAGAIN)
3854                         rte_delay_us(1);
3855                 else
3856                         return ret;
3857         }
3858
3859         PMD_DRV_LOG(ERR,
3860                     "Failed to program FDIR filter: programming status reported.");
3861         return -ETIMEDOUT;
3862
3863
3864 }