drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_ethdev_driver.h>
   6 #include <rte_net.h>
   7
   8 #include "rte_pmd_ice.h"
   9 #include "ice_rxtx.h"
  10
  11 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  12                 PKT_TX_IP_CKSUM |                \
  13                 PKT_TX_L4_MASK |                 \
  14                 PKT_TX_TCP_SEG |                 \
  15                 PKT_TX_OUTER_IP_CKSUM)
  16
  17 /* Offset of mbuf dynamic field for protocol extraction data */
  18 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  19
  20 /* Mask of mbuf dynamic flags for protocol extraction type */
  21 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  22 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  27
  28 static inline uint64_t
  29 ice_rxdid_to_proto_xtr_ol_flag(uint8_t rxdid, bool *chk_valid)
  30 {
  31         static struct {
  32                 uint64_t *ol_flag;
  33                 bool chk_valid;
  34         } ol_flag_map[] = {
  35                 [ICE_RXDID_COMMS_AUX_VLAN] = {
  36                         &rte_net_ice_dynflag_proto_xtr_vlan_mask, true },
  37                 [ICE_RXDID_COMMS_AUX_IPV4] = {
  38                         &rte_net_ice_dynflag_proto_xtr_ipv4_mask, true },
  39                 [ICE_RXDID_COMMS_AUX_IPV6] = {
  40                         &rte_net_ice_dynflag_proto_xtr_ipv6_mask, true },
  41                 [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = {
  42                         &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask, true },
  43                 [ICE_RXDID_COMMS_AUX_TCP] = {
  44                         &rte_net_ice_dynflag_proto_xtr_tcp_mask, true },
  45                 [ICE_RXDID_COMMS_AUX_IP_OFFSET] = {
  46                         &rte_net_ice_dynflag_proto_xtr_ip_offset_mask, false },
  47         };
  48         uint64_t *ol_flag;
  49
  50         if (rxdid < RTE_DIM(ol_flag_map)) {
  51                 ol_flag = ol_flag_map[rxdid].ol_flag;
  52                 if (!ol_flag)
  53                         return 0ULL;
  54
  55                 *chk_valid = ol_flag_map[rxdid].chk_valid;
  56                 return *ol_flag;
  57         }
  58
  59         return 0ULL;
  60 }
  61
  62 static inline uint8_t
  63 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  64 {
  65         static uint8_t rxdid_map[] = {
  66                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_OVS,
  67                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  68                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  69                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  70                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  71                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  72                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  73         };
  74
  75         return xtr_type < RTE_DIM(rxdid_map) ?
  76                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
  77 }
  78
  79 static enum ice_status
  80 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
  81 {
  82         struct ice_vsi *vsi = rxq->vsi;
  83         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
  84         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
  85         struct rte_eth_dev *dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
  86         struct ice_rlan_ctx rx_ctx;
  87         enum ice_status err;
  88         uint16_t buf_size, len;
  89         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  90         uint32_t rxdid = ICE_RXDID_COMMS_OVS;
  91         uint32_t regval;
  92
  93         /* Set buffer size as the head split is disabled. */
  94         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
  95                               RTE_PKTMBUF_HEADROOM);
  96         rxq->rx_hdr_len = 0;
  97         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
  98         len = ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len;
  99         rxq->max_pkt_len = RTE_MIN(len,
 100                                    dev->data->dev_conf.rxmode.max_rx_pkt_len);
 101
 102         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 103                 if (rxq->max_pkt_len <= RTE_ETHER_MAX_LEN ||
 104                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 105                         PMD_DRV_LOG(ERR, "maximum packet length must "
 106                                     "be larger than %u and smaller than %u,"
 107                                     "as jumbo frame is enabled",
 108                                     (uint32_t)RTE_ETHER_MAX_LEN,
 109                                     (uint32_t)ICE_FRAME_SIZE_MAX);
 110                         return -EINVAL;
 111                 }
 112         } else {
 113                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
 114                     rxq->max_pkt_len > RTE_ETHER_MAX_LEN) {
 115                         PMD_DRV_LOG(ERR, "maximum packet length must be "
 116                                     "larger than %u and smaller than %u, "
 117                                     "as jumbo frame is disabled",
 118                                     (uint32_t)RTE_ETHER_MIN_LEN,
 119                                     (uint32_t)RTE_ETHER_MAX_LEN);
 120                         return -EINVAL;
 121                 }
 122         }
 123
 124         memset(&rx_ctx, 0, sizeof(rx_ctx));
 125
 126         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 127         rx_ctx.qlen = rxq->nb_rx_desc;
 128         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 129         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 130         rx_ctx.dtype = 0; /* No Header Split mode */
 131 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 132         rx_ctx.dsize = 1; /* 32B descriptors */
 133 #endif
 134         rx_ctx.rxmax = rxq->max_pkt_len;
 135         /* TPH: Transaction Layer Packet (TLP) processing hints */
 136         rx_ctx.tphrdesc_ena = 1;
 137         rx_ctx.tphwdesc_ena = 1;
 138         rx_ctx.tphdata_ena = 1;
 139         rx_ctx.tphhead_ena = 1;
 140         /* Low Receive Queue Threshold defined in 64 descriptors units.
 141          * When the number of free descriptors goes below the lrxqthresh,
 142          * an immediate interrupt is triggered.
 143          */
 144         rx_ctx.lrxqthresh = 2;
 145         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 146         rx_ctx.l2tsel = 1;
 147         rx_ctx.showiv = 0;
 148         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 149
 150         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 151
 152         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 153                     rxq->port_id, rxq->queue_id, rxdid);
 154
 155         if (!(pf->supported_rxdid & BIT(rxdid))) {
 156                 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
 157                             rxdid);
 158                 return -EINVAL;
 159         }
 160
 161         /* Enable Flexible Descriptors in the queue context which
 162          * allows this driver to select a specific receive descriptor format
 163          */
 164         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 165                 QRXFLXP_CNTXT_RXDID_IDX_M;
 166
 167         /* increasing context priority to pick up profile ID;
 168          * default is 0x01; setting to 0x03 to ensure profile
 169          * is programming if prev context is of same priority
 170          */
 171         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 172                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 173
 174         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 175
 176         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 177         if (err) {
 178                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 179                             rxq->queue_id);
 180                 return -EINVAL;
 181         }
 182         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 183         if (err) {
 184                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 185                             rxq->queue_id);
 186                 return -EINVAL;
 187         }
 188
 189         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 190                               RTE_PKTMBUF_HEADROOM);
 191
 192         /* Check if scattered RX needs to be used. */
 193         if (rxq->max_pkt_len > buf_size)
 194                 dev->data->scattered_rx = 1;
 195
 196         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 197
 198         /* Init the Rx tail register*/
 199         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 200
 201         return 0;
 202 }
 203
 204 /* Allocate mbufs for all descriptors in rx queue */
 205 static int
 206 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 207 {
 208         struct ice_rx_entry *rxe = rxq->sw_ring;
 209         uint64_t dma_addr;
 210         uint16_t i;
 211
 212         for (i = 0; i < rxq->nb_rx_desc; i++) {
 213                 volatile union ice_rx_flex_desc *rxd;
 214                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 215
 216                 if (unlikely(!mbuf)) {
 217                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 218                         return -ENOMEM;
 219                 }
 220
 221                 rte_mbuf_refcnt_set(mbuf, 1);
 222                 mbuf->next = NULL;
 223                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 224                 mbuf->nb_segs = 1;
 225                 mbuf->port = rxq->port_id;
 226
 227                 dma_addr =
 228                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 229
 230                 rxd = &rxq->rx_ring[i];
 231                 rxd->read.pkt_addr = dma_addr;
 232                 rxd->read.hdr_addr = 0;
 233 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 234                 rxd->read.rsvd1 = 0;
 235                 rxd->read.rsvd2 = 0;
 236 #endif
 237                 rxe[i].mbuf = mbuf;
 238         }
 239
 240         return 0;
 241 }
 242
 243 /* Free all mbufs for descriptors in rx queue */
 244 static void
 245 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 246 {
 247         uint16_t i;
 248
 249         if (!rxq || !rxq->sw_ring) {
 250                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 251                 return;
 252         }
 253
 254         for (i = 0; i < rxq->nb_rx_desc; i++) {
 255                 if (rxq->sw_ring[i].mbuf) {
 256                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 257                         rxq->sw_ring[i].mbuf = NULL;
 258                 }
 259         }
 260         if (rxq->rx_nb_avail == 0)
 261                 return;
 262         for (i = 0; i < rxq->rx_nb_avail; i++)
 263                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 264
 265         rxq->rx_nb_avail = 0;
 266 }
 267
 268 /* turn on or off rx queue
 269  * @q_idx: queue index in pf scope
 270  * @on: turn on or off the queue
 271  */
 272 static int
 273 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 274 {
 275         uint32_t reg;
 276         uint16_t j;
 277
 278         /* QRX_CTRL = QRX_ENA */
 279         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 280
 281         if (on) {
 282                 if (reg & QRX_CTRL_QENA_STAT_M)
 283                         return 0; /* Already on, skip */
 284                 reg |= QRX_CTRL_QENA_REQ_M;
 285         } else {
 286                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 287                         return 0; /* Already off, skip */
 288                 reg &= ~QRX_CTRL_QENA_REQ_M;
 289         }
 290
 291         /* Write the register */
 292         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 293         /* Check the result. It is said that QENA_STAT
 294          * follows the QENA_REQ not more than 10 use.
 295          * TODO: need to change the wait counter later
 296          */
 297         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 298                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 299                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 300                 if (on) {
 301                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 302                             (reg & QRX_CTRL_QENA_STAT_M))
 303                                 break;
 304                 } else {
 305                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 306                             !(reg & QRX_CTRL_QENA_STAT_M))
 307                                 break;
 308                 }
 309         }
 310
 311         /* Check if it is timeout */
 312         if (j >= ICE_CHK_Q_ENA_COUNT) {
 313                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 314                             (on ? "enable" : "disable"), q_idx);
 315                 return -ETIMEDOUT;
 316         }
 317
 318         return 0;
 319 }
 320
 321 static inline int
 322 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 323 {
 324         int ret = 0;
 325
 326         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 327                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 328                              "rxq->rx_free_thresh=%d, "
 329                              "ICE_RX_MAX_BURST=%d",
 330                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 331                 ret = -EINVAL;
 332         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 333                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 334                              "rxq->rx_free_thresh=%d, "
 335                              "rxq->nb_rx_desc=%d",
 336                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 337                 ret = -EINVAL;
 338         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 339                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 340                              "rxq->nb_rx_desc=%d, "
 341                              "rxq->rx_free_thresh=%d",
 342                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 343                 ret = -EINVAL;
 344         }
 345
 346         return ret;
 347 }
 348
 349 /* reset fields in ice_rx_queue back to default */
 350 static void
 351 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 352 {
 353         unsigned int i;
 354         uint16_t len;
 355
 356         if (!rxq) {
 357                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 358                 return;
 359         }
 360
 361         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 362
 363         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 364                 ((volatile char *)rxq->rx_ring)[i] = 0;
 365
 366         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 367         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 368                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 369
 370         rxq->rx_nb_avail = 0;
 371         rxq->rx_next_avail = 0;
 372         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 373
 374         rxq->rx_tail = 0;
 375         rxq->nb_rx_hold = 0;
 376         rxq->pkt_first_seg = NULL;
 377         rxq->pkt_last_seg = NULL;
 378
 379         rxq->rxrearm_start = 0;
 380         rxq->rxrearm_nb = 0;
 381 }
 382
 383 int
 384 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 385 {
 386         struct ice_rx_queue *rxq;
 387         int err;
 388         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 389
 390         PMD_INIT_FUNC_TRACE();
 391
 392         if (rx_queue_id >= dev->data->nb_rx_queues) {
 393                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 394                             rx_queue_id, dev->data->nb_rx_queues);
 395                 return -EINVAL;
 396         }
 397
 398         rxq = dev->data->rx_queues[rx_queue_id];
 399         if (!rxq || !rxq->q_set) {
 400                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 401                             rx_queue_id);
 402                 return -EINVAL;
 403         }
 404
 405         err = ice_program_hw_rx_queue(rxq);
 406         if (err) {
 407                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 408                             rx_queue_id);
 409                 return -EIO;
 410         }
 411
 412         err = ice_alloc_rx_queue_mbufs(rxq);
 413         if (err) {
 414                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 415                 return -ENOMEM;
 416         }
 417
 418         /* Init the RX tail register. */
 419         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 420
 421         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 422         if (err) {
 423                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 424                             rx_queue_id);
 425
 426                 rxq->rx_rel_mbufs(rxq);
 427                 ice_reset_rx_queue(rxq);
 428                 return -EINVAL;
 429         }
 430
 431         dev->data->rx_queue_state[rx_queue_id] =
 432                 RTE_ETH_QUEUE_STATE_STARTED;
 433
 434         return 0;
 435 }
 436
 437 int
 438 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 439 {
 440         struct ice_rx_queue *rxq;
 441         int err;
 442         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 443
 444         if (rx_queue_id < dev->data->nb_rx_queues) {
 445                 rxq = dev->data->rx_queues[rx_queue_id];
 446
 447                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 448                 if (err) {
 449                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 450                                     rx_queue_id);
 451                         return -EINVAL;
 452                 }
 453                 rxq->rx_rel_mbufs(rxq);
 454                 ice_reset_rx_queue(rxq);
 455                 dev->data->rx_queue_state[rx_queue_id] =
 456                         RTE_ETH_QUEUE_STATE_STOPPED;
 457         }
 458
 459         return 0;
 460 }
 461
 462 int
 463 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 464 {
 465         struct ice_tx_queue *txq;
 466         int err;
 467         struct ice_vsi *vsi;
 468         struct ice_hw *hw;
 469         struct ice_aqc_add_tx_qgrp *txq_elem;
 470         struct ice_tlan_ctx tx_ctx;
 471         int buf_len;
 472
 473         PMD_INIT_FUNC_TRACE();
 474
 475         if (tx_queue_id >= dev->data->nb_tx_queues) {
 476                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 477                             tx_queue_id, dev->data->nb_tx_queues);
 478                 return -EINVAL;
 479         }
 480
 481         txq = dev->data->tx_queues[tx_queue_id];
 482         if (!txq || !txq->q_set) {
 483                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 484                             tx_queue_id);
 485                 return -EINVAL;
 486         }
 487
 488         buf_len = ice_struct_size(txq_elem, txqs, 1);
 489         txq_elem = ice_malloc(hw, buf_len);
 490         if (!txq_elem)
 491                 return -ENOMEM;
 492
 493         vsi = txq->vsi;
 494         hw = ICE_VSI_TO_HW(vsi);
 495
 496         memset(&tx_ctx, 0, sizeof(tx_ctx));
 497         txq_elem->num_txqs = 1;
 498         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 499
 500         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 501         tx_ctx.qlen = txq->nb_tx_desc;
 502         tx_ctx.pf_num = hw->pf_id;
 503         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 504         tx_ctx.src_vsi = vsi->vsi_id;
 505         tx_ctx.port_num = hw->port_info->lport;
 506         tx_ctx.tso_ena = 1; /* tso enable */
 507         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 508         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 509
 510         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 511                     ice_tlan_ctx_info);
 512
 513         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 514
 515         /* Init the Tx tail register*/
 516         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 517
 518         /* Fix me, we assume TC always 0 here */
 519         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 520                         txq_elem, buf_len, NULL);
 521         if (err) {
 522                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 523                 rte_free(txq_elem);
 524                 return -EIO;
 525         }
 526         /* store the schedule node id */
 527         txq->q_teid = txq_elem->txqs[0].q_teid;
 528
 529         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 530
 531         rte_free(txq_elem);
 532         return 0;
 533 }
 534
 535 static enum ice_status
 536 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 537 {
 538         struct ice_vsi *vsi = rxq->vsi;
 539         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 540         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 541         struct ice_rlan_ctx rx_ctx;
 542         enum ice_status err;
 543         uint32_t regval;
 544
 545         rxq->rx_hdr_len = 0;
 546         rxq->rx_buf_len = 1024;
 547
 548         memset(&rx_ctx, 0, sizeof(rx_ctx));
 549
 550         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 551         rx_ctx.qlen = rxq->nb_rx_desc;
 552         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 553         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 554         rx_ctx.dtype = 0; /* No Header Split mode */
 555         rx_ctx.dsize = 1; /* 32B descriptors */
 556         rx_ctx.rxmax = RTE_ETHER_MAX_LEN;
 557         /* TPH: Transaction Layer Packet (TLP) processing hints */
 558         rx_ctx.tphrdesc_ena = 1;
 559         rx_ctx.tphwdesc_ena = 1;
 560         rx_ctx.tphdata_ena = 1;
 561         rx_ctx.tphhead_ena = 1;
 562         /* Low Receive Queue Threshold defined in 64 descriptors units.
 563          * When the number of free descriptors goes below the lrxqthresh,
 564          * an immediate interrupt is triggered.
 565          */
 566         rx_ctx.lrxqthresh = 2;
 567         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 568         rx_ctx.l2tsel = 1;
 569         rx_ctx.showiv = 0;
 570         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 571
 572         /* Enable Flexible Descriptors in the queue context which
 573          * allows this driver to select a specific receive descriptor format
 574          */
 575         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 576                 QRXFLXP_CNTXT_RXDID_IDX_M;
 577
 578         /* increasing context priority to pick up profile ID;
 579          * default is 0x01; setting to 0x03 to ensure profile
 580          * is programming if prev context is of same priority
 581          */
 582         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 583                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 584
 585         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 586
 587         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 588         if (err) {
 589                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 590                             rxq->queue_id);
 591                 return -EINVAL;
 592         }
 593         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 594         if (err) {
 595                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 596                             rxq->queue_id);
 597                 return -EINVAL;
 598         }
 599
 600         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 601
 602         /* Init the Rx tail register*/
 603         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 604
 605         return 0;
 606 }
 607
 608 int
 609 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 610 {
 611         struct ice_rx_queue *rxq;
 612         int err;
 613         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 614         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 615
 616         PMD_INIT_FUNC_TRACE();
 617
 618         rxq = pf->fdir.rxq;
 619         if (!rxq || !rxq->q_set) {
 620                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 621                             rx_queue_id);
 622                 return -EINVAL;
 623         }
 624
 625         err = ice_fdir_program_hw_rx_queue(rxq);
 626         if (err) {
 627                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 628                             rx_queue_id);
 629                 return -EIO;
 630         }
 631
 632         /* Init the RX tail register. */
 633         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 634
 635         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 636         if (err) {
 637                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 638                             rx_queue_id);
 639
 640                 ice_reset_rx_queue(rxq);
 641                 return -EINVAL;
 642         }
 643
 644         return 0;
 645 }
 646
 647 int
 648 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 649 {
 650         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 651         struct ice_tx_queue *txq;
 652         int err;
 653         struct ice_vsi *vsi;
 654         struct ice_hw *hw;
 655         struct ice_aqc_add_tx_qgrp *txq_elem;
 656         struct ice_tlan_ctx tx_ctx;
 657         int buf_len;
 658
 659         PMD_INIT_FUNC_TRACE();
 660
 661         txq = pf->fdir.txq;
 662         if (!txq || !txq->q_set) {
 663                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 664                             tx_queue_id);
 665                 return -EINVAL;
 666         }
 667
 668         buf_len = ice_struct_size(txq_elem, txqs, 1);
 669         txq_elem = ice_malloc(hw, buf_len);
 670         if (!txq_elem)
 671                 return -ENOMEM;
 672
 673         vsi = txq->vsi;
 674         hw = ICE_VSI_TO_HW(vsi);
 675
 676         memset(&tx_ctx, 0, sizeof(tx_ctx));
 677         txq_elem->num_txqs = 1;
 678         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 679
 680         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 681         tx_ctx.qlen = txq->nb_tx_desc;
 682         tx_ctx.pf_num = hw->pf_id;
 683         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 684         tx_ctx.src_vsi = vsi->vsi_id;
 685         tx_ctx.port_num = hw->port_info->lport;
 686         tx_ctx.tso_ena = 1; /* tso enable */
 687         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 688         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 689
 690         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 691                     ice_tlan_ctx_info);
 692
 693         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 694
 695         /* Init the Tx tail register*/
 696         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 697
 698         /* Fix me, we assume TC always 0 here */
 699         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 700                               txq_elem, buf_len, NULL);
 701         if (err) {
 702                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 703                 rte_free(txq_elem);
 704                 return -EIO;
 705         }
 706         /* store the schedule node id */
 707         txq->q_teid = txq_elem->txqs[0].q_teid;
 708
 709         rte_free(txq_elem);
 710         return 0;
 711 }
 712
 713 /* Free all mbufs for descriptors in tx queue */
 714 static void
 715 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 716 {
 717         uint16_t i;
 718
 719         if (!txq || !txq->sw_ring) {
 720                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 721                 return;
 722         }
 723
 724         for (i = 0; i < txq->nb_tx_desc; i++) {
 725                 if (txq->sw_ring[i].mbuf) {
 726                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 727                         txq->sw_ring[i].mbuf = NULL;
 728                 }
 729         }
 730 }
 731
 732 static void
 733 ice_reset_tx_queue(struct ice_tx_queue *txq)
 734 {
 735         struct ice_tx_entry *txe;
 736         uint16_t i, prev, size;
 737
 738         if (!txq) {
 739                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 740                 return;
 741         }
 742
 743         txe = txq->sw_ring;
 744         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 745         for (i = 0; i < size; i++)
 746                 ((volatile char *)txq->tx_ring)[i] = 0;
 747
 748         prev = (uint16_t)(txq->nb_tx_desc - 1);
 749         for (i = 0; i < txq->nb_tx_desc; i++) {
 750                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 751
 752                 txd->cmd_type_offset_bsz =
 753                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 754                 txe[i].mbuf =  NULL;
 755                 txe[i].last_id = i;
 756                 txe[prev].next_id = i;
 757                 prev = i;
 758         }
 759
 760         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 761         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 762
 763         txq->tx_tail = 0;
 764         txq->nb_tx_used = 0;
 765
 766         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 767         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 768 }
 769
 770 int
 771 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 772 {
 773         struct ice_tx_queue *txq;
 774         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 775         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 776         struct ice_vsi *vsi = pf->main_vsi;
 777         enum ice_status status;
 778         uint16_t q_ids[1];
 779         uint32_t q_teids[1];
 780         uint16_t q_handle = tx_queue_id;
 781
 782         if (tx_queue_id >= dev->data->nb_tx_queues) {
 783                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 784                             tx_queue_id, dev->data->nb_tx_queues);
 785                 return -EINVAL;
 786         }
 787
 788         txq = dev->data->tx_queues[tx_queue_id];
 789         if (!txq) {
 790                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 791                             tx_queue_id);
 792                 return -EINVAL;
 793         }
 794
 795         q_ids[0] = txq->reg_idx;
 796         q_teids[0] = txq->q_teid;
 797
 798         /* Fix me, we assume TC always 0 here */
 799         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 800                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 801         if (status != ICE_SUCCESS) {
 802                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 803                 return -EINVAL;
 804         }
 805
 806         txq->tx_rel_mbufs(txq);
 807         ice_reset_tx_queue(txq);
 808         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 809
 810         return 0;
 811 }
 812
 813 int
 814 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 815 {
 816         struct ice_rx_queue *rxq;
 817         int err;
 818         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 819         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 820
 821         rxq = pf->fdir.rxq;
 822
 823         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 824         if (err) {
 825                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
 826                             rx_queue_id);
 827                 return -EINVAL;
 828         }
 829         rxq->rx_rel_mbufs(rxq);
 830
 831         return 0;
 832 }
 833
 834 int
 835 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 836 {
 837         struct ice_tx_queue *txq;
 838         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 839         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 840         struct ice_vsi *vsi = pf->main_vsi;
 841         enum ice_status status;
 842         uint16_t q_ids[1];
 843         uint32_t q_teids[1];
 844         uint16_t q_handle = tx_queue_id;
 845
 846         txq = pf->fdir.txq;
 847         if (!txq) {
 848                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 849                             tx_queue_id);
 850                 return -EINVAL;
 851         }
 852         vsi = txq->vsi;
 853
 854         q_ids[0] = txq->reg_idx;
 855         q_teids[0] = txq->q_teid;
 856
 857         /* Fix me, we assume TC always 0 here */
 858         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 859                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 860         if (status != ICE_SUCCESS) {
 861                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 862                 return -EINVAL;
 863         }
 864
 865         txq->tx_rel_mbufs(txq);
 866
 867         return 0;
 868 }
 869
 870 int
 871 ice_rx_queue_setup(struct rte_eth_dev *dev,
 872                    uint16_t queue_idx,
 873                    uint16_t nb_desc,
 874                    unsigned int socket_id,
 875                    const struct rte_eth_rxconf *rx_conf,
 876                    struct rte_mempool *mp)
 877 {
 878         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 879         struct ice_adapter *ad =
 880                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 881         struct ice_vsi *vsi = pf->main_vsi;
 882         struct ice_rx_queue *rxq;
 883         const struct rte_memzone *rz;
 884         uint32_t ring_size;
 885         uint16_t len;
 886         int use_def_burst_func = 1;
 887
 888         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
 889             nb_desc > ICE_MAX_RING_DESC ||
 890             nb_desc < ICE_MIN_RING_DESC) {
 891                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 892                              "invalid", nb_desc);
 893                 return -EINVAL;
 894         }
 895
 896         /* Free memory if needed */
 897         if (dev->data->rx_queues[queue_idx]) {
 898                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
 899                 dev->data->rx_queues[queue_idx] = NULL;
 900         }
 901
 902         /* Allocate the rx queue data structure */
 903         rxq = rte_zmalloc_socket(NULL,
 904                                  sizeof(struct ice_rx_queue),
 905                                  RTE_CACHE_LINE_SIZE,
 906                                  socket_id);
 907         if (!rxq) {
 908                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 909                              "rx queue data structure");
 910                 return -ENOMEM;
 911         }
 912         rxq->mp = mp;
 913         rxq->nb_rx_desc = nb_desc;
 914         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
 915         rxq->queue_id = queue_idx;
 916
 917         rxq->reg_idx = vsi->base_queue + queue_idx;
 918         rxq->port_id = dev->data->port_id;
 919         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
 920                 rxq->crc_len = RTE_ETHER_CRC_LEN;
 921         else
 922                 rxq->crc_len = 0;
 923
 924         rxq->drop_en = rx_conf->rx_drop_en;
 925         rxq->vsi = vsi;
 926         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 927         rxq->proto_xtr = pf->proto_xtr != NULL ?
 928                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
 929
 930         /* Allocate the maximun number of RX ring hardware descriptor. */
 931         len = ICE_MAX_RING_DESC;
 932
 933         /**
 934          * Allocating a little more memory because vectorized/bulk_alloc Rx
 935          * functions doesn't check boundaries each time.
 936          */
 937         len += ICE_RX_MAX_BURST;
 938
 939         /* Allocate the maximum number of RX ring hardware descriptor. */
 940         ring_size = sizeof(union ice_rx_flex_desc) * len;
 941         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
 942         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 943                                       ring_size, ICE_RING_BASE_ALIGN,
 944                                       socket_id);
 945         if (!rz) {
 946                 ice_rx_queue_release(rxq);
 947                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 948                 return -ENOMEM;
 949         }
 950
 951         /* Zero all the descriptors in the ring. */
 952         memset(rz->addr, 0, ring_size);
 953
 954         rxq->rx_ring_dma = rz->iova;
 955         rxq->rx_ring = rz->addr;
 956
 957         /* always reserve more for bulk alloc */
 958         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
 959
 960         /* Allocate the software ring. */
 961         rxq->sw_ring = rte_zmalloc_socket(NULL,
 962                                           sizeof(struct ice_rx_entry) * len,
 963                                           RTE_CACHE_LINE_SIZE,
 964                                           socket_id);
 965         if (!rxq->sw_ring) {
 966                 ice_rx_queue_release(rxq);
 967                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 968                 return -ENOMEM;
 969         }
 970
 971         ice_reset_rx_queue(rxq);
 972         rxq->q_set = true;
 973         dev->data->rx_queues[queue_idx] = rxq;
 974         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
 975
 976         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
 977
 978         if (!use_def_burst_func) {
 979                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 980                              "satisfied. Rx Burst Bulk Alloc function will be "
 981                              "used on port=%d, queue=%d.",
 982                              rxq->port_id, rxq->queue_id);
 983         } else {
 984                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 985                              "not satisfied, Scattered Rx is requested. "
 986                              "on port=%d, queue=%d.",
 987                              rxq->port_id, rxq->queue_id);
 988                 ad->rx_bulk_alloc_allowed = false;
 989         }
 990
 991         return 0;
 992 }
 993
 994 void
 995 ice_rx_queue_release(void *rxq)
 996 {
 997         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
 998
 999         if (!q) {
1000                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1001                 return;
1002         }
1003
1004         q->rx_rel_mbufs(q);
1005         rte_free(q->sw_ring);
1006         rte_free(q);
1007 }
1008
1009 int
1010 ice_tx_queue_setup(struct rte_eth_dev *dev,
1011                    uint16_t queue_idx,
1012                    uint16_t nb_desc,
1013                    unsigned int socket_id,
1014                    const struct rte_eth_txconf *tx_conf)
1015 {
1016         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1017         struct ice_vsi *vsi = pf->main_vsi;
1018         struct ice_tx_queue *txq;
1019         const struct rte_memzone *tz;
1020         uint32_t ring_size;
1021         uint16_t tx_rs_thresh, tx_free_thresh;
1022         uint64_t offloads;
1023
1024         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1025
1026         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1027             nb_desc > ICE_MAX_RING_DESC ||
1028             nb_desc < ICE_MIN_RING_DESC) {
1029                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1030                              "invalid", nb_desc);
1031                 return -EINVAL;
1032         }
1033
1034         /**
1035          * The following two parameters control the setting of the RS bit on
1036          * transmit descriptors. TX descriptors will have their RS bit set
1037          * after txq->tx_rs_thresh descriptors have been used. The TX
1038          * descriptor ring will be cleaned after txq->tx_free_thresh
1039          * descriptors are used or if the number of descriptors required to
1040          * transmit a packet is greater than the number of free TX descriptors.
1041          *
1042          * The following constraints must be satisfied:
1043          *  - tx_rs_thresh must be greater than 0.
1044          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1045          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1046          *  - tx_rs_thresh must be a divisor of the ring size.
1047          *  - tx_free_thresh must be greater than 0.
1048          *  - tx_free_thresh must be less than the size of the ring minus 3.
1049          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1050          *
1051          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1052          * race condition, hence the maximum threshold constraints. When set
1053          * to zero use default values.
1054          */
1055         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1056                                     tx_conf->tx_free_thresh :
1057                                     ICE_DEFAULT_TX_FREE_THRESH);
1058         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1059         tx_rs_thresh =
1060                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1061                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1062         if (tx_conf->tx_rs_thresh)
1063                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1064         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1065                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1066                                 "exceed nb_desc. (tx_rs_thresh=%u "
1067                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1068                                 (unsigned int)tx_rs_thresh,
1069                                 (unsigned int)tx_free_thresh,
1070                                 (unsigned int)nb_desc,
1071                                 (int)dev->data->port_id,
1072                                 (int)queue_idx);
1073                 return -EINVAL;
1074         }
1075         if (tx_rs_thresh >= (nb_desc - 2)) {
1076                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1077                              "number of TX descriptors minus 2. "
1078                              "(tx_rs_thresh=%u port=%d queue=%d)",
1079                              (unsigned int)tx_rs_thresh,
1080                              (int)dev->data->port_id,
1081                              (int)queue_idx);
1082                 return -EINVAL;
1083         }
1084         if (tx_free_thresh >= (nb_desc - 3)) {
1085                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1086                              "tx_free_thresh must be less than the "
1087                              "number of TX descriptors minus 3. "
1088                              "(tx_free_thresh=%u port=%d queue=%d)",
1089                              (unsigned int)tx_free_thresh,
1090                              (int)dev->data->port_id,
1091                              (int)queue_idx);
1092                 return -EINVAL;
1093         }
1094         if (tx_rs_thresh > tx_free_thresh) {
1095                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1096                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1097                              " tx_rs_thresh=%u port=%d queue=%d)",
1098                              (unsigned int)tx_free_thresh,
1099                              (unsigned int)tx_rs_thresh,
1100                              (int)dev->data->port_id,
1101                              (int)queue_idx);
1102                 return -EINVAL;
1103         }
1104         if ((nb_desc % tx_rs_thresh) != 0) {
1105                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1106                              "number of TX descriptors. (tx_rs_thresh=%u"
1107                              " port=%d queue=%d)",
1108                              (unsigned int)tx_rs_thresh,
1109                              (int)dev->data->port_id,
1110                              (int)queue_idx);
1111                 return -EINVAL;
1112         }
1113         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1114                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1115                              "tx_rs_thresh is greater than 1. "
1116                              "(tx_rs_thresh=%u port=%d queue=%d)",
1117                              (unsigned int)tx_rs_thresh,
1118                              (int)dev->data->port_id,
1119                              (int)queue_idx);
1120                 return -EINVAL;
1121         }
1122
1123         /* Free memory if needed. */
1124         if (dev->data->tx_queues[queue_idx]) {
1125                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1126                 dev->data->tx_queues[queue_idx] = NULL;
1127         }
1128
1129         /* Allocate the TX queue data structure. */
1130         txq = rte_zmalloc_socket(NULL,
1131                                  sizeof(struct ice_tx_queue),
1132                                  RTE_CACHE_LINE_SIZE,
1133                                  socket_id);
1134         if (!txq) {
1135                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1136                              "tx queue structure");
1137                 return -ENOMEM;
1138         }
1139
1140         /* Allocate TX hardware ring descriptors. */
1141         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1142         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1143         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1144                                       ring_size, ICE_RING_BASE_ALIGN,
1145                                       socket_id);
1146         if (!tz) {
1147                 ice_tx_queue_release(txq);
1148                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1149                 return -ENOMEM;
1150         }
1151
1152         txq->nb_tx_desc = nb_desc;
1153         txq->tx_rs_thresh = tx_rs_thresh;
1154         txq->tx_free_thresh = tx_free_thresh;
1155         txq->pthresh = tx_conf->tx_thresh.pthresh;
1156         txq->hthresh = tx_conf->tx_thresh.hthresh;
1157         txq->wthresh = tx_conf->tx_thresh.wthresh;
1158         txq->queue_id = queue_idx;
1159
1160         txq->reg_idx = vsi->base_queue + queue_idx;
1161         txq->port_id = dev->data->port_id;
1162         txq->offloads = offloads;
1163         txq->vsi = vsi;
1164         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1165
1166         txq->tx_ring_dma = tz->iova;
1167         txq->tx_ring = tz->addr;
1168
1169         /* Allocate software ring */
1170         txq->sw_ring =
1171                 rte_zmalloc_socket(NULL,
1172                                    sizeof(struct ice_tx_entry) * nb_desc,
1173                                    RTE_CACHE_LINE_SIZE,
1174                                    socket_id);
1175         if (!txq->sw_ring) {
1176                 ice_tx_queue_release(txq);
1177                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1178                 return -ENOMEM;
1179         }
1180
1181         ice_reset_tx_queue(txq);
1182         txq->q_set = true;
1183         dev->data->tx_queues[queue_idx] = txq;
1184         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1185         ice_set_tx_function_flag(dev, txq);
1186
1187         return 0;
1188 }
1189
1190 void
1191 ice_tx_queue_release(void *txq)
1192 {
1193         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1194
1195         if (!q) {
1196                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1197                 return;
1198         }
1199
1200         q->tx_rel_mbufs(q);
1201         rte_free(q->sw_ring);
1202         rte_free(q);
1203 }
1204
1205 void
1206 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1207                  struct rte_eth_rxq_info *qinfo)
1208 {
1209         struct ice_rx_queue *rxq;
1210
1211         rxq = dev->data->rx_queues[queue_id];
1212
1213         qinfo->mp = rxq->mp;
1214         qinfo->scattered_rx = dev->data->scattered_rx;
1215         qinfo->nb_desc = rxq->nb_rx_desc;
1216
1217         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1218         qinfo->conf.rx_drop_en = rxq->drop_en;
1219         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1220 }
1221
1222 void
1223 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1224                  struct rte_eth_txq_info *qinfo)
1225 {
1226         struct ice_tx_queue *txq;
1227
1228         txq = dev->data->tx_queues[queue_id];
1229
1230         qinfo->nb_desc = txq->nb_tx_desc;
1231
1232         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1233         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1234         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1235
1236         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1237         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1238         qinfo->conf.offloads = txq->offloads;
1239         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1240 }
1241
1242 uint32_t
1243 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1244 {
1245 #define ICE_RXQ_SCAN_INTERVAL 4
1246         volatile union ice_rx_flex_desc *rxdp;
1247         struct ice_rx_queue *rxq;
1248         uint16_t desc = 0;
1249
1250         rxq = dev->data->rx_queues[rx_queue_id];
1251         rxdp = &rxq->rx_ring[rxq->rx_tail];
1252         while ((desc < rxq->nb_rx_desc) &&
1253                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1254                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1255                 /**
1256                  * Check the DD bit of a rx descriptor of each 4 in a group,
1257                  * to avoid checking too frequently and downgrading performance
1258                  * too much.
1259                  */
1260                 desc += ICE_RXQ_SCAN_INTERVAL;
1261                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1262                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1263                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1264                                  desc - rxq->nb_rx_desc]);
1265         }
1266
1267         return desc;
1268 }
1269
1270 #define ICE_RX_FLEX_ERR0_BITS   \
1271         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1272          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1273          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1274          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1275          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1276          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1277
1278 /* Rx L3/L4 checksum */
1279 static inline uint64_t
1280 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1281 {
1282         uint64_t flags = 0;
1283
1284         /* check if HW has decoded the packet and checksum */
1285         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1286                 return 0;
1287
1288         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1289                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1290                 return flags;
1291         }
1292
1293         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1294                 flags |= PKT_RX_IP_CKSUM_BAD;
1295         else
1296                 flags |= PKT_RX_IP_CKSUM_GOOD;
1297
1298         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1299                 flags |= PKT_RX_L4_CKSUM_BAD;
1300         else
1301                 flags |= PKT_RX_L4_CKSUM_GOOD;
1302
1303         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1304                 flags |= PKT_RX_EIP_CKSUM_BAD;
1305
1306         return flags;
1307 }
1308
1309 static inline void
1310 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1311 {
1312         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1313             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1314                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1315                 mb->vlan_tci =
1316                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1317                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1318                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1319         } else {
1320                 mb->vlan_tci = 0;
1321         }
1322
1323 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1324         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1325             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1326                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1327                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1328                 mb->vlan_tci_outer = mb->vlan_tci;
1329                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1330                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1331                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1332                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1333         } else {
1334                 mb->vlan_tci_outer = 0;
1335         }
1336 #endif
1337         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1338                    mb->vlan_tci, mb->vlan_tci_outer);
1339 }
1340
1341 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1342 #define ICE_RX_PROTO_XTR_VALID \
1343         ((1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S) | \
1344          (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1345
1346 static void
1347 ice_rxd_to_proto_xtr(struct rte_mbuf *mb,
1348                      volatile struct ice_32b_rx_flex_desc_comms_ovs *desc)
1349 {
1350         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error1);
1351         uint32_t metadata = 0;
1352         uint64_t ol_flag;
1353         bool chk_valid;
1354
1355         ol_flag = ice_rxdid_to_proto_xtr_ol_flag(desc->rxdid, &chk_valid);
1356         if (unlikely(!ol_flag))
1357                 return;
1358
1359         if (chk_valid) {
1360                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
1361                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
1362
1363                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
1364                         metadata |=
1365                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
1366         } else {
1367                 if (rte_le_to_cpu_16(desc->flex_ts.flex.aux0) != 0xFFFF)
1368                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
1369                 else if (rte_le_to_cpu_16(desc->flex_ts.flex.aux1) != 0xFFFF)
1370                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
1371         }
1372
1373         if (!metadata)
1374                 return;
1375
1376         mb->ol_flags |= ol_flag;
1377
1378         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
1379 }
1380 #endif
1381
1382 static inline void
1383 ice_rxd_to_pkt_fields(struct rte_mbuf *mb,
1384                       volatile union ice_rx_flex_desc *rxdp)
1385 {
1386         volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
1387                         (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
1388 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1389         uint16_t stat_err;
1390
1391         stat_err = rte_le_to_cpu_16(desc->status_error0);
1392         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
1393                 mb->ol_flags |= PKT_RX_RSS_HASH;
1394                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
1395         }
1396 #endif
1397
1398         if (desc->flow_id != 0xFFFFFFFF) {
1399                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1400                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
1401         }
1402
1403 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1404         if (unlikely(rte_net_ice_dynf_proto_xtr_metadata_avail()))
1405                 ice_rxd_to_proto_xtr(mb, desc);
1406 #endif
1407 }
1408
1409 #define ICE_LOOK_AHEAD 8
1410 #if (ICE_LOOK_AHEAD != 8)
1411 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1412 #endif
1413 static inline int
1414 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1415 {
1416         volatile union ice_rx_flex_desc *rxdp;
1417         struct ice_rx_entry *rxep;
1418         struct rte_mbuf *mb;
1419         uint16_t stat_err0;
1420         uint16_t pkt_len;
1421         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1422         int32_t i, j, nb_rx = 0;
1423         uint64_t pkt_flags = 0;
1424         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1425
1426         rxdp = &rxq->rx_ring[rxq->rx_tail];
1427         rxep = &rxq->sw_ring[rxq->rx_tail];
1428
1429         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1430
1431         /* Make sure there is at least 1 packet to receive */
1432         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1433                 return 0;
1434
1435         /**
1436          * Scan LOOK_AHEAD descriptors at a time to determine which
1437          * descriptors reference packets that are ready to be received.
1438          */
1439         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1440              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1441                 /* Read desc statuses backwards to avoid race condition */
1442                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1443                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1444
1445                 rte_smp_rmb();
1446
1447                 /* Compute how many status bits were set */
1448                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1449                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1450
1451                 nb_rx += nb_dd;
1452
1453                 /* Translate descriptor info to mbuf parameters */
1454                 for (j = 0; j < nb_dd; j++) {
1455                         mb = rxep[j].mbuf;
1456                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1457                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1458                         mb->data_len = pkt_len;
1459                         mb->pkt_len = pkt_len;
1460                         mb->ol_flags = 0;
1461                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1462                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1463                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1464                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1465                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1466                         ice_rxd_to_pkt_fields(mb, &rxdp[j]);
1467
1468                         mb->ol_flags |= pkt_flags;
1469                 }
1470
1471                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1472                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1473
1474                 if (nb_dd != ICE_LOOK_AHEAD)
1475                         break;
1476         }
1477
1478         /* Clear software ring entries */
1479         for (i = 0; i < nb_rx; i++)
1480                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1481
1482         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1483                    "port_id=%u, queue_id=%u, nb_rx=%d",
1484                    rxq->port_id, rxq->queue_id, nb_rx);
1485
1486         return nb_rx;
1487 }
1488
1489 static inline uint16_t
1490 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1491                        struct rte_mbuf **rx_pkts,
1492                        uint16_t nb_pkts)
1493 {
1494         uint16_t i;
1495         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1496
1497         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1498
1499         for (i = 0; i < nb_pkts; i++)
1500                 rx_pkts[i] = stage[i];
1501
1502         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1503         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1504
1505         return nb_pkts;
1506 }
1507
1508 static inline int
1509 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1510 {
1511         volatile union ice_rx_flex_desc *rxdp;
1512         struct ice_rx_entry *rxep;
1513         struct rte_mbuf *mb;
1514         uint16_t alloc_idx, i;
1515         uint64_t dma_addr;
1516         int diag;
1517
1518         /* Allocate buffers in bulk */
1519         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1520                                (rxq->rx_free_thresh - 1));
1521         rxep = &rxq->sw_ring[alloc_idx];
1522         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1523                                     rxq->rx_free_thresh);
1524         if (unlikely(diag != 0)) {
1525                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1526                 return -ENOMEM;
1527         }
1528
1529         rxdp = &rxq->rx_ring[alloc_idx];
1530         for (i = 0; i < rxq->rx_free_thresh; i++) {
1531                 if (likely(i < (rxq->rx_free_thresh - 1)))
1532                         /* Prefetch next mbuf */
1533                         rte_prefetch0(rxep[i + 1].mbuf);
1534
1535                 mb = rxep[i].mbuf;
1536                 rte_mbuf_refcnt_set(mb, 1);
1537                 mb->next = NULL;
1538                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1539                 mb->nb_segs = 1;
1540                 mb->port = rxq->port_id;
1541                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1542                 rxdp[i].read.hdr_addr = 0;
1543                 rxdp[i].read.pkt_addr = dma_addr;
1544         }
1545
1546         /* Update rx tail regsiter */
1547         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1548
1549         rxq->rx_free_trigger =
1550                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1551         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1552                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1553
1554         return 0;
1555 }
1556
1557 static inline uint16_t
1558 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1559 {
1560         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1561         uint16_t nb_rx = 0;
1562         struct rte_eth_dev *dev;
1563
1564         if (!nb_pkts)
1565                 return 0;
1566
1567         if (rxq->rx_nb_avail)
1568                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1569
1570         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1571         rxq->rx_next_avail = 0;
1572         rxq->rx_nb_avail = nb_rx;
1573         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1574
1575         if (rxq->rx_tail > rxq->rx_free_trigger) {
1576                 if (ice_rx_alloc_bufs(rxq) != 0) {
1577                         uint16_t i, j;
1578
1579                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1580                         dev->data->rx_mbuf_alloc_failed +=
1581                                 rxq->rx_free_thresh;
1582                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1583                                    "port_id=%u, queue_id=%u",
1584                                    rxq->port_id, rxq->queue_id);
1585                         rxq->rx_nb_avail = 0;
1586                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1587                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1588                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1589
1590                         return 0;
1591                 }
1592         }
1593
1594         if (rxq->rx_tail >= rxq->nb_rx_desc)
1595                 rxq->rx_tail = 0;
1596
1597         if (rxq->rx_nb_avail)
1598                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1599
1600         return 0;
1601 }
1602
1603 static uint16_t
1604 ice_recv_pkts_bulk_alloc(void *rx_queue,
1605                          struct rte_mbuf **rx_pkts,
1606                          uint16_t nb_pkts)
1607 {
1608         uint16_t nb_rx = 0;
1609         uint16_t n;
1610         uint16_t count;
1611
1612         if (unlikely(nb_pkts == 0))
1613                 return nb_rx;
1614
1615         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1616                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1617
1618         while (nb_pkts) {
1619                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1620                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1621                 nb_rx = (uint16_t)(nb_rx + count);
1622                 nb_pkts = (uint16_t)(nb_pkts - count);
1623                 if (count < n)
1624                         break;
1625         }
1626
1627         return nb_rx;
1628 }
1629
1630 static uint16_t
1631 ice_recv_scattered_pkts(void *rx_queue,
1632                         struct rte_mbuf **rx_pkts,
1633                         uint16_t nb_pkts)
1634 {
1635         struct ice_rx_queue *rxq = rx_queue;
1636         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1637         volatile union ice_rx_flex_desc *rxdp;
1638         union ice_rx_flex_desc rxd;
1639         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1640         struct ice_rx_entry *rxe;
1641         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1642         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1643         struct rte_mbuf *nmb; /* new allocated mbuf */
1644         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1645         uint16_t rx_id = rxq->rx_tail;
1646         uint16_t nb_rx = 0;
1647         uint16_t nb_hold = 0;
1648         uint16_t rx_packet_len;
1649         uint16_t rx_stat_err0;
1650         uint64_t dma_addr;
1651         uint64_t pkt_flags;
1652         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1653         struct rte_eth_dev *dev;
1654
1655         while (nb_rx < nb_pkts) {
1656                 rxdp = &rx_ring[rx_id];
1657                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1658
1659                 /* Check the DD bit first */
1660                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1661                         break;
1662
1663                 /* allocate mbuf */
1664                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1665                 if (unlikely(!nmb)) {
1666                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
1667                         dev->data->rx_mbuf_alloc_failed++;
1668                         break;
1669                 }
1670                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1671
1672                 nb_hold++;
1673                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1674                 rx_id++;
1675                 if (unlikely(rx_id == rxq->nb_rx_desc))
1676                         rx_id = 0;
1677
1678                 /* Prefetch next mbuf */
1679                 rte_prefetch0(sw_ring[rx_id].mbuf);
1680
1681                 /**
1682                  * When next RX descriptor is on a cache line boundary,
1683                  * prefetch the next 4 RX descriptors and next 8 pointers
1684                  * to mbufs.
1685                  */
1686                 if ((rx_id & 0x3) == 0) {
1687                         rte_prefetch0(&rx_ring[rx_id]);
1688                         rte_prefetch0(&sw_ring[rx_id]);
1689                 }
1690
1691                 rxm = rxe->mbuf;
1692                 rxe->mbuf = nmb;
1693                 dma_addr =
1694                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1695
1696                 /* Set data buffer address and data length of the mbuf */
1697                 rxdp->read.hdr_addr = 0;
1698                 rxdp->read.pkt_addr = dma_addr;
1699                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1700                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1701                 rxm->data_len = rx_packet_len;
1702                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1703
1704                 /**
1705                  * If this is the first buffer of the received packet, set the
1706                  * pointer to the first mbuf of the packet and initialize its
1707                  * context. Otherwise, update the total length and the number
1708                  * of segments of the current scattered packet, and update the
1709                  * pointer to the last mbuf of the current packet.
1710                  */
1711                 if (!first_seg) {
1712                         first_seg = rxm;
1713                         first_seg->nb_segs = 1;
1714                         first_seg->pkt_len = rx_packet_len;
1715                 } else {
1716                         first_seg->pkt_len =
1717                                 (uint16_t)(first_seg->pkt_len +
1718                                            rx_packet_len);
1719                         first_seg->nb_segs++;
1720                         last_seg->next = rxm;
1721                 }
1722
1723                 /**
1724                  * If this is not the last buffer of the received packet,
1725                  * update the pointer to the last mbuf of the current scattered
1726                  * packet and continue to parse the RX ring.
1727                  */
1728                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1729                         last_seg = rxm;
1730                         continue;
1731                 }
1732
1733                 /**
1734                  * This is the last buffer of the received packet. If the CRC
1735                  * is not stripped by the hardware:
1736                  *  - Subtract the CRC length from the total packet length.
1737                  *  - If the last buffer only contains the whole CRC or a part
1738                  *  of it, free the mbuf associated to the last buffer. If part
1739                  *  of the CRC is also contained in the previous mbuf, subtract
1740                  *  the length of that CRC part from the data length of the
1741                  *  previous mbuf.
1742                  */
1743                 rxm->next = NULL;
1744                 if (unlikely(rxq->crc_len > 0)) {
1745                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1746                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1747                                 rte_pktmbuf_free_seg(rxm);
1748                                 first_seg->nb_segs--;
1749                                 last_seg->data_len =
1750                                         (uint16_t)(last_seg->data_len -
1751                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1752                                 last_seg->next = NULL;
1753                         } else
1754                                 rxm->data_len = (uint16_t)(rx_packet_len -
1755                                                            RTE_ETHER_CRC_LEN);
1756                 }
1757
1758                 first_seg->port = rxq->port_id;
1759                 first_seg->ol_flags = 0;
1760                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1761                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1762                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1763                 ice_rxd_to_pkt_fields(first_seg, &rxd);
1764                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1765                 first_seg->ol_flags |= pkt_flags;
1766                 /* Prefetch data of first segment, if configured to do so. */
1767                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1768                                           first_seg->data_off));
1769                 rx_pkts[nb_rx++] = first_seg;
1770                 first_seg = NULL;
1771         }
1772
1773         /* Record index of the next RX descriptor to probe. */
1774         rxq->rx_tail = rx_id;
1775         rxq->pkt_first_seg = first_seg;
1776         rxq->pkt_last_seg = last_seg;
1777
1778         /**
1779          * If the number of free RX descriptors is greater than the RX free
1780          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1781          * register. Update the RDT with the value of the last processed RX
1782          * descriptor minus 1, to guarantee that the RDT register is never
1783          * equal to the RDH register, which creates a "full" ring situtation
1784          * from the hardware point of view.
1785          */
1786         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1787         if (nb_hold > rxq->rx_free_thresh) {
1788                 rx_id = (uint16_t)(rx_id == 0 ?
1789                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1790                 /* write TAIL register */
1791                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1792                 nb_hold = 0;
1793         }
1794         rxq->nb_rx_hold = nb_hold;
1795
1796         /* return received packet in the burst */
1797         return nb_rx;
1798 }
1799
1800 const uint32_t *
1801 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1802 {
1803         struct ice_adapter *ad =
1804                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1805         const uint32_t *ptypes;
1806
1807         static const uint32_t ptypes_os[] = {
1808                 /* refers to ice_get_default_pkt_type() */
1809                 RTE_PTYPE_L2_ETHER,
1810                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1811                 RTE_PTYPE_L2_ETHER_LLDP,
1812                 RTE_PTYPE_L2_ETHER_ARP,
1813                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1814                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1815                 RTE_PTYPE_L4_FRAG,
1816                 RTE_PTYPE_L4_ICMP,
1817                 RTE_PTYPE_L4_NONFRAG,
1818                 RTE_PTYPE_L4_SCTP,
1819                 RTE_PTYPE_L4_TCP,
1820                 RTE_PTYPE_L4_UDP,
1821                 RTE_PTYPE_TUNNEL_GRENAT,
1822                 RTE_PTYPE_TUNNEL_IP,
1823                 RTE_PTYPE_INNER_L2_ETHER,
1824                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1825                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1826                 RTE_PTYPE_INNER_L4_FRAG,
1827                 RTE_PTYPE_INNER_L4_ICMP,
1828                 RTE_PTYPE_INNER_L4_NONFRAG,
1829                 RTE_PTYPE_INNER_L4_SCTP,
1830                 RTE_PTYPE_INNER_L4_TCP,
1831                 RTE_PTYPE_INNER_L4_UDP,
1832                 RTE_PTYPE_UNKNOWN
1833         };
1834
1835         static const uint32_t ptypes_comms[] = {
1836                 /* refers to ice_get_default_pkt_type() */
1837                 RTE_PTYPE_L2_ETHER,
1838                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1839                 RTE_PTYPE_L2_ETHER_LLDP,
1840                 RTE_PTYPE_L2_ETHER_ARP,
1841                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1842                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1843                 RTE_PTYPE_L4_FRAG,
1844                 RTE_PTYPE_L4_ICMP,
1845                 RTE_PTYPE_L4_NONFRAG,
1846                 RTE_PTYPE_L4_SCTP,
1847                 RTE_PTYPE_L4_TCP,
1848                 RTE_PTYPE_L4_UDP,
1849                 RTE_PTYPE_TUNNEL_GRENAT,
1850                 RTE_PTYPE_TUNNEL_IP,
1851                 RTE_PTYPE_INNER_L2_ETHER,
1852                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1853                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1854                 RTE_PTYPE_INNER_L4_FRAG,
1855                 RTE_PTYPE_INNER_L4_ICMP,
1856                 RTE_PTYPE_INNER_L4_NONFRAG,
1857                 RTE_PTYPE_INNER_L4_SCTP,
1858                 RTE_PTYPE_INNER_L4_TCP,
1859                 RTE_PTYPE_INNER_L4_UDP,
1860                 RTE_PTYPE_TUNNEL_GTPC,
1861                 RTE_PTYPE_TUNNEL_GTPU,
1862                 RTE_PTYPE_L2_ETHER_PPPOE,
1863                 RTE_PTYPE_UNKNOWN
1864         };
1865
1866         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
1867                 ptypes = ptypes_comms;
1868         else
1869                 ptypes = ptypes_os;
1870
1871         if (dev->rx_pkt_burst == ice_recv_pkts ||
1872             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
1873             dev->rx_pkt_burst == ice_recv_scattered_pkts)
1874                 return ptypes;
1875
1876 #ifdef RTE_ARCH_X86
1877         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
1878             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
1879             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
1880             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2)
1881                 return ptypes;
1882 #endif
1883
1884         return NULL;
1885 }
1886
1887 int
1888 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
1889 {
1890         volatile union ice_rx_flex_desc *rxdp;
1891         struct ice_rx_queue *rxq = rx_queue;
1892         uint32_t desc;
1893
1894         if (unlikely(offset >= rxq->nb_rx_desc))
1895                 return -EINVAL;
1896
1897         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1898                 return RTE_ETH_RX_DESC_UNAVAIL;
1899
1900         desc = rxq->rx_tail + offset;
1901         if (desc >= rxq->nb_rx_desc)
1902                 desc -= rxq->nb_rx_desc;
1903
1904         rxdp = &rxq->rx_ring[desc];
1905         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1906             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
1907                 return RTE_ETH_RX_DESC_DONE;
1908
1909         return RTE_ETH_RX_DESC_AVAIL;
1910 }
1911
1912 int
1913 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
1914 {
1915         struct ice_tx_queue *txq = tx_queue;
1916         volatile uint64_t *status;
1917         uint64_t mask, expect;
1918         uint32_t desc;
1919
1920         if (unlikely(offset >= txq->nb_tx_desc))
1921                 return -EINVAL;
1922
1923         desc = txq->tx_tail + offset;
1924         /* go to next desc that has the RS bit */
1925         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1926                 txq->tx_rs_thresh;
1927         if (desc >= txq->nb_tx_desc) {
1928                 desc -= txq->nb_tx_desc;
1929                 if (desc >= txq->nb_tx_desc)
1930                         desc -= txq->nb_tx_desc;
1931         }
1932
1933         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1934         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
1935         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
1936                                   ICE_TXD_QW1_DTYPE_S);
1937         if ((*status & mask) == expect)
1938                 return RTE_ETH_TX_DESC_DONE;
1939
1940         return RTE_ETH_TX_DESC_FULL;
1941 }
1942
1943 void
1944 ice_free_queues(struct rte_eth_dev *dev)
1945 {
1946         uint16_t i;
1947
1948         PMD_INIT_FUNC_TRACE();
1949
1950         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1951                 if (!dev->data->rx_queues[i])
1952                         continue;
1953                 ice_rx_queue_release(dev->data->rx_queues[i]);
1954                 dev->data->rx_queues[i] = NULL;
1955                 rte_eth_dma_zone_free(dev, "rx_ring", i);
1956         }
1957         dev->data->nb_rx_queues = 0;
1958
1959         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1960                 if (!dev->data->tx_queues[i])
1961                         continue;
1962                 ice_tx_queue_release(dev->data->tx_queues[i]);
1963                 dev->data->tx_queues[i] = NULL;
1964                 rte_eth_dma_zone_free(dev, "tx_ring", i);
1965         }
1966         dev->data->nb_tx_queues = 0;
1967 }
1968
1969 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
1970 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
1971
1972 int
1973 ice_fdir_setup_tx_resources(struct ice_pf *pf)
1974 {
1975         struct ice_tx_queue *txq;
1976         const struct rte_memzone *tz = NULL;
1977         uint32_t ring_size;
1978         struct rte_eth_dev *dev;
1979
1980         if (!pf) {
1981                 PMD_DRV_LOG(ERR, "PF is not available");
1982                 return -EINVAL;
1983         }
1984
1985         dev = pf->adapter->eth_dev;
1986
1987         /* Allocate the TX queue data structure. */
1988         txq = rte_zmalloc_socket("ice fdir tx queue",
1989                                  sizeof(struct ice_tx_queue),
1990                                  RTE_CACHE_LINE_SIZE,
1991                                  SOCKET_ID_ANY);
1992         if (!txq) {
1993                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1994                             "tx queue structure.");
1995                 return -ENOMEM;
1996         }
1997
1998         /* Allocate TX hardware ring descriptors. */
1999         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2000         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2001
2002         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2003                                       ICE_FDIR_QUEUE_ID, ring_size,
2004                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2005         if (!tz) {
2006                 ice_tx_queue_release(txq);
2007                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2008                 return -ENOMEM;
2009         }
2010
2011         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2012         txq->queue_id = ICE_FDIR_QUEUE_ID;
2013         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2014         txq->vsi = pf->fdir.fdir_vsi;
2015
2016         txq->tx_ring_dma = tz->iova;
2017         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2018         /*
2019          * don't need to allocate software ring and reset for the fdir
2020          * program queue just set the queue has been configured.
2021          */
2022         txq->q_set = true;
2023         pf->fdir.txq = txq;
2024
2025         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2026
2027         return ICE_SUCCESS;
2028 }
2029
2030 int
2031 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2032 {
2033         struct ice_rx_queue *rxq;
2034         const struct rte_memzone *rz = NULL;
2035         uint32_t ring_size;
2036         struct rte_eth_dev *dev;
2037
2038         if (!pf) {
2039                 PMD_DRV_LOG(ERR, "PF is not available");
2040                 return -EINVAL;
2041         }
2042
2043         dev = pf->adapter->eth_dev;
2044
2045         /* Allocate the RX queue data structure. */
2046         rxq = rte_zmalloc_socket("ice fdir rx queue",
2047                                  sizeof(struct ice_rx_queue),
2048                                  RTE_CACHE_LINE_SIZE,
2049                                  SOCKET_ID_ANY);
2050         if (!rxq) {
2051                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2052                             "rx queue structure.");
2053                 return -ENOMEM;
2054         }
2055
2056         /* Allocate RX hardware ring descriptors. */
2057         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2058         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2059
2060         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2061                                       ICE_FDIR_QUEUE_ID, ring_size,
2062                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2063         if (!rz) {
2064                 ice_rx_queue_release(rxq);
2065                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2066                 return -ENOMEM;
2067         }
2068
2069         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2070         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2071         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2072         rxq->vsi = pf->fdir.fdir_vsi;
2073
2074         rxq->rx_ring_dma = rz->iova;
2075         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2076                sizeof(union ice_32byte_rx_desc));
2077         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2078
2079         /*
2080          * Don't need to allocate software ring and reset for the fdir
2081          * rx queue, just set the queue has been configured.
2082          */
2083         rxq->q_set = true;
2084         pf->fdir.rxq = rxq;
2085
2086         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2087
2088         return ICE_SUCCESS;
2089 }
2090
2091 uint16_t
2092 ice_recv_pkts(void *rx_queue,
2093               struct rte_mbuf **rx_pkts,
2094               uint16_t nb_pkts)
2095 {
2096         struct ice_rx_queue *rxq = rx_queue;
2097         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2098         volatile union ice_rx_flex_desc *rxdp;
2099         union ice_rx_flex_desc rxd;
2100         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2101         struct ice_rx_entry *rxe;
2102         struct rte_mbuf *nmb; /* new allocated mbuf */
2103         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2104         uint16_t rx_id = rxq->rx_tail;
2105         uint16_t nb_rx = 0;
2106         uint16_t nb_hold = 0;
2107         uint16_t rx_packet_len;
2108         uint16_t rx_stat_err0;
2109         uint64_t dma_addr;
2110         uint64_t pkt_flags;
2111         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2112         struct rte_eth_dev *dev;
2113
2114         while (nb_rx < nb_pkts) {
2115                 rxdp = &rx_ring[rx_id];
2116                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2117
2118                 /* Check the DD bit first */
2119                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2120                         break;
2121
2122                 /* allocate mbuf */
2123                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2124                 if (unlikely(!nmb)) {
2125                         dev = ICE_VSI_TO_ETH_DEV(rxq->vsi);
2126                         dev->data->rx_mbuf_alloc_failed++;
2127                         break;
2128                 }
2129                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2130
2131                 nb_hold++;
2132                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2133                 rx_id++;
2134                 if (unlikely(rx_id == rxq->nb_rx_desc))
2135                         rx_id = 0;
2136                 rxm = rxe->mbuf;
2137                 rxe->mbuf = nmb;
2138                 dma_addr =
2139                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2140
2141                 /**
2142                  * fill the read format of descriptor with physic address in
2143                  * new allocated mbuf: nmb
2144                  */
2145                 rxdp->read.hdr_addr = 0;
2146                 rxdp->read.pkt_addr = dma_addr;
2147
2148                 /* calculate rx_packet_len of the received pkt */
2149                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2150                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2151
2152                 /* fill old mbuf with received descriptor: rxd */
2153                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2154                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2155                 rxm->nb_segs = 1;
2156                 rxm->next = NULL;
2157                 rxm->pkt_len = rx_packet_len;
2158                 rxm->data_len = rx_packet_len;
2159                 rxm->port = rxq->port_id;
2160                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2161                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2162                 ice_rxd_to_vlan_tci(rxm, &rxd);
2163                 ice_rxd_to_pkt_fields(rxm, &rxd);
2164                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2165                 rxm->ol_flags |= pkt_flags;
2166                 /* copy old mbuf to rx_pkts */
2167                 rx_pkts[nb_rx++] = rxm;
2168         }
2169         rxq->rx_tail = rx_id;
2170         /**
2171          * If the number of free RX descriptors is greater than the RX free
2172          * threshold of the queue, advance the receive tail register of queue.
2173          * Update that register with the value of the last processed RX
2174          * descriptor minus 1.
2175          */
2176         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2177         if (nb_hold > rxq->rx_free_thresh) {
2178                 rx_id = (uint16_t)(rx_id == 0 ?
2179                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2180                 /* write TAIL register */
2181                 ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
2182                 nb_hold = 0;
2183         }
2184         rxq->nb_rx_hold = nb_hold;
2185
2186         /* return received packet in the burst */
2187         return nb_rx;
2188 }
2189
2190 static inline void
2191 ice_parse_tunneling_params(uint64_t ol_flags,
2192                             union ice_tx_offload tx_offload,
2193                             uint32_t *cd_tunneling)
2194 {
2195         /* EIPT: External (outer) IP header type */
2196         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2197                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2198         else if (ol_flags & PKT_TX_OUTER_IPV4)
2199                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2200         else if (ol_flags & PKT_TX_OUTER_IPV6)
2201                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2202
2203         /* EIPLEN: External (outer) IP header length, in DWords */
2204         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2205                 ICE_TXD_CTX_QW0_EIPLEN_S;
2206
2207         /* L4TUNT: L4 Tunneling Type */
2208         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2209         case PKT_TX_TUNNEL_IPIP:
2210                 /* for non UDP / GRE tunneling, set to 00b */
2211                 break;
2212         case PKT_TX_TUNNEL_VXLAN:
2213         case PKT_TX_TUNNEL_GTP:
2214         case PKT_TX_TUNNEL_GENEVE:
2215                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2216                 break;
2217         case PKT_TX_TUNNEL_GRE:
2218                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2219                 break;
2220         default:
2221                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2222                 return;
2223         }
2224
2225         /* L4TUNLEN: L4 Tunneling Length, in Words
2226          *
2227          * We depend on app to set rte_mbuf.l2_len correctly.
2228          * For IP in GRE it should be set to the length of the GRE
2229          * header;
2230          * For MAC in GRE or MAC in UDP it should be set to the length
2231          * of the GRE or UDP headers plus the inner MAC up to including
2232          * its last Ethertype.
2233          * If MPLS labels exists, it should include them as well.
2234          */
2235         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2236                 ICE_TXD_CTX_QW0_NATLEN_S;
2237
2238         if ((ol_flags & PKT_TX_OUTER_UDP_CKSUM) &&
2239             (ol_flags & PKT_TX_OUTER_IP_CKSUM) &&
2240             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2241                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2242 }
2243
2244 static inline void
2245 ice_txd_enable_checksum(uint64_t ol_flags,
2246                         uint32_t *td_cmd,
2247                         uint32_t *td_offset,
2248                         union ice_tx_offload tx_offload)
2249 {
2250         /* Set MACLEN */
2251         if (ol_flags & PKT_TX_TUNNEL_MASK)
2252                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2253                         << ICE_TX_DESC_LEN_MACLEN_S;
2254         else
2255                 *td_offset |= (tx_offload.l2_len >> 1)
2256                         << ICE_TX_DESC_LEN_MACLEN_S;
2257
2258         /* Enable L3 checksum offloads */
2259         if (ol_flags & PKT_TX_IP_CKSUM) {
2260                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2261                 *td_offset |= (tx_offload.l3_len >> 2) <<
2262                               ICE_TX_DESC_LEN_IPLEN_S;
2263         } else if (ol_flags & PKT_TX_IPV4) {
2264                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2265                 *td_offset |= (tx_offload.l3_len >> 2) <<
2266                               ICE_TX_DESC_LEN_IPLEN_S;
2267         } else if (ol_flags & PKT_TX_IPV6) {
2268                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2269                 *td_offset |= (tx_offload.l3_len >> 2) <<
2270                               ICE_TX_DESC_LEN_IPLEN_S;
2271         }
2272
2273         if (ol_flags & PKT_TX_TCP_SEG) {
2274                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2275                 *td_offset |= (tx_offload.l4_len >> 2) <<
2276                               ICE_TX_DESC_LEN_L4_LEN_S;
2277                 return;
2278         }
2279
2280         /* Enable L4 checksum offloads */
2281         switch (ol_flags & PKT_TX_L4_MASK) {
2282         case PKT_TX_TCP_CKSUM:
2283                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2284                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2285                               ICE_TX_DESC_LEN_L4_LEN_S;
2286                 break;
2287         case PKT_TX_SCTP_CKSUM:
2288                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2289                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2290                               ICE_TX_DESC_LEN_L4_LEN_S;
2291                 break;
2292         case PKT_TX_UDP_CKSUM:
2293                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2294                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2295                               ICE_TX_DESC_LEN_L4_LEN_S;
2296                 break;
2297         default:
2298                 break;
2299         }
2300 }
2301
2302 static inline int
2303 ice_xmit_cleanup(struct ice_tx_queue *txq)
2304 {
2305         struct ice_tx_entry *sw_ring = txq->sw_ring;
2306         volatile struct ice_tx_desc *txd = txq->tx_ring;
2307         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2308         uint16_t nb_tx_desc = txq->nb_tx_desc;
2309         uint16_t desc_to_clean_to;
2310         uint16_t nb_tx_to_clean;
2311
2312         /* Determine the last descriptor needing to be cleaned */
2313         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2314         if (desc_to_clean_to >= nb_tx_desc)
2315                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2316
2317         /* Check to make sure the last descriptor to clean is done */
2318         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2319         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2320             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2321                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
2322                                 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2323                                 desc_to_clean_to,
2324                                 txq->port_id, txq->queue_id,
2325                                 txd[desc_to_clean_to].cmd_type_offset_bsz);
2326                 /* Failed to clean any descriptors */
2327                 return -1;
2328         }
2329
2330         /* Figure out how many descriptors will be cleaned */
2331         if (last_desc_cleaned > desc_to_clean_to)
2332                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2333                                             desc_to_clean_to);
2334         else
2335                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2336                                             last_desc_cleaned);
2337
2338         /* The last descriptor to clean is done, so that means all the
2339          * descriptors from the last descriptor that was cleaned
2340          * up to the last descriptor with the RS bit set
2341          * are done. Only reset the threshold descriptor.
2342          */
2343         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2344
2345         /* Update the txq to reflect the last descriptor that was cleaned */
2346         txq->last_desc_cleaned = desc_to_clean_to;
2347         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2348
2349         return 0;
2350 }
2351
2352 /* Construct the tx flags */
2353 static inline uint64_t
2354 ice_build_ctob(uint32_t td_cmd,
2355                uint32_t td_offset,
2356                uint16_t size,
2357                uint32_t td_tag)
2358 {
2359         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2360                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2361                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2362                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2363                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2364 }
2365
2366 /* Check if the context descriptor is needed for TX offloading */
2367 static inline uint16_t
2368 ice_calc_context_desc(uint64_t flags)
2369 {
2370         static uint64_t mask = PKT_TX_TCP_SEG |
2371                 PKT_TX_QINQ |
2372                 PKT_TX_OUTER_IP_CKSUM |
2373                 PKT_TX_TUNNEL_MASK;
2374
2375         return (flags & mask) ? 1 : 0;
2376 }
2377
2378 /* set ice TSO context descriptor */
2379 static inline uint64_t
2380 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2381 {
2382         uint64_t ctx_desc = 0;
2383         uint32_t cd_cmd, hdr_len, cd_tso_len;
2384
2385         if (!tx_offload.l4_len) {
2386                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2387                 return ctx_desc;
2388         }
2389
2390         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2391         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2392                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2393
2394         cd_cmd = ICE_TX_CTX_DESC_TSO;
2395         cd_tso_len = mbuf->pkt_len - hdr_len;
2396         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2397                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2398                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2399
2400         return ctx_desc;
2401 }
2402
2403 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2404 #define ICE_MAX_DATA_PER_TXD \
2405         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2406 /* Calculate the number of TX descriptors needed for each pkt */
2407 static inline uint16_t
2408 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2409 {
2410         struct rte_mbuf *txd = tx_pkt;
2411         uint16_t count = 0;
2412
2413         while (txd != NULL) {
2414                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2415                 txd = txd->next;
2416         }
2417
2418         return count;
2419 }
2420
2421 uint16_t
2422 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2423 {
2424         struct ice_tx_queue *txq;
2425         volatile struct ice_tx_desc *tx_ring;
2426         volatile struct ice_tx_desc *txd;
2427         struct ice_tx_entry *sw_ring;
2428         struct ice_tx_entry *txe, *txn;
2429         struct rte_mbuf *tx_pkt;
2430         struct rte_mbuf *m_seg;
2431         uint32_t cd_tunneling_params;
2432         uint16_t tx_id;
2433         uint16_t nb_tx;
2434         uint16_t nb_used;
2435         uint16_t nb_ctx;
2436         uint32_t td_cmd = 0;
2437         uint32_t td_offset = 0;
2438         uint32_t td_tag = 0;
2439         uint16_t tx_last;
2440         uint16_t slen;
2441         uint64_t buf_dma_addr;
2442         uint64_t ol_flags;
2443         union ice_tx_offload tx_offload = {0};
2444
2445         txq = tx_queue;
2446         sw_ring = txq->sw_ring;
2447         tx_ring = txq->tx_ring;
2448         tx_id = txq->tx_tail;
2449         txe = &sw_ring[tx_id];
2450
2451         /* Check if the descriptor ring needs to be cleaned. */
2452         if (txq->nb_tx_free < txq->tx_free_thresh)
2453                 (void)ice_xmit_cleanup(txq);
2454
2455         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2456                 tx_pkt = *tx_pkts++;
2457
2458                 td_cmd = 0;
2459                 td_tag = 0;
2460                 td_offset = 0;
2461                 ol_flags = tx_pkt->ol_flags;
2462                 tx_offload.l2_len = tx_pkt->l2_len;
2463                 tx_offload.l3_len = tx_pkt->l3_len;
2464                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2465                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2466                 tx_offload.l4_len = tx_pkt->l4_len;
2467                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2468                 /* Calculate the number of context descriptors needed. */
2469                 nb_ctx = ice_calc_context_desc(ol_flags);
2470
2471                 /* The number of descriptors that must be allocated for
2472                  * a packet equals to the number of the segments of that
2473                  * packet plus the number of context descriptor if needed.
2474                  * Recalculate the needed tx descs when TSO enabled in case
2475                  * the mbuf data size exceeds max data size that hw allows
2476                  * per tx desc.
2477                  */
2478                 if (ol_flags & PKT_TX_TCP_SEG)
2479                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2480                                              nb_ctx);
2481                 else
2482                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2483                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2484
2485                 /* Circular ring */
2486                 if (tx_last >= txq->nb_tx_desc)
2487                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2488
2489                 if (nb_used > txq->nb_tx_free) {
2490                         if (ice_xmit_cleanup(txq) != 0) {
2491                                 if (nb_tx == 0)
2492                                         return 0;
2493                                 goto end_of_tx;
2494                         }
2495                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2496                                 while (nb_used > txq->nb_tx_free) {
2497                                         if (ice_xmit_cleanup(txq) != 0) {
2498                                                 if (nb_tx == 0)
2499                                                         return 0;
2500                                                 goto end_of_tx;
2501                                         }
2502                                 }
2503                         }
2504                 }
2505
2506                 /* Descriptor based VLAN insertion */
2507                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2508                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2509                         td_tag = tx_pkt->vlan_tci;
2510                 }
2511
2512                 /* Fill in tunneling parameters if necessary */
2513                 cd_tunneling_params = 0;
2514                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2515                         ice_parse_tunneling_params(ol_flags, tx_offload,
2516                                                    &cd_tunneling_params);
2517
2518                 /* Enable checksum offloading */
2519                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2520                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2521                                                 &td_offset, tx_offload);
2522
2523                 if (nb_ctx) {
2524                         /* Setup TX context descriptor if required */
2525                         volatile struct ice_tx_ctx_desc *ctx_txd =
2526                                 (volatile struct ice_tx_ctx_desc *)
2527                                         &tx_ring[tx_id];
2528                         uint16_t cd_l2tag2 = 0;
2529                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2530
2531                         txn = &sw_ring[txe->next_id];
2532                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2533                         if (txe->mbuf) {
2534                                 rte_pktmbuf_free_seg(txe->mbuf);
2535                                 txe->mbuf = NULL;
2536                         }
2537
2538                         if (ol_flags & PKT_TX_TCP_SEG)
2539                                 cd_type_cmd_tso_mss |=
2540                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2541
2542                         ctx_txd->tunneling_params =
2543                                 rte_cpu_to_le_32(cd_tunneling_params);
2544
2545                         /* TX context descriptor based double VLAN insert */
2546                         if (ol_flags & PKT_TX_QINQ) {
2547                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2548                                 cd_type_cmd_tso_mss |=
2549                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2550                                          ICE_TXD_CTX_QW1_CMD_S);
2551                         }
2552                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2553                         ctx_txd->qw1 =
2554                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2555
2556                         txe->last_id = tx_last;
2557                         tx_id = txe->next_id;
2558                         txe = txn;
2559                 }
2560                 m_seg = tx_pkt;
2561
2562                 do {
2563                         txd = &tx_ring[tx_id];
2564                         txn = &sw_ring[txe->next_id];
2565
2566                         if (txe->mbuf)
2567                                 rte_pktmbuf_free_seg(txe->mbuf);
2568                         txe->mbuf = m_seg;
2569
2570                         /* Setup TX Descriptor */
2571                         slen = m_seg->data_len;
2572                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2573
2574                         while ((ol_flags & PKT_TX_TCP_SEG) &&
2575                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2576                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2577                                 txd->cmd_type_offset_bsz =
2578                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2579                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2580                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2581                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2582                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2583                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2584
2585                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2586                                 slen -= ICE_MAX_DATA_PER_TXD;
2587
2588                                 txe->last_id = tx_last;
2589                                 tx_id = txe->next_id;
2590                                 txe = txn;
2591                                 txd = &tx_ring[tx_id];
2592                                 txn = &sw_ring[txe->next_id];
2593                         }
2594
2595                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2596                         txd->cmd_type_offset_bsz =
2597                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2598                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2599                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2600                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2601                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2602
2603                         txe->last_id = tx_last;
2604                         tx_id = txe->next_id;
2605                         txe = txn;
2606                         m_seg = m_seg->next;
2607                 } while (m_seg);
2608
2609                 /* fill the last descriptor with End of Packet (EOP) bit */
2610                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2611                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2612                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2613
2614                 /* set RS bit on the last descriptor of one packet */
2615                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2616                         PMD_TX_FREE_LOG(DEBUG,
2617                                         "Setting RS bit on TXD id="
2618                                         "%4u (port=%d queue=%d)",
2619                                         tx_last, txq->port_id, txq->queue_id);
2620
2621                         td_cmd |= ICE_TX_DESC_CMD_RS;
2622
2623                         /* Update txq RS bit counters */
2624                         txq->nb_tx_used = 0;
2625                 }
2626                 txd->cmd_type_offset_bsz |=
2627                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2628                                          ICE_TXD_QW1_CMD_S);
2629         }
2630 end_of_tx:
2631         /* update Tail register */
2632         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2633         txq->tx_tail = tx_id;
2634
2635         return nb_tx;
2636 }
2637
2638 static __rte_always_inline int
2639 ice_tx_free_bufs(struct ice_tx_queue *txq)
2640 {
2641         struct ice_tx_entry *txep;
2642         uint16_t i;
2643
2644         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2645              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2646             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2647                 return 0;
2648
2649         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2650
2651         for (i = 0; i < txq->tx_rs_thresh; i++)
2652                 rte_prefetch0((txep + i)->mbuf);
2653
2654         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2655                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2656                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2657                         txep->mbuf = NULL;
2658                 }
2659         } else {
2660                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2661                         rte_pktmbuf_free_seg(txep->mbuf);
2662                         txep->mbuf = NULL;
2663                 }
2664         }
2665
2666         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2667         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2668         if (txq->tx_next_dd >= txq->nb_tx_desc)
2669                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2670
2671         return txq->tx_rs_thresh;
2672 }
2673
2674 static int
2675 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2676                         uint32_t free_cnt)
2677 {
2678         struct ice_tx_entry *swr_ring = txq->sw_ring;
2679         uint16_t i, tx_last, tx_id;
2680         uint16_t nb_tx_free_last;
2681         uint16_t nb_tx_to_clean;
2682         uint32_t pkt_cnt;
2683
2684         /* Start free mbuf from the next of tx_tail */
2685         tx_last = txq->tx_tail;
2686         tx_id  = swr_ring[tx_last].next_id;
2687
2688         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2689                 return 0;
2690
2691         nb_tx_to_clean = txq->nb_tx_free;
2692         nb_tx_free_last = txq->nb_tx_free;
2693         if (!free_cnt)
2694                 free_cnt = txq->nb_tx_desc;
2695
2696         /* Loop through swr_ring to count the amount of
2697          * freeable mubfs and packets.
2698          */
2699         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2700                 for (i = 0; i < nb_tx_to_clean &&
2701                         pkt_cnt < free_cnt &&
2702                         tx_id != tx_last; i++) {
2703                         if (swr_ring[tx_id].mbuf != NULL) {
2704                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2705                                 swr_ring[tx_id].mbuf = NULL;
2706
2707                                 /*
2708                                  * last segment in the packet,
2709                                  * increment packet count
2710                                  */
2711                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2712                         }
2713
2714                         tx_id = swr_ring[tx_id].next_id;
2715                 }
2716
2717                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2718                         txq->nb_tx_free || tx_id == tx_last)
2719                         break;
2720
2721                 if (pkt_cnt < free_cnt) {
2722                         if (ice_xmit_cleanup(txq))
2723                                 break;
2724
2725                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2726                         nb_tx_free_last = txq->nb_tx_free;
2727                 }
2728         }
2729
2730         return (int)pkt_cnt;
2731 }
2732
2733 #ifdef RTE_ARCH_X86
2734 static int
2735 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2736                         uint32_t free_cnt __rte_unused)
2737 {
2738         return -ENOTSUP;
2739 }
2740 #endif
2741
2742 static int
2743 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2744                         uint32_t free_cnt)
2745 {
2746         int i, n, cnt;
2747
2748         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2749                 free_cnt = txq->nb_tx_desc;
2750
2751         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2752
2753         for (i = 0; i < cnt; i += n) {
2754                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2755                         break;
2756
2757                 n = ice_tx_free_bufs(txq);
2758
2759                 if (n == 0)
2760                         break;
2761         }
2762
2763         return i;
2764 }
2765
2766 int
2767 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2768 {
2769         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2770         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2771         struct ice_adapter *ad =
2772                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2773
2774 #ifdef RTE_ARCH_X86
2775         if (ad->tx_vec_allowed)
2776                 return ice_tx_done_cleanup_vec(q, free_cnt);
2777 #endif
2778         if (ad->tx_simple_allowed)
2779                 return ice_tx_done_cleanup_simple(q, free_cnt);
2780         else
2781                 return ice_tx_done_cleanup_full(q, free_cnt);
2782 }
2783
2784 /* Populate 4 descriptors with data from 4 mbufs */
2785 static inline void
2786 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2787 {
2788         uint64_t dma_addr;
2789         uint32_t i;
2790
2791         for (i = 0; i < 4; i++, txdp++, pkts++) {
2792                 dma_addr = rte_mbuf_data_iova(*pkts);
2793                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2794                 txdp->cmd_type_offset_bsz =
2795                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2796                                        (*pkts)->data_len, 0);
2797         }
2798 }
2799
2800 /* Populate 1 descriptor with data from 1 mbuf */
2801 static inline void
2802 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2803 {
2804         uint64_t dma_addr;
2805
2806         dma_addr = rte_mbuf_data_iova(*pkts);
2807         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2808         txdp->cmd_type_offset_bsz =
2809                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2810                                (*pkts)->data_len, 0);
2811 }
2812
2813 static inline void
2814 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
2815                     uint16_t nb_pkts)
2816 {
2817         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
2818         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
2819         const int N_PER_LOOP = 4;
2820         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
2821         int mainpart, leftover;
2822         int i, j;
2823
2824         /**
2825          * Process most of the packets in chunks of N pkts.  Any
2826          * leftover packets will get processed one at a time.
2827          */
2828         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
2829         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
2830         for (i = 0; i < mainpart; i += N_PER_LOOP) {
2831                 /* Copy N mbuf pointers to the S/W ring */
2832                 for (j = 0; j < N_PER_LOOP; ++j)
2833                         (txep + i + j)->mbuf = *(pkts + i + j);
2834                 tx4(txdp + i, pkts + i);
2835         }
2836
2837         if (unlikely(leftover > 0)) {
2838                 for (i = 0; i < leftover; ++i) {
2839                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
2840                         tx1(txdp + mainpart + i, pkts + mainpart + i);
2841                 }
2842         }
2843 }
2844
2845 static inline uint16_t
2846 tx_xmit_pkts(struct ice_tx_queue *txq,
2847              struct rte_mbuf **tx_pkts,
2848              uint16_t nb_pkts)
2849 {
2850         volatile struct ice_tx_desc *txr = txq->tx_ring;
2851         uint16_t n = 0;
2852
2853         /**
2854          * Begin scanning the H/W ring for done descriptors when the number
2855          * of available descriptors drops below tx_free_thresh. For each done
2856          * descriptor, free the associated buffer.
2857          */
2858         if (txq->nb_tx_free < txq->tx_free_thresh)
2859                 ice_tx_free_bufs(txq);
2860
2861         /* Use available descriptor only */
2862         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
2863         if (unlikely(!nb_pkts))
2864                 return 0;
2865
2866         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
2867         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
2868                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
2869                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
2870                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2871                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2872                                          ICE_TXD_QW1_CMD_S);
2873                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2874                 txq->tx_tail = 0;
2875         }
2876
2877         /* Fill hardware descriptor ring with mbuf data */
2878         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
2879         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
2880
2881         /* Determin if RS bit needs to be set */
2882         if (txq->tx_tail > txq->tx_next_rs) {
2883                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
2884                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
2885                                          ICE_TXD_QW1_CMD_S);
2886                 txq->tx_next_rs =
2887                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
2888                 if (txq->tx_next_rs >= txq->nb_tx_desc)
2889                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2890         }
2891
2892         if (txq->tx_tail >= txq->nb_tx_desc)
2893                 txq->tx_tail = 0;
2894
2895         /* Update the tx tail register */
2896         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
2897
2898         return nb_pkts;
2899 }
2900
2901 static uint16_t
2902 ice_xmit_pkts_simple(void *tx_queue,
2903                      struct rte_mbuf **tx_pkts,
2904                      uint16_t nb_pkts)
2905 {
2906         uint16_t nb_tx = 0;
2907
2908         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
2909                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2910                                     tx_pkts, nb_pkts);
2911
2912         while (nb_pkts) {
2913                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
2914                                                       ICE_TX_MAX_BURST);
2915
2916                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
2917                                    &tx_pkts[nb_tx], num);
2918                 nb_tx = (uint16_t)(nb_tx + ret);
2919                 nb_pkts = (uint16_t)(nb_pkts - ret);
2920                 if (ret < num)
2921                         break;
2922         }
2923
2924         return nb_tx;
2925 }
2926
2927 void __rte_cold
2928 ice_set_rx_function(struct rte_eth_dev *dev)
2929 {
2930         PMD_INIT_FUNC_TRACE();
2931         struct ice_adapter *ad =
2932                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2933 #ifdef RTE_ARCH_X86
2934         struct ice_rx_queue *rxq;
2935         int i;
2936         bool use_avx2 = false;
2937
2938         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2939                 if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) {
2940                         ad->rx_vec_allowed = true;
2941                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2942                                 rxq = dev->data->rx_queues[i];
2943                                 if (rxq && ice_rxq_vec_setup(rxq)) {
2944                                         ad->rx_vec_allowed = false;
2945                                         break;
2946                                 }
2947                         }
2948
2949                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2950                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2951                                 use_avx2 = true;
2952
2953                 } else {
2954                         ad->rx_vec_allowed = false;
2955                 }
2956         }
2957
2958         if (ad->rx_vec_allowed) {
2959                 if (dev->data->scattered_rx) {
2960                         PMD_DRV_LOG(DEBUG,
2961                                         "Using %sVector Scattered Rx (port %d).",
2962                                         use_avx2 ? "avx2 " : "",
2963                                         dev->data->port_id);
2964                         dev->rx_pkt_burst = use_avx2 ?
2965                                         ice_recv_scattered_pkts_vec_avx2 :
2966                                         ice_recv_scattered_pkts_vec;
2967                 } else {
2968                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2969                                         use_avx2 ? "avx2 " : "",
2970                                         dev->data->port_id);
2971                         dev->rx_pkt_burst = use_avx2 ?
2972                                                 ice_recv_pkts_vec_avx2 :
2973                                                 ice_recv_pkts_vec;
2974                 }
2975                 return;
2976         }
2977
2978 #endif
2979
2980         if (dev->data->scattered_rx) {
2981                 /* Set the non-LRO scattered function */
2982                 PMD_INIT_LOG(DEBUG,
2983                              "Using a Scattered function on port %d.",
2984                              dev->data->port_id);
2985                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
2986         } else if (ad->rx_bulk_alloc_allowed) {
2987                 PMD_INIT_LOG(DEBUG,
2988                              "Rx Burst Bulk Alloc Preconditions are "
2989                              "satisfied. Rx Burst Bulk Alloc function "
2990                              "will be used on port %d.",
2991                              dev->data->port_id);
2992                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
2993         } else {
2994                 PMD_INIT_LOG(DEBUG,
2995                              "Rx Burst Bulk Alloc Preconditions are not "
2996                              "satisfied, Normal Rx will be used on port %d.",
2997                              dev->data->port_id);
2998                 dev->rx_pkt_burst = ice_recv_pkts;
2999         }
3000 }
3001
3002 static const struct {
3003         eth_rx_burst_t pkt_burst;
3004         const char *info;
3005 } ice_rx_burst_infos[] = {
3006         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3007         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3008         { ice_recv_pkts,                    "Scalar" },
3009 #ifdef RTE_ARCH_X86
3010         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3011         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3012         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3013         { ice_recv_pkts_vec,                "Vector SSE" },
3014 #endif
3015 };
3016
3017 int
3018 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3019                       struct rte_eth_burst_mode *mode)
3020 {
3021         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3022         int ret = -EINVAL;
3023         unsigned int i;
3024
3025         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3026                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3027                         snprintf(mode->info, sizeof(mode->info), "%s",
3028                                  ice_rx_burst_infos[i].info);
3029                         ret = 0;
3030                         break;
3031                 }
3032         }
3033
3034         return ret;
3035 }
3036
3037 void __rte_cold
3038 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3039 {
3040         struct ice_adapter *ad =
3041                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3042
3043         /* Use a simple Tx queue if possible (only fast free is allowed) */
3044         ad->tx_simple_allowed =
3045                 (txq->offloads ==
3046                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3047                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3048
3049         if (ad->tx_simple_allowed)
3050                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3051                              txq->queue_id);
3052         else
3053                 PMD_INIT_LOG(DEBUG,
3054                              "Simple Tx can NOT be enabled on Tx queue %u.",
3055                              txq->queue_id);
3056 }
3057
3058 /*********************************************************************
3059  *
3060  *  TX prep functions
3061  *
3062  **********************************************************************/
3063 /* The default values of TSO MSS */
3064 #define ICE_MIN_TSO_MSS            64
3065 #define ICE_MAX_TSO_MSS            9728
3066 #define ICE_MAX_TSO_FRAME_SIZE     262144
3067 uint16_t
3068 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3069               uint16_t nb_pkts)
3070 {
3071         int i, ret;
3072         uint64_t ol_flags;
3073         struct rte_mbuf *m;
3074
3075         for (i = 0; i < nb_pkts; i++) {
3076                 m = tx_pkts[i];
3077                 ol_flags = m->ol_flags;
3078
3079                 if (ol_flags & PKT_TX_TCP_SEG &&
3080                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3081                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3082                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3083                         /**
3084                          * MSS outside the range are considered malicious
3085                          */
3086                         rte_errno = EINVAL;
3087                         return i;
3088                 }
3089
3090 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3091                 ret = rte_validate_tx_offload(m);
3092                 if (ret != 0) {
3093                         rte_errno = -ret;
3094                         return i;
3095                 }
3096 #endif
3097                 ret = rte_net_intel_cksum_prepare(m);
3098                 if (ret != 0) {
3099                         rte_errno = -ret;
3100                         return i;
3101                 }
3102         }
3103         return i;
3104 }
3105
3106 void __rte_cold
3107 ice_set_tx_function(struct rte_eth_dev *dev)
3108 {
3109         struct ice_adapter *ad =
3110                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3111 #ifdef RTE_ARCH_X86
3112         struct ice_tx_queue *txq;
3113         int i;
3114         bool use_avx2 = false;
3115
3116         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3117                 if (!ice_tx_vec_dev_check(dev)) {
3118                         ad->tx_vec_allowed = true;
3119                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3120                                 txq = dev->data->tx_queues[i];
3121                                 if (txq && ice_txq_vec_setup(txq)) {
3122                                         ad->tx_vec_allowed = false;
3123                                         break;
3124                                 }
3125                         }
3126
3127                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3128                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
3129                                 use_avx2 = true;
3130
3131                 } else {
3132                         ad->tx_vec_allowed = false;
3133                 }
3134         }
3135
3136         if (ad->tx_vec_allowed) {
3137                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3138                             use_avx2 ? "avx2 " : "",
3139                             dev->data->port_id);
3140                 dev->tx_pkt_burst = use_avx2 ?
3141                                     ice_xmit_pkts_vec_avx2 :
3142                                     ice_xmit_pkts_vec;
3143                 dev->tx_pkt_prepare = NULL;
3144
3145                 return;
3146         }
3147 #endif
3148
3149         if (ad->tx_simple_allowed) {
3150                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3151                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3152                 dev->tx_pkt_prepare = NULL;
3153         } else {
3154                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3155                 dev->tx_pkt_burst = ice_xmit_pkts;
3156                 dev->tx_pkt_prepare = ice_prep_pkts;
3157         }
3158 }
3159
3160 static const struct {
3161         eth_tx_burst_t pkt_burst;
3162         const char *info;
3163 } ice_tx_burst_infos[] = {
3164         { ice_xmit_pkts_simple,   "Scalar Simple" },
3165         { ice_xmit_pkts,          "Scalar" },
3166 #ifdef RTE_ARCH_X86
3167         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3168         { ice_xmit_pkts_vec,      "Vector SSE" },
3169 #endif
3170 };
3171
3172 int
3173 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3174                       struct rte_eth_burst_mode *mode)
3175 {
3176         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3177         int ret = -EINVAL;
3178         unsigned int i;
3179
3180         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3181                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3182                         snprintf(mode->info, sizeof(mode->info), "%s",
3183                                  ice_tx_burst_infos[i].info);
3184                         ret = 0;
3185                         break;
3186                 }
3187         }
3188
3189         return ret;
3190 }
3191
3192 /* For each value it means, datasheet of hardware can tell more details
3193  *
3194  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3195  */
3196 static inline uint32_t
3197 ice_get_default_pkt_type(uint16_t ptype)
3198 {
3199         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3200                 __rte_cache_aligned = {
3201                 /* L2 types */
3202                 /* [0] reserved */
3203                 [1] = RTE_PTYPE_L2_ETHER,
3204                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3205                 /* [3] - [5] reserved */
3206                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3207                 /* [7] - [10] reserved */
3208                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3209                 /* [12] - [21] reserved */
3210
3211                 /* Non tunneled IPv4 */
3212                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3213                        RTE_PTYPE_L4_FRAG,
3214                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3215                        RTE_PTYPE_L4_NONFRAG,
3216                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3217                        RTE_PTYPE_L4_UDP,
3218                 /* [25] reserved */
3219                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3220                        RTE_PTYPE_L4_TCP,
3221                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3222                        RTE_PTYPE_L4_SCTP,
3223                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3224                        RTE_PTYPE_L4_ICMP,
3225
3226                 /* IPv4 --> IPv4 */
3227                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3228                        RTE_PTYPE_TUNNEL_IP |
3229                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3230                        RTE_PTYPE_INNER_L4_FRAG,
3231                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3232                        RTE_PTYPE_TUNNEL_IP |
3233                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3234                        RTE_PTYPE_INNER_L4_NONFRAG,
3235                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3236                        RTE_PTYPE_TUNNEL_IP |
3237                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3238                        RTE_PTYPE_INNER_L4_UDP,
3239                 /* [32] reserved */
3240                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3241                        RTE_PTYPE_TUNNEL_IP |
3242                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3243                        RTE_PTYPE_INNER_L4_TCP,
3244                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3245                        RTE_PTYPE_TUNNEL_IP |
3246                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3247                        RTE_PTYPE_INNER_L4_SCTP,
3248                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3249                        RTE_PTYPE_TUNNEL_IP |
3250                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3251                        RTE_PTYPE_INNER_L4_ICMP,
3252
3253                 /* IPv4 --> IPv6 */
3254                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3255                        RTE_PTYPE_TUNNEL_IP |
3256                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3257                        RTE_PTYPE_INNER_L4_FRAG,
3258                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3259                        RTE_PTYPE_TUNNEL_IP |
3260                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3261                        RTE_PTYPE_INNER_L4_NONFRAG,
3262                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3263                        RTE_PTYPE_TUNNEL_IP |
3264                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3265                        RTE_PTYPE_INNER_L4_UDP,
3266                 /* [39] reserved */
3267                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3268                        RTE_PTYPE_TUNNEL_IP |
3269                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3270                        RTE_PTYPE_INNER_L4_TCP,
3271                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3272                        RTE_PTYPE_TUNNEL_IP |
3273                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3274                        RTE_PTYPE_INNER_L4_SCTP,
3275                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3276                        RTE_PTYPE_TUNNEL_IP |
3277                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3278                        RTE_PTYPE_INNER_L4_ICMP,
3279
3280                 /* IPv4 --> GRE/Teredo/VXLAN */
3281                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3282                        RTE_PTYPE_TUNNEL_GRENAT,
3283
3284                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3285                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3286                        RTE_PTYPE_TUNNEL_GRENAT |
3287                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3288                        RTE_PTYPE_INNER_L4_FRAG,
3289                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3290                        RTE_PTYPE_TUNNEL_GRENAT |
3291                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3292                        RTE_PTYPE_INNER_L4_NONFRAG,
3293                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3294                        RTE_PTYPE_TUNNEL_GRENAT |
3295                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3296                        RTE_PTYPE_INNER_L4_UDP,
3297                 /* [47] reserved */
3298                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3299                        RTE_PTYPE_TUNNEL_GRENAT |
3300                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3301                        RTE_PTYPE_INNER_L4_TCP,
3302                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3303                        RTE_PTYPE_TUNNEL_GRENAT |
3304                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3305                        RTE_PTYPE_INNER_L4_SCTP,
3306                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3307                        RTE_PTYPE_TUNNEL_GRENAT |
3308                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3309                        RTE_PTYPE_INNER_L4_ICMP,
3310
3311                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3312                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3313                        RTE_PTYPE_TUNNEL_GRENAT |
3314                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3315                        RTE_PTYPE_INNER_L4_FRAG,
3316                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3317                        RTE_PTYPE_TUNNEL_GRENAT |
3318                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3319                        RTE_PTYPE_INNER_L4_NONFRAG,
3320                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3321                        RTE_PTYPE_TUNNEL_GRENAT |
3322                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3323                        RTE_PTYPE_INNER_L4_UDP,
3324                 /* [54] reserved */
3325                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3326                        RTE_PTYPE_TUNNEL_GRENAT |
3327                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3328                        RTE_PTYPE_INNER_L4_TCP,
3329                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3330                        RTE_PTYPE_TUNNEL_GRENAT |
3331                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3332                        RTE_PTYPE_INNER_L4_SCTP,
3333                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3334                        RTE_PTYPE_TUNNEL_GRENAT |
3335                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3336                        RTE_PTYPE_INNER_L4_ICMP,
3337
3338                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3339                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3340                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3341
3342                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3343                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3344                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3345                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3346                        RTE_PTYPE_INNER_L4_FRAG,
3347                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3348                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3349                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3350                        RTE_PTYPE_INNER_L4_NONFRAG,
3351                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3352                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3353                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3354                        RTE_PTYPE_INNER_L4_UDP,
3355                 /* [62] reserved */
3356                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3357                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3358                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3359                        RTE_PTYPE_INNER_L4_TCP,
3360                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3361                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3362                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3363                        RTE_PTYPE_INNER_L4_SCTP,
3364                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3365                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3366                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3367                        RTE_PTYPE_INNER_L4_ICMP,
3368
3369                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3370                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3371                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3372                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3373                        RTE_PTYPE_INNER_L4_FRAG,
3374                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3375                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3376                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3377                        RTE_PTYPE_INNER_L4_NONFRAG,
3378                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3379                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3380                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3381                        RTE_PTYPE_INNER_L4_UDP,
3382                 /* [69] reserved */
3383                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3384                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3385                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3386                        RTE_PTYPE_INNER_L4_TCP,
3387                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3388                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3389                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3390                        RTE_PTYPE_INNER_L4_SCTP,
3391                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3392                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3393                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3394                        RTE_PTYPE_INNER_L4_ICMP,
3395                 /* [73] - [87] reserved */
3396
3397                 /* Non tunneled IPv6 */
3398                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3399                        RTE_PTYPE_L4_FRAG,
3400                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3401                        RTE_PTYPE_L4_NONFRAG,
3402                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3403                        RTE_PTYPE_L4_UDP,
3404                 /* [91] reserved */
3405                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3406                        RTE_PTYPE_L4_TCP,
3407                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3408                        RTE_PTYPE_L4_SCTP,
3409                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3410                        RTE_PTYPE_L4_ICMP,
3411
3412                 /* IPv6 --> IPv4 */
3413                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3414                        RTE_PTYPE_TUNNEL_IP |
3415                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3416                        RTE_PTYPE_INNER_L4_FRAG,
3417                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3418                        RTE_PTYPE_TUNNEL_IP |
3419                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3420                        RTE_PTYPE_INNER_L4_NONFRAG,
3421                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3422                        RTE_PTYPE_TUNNEL_IP |
3423                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3424                        RTE_PTYPE_INNER_L4_UDP,
3425                 /* [98] reserved */
3426                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3427                        RTE_PTYPE_TUNNEL_IP |
3428                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3429                        RTE_PTYPE_INNER_L4_TCP,
3430                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3431                         RTE_PTYPE_TUNNEL_IP |
3432                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3433                         RTE_PTYPE_INNER_L4_SCTP,
3434                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3435                         RTE_PTYPE_TUNNEL_IP |
3436                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3437                         RTE_PTYPE_INNER_L4_ICMP,
3438
3439                 /* IPv6 --> IPv6 */
3440                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3441                         RTE_PTYPE_TUNNEL_IP |
3442                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3443                         RTE_PTYPE_INNER_L4_FRAG,
3444                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3445                         RTE_PTYPE_TUNNEL_IP |
3446                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3447                         RTE_PTYPE_INNER_L4_NONFRAG,
3448                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3449                         RTE_PTYPE_TUNNEL_IP |
3450                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3451                         RTE_PTYPE_INNER_L4_UDP,
3452                 /* [105] reserved */
3453                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3454                         RTE_PTYPE_TUNNEL_IP |
3455                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3456                         RTE_PTYPE_INNER_L4_TCP,
3457                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3458                         RTE_PTYPE_TUNNEL_IP |
3459                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3460                         RTE_PTYPE_INNER_L4_SCTP,
3461                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3462                         RTE_PTYPE_TUNNEL_IP |
3463                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3464                         RTE_PTYPE_INNER_L4_ICMP,
3465
3466                 /* IPv6 --> GRE/Teredo/VXLAN */
3467                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3468                         RTE_PTYPE_TUNNEL_GRENAT,
3469
3470                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3471                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3472                         RTE_PTYPE_TUNNEL_GRENAT |
3473                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3474                         RTE_PTYPE_INNER_L4_FRAG,
3475                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3476                         RTE_PTYPE_TUNNEL_GRENAT |
3477                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3478                         RTE_PTYPE_INNER_L4_NONFRAG,
3479                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3480                         RTE_PTYPE_TUNNEL_GRENAT |
3481                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3482                         RTE_PTYPE_INNER_L4_UDP,
3483                 /* [113] reserved */
3484                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3485                         RTE_PTYPE_TUNNEL_GRENAT |
3486                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3487                         RTE_PTYPE_INNER_L4_TCP,
3488                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3489                         RTE_PTYPE_TUNNEL_GRENAT |
3490                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3491                         RTE_PTYPE_INNER_L4_SCTP,
3492                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3493                         RTE_PTYPE_TUNNEL_GRENAT |
3494                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3495                         RTE_PTYPE_INNER_L4_ICMP,
3496
3497                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3498                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3499                         RTE_PTYPE_TUNNEL_GRENAT |
3500                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3501                         RTE_PTYPE_INNER_L4_FRAG,
3502                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3503                         RTE_PTYPE_TUNNEL_GRENAT |
3504                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3505                         RTE_PTYPE_INNER_L4_NONFRAG,
3506                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3507                         RTE_PTYPE_TUNNEL_GRENAT |
3508                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3509                         RTE_PTYPE_INNER_L4_UDP,
3510                 /* [120] reserved */
3511                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3512                         RTE_PTYPE_TUNNEL_GRENAT |
3513                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3514                         RTE_PTYPE_INNER_L4_TCP,
3515                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3516                         RTE_PTYPE_TUNNEL_GRENAT |
3517                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3518                         RTE_PTYPE_INNER_L4_SCTP,
3519                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3520                         RTE_PTYPE_TUNNEL_GRENAT |
3521                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3522                         RTE_PTYPE_INNER_L4_ICMP,
3523
3524                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3525                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3526                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3527
3528                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3529                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3530                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3531                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3532                         RTE_PTYPE_INNER_L4_FRAG,
3533                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3534                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3535                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3536                         RTE_PTYPE_INNER_L4_NONFRAG,
3537                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3538                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3539                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3540                         RTE_PTYPE_INNER_L4_UDP,
3541                 /* [128] reserved */
3542                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3543                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3544                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3545                         RTE_PTYPE_INNER_L4_TCP,
3546                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3547                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3548                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3549                         RTE_PTYPE_INNER_L4_SCTP,
3550                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3551                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3552                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3553                         RTE_PTYPE_INNER_L4_ICMP,
3554
3555                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3556                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3557                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3558                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3559                         RTE_PTYPE_INNER_L4_FRAG,
3560                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3561                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3562                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3563                         RTE_PTYPE_INNER_L4_NONFRAG,
3564                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3565                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3566                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3567                         RTE_PTYPE_INNER_L4_UDP,
3568                 /* [135] reserved */
3569                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3570                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3571                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3572                         RTE_PTYPE_INNER_L4_TCP,
3573                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3574                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3575                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3576                         RTE_PTYPE_INNER_L4_SCTP,
3577                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3578                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3579                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3580                         RTE_PTYPE_INNER_L4_ICMP,
3581                 /* [139] - [299] reserved */
3582
3583                 /* PPPoE */
3584                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3585                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3586
3587                 /* PPPoE --> IPv4 */
3588                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3589                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3590                         RTE_PTYPE_L4_FRAG,
3591                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3592                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3593                         RTE_PTYPE_L4_NONFRAG,
3594                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3595                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3596                         RTE_PTYPE_L4_UDP,
3597                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3598                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3599                         RTE_PTYPE_L4_TCP,
3600                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3601                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3602                         RTE_PTYPE_L4_SCTP,
3603                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3604                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3605                         RTE_PTYPE_L4_ICMP,
3606
3607                 /* PPPoE --> IPv6 */
3608                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3609                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3610                         RTE_PTYPE_L4_FRAG,
3611                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3612                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3613                         RTE_PTYPE_L4_NONFRAG,
3614                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3615                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3616                         RTE_PTYPE_L4_UDP,
3617                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3618                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3619                         RTE_PTYPE_L4_TCP,
3620                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3621                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3622                         RTE_PTYPE_L4_SCTP,
3623                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3624                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3625                         RTE_PTYPE_L4_ICMP,
3626                 /* [314] - [324] reserved */
3627
3628                 /* IPv4/IPv6 --> GTPC/GTPU */
3629                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3630                         RTE_PTYPE_TUNNEL_GTPC,
3631                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3632                         RTE_PTYPE_TUNNEL_GTPC,
3633                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3634                         RTE_PTYPE_TUNNEL_GTPC,
3635                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3636                         RTE_PTYPE_TUNNEL_GTPC,
3637                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3638                         RTE_PTYPE_TUNNEL_GTPU,
3639                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3640                         RTE_PTYPE_TUNNEL_GTPU,
3641
3642                 /* IPv4 --> GTPU --> IPv4 */
3643                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3644                         RTE_PTYPE_TUNNEL_GTPU |
3645                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3646                         RTE_PTYPE_INNER_L4_FRAG,
3647                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3648                         RTE_PTYPE_TUNNEL_GTPU |
3649                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3650                         RTE_PTYPE_INNER_L4_NONFRAG,
3651                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3652                         RTE_PTYPE_TUNNEL_GTPU |
3653                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3654                         RTE_PTYPE_INNER_L4_UDP,
3655                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3656                         RTE_PTYPE_TUNNEL_GTPU |
3657                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3658                         RTE_PTYPE_INNER_L4_TCP,
3659                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3660                         RTE_PTYPE_TUNNEL_GTPU |
3661                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3662                         RTE_PTYPE_INNER_L4_ICMP,
3663
3664                 /* IPv6 --> GTPU --> IPv4 */
3665                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3666                         RTE_PTYPE_TUNNEL_GTPU |
3667                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3668                         RTE_PTYPE_INNER_L4_FRAG,
3669                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3670                         RTE_PTYPE_TUNNEL_GTPU |
3671                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3672                         RTE_PTYPE_INNER_L4_NONFRAG,
3673                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3674                         RTE_PTYPE_TUNNEL_GTPU |
3675                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3676                         RTE_PTYPE_INNER_L4_UDP,
3677                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3678                         RTE_PTYPE_TUNNEL_GTPU |
3679                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3680                         RTE_PTYPE_INNER_L4_TCP,
3681                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3682                         RTE_PTYPE_TUNNEL_GTPU |
3683                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3684                         RTE_PTYPE_INNER_L4_ICMP,
3685
3686                 /* IPv4 --> GTPU --> IPv6 */
3687                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3688                         RTE_PTYPE_TUNNEL_GTPU |
3689                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3690                         RTE_PTYPE_INNER_L4_FRAG,
3691                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3692                         RTE_PTYPE_TUNNEL_GTPU |
3693                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3694                         RTE_PTYPE_INNER_L4_NONFRAG,
3695                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3696                         RTE_PTYPE_TUNNEL_GTPU |
3697                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3698                         RTE_PTYPE_INNER_L4_UDP,
3699                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3700                         RTE_PTYPE_TUNNEL_GTPU |
3701                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3702                         RTE_PTYPE_INNER_L4_TCP,
3703                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3704                         RTE_PTYPE_TUNNEL_GTPU |
3705                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3706                         RTE_PTYPE_INNER_L4_ICMP,
3707
3708                 /* IPv6 --> GTPU --> IPv6 */
3709                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3710                         RTE_PTYPE_TUNNEL_GTPU |
3711                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3712                         RTE_PTYPE_INNER_L4_FRAG,
3713                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3714                         RTE_PTYPE_TUNNEL_GTPU |
3715                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3716                         RTE_PTYPE_INNER_L4_NONFRAG,
3717                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3718                         RTE_PTYPE_TUNNEL_GTPU |
3719                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3720                         RTE_PTYPE_INNER_L4_UDP,
3721                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3722                         RTE_PTYPE_TUNNEL_GTPU |
3723                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3724                         RTE_PTYPE_INNER_L4_TCP,
3725                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3726                         RTE_PTYPE_TUNNEL_GTPU |
3727                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3728                         RTE_PTYPE_INNER_L4_ICMP,
3729                 /* All others reserved */
3730         };
3731
3732         return type_table[ptype];
3733 }
3734
3735 void __rte_cold
3736 ice_set_default_ptype_table(struct rte_eth_dev *dev)
3737 {
3738         struct ice_adapter *ad =
3739                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3740         int i;
3741
3742         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
3743                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
3744 }
3745
3746 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
3747 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
3748                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
3749 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
3750 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
3751
3752 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
3753 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
3754         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
3755 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
3756 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
3757         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
3758
3759 /*
3760  * check the programming status descriptor in rx queue.
3761  * done after Programming Flow Director is programmed on
3762  * tx queue
3763  */
3764 static inline int
3765 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
3766 {
3767         volatile union ice_32byte_rx_desc *rxdp;
3768         uint64_t qword1;
3769         uint32_t rx_status;
3770         uint32_t error;
3771         uint32_t id;
3772         int ret = -EAGAIN;
3773
3774         rxdp = (volatile union ice_32byte_rx_desc *)
3775                 (&rxq->rx_ring[rxq->rx_tail]);
3776         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
3777         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
3778                         >> ICE_RXD_QW1_STATUS_S;
3779
3780         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
3781                 ret = 0;
3782                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
3783                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
3784                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
3785                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
3786                 if (error) {
3787                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
3788                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
3789                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
3790                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
3791                         ret = -EINVAL;
3792                         goto err;
3793                 }
3794                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
3795                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
3796                 if (error) {
3797                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
3798                         ret = -EINVAL;
3799                 }
3800 err:
3801                 rxdp->wb.qword1.status_error_len = 0;
3802                 rxq->rx_tail++;
3803                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
3804                         rxq->rx_tail = 0;
3805                 if (rxq->rx_tail == 0)
3806                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
3807                 else
3808                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
3809         }
3810
3811         return ret;
3812 }
3813
3814 #define ICE_FDIR_MAX_WAIT_US 10000
3815
3816 int
3817 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
3818 {
3819         struct ice_tx_queue *txq = pf->fdir.txq;
3820         struct ice_rx_queue *rxq = pf->fdir.rxq;
3821         volatile struct ice_fltr_desc *fdirdp;
3822         volatile struct ice_tx_desc *txdp;
3823         uint32_t td_cmd;
3824         uint16_t i;
3825
3826         fdirdp = (volatile struct ice_fltr_desc *)
3827                 (&txq->tx_ring[txq->tx_tail]);
3828         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
3829         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
3830
3831         txdp = &txq->tx_ring[txq->tx_tail + 1];
3832         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
3833         td_cmd = ICE_TX_DESC_CMD_EOP |
3834                 ICE_TX_DESC_CMD_RS  |
3835                 ICE_TX_DESC_CMD_DUMMY;
3836
3837         txdp->cmd_type_offset_bsz =
3838                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
3839
3840         txq->tx_tail += 2;
3841         if (txq->tx_tail >= txq->nb_tx_desc)
3842                 txq->tx_tail = 0;
3843         /* Update the tx tail register */
3844         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
3845         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
3846                 if ((txdp->cmd_type_offset_bsz &
3847                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
3848                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
3849                         break;
3850                 rte_delay_us(1);
3851         }
3852         if (i >= ICE_FDIR_MAX_WAIT_US) {
3853                 PMD_DRV_LOG(ERR,
3854                             "Failed to program FDIR filter: time out to get DD on tx queue.");
3855                 return -ETIMEDOUT;
3856         }
3857
3858         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
3859                 int ret;
3860
3861                 ret = ice_check_fdir_programming_status(rxq);
3862                 if (ret == -EAGAIN)
3863                         rte_delay_us(1);
3864                 else
3865                         return ret;
3866         }
3867
3868         PMD_DRV_LOG(ERR,
3869                     "Failed to program FDIR filter: programming status reported.");
3870         return -ETIMEDOUT;
3871
3872
3873 }