1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
5 #include <ethdev_driver.h>
9 #include "rte_pmd_ice.h"
11 #include "ice_rxtx_vec_common.h"
13 #define ICE_TX_CKSUM_OFFLOAD_MASK ( \
17 PKT_TX_OUTER_IP_CKSUM)
19 /* Offset of mbuf dynamic field for protocol extraction data */
20 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
22 /* Mask of mbuf dynamic flags for protocol extraction type */
23 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
26 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
27 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
28 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
31 ice_monitor_callback(const uint64_t value,
32 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
34 const uint64_t m = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
36 * we expect the DD bit to be set to 1 if this descriptor was already
39 return (value & m) == m ? -1 : 0;
43 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
45 volatile union ice_rx_flex_desc *rxdp;
46 struct ice_rx_queue *rxq = rx_queue;
50 rxdp = &rxq->rx_ring[desc];
51 /* watch for changes in status bit */
52 pmc->addr = &rxdp->wb.status_error0;
54 /* comparison callback */
55 pmc->fn = ice_monitor_callback;
57 /* register is 16-bit */
58 pmc->size = sizeof(uint16_t);
65 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
67 static uint8_t rxdid_map[] = {
68 [PROTO_XTR_NONE] = ICE_RXDID_COMMS_OVS,
69 [PROTO_XTR_VLAN] = ICE_RXDID_COMMS_AUX_VLAN,
70 [PROTO_XTR_IPV4] = ICE_RXDID_COMMS_AUX_IPV4,
71 [PROTO_XTR_IPV6] = ICE_RXDID_COMMS_AUX_IPV6,
72 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
73 [PROTO_XTR_TCP] = ICE_RXDID_COMMS_AUX_TCP,
74 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
77 return xtr_type < RTE_DIM(rxdid_map) ?
78 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
82 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
84 volatile union ice_rx_flex_desc *rxdp)
86 volatile struct ice_32b_rx_flex_desc_comms *desc =
87 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
88 uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
90 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
91 mb->ol_flags |= PKT_RX_RSS_HASH;
92 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
95 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
96 if (desc->flow_id != 0xFFFFFFFF) {
97 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
98 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
104 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
106 volatile union ice_rx_flex_desc *rxdp)
108 volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
109 (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
110 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
114 if (desc->flow_id != 0xFFFFFFFF) {
115 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
116 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
119 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
120 stat_err = rte_le_to_cpu_16(desc->status_error0);
121 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
122 mb->ol_flags |= PKT_RX_RSS_HASH;
123 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
129 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
131 volatile union ice_rx_flex_desc *rxdp)
133 volatile struct ice_32b_rx_flex_desc_comms *desc =
134 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
137 stat_err = rte_le_to_cpu_16(desc->status_error0);
138 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
139 mb->ol_flags |= PKT_RX_RSS_HASH;
140 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
143 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
144 if (desc->flow_id != 0xFFFFFFFF) {
145 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
146 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
149 if (rxq->xtr_ol_flag) {
150 uint32_t metadata = 0;
152 stat_err = rte_le_to_cpu_16(desc->status_error1);
154 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
155 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
157 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
159 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
162 mb->ol_flags |= rxq->xtr_ol_flag;
164 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
171 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
173 volatile union ice_rx_flex_desc *rxdp)
175 volatile struct ice_32b_rx_flex_desc_comms *desc =
176 (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
179 stat_err = rte_le_to_cpu_16(desc->status_error0);
180 if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
181 mb->ol_flags |= PKT_RX_RSS_HASH;
182 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
185 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
186 if (desc->flow_id != 0xFFFFFFFF) {
187 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
188 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
191 if (rxq->xtr_ol_flag) {
192 uint32_t metadata = 0;
194 if (desc->flex_ts.flex.aux0 != 0xFFFF)
195 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
196 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
197 metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
200 mb->ol_flags |= rxq->xtr_ol_flag;
202 *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
209 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
212 case ICE_RXDID_COMMS_AUX_VLAN:
213 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
214 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
217 case ICE_RXDID_COMMS_AUX_IPV4:
218 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
219 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
222 case ICE_RXDID_COMMS_AUX_IPV6:
223 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
224 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
227 case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
228 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
229 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
232 case ICE_RXDID_COMMS_AUX_TCP:
233 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
234 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
237 case ICE_RXDID_COMMS_AUX_IP_OFFSET:
238 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
239 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v2;
242 case ICE_RXDID_COMMS_GENERIC:
243 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_generic;
246 case ICE_RXDID_COMMS_OVS:
247 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
251 /* update this according to the RXDID for PROTO_XTR_NONE */
252 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
256 if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
257 rxq->xtr_ol_flag = 0;
260 static enum ice_status
261 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
263 struct ice_vsi *vsi = rxq->vsi;
264 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
265 struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
266 struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
267 struct ice_rlan_ctx rx_ctx;
270 struct rte_eth_rxmode *rxmode = &dev_data->dev_conf.rxmode;
271 uint32_t rxdid = ICE_RXDID_COMMS_OVS;
273 struct ice_adapter *ad = rxq->vsi->adapter;
275 /* Set buffer size as the head split is disabled. */
276 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
277 RTE_PKTMBUF_HEADROOM);
279 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
280 rxq->max_pkt_len = RTE_MIN((uint32_t)
281 ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
282 dev_data->dev_conf.rxmode.max_rx_pkt_len);
284 if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
285 if (rxq->max_pkt_len <= ICE_ETH_MAX_LEN ||
286 rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
287 PMD_DRV_LOG(ERR, "maximum packet length must "
288 "be larger than %u and smaller than %u,"
289 "as jumbo frame is enabled",
290 (uint32_t)ICE_ETH_MAX_LEN,
291 (uint32_t)ICE_FRAME_SIZE_MAX);
295 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
296 rxq->max_pkt_len > ICE_ETH_MAX_LEN) {
297 PMD_DRV_LOG(ERR, "maximum packet length must be "
298 "larger than %u and smaller than %u, "
299 "as jumbo frame is disabled",
300 (uint32_t)RTE_ETHER_MIN_LEN,
301 (uint32_t)ICE_ETH_MAX_LEN);
306 if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
307 /* Register mbuf field and flag for Rx timestamp */
308 err = rte_mbuf_dyn_rx_timestamp_register(
309 &ice_timestamp_dynfield_offset,
310 &ice_timestamp_dynflag);
313 "Cannot register mbuf field/flag for timestamp");
318 memset(&rx_ctx, 0, sizeof(rx_ctx));
320 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
321 rx_ctx.qlen = rxq->nb_rx_desc;
322 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
323 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
324 rx_ctx.dtype = 0; /* No Header Split mode */
325 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
326 rx_ctx.dsize = 1; /* 32B descriptors */
328 rx_ctx.rxmax = rxq->max_pkt_len;
329 /* TPH: Transaction Layer Packet (TLP) processing hints */
330 rx_ctx.tphrdesc_ena = 1;
331 rx_ctx.tphwdesc_ena = 1;
332 rx_ctx.tphdata_ena = 1;
333 rx_ctx.tphhead_ena = 1;
334 /* Low Receive Queue Threshold defined in 64 descriptors units.
335 * When the number of free descriptors goes below the lrxqthresh,
336 * an immediate interrupt is triggered.
338 rx_ctx.lrxqthresh = 2;
339 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
342 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
344 rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
346 PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
347 rxq->port_id, rxq->queue_id, rxdid);
349 if (!(pf->supported_rxdid & BIT(rxdid))) {
350 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
355 ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
357 /* Enable Flexible Descriptors in the queue context which
358 * allows this driver to select a specific receive descriptor format
360 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
361 QRXFLXP_CNTXT_RXDID_IDX_M;
363 /* increasing context priority to pick up profile ID;
364 * default is 0x01; setting to 0x03 to ensure profile
365 * is programming if prev context is of same priority
367 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
368 QRXFLXP_CNTXT_RXDID_PRIO_M;
370 if (ad->ptp_ena || rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP)
371 regval |= QRXFLXP_CNTXT_TS_M;
373 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
375 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
377 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
381 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
383 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
388 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
389 RTE_PKTMBUF_HEADROOM);
391 /* Check if scattered RX needs to be used. */
392 if (rxq->max_pkt_len > buf_size)
393 dev_data->scattered_rx = 1;
395 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
397 /* Init the Rx tail register*/
398 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
403 /* Allocate mbufs for all descriptors in rx queue */
405 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
407 struct ice_rx_entry *rxe = rxq->sw_ring;
411 for (i = 0; i < rxq->nb_rx_desc; i++) {
412 volatile union ice_rx_flex_desc *rxd;
413 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
415 if (unlikely(!mbuf)) {
416 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
420 rte_mbuf_refcnt_set(mbuf, 1);
422 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
424 mbuf->port = rxq->port_id;
427 rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
429 rxd = &rxq->rx_ring[i];
430 rxd->read.pkt_addr = dma_addr;
431 rxd->read.hdr_addr = 0;
432 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
442 /* Free all mbufs for descriptors in rx queue */
444 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
448 if (!rxq || !rxq->sw_ring) {
449 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
453 for (i = 0; i < rxq->nb_rx_desc; i++) {
454 if (rxq->sw_ring[i].mbuf) {
455 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
456 rxq->sw_ring[i].mbuf = NULL;
459 if (rxq->rx_nb_avail == 0)
461 for (i = 0; i < rxq->rx_nb_avail; i++)
462 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
464 rxq->rx_nb_avail = 0;
467 /* turn on or off rx queue
468 * @q_idx: queue index in pf scope
469 * @on: turn on or off the queue
472 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
477 /* QRX_CTRL = QRX_ENA */
478 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
481 if (reg & QRX_CTRL_QENA_STAT_M)
482 return 0; /* Already on, skip */
483 reg |= QRX_CTRL_QENA_REQ_M;
485 if (!(reg & QRX_CTRL_QENA_STAT_M))
486 return 0; /* Already off, skip */
487 reg &= ~QRX_CTRL_QENA_REQ_M;
490 /* Write the register */
491 ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
492 /* Check the result. It is said that QENA_STAT
493 * follows the QENA_REQ not more than 10 use.
494 * TODO: need to change the wait counter later
496 for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
497 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
498 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
500 if ((reg & QRX_CTRL_QENA_REQ_M) &&
501 (reg & QRX_CTRL_QENA_STAT_M))
504 if (!(reg & QRX_CTRL_QENA_REQ_M) &&
505 !(reg & QRX_CTRL_QENA_STAT_M))
510 /* Check if it is timeout */
511 if (j >= ICE_CHK_Q_ENA_COUNT) {
512 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
513 (on ? "enable" : "disable"), q_idx);
521 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
525 if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
526 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
527 "rxq->rx_free_thresh=%d, "
528 "ICE_RX_MAX_BURST=%d",
529 rxq->rx_free_thresh, ICE_RX_MAX_BURST);
531 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
532 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
533 "rxq->rx_free_thresh=%d, "
534 "rxq->nb_rx_desc=%d",
535 rxq->rx_free_thresh, rxq->nb_rx_desc);
537 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
538 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
539 "rxq->nb_rx_desc=%d, "
540 "rxq->rx_free_thresh=%d",
541 rxq->nb_rx_desc, rxq->rx_free_thresh);
548 /* reset fields in ice_rx_queue back to default */
550 ice_reset_rx_queue(struct ice_rx_queue *rxq)
556 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
560 len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
562 for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
563 ((volatile char *)rxq->rx_ring)[i] = 0;
565 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
566 for (i = 0; i < ICE_RX_MAX_BURST; ++i)
567 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
569 rxq->rx_nb_avail = 0;
570 rxq->rx_next_avail = 0;
571 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
575 rxq->pkt_first_seg = NULL;
576 rxq->pkt_last_seg = NULL;
578 rxq->rxrearm_start = 0;
583 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
585 struct ice_rx_queue *rxq;
587 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
589 PMD_INIT_FUNC_TRACE();
591 if (rx_queue_id >= dev->data->nb_rx_queues) {
592 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
593 rx_queue_id, dev->data->nb_rx_queues);
597 rxq = dev->data->rx_queues[rx_queue_id];
598 if (!rxq || !rxq->q_set) {
599 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
604 err = ice_program_hw_rx_queue(rxq);
606 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
611 err = ice_alloc_rx_queue_mbufs(rxq);
613 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
617 /* Init the RX tail register. */
618 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
620 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
622 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
625 rxq->rx_rel_mbufs(rxq);
626 ice_reset_rx_queue(rxq);
630 dev->data->rx_queue_state[rx_queue_id] =
631 RTE_ETH_QUEUE_STATE_STARTED;
637 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
639 struct ice_rx_queue *rxq;
641 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
643 if (rx_queue_id < dev->data->nb_rx_queues) {
644 rxq = dev->data->rx_queues[rx_queue_id];
646 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
648 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
652 rxq->rx_rel_mbufs(rxq);
653 ice_reset_rx_queue(rxq);
654 dev->data->rx_queue_state[rx_queue_id] =
655 RTE_ETH_QUEUE_STATE_STOPPED;
662 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
664 struct ice_tx_queue *txq;
668 struct ice_aqc_add_tx_qgrp *txq_elem;
669 struct ice_tlan_ctx tx_ctx;
672 PMD_INIT_FUNC_TRACE();
674 if (tx_queue_id >= dev->data->nb_tx_queues) {
675 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
676 tx_queue_id, dev->data->nb_tx_queues);
680 txq = dev->data->tx_queues[tx_queue_id];
681 if (!txq || !txq->q_set) {
682 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
687 buf_len = ice_struct_size(txq_elem, txqs, 1);
688 txq_elem = ice_malloc(hw, buf_len);
693 hw = ICE_VSI_TO_HW(vsi);
695 memset(&tx_ctx, 0, sizeof(tx_ctx));
696 txq_elem->num_txqs = 1;
697 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
699 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
700 tx_ctx.qlen = txq->nb_tx_desc;
701 tx_ctx.pf_num = hw->pf_id;
702 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
703 tx_ctx.src_vsi = vsi->vsi_id;
704 tx_ctx.port_num = hw->port_info->lport;
705 tx_ctx.tso_ena = 1; /* tso enable */
706 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
707 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
710 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
713 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
715 /* Init the Tx tail register*/
716 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
718 /* Fix me, we assume TC always 0 here */
719 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
720 txq_elem, buf_len, NULL);
722 PMD_DRV_LOG(ERR, "Failed to add lan txq");
726 /* store the schedule node id */
727 txq->q_teid = txq_elem->txqs[0].q_teid;
729 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
735 static enum ice_status
736 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
738 struct ice_vsi *vsi = rxq->vsi;
739 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
740 uint32_t rxdid = ICE_RXDID_LEGACY_1;
741 struct ice_rlan_ctx rx_ctx;
746 rxq->rx_buf_len = 1024;
748 memset(&rx_ctx, 0, sizeof(rx_ctx));
750 rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
751 rx_ctx.qlen = rxq->nb_rx_desc;
752 rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
753 rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
754 rx_ctx.dtype = 0; /* No Header Split mode */
755 rx_ctx.dsize = 1; /* 32B descriptors */
756 rx_ctx.rxmax = ICE_ETH_MAX_LEN;
757 /* TPH: Transaction Layer Packet (TLP) processing hints */
758 rx_ctx.tphrdesc_ena = 1;
759 rx_ctx.tphwdesc_ena = 1;
760 rx_ctx.tphdata_ena = 1;
761 rx_ctx.tphhead_ena = 1;
762 /* Low Receive Queue Threshold defined in 64 descriptors units.
763 * When the number of free descriptors goes below the lrxqthresh,
764 * an immediate interrupt is triggered.
766 rx_ctx.lrxqthresh = 2;
767 /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
770 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
772 /* Enable Flexible Descriptors in the queue context which
773 * allows this driver to select a specific receive descriptor format
775 regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
776 QRXFLXP_CNTXT_RXDID_IDX_M;
778 /* increasing context priority to pick up profile ID;
779 * default is 0x01; setting to 0x03 to ensure profile
780 * is programming if prev context is of same priority
782 regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
783 QRXFLXP_CNTXT_RXDID_PRIO_M;
785 ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
787 err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
789 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
793 err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
795 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
800 rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
802 /* Init the Rx tail register*/
803 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
809 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
811 struct ice_rx_queue *rxq;
813 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
814 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
816 PMD_INIT_FUNC_TRACE();
819 if (!rxq || !rxq->q_set) {
820 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
825 err = ice_fdir_program_hw_rx_queue(rxq);
827 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
832 /* Init the RX tail register. */
833 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
835 err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
837 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
840 ice_reset_rx_queue(rxq);
848 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
850 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
851 struct ice_tx_queue *txq;
855 struct ice_aqc_add_tx_qgrp *txq_elem;
856 struct ice_tlan_ctx tx_ctx;
859 PMD_INIT_FUNC_TRACE();
862 if (!txq || !txq->q_set) {
863 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
868 buf_len = ice_struct_size(txq_elem, txqs, 1);
869 txq_elem = ice_malloc(hw, buf_len);
874 hw = ICE_VSI_TO_HW(vsi);
876 memset(&tx_ctx, 0, sizeof(tx_ctx));
877 txq_elem->num_txqs = 1;
878 txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
880 tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
881 tx_ctx.qlen = txq->nb_tx_desc;
882 tx_ctx.pf_num = hw->pf_id;
883 tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
884 tx_ctx.src_vsi = vsi->vsi_id;
885 tx_ctx.port_num = hw->port_info->lport;
886 tx_ctx.tso_ena = 1; /* tso enable */
887 tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
888 tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
890 ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
893 txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
895 /* Init the Tx tail register*/
896 ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
898 /* Fix me, we assume TC always 0 here */
899 err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
900 txq_elem, buf_len, NULL);
902 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
906 /* store the schedule node id */
907 txq->q_teid = txq_elem->txqs[0].q_teid;
913 /* Free all mbufs for descriptors in tx queue */
915 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
919 if (!txq || !txq->sw_ring) {
920 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
924 for (i = 0; i < txq->nb_tx_desc; i++) {
925 if (txq->sw_ring[i].mbuf) {
926 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
927 txq->sw_ring[i].mbuf = NULL;
933 ice_reset_tx_queue(struct ice_tx_queue *txq)
935 struct ice_tx_entry *txe;
936 uint16_t i, prev, size;
939 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
944 size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
945 for (i = 0; i < size; i++)
946 ((volatile char *)txq->tx_ring)[i] = 0;
948 prev = (uint16_t)(txq->nb_tx_desc - 1);
949 for (i = 0; i < txq->nb_tx_desc; i++) {
950 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
952 txd->cmd_type_offset_bsz =
953 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
956 txe[prev].next_id = i;
960 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
961 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
966 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
967 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
971 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
973 struct ice_tx_queue *txq;
974 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
975 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
976 struct ice_vsi *vsi = pf->main_vsi;
977 enum ice_status status;
980 uint16_t q_handle = tx_queue_id;
982 if (tx_queue_id >= dev->data->nb_tx_queues) {
983 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
984 tx_queue_id, dev->data->nb_tx_queues);
988 txq = dev->data->tx_queues[tx_queue_id];
990 PMD_DRV_LOG(ERR, "TX queue %u is not available",
995 q_ids[0] = txq->reg_idx;
996 q_teids[0] = txq->q_teid;
998 /* Fix me, we assume TC always 0 here */
999 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1000 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1001 if (status != ICE_SUCCESS) {
1002 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1006 txq->tx_rel_mbufs(txq);
1007 ice_reset_tx_queue(txq);
1008 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1014 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1016 struct ice_rx_queue *rxq;
1018 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1019 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1023 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1025 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1029 rxq->rx_rel_mbufs(rxq);
1035 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1037 struct ice_tx_queue *txq;
1038 struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1039 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1040 struct ice_vsi *vsi = pf->main_vsi;
1041 enum ice_status status;
1043 uint32_t q_teids[1];
1044 uint16_t q_handle = tx_queue_id;
1048 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1054 q_ids[0] = txq->reg_idx;
1055 q_teids[0] = txq->q_teid;
1057 /* Fix me, we assume TC always 0 here */
1058 status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1059 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1060 if (status != ICE_SUCCESS) {
1061 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1065 txq->tx_rel_mbufs(txq);
1071 ice_rx_queue_setup(struct rte_eth_dev *dev,
1074 unsigned int socket_id,
1075 const struct rte_eth_rxconf *rx_conf,
1076 struct rte_mempool *mp)
1078 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1079 struct ice_adapter *ad =
1080 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1081 struct ice_vsi *vsi = pf->main_vsi;
1082 struct ice_rx_queue *rxq;
1083 const struct rte_memzone *rz;
1086 int use_def_burst_func = 1;
1089 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1090 nb_desc > ICE_MAX_RING_DESC ||
1091 nb_desc < ICE_MIN_RING_DESC) {
1092 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1093 "invalid", nb_desc);
1097 offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1099 /* Free memory if needed */
1100 if (dev->data->rx_queues[queue_idx]) {
1101 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1102 dev->data->rx_queues[queue_idx] = NULL;
1105 /* Allocate the rx queue data structure */
1106 rxq = rte_zmalloc_socket(NULL,
1107 sizeof(struct ice_rx_queue),
1108 RTE_CACHE_LINE_SIZE,
1111 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1112 "rx queue data structure");
1116 rxq->nb_rx_desc = nb_desc;
1117 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1118 rxq->queue_id = queue_idx;
1119 rxq->offloads = offloads;
1121 rxq->reg_idx = vsi->base_queue + queue_idx;
1122 rxq->port_id = dev->data->port_id;
1123 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1124 rxq->crc_len = RTE_ETHER_CRC_LEN;
1128 rxq->drop_en = rx_conf->rx_drop_en;
1130 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1131 rxq->proto_xtr = pf->proto_xtr != NULL ?
1132 pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1134 /* Allocate the maximun number of RX ring hardware descriptor. */
1135 len = ICE_MAX_RING_DESC;
1138 * Allocating a little more memory because vectorized/bulk_alloc Rx
1139 * functions doesn't check boundaries each time.
1141 len += ICE_RX_MAX_BURST;
1143 /* Allocate the maximum number of RX ring hardware descriptor. */
1144 ring_size = sizeof(union ice_rx_flex_desc) * len;
1145 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1146 rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1147 ring_size, ICE_RING_BASE_ALIGN,
1150 ice_rx_queue_release(rxq);
1151 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1155 /* Zero all the descriptors in the ring. */
1156 memset(rz->addr, 0, ring_size);
1158 rxq->rx_ring_dma = rz->iova;
1159 rxq->rx_ring = rz->addr;
1161 /* always reserve more for bulk alloc */
1162 len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1164 /* Allocate the software ring. */
1165 rxq->sw_ring = rte_zmalloc_socket(NULL,
1166 sizeof(struct ice_rx_entry) * len,
1167 RTE_CACHE_LINE_SIZE,
1169 if (!rxq->sw_ring) {
1170 ice_rx_queue_release(rxq);
1171 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1175 ice_reset_rx_queue(rxq);
1177 dev->data->rx_queues[queue_idx] = rxq;
1178 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1180 use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1182 if (!use_def_burst_func) {
1183 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1184 "satisfied. Rx Burst Bulk Alloc function will be "
1185 "used on port=%d, queue=%d.",
1186 rxq->port_id, rxq->queue_id);
1188 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1189 "not satisfied, Scattered Rx is requested. "
1190 "on port=%d, queue=%d.",
1191 rxq->port_id, rxq->queue_id);
1192 ad->rx_bulk_alloc_allowed = false;
1199 ice_rx_queue_release(void *rxq)
1201 struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1204 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1209 rte_free(q->sw_ring);
1214 ice_tx_queue_setup(struct rte_eth_dev *dev,
1217 unsigned int socket_id,
1218 const struct rte_eth_txconf *tx_conf)
1220 struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1221 struct ice_vsi *vsi = pf->main_vsi;
1222 struct ice_tx_queue *txq;
1223 const struct rte_memzone *tz;
1225 uint16_t tx_rs_thresh, tx_free_thresh;
1228 offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1230 if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1231 nb_desc > ICE_MAX_RING_DESC ||
1232 nb_desc < ICE_MIN_RING_DESC) {
1233 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1234 "invalid", nb_desc);
1239 * The following two parameters control the setting of the RS bit on
1240 * transmit descriptors. TX descriptors will have their RS bit set
1241 * after txq->tx_rs_thresh descriptors have been used. The TX
1242 * descriptor ring will be cleaned after txq->tx_free_thresh
1243 * descriptors are used or if the number of descriptors required to
1244 * transmit a packet is greater than the number of free TX descriptors.
1246 * The following constraints must be satisfied:
1247 * - tx_rs_thresh must be greater than 0.
1248 * - tx_rs_thresh must be less than the size of the ring minus 2.
1249 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1250 * - tx_rs_thresh must be a divisor of the ring size.
1251 * - tx_free_thresh must be greater than 0.
1252 * - tx_free_thresh must be less than the size of the ring minus 3.
1253 * - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1255 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1256 * race condition, hence the maximum threshold constraints. When set
1257 * to zero use default values.
1259 tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1260 tx_conf->tx_free_thresh :
1261 ICE_DEFAULT_TX_FREE_THRESH);
1262 /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1264 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1265 nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1266 if (tx_conf->tx_rs_thresh)
1267 tx_rs_thresh = tx_conf->tx_rs_thresh;
1268 if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1269 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1270 "exceed nb_desc. (tx_rs_thresh=%u "
1271 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1272 (unsigned int)tx_rs_thresh,
1273 (unsigned int)tx_free_thresh,
1274 (unsigned int)nb_desc,
1275 (int)dev->data->port_id,
1279 if (tx_rs_thresh >= (nb_desc - 2)) {
1280 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1281 "number of TX descriptors minus 2. "
1282 "(tx_rs_thresh=%u port=%d queue=%d)",
1283 (unsigned int)tx_rs_thresh,
1284 (int)dev->data->port_id,
1288 if (tx_free_thresh >= (nb_desc - 3)) {
1289 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1290 "tx_free_thresh must be less than the "
1291 "number of TX descriptors minus 3. "
1292 "(tx_free_thresh=%u port=%d queue=%d)",
1293 (unsigned int)tx_free_thresh,
1294 (int)dev->data->port_id,
1298 if (tx_rs_thresh > tx_free_thresh) {
1299 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1300 "equal to tx_free_thresh. (tx_free_thresh=%u"
1301 " tx_rs_thresh=%u port=%d queue=%d)",
1302 (unsigned int)tx_free_thresh,
1303 (unsigned int)tx_rs_thresh,
1304 (int)dev->data->port_id,
1308 if ((nb_desc % tx_rs_thresh) != 0) {
1309 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1310 "number of TX descriptors. (tx_rs_thresh=%u"
1311 " port=%d queue=%d)",
1312 (unsigned int)tx_rs_thresh,
1313 (int)dev->data->port_id,
1317 if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1318 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1319 "tx_rs_thresh is greater than 1. "
1320 "(tx_rs_thresh=%u port=%d queue=%d)",
1321 (unsigned int)tx_rs_thresh,
1322 (int)dev->data->port_id,
1327 /* Free memory if needed. */
1328 if (dev->data->tx_queues[queue_idx]) {
1329 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1330 dev->data->tx_queues[queue_idx] = NULL;
1333 /* Allocate the TX queue data structure. */
1334 txq = rte_zmalloc_socket(NULL,
1335 sizeof(struct ice_tx_queue),
1336 RTE_CACHE_LINE_SIZE,
1339 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1340 "tx queue structure");
1344 /* Allocate TX hardware ring descriptors. */
1345 ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1346 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1347 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1348 ring_size, ICE_RING_BASE_ALIGN,
1351 ice_tx_queue_release(txq);
1352 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1356 txq->nb_tx_desc = nb_desc;
1357 txq->tx_rs_thresh = tx_rs_thresh;
1358 txq->tx_free_thresh = tx_free_thresh;
1359 txq->pthresh = tx_conf->tx_thresh.pthresh;
1360 txq->hthresh = tx_conf->tx_thresh.hthresh;
1361 txq->wthresh = tx_conf->tx_thresh.wthresh;
1362 txq->queue_id = queue_idx;
1364 txq->reg_idx = vsi->base_queue + queue_idx;
1365 txq->port_id = dev->data->port_id;
1366 txq->offloads = offloads;
1368 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1370 txq->tx_ring_dma = tz->iova;
1371 txq->tx_ring = tz->addr;
1373 /* Allocate software ring */
1375 rte_zmalloc_socket(NULL,
1376 sizeof(struct ice_tx_entry) * nb_desc,
1377 RTE_CACHE_LINE_SIZE,
1379 if (!txq->sw_ring) {
1380 ice_tx_queue_release(txq);
1381 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1385 ice_reset_tx_queue(txq);
1387 dev->data->tx_queues[queue_idx] = txq;
1388 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1389 ice_set_tx_function_flag(dev, txq);
1395 ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1397 ice_rx_queue_release(dev->data->rx_queues[qid]);
1401 ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1403 ice_tx_queue_release(dev->data->tx_queues[qid]);
1407 ice_tx_queue_release(void *txq)
1409 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1412 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1417 rte_free(q->sw_ring);
1422 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1423 struct rte_eth_rxq_info *qinfo)
1425 struct ice_rx_queue *rxq;
1427 rxq = dev->data->rx_queues[queue_id];
1429 qinfo->mp = rxq->mp;
1430 qinfo->scattered_rx = dev->data->scattered_rx;
1431 qinfo->nb_desc = rxq->nb_rx_desc;
1433 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1434 qinfo->conf.rx_drop_en = rxq->drop_en;
1435 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1439 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1440 struct rte_eth_txq_info *qinfo)
1442 struct ice_tx_queue *txq;
1444 txq = dev->data->tx_queues[queue_id];
1446 qinfo->nb_desc = txq->nb_tx_desc;
1448 qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1449 qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1450 qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1452 qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1453 qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1454 qinfo->conf.offloads = txq->offloads;
1455 qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1459 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1461 #define ICE_RXQ_SCAN_INTERVAL 4
1462 volatile union ice_rx_flex_desc *rxdp;
1463 struct ice_rx_queue *rxq;
1466 rxq = dev->data->rx_queues[rx_queue_id];
1467 rxdp = &rxq->rx_ring[rxq->rx_tail];
1468 while ((desc < rxq->nb_rx_desc) &&
1469 rte_le_to_cpu_16(rxdp->wb.status_error0) &
1470 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1472 * Check the DD bit of a rx descriptor of each 4 in a group,
1473 * to avoid checking too frequently and downgrading performance
1476 desc += ICE_RXQ_SCAN_INTERVAL;
1477 rxdp += ICE_RXQ_SCAN_INTERVAL;
1478 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1479 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1480 desc - rxq->nb_rx_desc]);
1486 #define ICE_RX_FLEX_ERR0_BITS \
1487 ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) | \
1488 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) | \
1489 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) | \
1490 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
1491 (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1492 (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1494 /* Rx L3/L4 checksum */
1495 static inline uint64_t
1496 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1500 /* check if HW has decoded the packet and checksum */
1501 if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1504 if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1505 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1509 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1510 flags |= PKT_RX_IP_CKSUM_BAD;
1512 flags |= PKT_RX_IP_CKSUM_GOOD;
1514 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1515 flags |= PKT_RX_L4_CKSUM_BAD;
1517 flags |= PKT_RX_L4_CKSUM_GOOD;
1519 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1520 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1522 if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1523 flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
1525 flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
1531 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1533 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1534 (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1535 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1537 rte_le_to_cpu_16(rxdp->wb.l2tag1);
1538 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1539 rte_le_to_cpu_16(rxdp->wb.l2tag1));
1544 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1545 if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1546 (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1547 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1548 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1549 mb->vlan_tci_outer = mb->vlan_tci;
1550 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1551 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1552 rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1553 rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1555 mb->vlan_tci_outer = 0;
1558 PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1559 mb->vlan_tci, mb->vlan_tci_outer);
1562 #define ICE_LOOK_AHEAD 8
1563 #if (ICE_LOOK_AHEAD != 8)
1564 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1567 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1569 volatile union ice_rx_flex_desc *rxdp;
1570 struct ice_rx_entry *rxep;
1571 struct rte_mbuf *mb;
1574 int32_t s[ICE_LOOK_AHEAD], nb_dd;
1575 int32_t i, j, nb_rx = 0;
1576 uint64_t pkt_flags = 0;
1577 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1578 struct ice_vsi *vsi = rxq->vsi;
1579 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1581 struct ice_adapter *ad = rxq->vsi->adapter;
1583 rxdp = &rxq->rx_ring[rxq->rx_tail];
1584 rxep = &rxq->sw_ring[rxq->rx_tail];
1586 stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1588 /* Make sure there is at least 1 packet to receive */
1589 if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1593 * Scan LOOK_AHEAD descriptors at a time to determine which
1594 * descriptors reference packets that are ready to be received.
1596 for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1597 rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1598 /* Read desc statuses backwards to avoid race condition */
1599 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1600 s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1604 /* Compute how many status bits were set */
1605 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1606 nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1610 /* Translate descriptor info to mbuf parameters */
1611 for (j = 0; j < nb_dd; j++) {
1613 pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1614 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1615 mb->data_len = pkt_len;
1616 mb->pkt_len = pkt_len;
1618 stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1619 pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1620 mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1621 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1622 ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1623 rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1625 if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
1626 ts_ns = ice_tstamp_convert_32b_64b(hw,
1627 rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high));
1628 if (ice_timestamp_dynflag > 0) {
1629 *RTE_MBUF_DYNFIELD(mb,
1630 ice_timestamp_dynfield_offset,
1631 rte_mbuf_timestamp_t *) = ts_ns;
1632 mb->ol_flags |= ice_timestamp_dynflag;
1636 if (ad->ptp_ena && ((mb->packet_type &
1637 RTE_PTYPE_L2_MASK) == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1639 rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high);
1640 mb->timesync = rxq->queue_id;
1641 pkt_flags |= PKT_RX_IEEE1588_PTP;
1644 mb->ol_flags |= pkt_flags;
1647 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1648 rxq->rx_stage[i + j] = rxep[j].mbuf;
1650 if (nb_dd != ICE_LOOK_AHEAD)
1654 /* Clear software ring entries */
1655 for (i = 0; i < nb_rx; i++)
1656 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1658 PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1659 "port_id=%u, queue_id=%u, nb_rx=%d",
1660 rxq->port_id, rxq->queue_id, nb_rx);
1665 static inline uint16_t
1666 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1667 struct rte_mbuf **rx_pkts,
1671 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1673 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1675 for (i = 0; i < nb_pkts; i++)
1676 rx_pkts[i] = stage[i];
1678 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1679 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1685 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1687 volatile union ice_rx_flex_desc *rxdp;
1688 struct ice_rx_entry *rxep;
1689 struct rte_mbuf *mb;
1690 uint16_t alloc_idx, i;
1694 /* Allocate buffers in bulk */
1695 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1696 (rxq->rx_free_thresh - 1));
1697 rxep = &rxq->sw_ring[alloc_idx];
1698 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1699 rxq->rx_free_thresh);
1700 if (unlikely(diag != 0)) {
1701 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1705 rxdp = &rxq->rx_ring[alloc_idx];
1706 for (i = 0; i < rxq->rx_free_thresh; i++) {
1707 if (likely(i < (rxq->rx_free_thresh - 1)))
1708 /* Prefetch next mbuf */
1709 rte_prefetch0(rxep[i + 1].mbuf);
1712 rte_mbuf_refcnt_set(mb, 1);
1714 mb->data_off = RTE_PKTMBUF_HEADROOM;
1716 mb->port = rxq->port_id;
1717 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1718 rxdp[i].read.hdr_addr = 0;
1719 rxdp[i].read.pkt_addr = dma_addr;
1722 /* Update rx tail regsiter */
1723 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1725 rxq->rx_free_trigger =
1726 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1727 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1728 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1733 static inline uint16_t
1734 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1736 struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1742 if (rxq->rx_nb_avail)
1743 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1745 nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1746 rxq->rx_next_avail = 0;
1747 rxq->rx_nb_avail = nb_rx;
1748 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1750 if (rxq->rx_tail > rxq->rx_free_trigger) {
1751 if (ice_rx_alloc_bufs(rxq) != 0) {
1754 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1755 rxq->rx_free_thresh;
1756 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1757 "port_id=%u, queue_id=%u",
1758 rxq->port_id, rxq->queue_id);
1759 rxq->rx_nb_avail = 0;
1760 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1761 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1762 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1768 if (rxq->rx_tail >= rxq->nb_rx_desc)
1771 if (rxq->rx_nb_avail)
1772 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1778 ice_recv_pkts_bulk_alloc(void *rx_queue,
1779 struct rte_mbuf **rx_pkts,
1786 if (unlikely(nb_pkts == 0))
1789 if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1790 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1793 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1794 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1795 nb_rx = (uint16_t)(nb_rx + count);
1796 nb_pkts = (uint16_t)(nb_pkts - count);
1805 ice_recv_scattered_pkts(void *rx_queue,
1806 struct rte_mbuf **rx_pkts,
1809 struct ice_rx_queue *rxq = rx_queue;
1810 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1811 volatile union ice_rx_flex_desc *rxdp;
1812 union ice_rx_flex_desc rxd;
1813 struct ice_rx_entry *sw_ring = rxq->sw_ring;
1814 struct ice_rx_entry *rxe;
1815 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1816 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1817 struct rte_mbuf *nmb; /* new allocated mbuf */
1818 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1819 uint16_t rx_id = rxq->rx_tail;
1821 uint16_t nb_hold = 0;
1822 uint16_t rx_packet_len;
1823 uint16_t rx_stat_err0;
1826 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1827 struct ice_vsi *vsi = rxq->vsi;
1828 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1830 struct ice_adapter *ad = rxq->vsi->adapter;
1832 while (nb_rx < nb_pkts) {
1833 rxdp = &rx_ring[rx_id];
1834 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1836 /* Check the DD bit first */
1837 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1841 nmb = rte_mbuf_raw_alloc(rxq->mp);
1842 if (unlikely(!nmb)) {
1843 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1846 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1849 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1851 if (unlikely(rx_id == rxq->nb_rx_desc))
1854 /* Prefetch next mbuf */
1855 rte_prefetch0(sw_ring[rx_id].mbuf);
1858 * When next RX descriptor is on a cache line boundary,
1859 * prefetch the next 4 RX descriptors and next 8 pointers
1862 if ((rx_id & 0x3) == 0) {
1863 rte_prefetch0(&rx_ring[rx_id]);
1864 rte_prefetch0(&sw_ring[rx_id]);
1870 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1872 /* Set data buffer address and data length of the mbuf */
1873 rxdp->read.hdr_addr = 0;
1874 rxdp->read.pkt_addr = dma_addr;
1875 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1876 ICE_RX_FLX_DESC_PKT_LEN_M;
1877 rxm->data_len = rx_packet_len;
1878 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1881 * If this is the first buffer of the received packet, set the
1882 * pointer to the first mbuf of the packet and initialize its
1883 * context. Otherwise, update the total length and the number
1884 * of segments of the current scattered packet, and update the
1885 * pointer to the last mbuf of the current packet.
1889 first_seg->nb_segs = 1;
1890 first_seg->pkt_len = rx_packet_len;
1892 first_seg->pkt_len =
1893 (uint16_t)(first_seg->pkt_len +
1895 first_seg->nb_segs++;
1896 last_seg->next = rxm;
1900 * If this is not the last buffer of the received packet,
1901 * update the pointer to the last mbuf of the current scattered
1902 * packet and continue to parse the RX ring.
1904 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1910 * This is the last buffer of the received packet. If the CRC
1911 * is not stripped by the hardware:
1912 * - Subtract the CRC length from the total packet length.
1913 * - If the last buffer only contains the whole CRC or a part
1914 * of it, free the mbuf associated to the last buffer. If part
1915 * of the CRC is also contained in the previous mbuf, subtract
1916 * the length of that CRC part from the data length of the
1920 if (unlikely(rxq->crc_len > 0)) {
1921 first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1922 if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1923 rte_pktmbuf_free_seg(rxm);
1924 first_seg->nb_segs--;
1925 last_seg->data_len =
1926 (uint16_t)(last_seg->data_len -
1927 (RTE_ETHER_CRC_LEN - rx_packet_len));
1928 last_seg->next = NULL;
1930 rxm->data_len = (uint16_t)(rx_packet_len -
1934 first_seg->port = rxq->port_id;
1935 first_seg->ol_flags = 0;
1936 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1937 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1938 ice_rxd_to_vlan_tci(first_seg, &rxd);
1939 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1940 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1942 if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
1943 ts_ns = ice_tstamp_convert_32b_64b(hw,
1944 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1945 if (ice_timestamp_dynflag > 0) {
1946 *RTE_MBUF_DYNFIELD(first_seg,
1947 ice_timestamp_dynfield_offset,
1948 rte_mbuf_timestamp_t *) = ts_ns;
1949 first_seg->ol_flags |= ice_timestamp_dynflag;
1953 if (ad->ptp_ena && ((first_seg->packet_type & RTE_PTYPE_L2_MASK)
1954 == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1956 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
1957 first_seg->timesync = rxq->queue_id;
1958 pkt_flags |= PKT_RX_IEEE1588_PTP;
1961 first_seg->ol_flags |= pkt_flags;
1962 /* Prefetch data of first segment, if configured to do so. */
1963 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1964 first_seg->data_off));
1965 rx_pkts[nb_rx++] = first_seg;
1969 /* Record index of the next RX descriptor to probe. */
1970 rxq->rx_tail = rx_id;
1971 rxq->pkt_first_seg = first_seg;
1972 rxq->pkt_last_seg = last_seg;
1975 * If the number of free RX descriptors is greater than the RX free
1976 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1977 * register. Update the RDT with the value of the last processed RX
1978 * descriptor minus 1, to guarantee that the RDT register is never
1979 * equal to the RDH register, which creates a "full" ring situtation
1980 * from the hardware point of view.
1982 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1983 if (nb_hold > rxq->rx_free_thresh) {
1984 rx_id = (uint16_t)(rx_id == 0 ?
1985 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1986 /* write TAIL register */
1987 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1990 rxq->nb_rx_hold = nb_hold;
1992 /* return received packet in the burst */
1997 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1999 struct ice_adapter *ad =
2000 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2001 const uint32_t *ptypes;
2003 static const uint32_t ptypes_os[] = {
2004 /* refers to ice_get_default_pkt_type() */
2006 RTE_PTYPE_L2_ETHER_TIMESYNC,
2007 RTE_PTYPE_L2_ETHER_LLDP,
2008 RTE_PTYPE_L2_ETHER_ARP,
2009 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2010 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2013 RTE_PTYPE_L4_NONFRAG,
2017 RTE_PTYPE_TUNNEL_GRENAT,
2018 RTE_PTYPE_TUNNEL_IP,
2019 RTE_PTYPE_INNER_L2_ETHER,
2020 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2021 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2022 RTE_PTYPE_INNER_L4_FRAG,
2023 RTE_PTYPE_INNER_L4_ICMP,
2024 RTE_PTYPE_INNER_L4_NONFRAG,
2025 RTE_PTYPE_INNER_L4_SCTP,
2026 RTE_PTYPE_INNER_L4_TCP,
2027 RTE_PTYPE_INNER_L4_UDP,
2031 static const uint32_t ptypes_comms[] = {
2032 /* refers to ice_get_default_pkt_type() */
2034 RTE_PTYPE_L2_ETHER_TIMESYNC,
2035 RTE_PTYPE_L2_ETHER_LLDP,
2036 RTE_PTYPE_L2_ETHER_ARP,
2037 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2038 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2041 RTE_PTYPE_L4_NONFRAG,
2045 RTE_PTYPE_TUNNEL_GRENAT,
2046 RTE_PTYPE_TUNNEL_IP,
2047 RTE_PTYPE_INNER_L2_ETHER,
2048 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2049 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2050 RTE_PTYPE_INNER_L4_FRAG,
2051 RTE_PTYPE_INNER_L4_ICMP,
2052 RTE_PTYPE_INNER_L4_NONFRAG,
2053 RTE_PTYPE_INNER_L4_SCTP,
2054 RTE_PTYPE_INNER_L4_TCP,
2055 RTE_PTYPE_INNER_L4_UDP,
2056 RTE_PTYPE_TUNNEL_GTPC,
2057 RTE_PTYPE_TUNNEL_GTPU,
2058 RTE_PTYPE_L2_ETHER_PPPOE,
2062 if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
2063 ptypes = ptypes_comms;
2067 if (dev->rx_pkt_burst == ice_recv_pkts ||
2068 dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
2069 dev->rx_pkt_burst == ice_recv_scattered_pkts)
2073 if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
2074 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
2075 #ifdef CC_AVX512_SUPPORT
2076 dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
2077 dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
2078 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
2079 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
2081 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
2082 dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
2083 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2084 dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2092 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2094 volatile union ice_rx_flex_desc *rxdp;
2095 struct ice_rx_queue *rxq = rx_queue;
2098 if (unlikely(offset >= rxq->nb_rx_desc))
2101 if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2102 return RTE_ETH_RX_DESC_UNAVAIL;
2104 desc = rxq->rx_tail + offset;
2105 if (desc >= rxq->nb_rx_desc)
2106 desc -= rxq->nb_rx_desc;
2108 rxdp = &rxq->rx_ring[desc];
2109 if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2110 (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2111 return RTE_ETH_RX_DESC_DONE;
2113 return RTE_ETH_RX_DESC_AVAIL;
2117 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2119 struct ice_tx_queue *txq = tx_queue;
2120 volatile uint64_t *status;
2121 uint64_t mask, expect;
2124 if (unlikely(offset >= txq->nb_tx_desc))
2127 desc = txq->tx_tail + offset;
2128 /* go to next desc that has the RS bit */
2129 desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2131 if (desc >= txq->nb_tx_desc) {
2132 desc -= txq->nb_tx_desc;
2133 if (desc >= txq->nb_tx_desc)
2134 desc -= txq->nb_tx_desc;
2137 status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2138 mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2139 expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2140 ICE_TXD_QW1_DTYPE_S);
2141 if ((*status & mask) == expect)
2142 return RTE_ETH_TX_DESC_DONE;
2144 return RTE_ETH_TX_DESC_FULL;
2148 ice_free_queues(struct rte_eth_dev *dev)
2152 PMD_INIT_FUNC_TRACE();
2154 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2155 if (!dev->data->rx_queues[i])
2157 ice_rx_queue_release(dev->data->rx_queues[i]);
2158 dev->data->rx_queues[i] = NULL;
2159 rte_eth_dma_zone_free(dev, "rx_ring", i);
2161 dev->data->nb_rx_queues = 0;
2163 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2164 if (!dev->data->tx_queues[i])
2166 ice_tx_queue_release(dev->data->tx_queues[i]);
2167 dev->data->tx_queues[i] = NULL;
2168 rte_eth_dma_zone_free(dev, "tx_ring", i);
2170 dev->data->nb_tx_queues = 0;
2173 #define ICE_FDIR_NUM_TX_DESC ICE_MIN_RING_DESC
2174 #define ICE_FDIR_NUM_RX_DESC ICE_MIN_RING_DESC
2177 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2179 struct ice_tx_queue *txq;
2180 const struct rte_memzone *tz = NULL;
2182 struct rte_eth_dev *dev;
2185 PMD_DRV_LOG(ERR, "PF is not available");
2189 dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2191 /* Allocate the TX queue data structure. */
2192 txq = rte_zmalloc_socket("ice fdir tx queue",
2193 sizeof(struct ice_tx_queue),
2194 RTE_CACHE_LINE_SIZE,
2197 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2198 "tx queue structure.");
2202 /* Allocate TX hardware ring descriptors. */
2203 ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2204 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2206 tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2207 ICE_FDIR_QUEUE_ID, ring_size,
2208 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2210 ice_tx_queue_release(txq);
2211 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2215 txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2216 txq->queue_id = ICE_FDIR_QUEUE_ID;
2217 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2218 txq->vsi = pf->fdir.fdir_vsi;
2220 txq->tx_ring_dma = tz->iova;
2221 txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2223 * don't need to allocate software ring and reset for the fdir
2224 * program queue just set the queue has been configured.
2229 txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2235 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2237 struct ice_rx_queue *rxq;
2238 const struct rte_memzone *rz = NULL;
2240 struct rte_eth_dev *dev;
2243 PMD_DRV_LOG(ERR, "PF is not available");
2247 dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2249 /* Allocate the RX queue data structure. */
2250 rxq = rte_zmalloc_socket("ice fdir rx queue",
2251 sizeof(struct ice_rx_queue),
2252 RTE_CACHE_LINE_SIZE,
2255 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2256 "rx queue structure.");
2260 /* Allocate RX hardware ring descriptors. */
2261 ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2262 ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2264 rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2265 ICE_FDIR_QUEUE_ID, ring_size,
2266 ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2268 ice_rx_queue_release(rxq);
2269 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2273 rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2274 rxq->queue_id = ICE_FDIR_QUEUE_ID;
2275 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2276 rxq->vsi = pf->fdir.fdir_vsi;
2278 rxq->rx_ring_dma = rz->iova;
2279 memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2280 sizeof(union ice_32byte_rx_desc));
2281 rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2284 * Don't need to allocate software ring and reset for the fdir
2285 * rx queue, just set the queue has been configured.
2290 rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2296 ice_recv_pkts(void *rx_queue,
2297 struct rte_mbuf **rx_pkts,
2300 struct ice_rx_queue *rxq = rx_queue;
2301 volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2302 volatile union ice_rx_flex_desc *rxdp;
2303 union ice_rx_flex_desc rxd;
2304 struct ice_rx_entry *sw_ring = rxq->sw_ring;
2305 struct ice_rx_entry *rxe;
2306 struct rte_mbuf *nmb; /* new allocated mbuf */
2307 struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2308 uint16_t rx_id = rxq->rx_tail;
2310 uint16_t nb_hold = 0;
2311 uint16_t rx_packet_len;
2312 uint16_t rx_stat_err0;
2315 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2316 struct ice_vsi *vsi = rxq->vsi;
2317 struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2319 struct ice_adapter *ad = rxq->vsi->adapter;
2321 while (nb_rx < nb_pkts) {
2322 rxdp = &rx_ring[rx_id];
2323 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2325 /* Check the DD bit first */
2326 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2330 nmb = rte_mbuf_raw_alloc(rxq->mp);
2331 if (unlikely(!nmb)) {
2332 rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2335 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2338 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2340 if (unlikely(rx_id == rxq->nb_rx_desc))
2345 rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2348 * fill the read format of descriptor with physic address in
2349 * new allocated mbuf: nmb
2351 rxdp->read.hdr_addr = 0;
2352 rxdp->read.pkt_addr = dma_addr;
2354 /* calculate rx_packet_len of the received pkt */
2355 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2356 ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2358 /* fill old mbuf with received descriptor: rxd */
2359 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2360 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2363 rxm->pkt_len = rx_packet_len;
2364 rxm->data_len = rx_packet_len;
2365 rxm->port = rxq->port_id;
2366 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2367 rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2368 ice_rxd_to_vlan_tci(rxm, &rxd);
2369 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
2370 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2372 if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
2373 ts_ns = ice_tstamp_convert_32b_64b(hw,
2374 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
2375 if (ice_timestamp_dynflag > 0) {
2376 *RTE_MBUF_DYNFIELD(rxm,
2377 ice_timestamp_dynfield_offset,
2378 rte_mbuf_timestamp_t *) = ts_ns;
2379 rxm->ol_flags |= ice_timestamp_dynflag;
2383 if (ad->ptp_ena && ((rxm->packet_type & RTE_PTYPE_L2_MASK) ==
2384 RTE_PTYPE_L2_ETHER_TIMESYNC)) {
2386 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2387 rxm->timesync = rxq->queue_id;
2388 pkt_flags |= PKT_RX_IEEE1588_PTP;
2391 rxm->ol_flags |= pkt_flags;
2392 /* copy old mbuf to rx_pkts */
2393 rx_pkts[nb_rx++] = rxm;
2395 rxq->rx_tail = rx_id;
2397 * If the number of free RX descriptors is greater than the RX free
2398 * threshold of the queue, advance the receive tail register of queue.
2399 * Update that register with the value of the last processed RX
2400 * descriptor minus 1.
2402 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2403 if (nb_hold > rxq->rx_free_thresh) {
2404 rx_id = (uint16_t)(rx_id == 0 ?
2405 (rxq->nb_rx_desc - 1) : (rx_id - 1));
2406 /* write TAIL register */
2407 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2410 rxq->nb_rx_hold = nb_hold;
2412 /* return received packet in the burst */
2417 ice_parse_tunneling_params(uint64_t ol_flags,
2418 union ice_tx_offload tx_offload,
2419 uint32_t *cd_tunneling)
2421 /* EIPT: External (outer) IP header type */
2422 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2423 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2424 else if (ol_flags & PKT_TX_OUTER_IPV4)
2425 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2426 else if (ol_flags & PKT_TX_OUTER_IPV6)
2427 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2429 /* EIPLEN: External (outer) IP header length, in DWords */
2430 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2431 ICE_TXD_CTX_QW0_EIPLEN_S;
2433 /* L4TUNT: L4 Tunneling Type */
2434 switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2435 case PKT_TX_TUNNEL_IPIP:
2436 /* for non UDP / GRE tunneling, set to 00b */
2438 case PKT_TX_TUNNEL_VXLAN:
2439 case PKT_TX_TUNNEL_GTP:
2440 case PKT_TX_TUNNEL_GENEVE:
2441 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2443 case PKT_TX_TUNNEL_GRE:
2444 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2447 PMD_TX_LOG(ERR, "Tunnel type not supported");
2451 /* L4TUNLEN: L4 Tunneling Length, in Words
2453 * We depend on app to set rte_mbuf.l2_len correctly.
2454 * For IP in GRE it should be set to the length of the GRE
2456 * For MAC in GRE or MAC in UDP it should be set to the length
2457 * of the GRE or UDP headers plus the inner MAC up to including
2458 * its last Ethertype.
2459 * If MPLS labels exists, it should include them as well.
2461 *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2462 ICE_TXD_CTX_QW0_NATLEN_S;
2465 * Calculate the tunneling UDP checksum.
2466 * Shall be set only if L4TUNT = 01b and EIPT is not zero
2468 if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2469 (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2470 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2474 ice_txd_enable_checksum(uint64_t ol_flags,
2476 uint32_t *td_offset,
2477 union ice_tx_offload tx_offload)
2480 if (ol_flags & PKT_TX_TUNNEL_MASK)
2481 *td_offset |= (tx_offload.outer_l2_len >> 1)
2482 << ICE_TX_DESC_LEN_MACLEN_S;
2484 *td_offset |= (tx_offload.l2_len >> 1)
2485 << ICE_TX_DESC_LEN_MACLEN_S;
2487 /* Enable L3 checksum offloads */
2488 if (ol_flags & PKT_TX_IP_CKSUM) {
2489 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2490 *td_offset |= (tx_offload.l3_len >> 2) <<
2491 ICE_TX_DESC_LEN_IPLEN_S;
2492 } else if (ol_flags & PKT_TX_IPV4) {
2493 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2494 *td_offset |= (tx_offload.l3_len >> 2) <<
2495 ICE_TX_DESC_LEN_IPLEN_S;
2496 } else if (ol_flags & PKT_TX_IPV6) {
2497 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2498 *td_offset |= (tx_offload.l3_len >> 2) <<
2499 ICE_TX_DESC_LEN_IPLEN_S;
2502 if (ol_flags & PKT_TX_TCP_SEG) {
2503 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2504 *td_offset |= (tx_offload.l4_len >> 2) <<
2505 ICE_TX_DESC_LEN_L4_LEN_S;
2509 /* Enable L4 checksum offloads */
2510 switch (ol_flags & PKT_TX_L4_MASK) {
2511 case PKT_TX_TCP_CKSUM:
2512 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2513 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2514 ICE_TX_DESC_LEN_L4_LEN_S;
2516 case PKT_TX_SCTP_CKSUM:
2517 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2518 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2519 ICE_TX_DESC_LEN_L4_LEN_S;
2521 case PKT_TX_UDP_CKSUM:
2522 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2523 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2524 ICE_TX_DESC_LEN_L4_LEN_S;
2532 ice_xmit_cleanup(struct ice_tx_queue *txq)
2534 struct ice_tx_entry *sw_ring = txq->sw_ring;
2535 volatile struct ice_tx_desc *txd = txq->tx_ring;
2536 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2537 uint16_t nb_tx_desc = txq->nb_tx_desc;
2538 uint16_t desc_to_clean_to;
2539 uint16_t nb_tx_to_clean;
2541 /* Determine the last descriptor needing to be cleaned */
2542 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2543 if (desc_to_clean_to >= nb_tx_desc)
2544 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2546 /* Check to make sure the last descriptor to clean is done */
2547 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2548 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2549 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2550 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2551 "(port=%d queue=%d) value=0x%"PRIx64"\n",
2553 txq->port_id, txq->queue_id,
2554 txd[desc_to_clean_to].cmd_type_offset_bsz);
2555 /* Failed to clean any descriptors */
2559 /* Figure out how many descriptors will be cleaned */
2560 if (last_desc_cleaned > desc_to_clean_to)
2561 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2564 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2567 /* The last descriptor to clean is done, so that means all the
2568 * descriptors from the last descriptor that was cleaned
2569 * up to the last descriptor with the RS bit set
2570 * are done. Only reset the threshold descriptor.
2572 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2574 /* Update the txq to reflect the last descriptor that was cleaned */
2575 txq->last_desc_cleaned = desc_to_clean_to;
2576 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2581 /* Construct the tx flags */
2582 static inline uint64_t
2583 ice_build_ctob(uint32_t td_cmd,
2588 return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2589 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2590 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2591 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2592 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2595 /* Check if the context descriptor is needed for TX offloading */
2596 static inline uint16_t
2597 ice_calc_context_desc(uint64_t flags)
2599 static uint64_t mask = PKT_TX_TCP_SEG |
2601 PKT_TX_OUTER_IP_CKSUM |
2602 PKT_TX_TUNNEL_MASK |
2603 PKT_TX_IEEE1588_TMST;
2605 return (flags & mask) ? 1 : 0;
2608 /* set ice TSO context descriptor */
2609 static inline uint64_t
2610 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2612 uint64_t ctx_desc = 0;
2613 uint32_t cd_cmd, hdr_len, cd_tso_len;
2615 if (!tx_offload.l4_len) {
2616 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2620 hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2621 hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2622 tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2624 cd_cmd = ICE_TX_CTX_DESC_TSO;
2625 cd_tso_len = mbuf->pkt_len - hdr_len;
2626 ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2627 ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2628 ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2633 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2634 #define ICE_MAX_DATA_PER_TXD \
2635 (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2636 /* Calculate the number of TX descriptors needed for each pkt */
2637 static inline uint16_t
2638 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2640 struct rte_mbuf *txd = tx_pkt;
2643 while (txd != NULL) {
2644 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2652 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2654 struct ice_tx_queue *txq;
2655 volatile struct ice_tx_desc *tx_ring;
2656 volatile struct ice_tx_desc *txd;
2657 struct ice_tx_entry *sw_ring;
2658 struct ice_tx_entry *txe, *txn;
2659 struct rte_mbuf *tx_pkt;
2660 struct rte_mbuf *m_seg;
2661 uint32_t cd_tunneling_params;
2666 uint32_t td_cmd = 0;
2667 uint32_t td_offset = 0;
2668 uint32_t td_tag = 0;
2671 uint64_t buf_dma_addr;
2673 union ice_tx_offload tx_offload = {0};
2676 sw_ring = txq->sw_ring;
2677 tx_ring = txq->tx_ring;
2678 tx_id = txq->tx_tail;
2679 txe = &sw_ring[tx_id];
2681 /* Check if the descriptor ring needs to be cleaned. */
2682 if (txq->nb_tx_free < txq->tx_free_thresh)
2683 (void)ice_xmit_cleanup(txq);
2685 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2686 tx_pkt = *tx_pkts++;
2691 ol_flags = tx_pkt->ol_flags;
2692 tx_offload.l2_len = tx_pkt->l2_len;
2693 tx_offload.l3_len = tx_pkt->l3_len;
2694 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2695 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2696 tx_offload.l4_len = tx_pkt->l4_len;
2697 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2698 /* Calculate the number of context descriptors needed. */
2699 nb_ctx = ice_calc_context_desc(ol_flags);
2701 /* The number of descriptors that must be allocated for
2702 * a packet equals to the number of the segments of that
2703 * packet plus the number of context descriptor if needed.
2704 * Recalculate the needed tx descs when TSO enabled in case
2705 * the mbuf data size exceeds max data size that hw allows
2708 if (ol_flags & PKT_TX_TCP_SEG)
2709 nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2712 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2713 tx_last = (uint16_t)(tx_id + nb_used - 1);
2716 if (tx_last >= txq->nb_tx_desc)
2717 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2719 if (nb_used > txq->nb_tx_free) {
2720 if (ice_xmit_cleanup(txq) != 0) {
2725 if (unlikely(nb_used > txq->tx_rs_thresh)) {
2726 while (nb_used > txq->nb_tx_free) {
2727 if (ice_xmit_cleanup(txq) != 0) {
2736 /* Descriptor based VLAN insertion */
2737 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2738 td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2739 td_tag = tx_pkt->vlan_tci;
2742 /* Fill in tunneling parameters if necessary */
2743 cd_tunneling_params = 0;
2744 if (ol_flags & PKT_TX_TUNNEL_MASK)
2745 ice_parse_tunneling_params(ol_flags, tx_offload,
2746 &cd_tunneling_params);
2748 /* Enable checksum offloading */
2749 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2750 ice_txd_enable_checksum(ol_flags, &td_cmd,
2751 &td_offset, tx_offload);
2754 /* Setup TX context descriptor if required */
2755 volatile struct ice_tx_ctx_desc *ctx_txd =
2756 (volatile struct ice_tx_ctx_desc *)
2758 uint16_t cd_l2tag2 = 0;
2759 uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2761 txn = &sw_ring[txe->next_id];
2762 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2764 rte_pktmbuf_free_seg(txe->mbuf);
2768 if (ol_flags & PKT_TX_TCP_SEG)
2769 cd_type_cmd_tso_mss |=
2770 ice_set_tso_ctx(tx_pkt, tx_offload);
2771 else if (ol_flags & PKT_TX_IEEE1588_TMST)
2772 cd_type_cmd_tso_mss |=
2773 ((uint64_t)ICE_TX_CTX_DESC_TSYN <<
2774 ICE_TXD_CTX_QW1_CMD_S);
2776 ctx_txd->tunneling_params =
2777 rte_cpu_to_le_32(cd_tunneling_params);
2779 /* TX context descriptor based double VLAN insert */
2780 if (ol_flags & PKT_TX_QINQ) {
2781 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2782 cd_type_cmd_tso_mss |=
2783 ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2784 ICE_TXD_CTX_QW1_CMD_S);
2786 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2788 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2790 txe->last_id = tx_last;
2791 tx_id = txe->next_id;
2797 txd = &tx_ring[tx_id];
2798 txn = &sw_ring[txe->next_id];
2801 rte_pktmbuf_free_seg(txe->mbuf);
2804 /* Setup TX Descriptor */
2805 slen = m_seg->data_len;
2806 buf_dma_addr = rte_mbuf_data_iova(m_seg);
2808 while ((ol_flags & PKT_TX_TCP_SEG) &&
2809 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2810 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2811 txd->cmd_type_offset_bsz =
2812 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2813 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2814 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2815 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2816 ICE_TXD_QW1_TX_BUF_SZ_S) |
2817 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2819 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2820 slen -= ICE_MAX_DATA_PER_TXD;
2822 txe->last_id = tx_last;
2823 tx_id = txe->next_id;
2825 txd = &tx_ring[tx_id];
2826 txn = &sw_ring[txe->next_id];
2829 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2830 txd->cmd_type_offset_bsz =
2831 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2832 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2833 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2834 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2835 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2837 txe->last_id = tx_last;
2838 tx_id = txe->next_id;
2840 m_seg = m_seg->next;
2843 /* fill the last descriptor with End of Packet (EOP) bit */
2844 td_cmd |= ICE_TX_DESC_CMD_EOP;
2845 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2846 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2848 /* set RS bit on the last descriptor of one packet */
2849 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2851 "Setting RS bit on TXD id="
2852 "%4u (port=%d queue=%d)",
2853 tx_last, txq->port_id, txq->queue_id);
2855 td_cmd |= ICE_TX_DESC_CMD_RS;
2857 /* Update txq RS bit counters */
2858 txq->nb_tx_used = 0;
2860 txd->cmd_type_offset_bsz |=
2861 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2865 /* update Tail register */
2866 ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2867 txq->tx_tail = tx_id;
2872 static __rte_always_inline int
2873 ice_tx_free_bufs(struct ice_tx_queue *txq)
2875 struct ice_tx_entry *txep;
2878 if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2879 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2880 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2883 txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2885 for (i = 0; i < txq->tx_rs_thresh; i++)
2886 rte_prefetch0((txep + i)->mbuf);
2888 if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2889 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2890 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2894 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2895 rte_pktmbuf_free_seg(txep->mbuf);
2900 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2901 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2902 if (txq->tx_next_dd >= txq->nb_tx_desc)
2903 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2905 return txq->tx_rs_thresh;
2909 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2912 struct ice_tx_entry *swr_ring = txq->sw_ring;
2913 uint16_t i, tx_last, tx_id;
2914 uint16_t nb_tx_free_last;
2915 uint16_t nb_tx_to_clean;
2918 /* Start free mbuf from the next of tx_tail */
2919 tx_last = txq->tx_tail;
2920 tx_id = swr_ring[tx_last].next_id;
2922 if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2925 nb_tx_to_clean = txq->nb_tx_free;
2926 nb_tx_free_last = txq->nb_tx_free;
2928 free_cnt = txq->nb_tx_desc;
2930 /* Loop through swr_ring to count the amount of
2931 * freeable mubfs and packets.
2933 for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2934 for (i = 0; i < nb_tx_to_clean &&
2935 pkt_cnt < free_cnt &&
2936 tx_id != tx_last; i++) {
2937 if (swr_ring[tx_id].mbuf != NULL) {
2938 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2939 swr_ring[tx_id].mbuf = NULL;
2942 * last segment in the packet,
2943 * increment packet count
2945 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2948 tx_id = swr_ring[tx_id].next_id;
2951 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2952 txq->nb_tx_free || tx_id == tx_last)
2955 if (pkt_cnt < free_cnt) {
2956 if (ice_xmit_cleanup(txq))
2959 nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2960 nb_tx_free_last = txq->nb_tx_free;
2964 return (int)pkt_cnt;
2969 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2970 uint32_t free_cnt __rte_unused)
2977 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2982 if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2983 free_cnt = txq->nb_tx_desc;
2985 cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2987 for (i = 0; i < cnt; i += n) {
2988 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2991 n = ice_tx_free_bufs(txq);
3001 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
3003 struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
3004 struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
3005 struct ice_adapter *ad =
3006 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3009 if (ad->tx_vec_allowed)
3010 return ice_tx_done_cleanup_vec(q, free_cnt);
3012 if (ad->tx_simple_allowed)
3013 return ice_tx_done_cleanup_simple(q, free_cnt);
3015 return ice_tx_done_cleanup_full(q, free_cnt);
3018 /* Populate 4 descriptors with data from 4 mbufs */
3020 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3025 for (i = 0; i < 4; i++, txdp++, pkts++) {
3026 dma_addr = rte_mbuf_data_iova(*pkts);
3027 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3028 txdp->cmd_type_offset_bsz =
3029 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3030 (*pkts)->data_len, 0);
3034 /* Populate 1 descriptor with data from 1 mbuf */
3036 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3040 dma_addr = rte_mbuf_data_iova(*pkts);
3041 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3042 txdp->cmd_type_offset_bsz =
3043 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3044 (*pkts)->data_len, 0);
3048 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
3051 volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
3052 struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
3053 const int N_PER_LOOP = 4;
3054 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
3055 int mainpart, leftover;
3059 * Process most of the packets in chunks of N pkts. Any
3060 * leftover packets will get processed one at a time.
3062 mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
3063 leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
3064 for (i = 0; i < mainpart; i += N_PER_LOOP) {
3065 /* Copy N mbuf pointers to the S/W ring */
3066 for (j = 0; j < N_PER_LOOP; ++j)
3067 (txep + i + j)->mbuf = *(pkts + i + j);
3068 tx4(txdp + i, pkts + i);
3071 if (unlikely(leftover > 0)) {
3072 for (i = 0; i < leftover; ++i) {
3073 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
3074 tx1(txdp + mainpart + i, pkts + mainpart + i);
3079 static inline uint16_t
3080 tx_xmit_pkts(struct ice_tx_queue *txq,
3081 struct rte_mbuf **tx_pkts,
3084 volatile struct ice_tx_desc *txr = txq->tx_ring;
3088 * Begin scanning the H/W ring for done descriptors when the number
3089 * of available descriptors drops below tx_free_thresh. For each done
3090 * descriptor, free the associated buffer.
3092 if (txq->nb_tx_free < txq->tx_free_thresh)
3093 ice_tx_free_bufs(txq);
3095 /* Use available descriptor only */
3096 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
3097 if (unlikely(!nb_pkts))
3100 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
3101 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
3102 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
3103 ice_tx_fill_hw_ring(txq, tx_pkts, n);
3104 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3105 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3107 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3111 /* Fill hardware descriptor ring with mbuf data */
3112 ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3113 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3115 /* Determin if RS bit needs to be set */
3116 if (txq->tx_tail > txq->tx_next_rs) {
3117 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3118 rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3121 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3122 if (txq->tx_next_rs >= txq->nb_tx_desc)
3123 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3126 if (txq->tx_tail >= txq->nb_tx_desc)
3129 /* Update the tx tail register */
3130 ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3136 ice_xmit_pkts_simple(void *tx_queue,
3137 struct rte_mbuf **tx_pkts,
3142 if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3143 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3147 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3150 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3151 &tx_pkts[nb_tx], num);
3152 nb_tx = (uint16_t)(nb_tx + ret);
3153 nb_pkts = (uint16_t)(nb_pkts - ret);
3162 ice_set_rx_function(struct rte_eth_dev *dev)
3164 PMD_INIT_FUNC_TRACE();
3165 struct ice_adapter *ad =
3166 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3168 struct ice_rx_queue *rxq;
3170 int rx_check_ret = -1;
3172 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3173 ad->rx_use_avx512 = false;
3174 ad->rx_use_avx2 = false;
3175 rx_check_ret = ice_rx_vec_dev_check(dev);
3178 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3179 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3180 ad->rx_vec_allowed = true;
3181 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3182 rxq = dev->data->rx_queues[i];
3183 if (rxq && ice_rxq_vec_setup(rxq)) {
3184 ad->rx_vec_allowed = false;
3189 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3190 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3191 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3192 #ifdef CC_AVX512_SUPPORT
3193 ad->rx_use_avx512 = true;
3196 "AVX512 is not supported in build env");
3198 if (!ad->rx_use_avx512 &&
3199 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3200 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3201 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3202 ad->rx_use_avx2 = true;
3205 ad->rx_vec_allowed = false;
3209 if (ad->rx_vec_allowed) {
3210 if (dev->data->scattered_rx) {
3211 if (ad->rx_use_avx512) {
3212 #ifdef CC_AVX512_SUPPORT
3213 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3215 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3216 dev->data->port_id);
3218 ice_recv_scattered_pkts_vec_avx512_offload;
3221 "Using AVX512 Vector Scattered Rx (port %d).",
3222 dev->data->port_id);
3224 ice_recv_scattered_pkts_vec_avx512;
3227 } else if (ad->rx_use_avx2) {
3228 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3230 "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3231 dev->data->port_id);
3233 ice_recv_scattered_pkts_vec_avx2_offload;
3236 "Using AVX2 Vector Scattered Rx (port %d).",
3237 dev->data->port_id);
3239 ice_recv_scattered_pkts_vec_avx2;
3243 "Using Vector Scattered Rx (port %d).",
3244 dev->data->port_id);
3245 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3248 if (ad->rx_use_avx512) {
3249 #ifdef CC_AVX512_SUPPORT
3250 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3252 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3253 dev->data->port_id);
3255 ice_recv_pkts_vec_avx512_offload;
3258 "Using AVX512 Vector Rx (port %d).",
3259 dev->data->port_id);
3261 ice_recv_pkts_vec_avx512;
3264 } else if (ad->rx_use_avx2) {
3265 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3267 "Using AVX2 OFFLOAD Vector Rx (port %d).",
3268 dev->data->port_id);
3270 ice_recv_pkts_vec_avx2_offload;
3273 "Using AVX2 Vector Rx (port %d).",
3274 dev->data->port_id);
3276 ice_recv_pkts_vec_avx2;
3280 "Using Vector Rx (port %d).",
3281 dev->data->port_id);
3282 dev->rx_pkt_burst = ice_recv_pkts_vec;
3290 if (dev->data->scattered_rx) {
3291 /* Set the non-LRO scattered function */
3293 "Using a Scattered function on port %d.",
3294 dev->data->port_id);
3295 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3296 } else if (ad->rx_bulk_alloc_allowed) {
3298 "Rx Burst Bulk Alloc Preconditions are "
3299 "satisfied. Rx Burst Bulk Alloc function "
3300 "will be used on port %d.",
3301 dev->data->port_id);
3302 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3305 "Rx Burst Bulk Alloc Preconditions are not "
3306 "satisfied, Normal Rx will be used on port %d.",
3307 dev->data->port_id);
3308 dev->rx_pkt_burst = ice_recv_pkts;
3312 static const struct {
3313 eth_rx_burst_t pkt_burst;
3315 } ice_rx_burst_infos[] = {
3316 { ice_recv_scattered_pkts, "Scalar Scattered" },
3317 { ice_recv_pkts_bulk_alloc, "Scalar Bulk Alloc" },
3318 { ice_recv_pkts, "Scalar" },
3320 #ifdef CC_AVX512_SUPPORT
3321 { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3322 { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3323 { ice_recv_pkts_vec_avx512, "Vector AVX512" },
3324 { ice_recv_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3326 { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3327 { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3328 { ice_recv_pkts_vec_avx2, "Vector AVX2" },
3329 { ice_recv_pkts_vec_avx2_offload, "Offload Vector AVX2" },
3330 { ice_recv_scattered_pkts_vec, "Vector SSE Scattered" },
3331 { ice_recv_pkts_vec, "Vector SSE" },
3336 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3337 struct rte_eth_burst_mode *mode)
3339 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3343 for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3344 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3345 snprintf(mode->info, sizeof(mode->info), "%s",
3346 ice_rx_burst_infos[i].info);
3356 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3358 struct ice_adapter *ad =
3359 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3361 /* Use a simple Tx queue if possible (only fast free is allowed) */
3362 ad->tx_simple_allowed =
3364 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3365 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3367 if (ad->tx_simple_allowed)
3368 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3372 "Simple Tx can NOT be enabled on Tx queue %u.",
3376 /*********************************************************************
3380 **********************************************************************/
3381 /* The default values of TSO MSS */
3382 #define ICE_MIN_TSO_MSS 64
3383 #define ICE_MAX_TSO_MSS 9728
3384 #define ICE_MAX_TSO_FRAME_SIZE 262144
3386 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3393 for (i = 0; i < nb_pkts; i++) {
3395 ol_flags = m->ol_flags;
3397 if (ol_flags & PKT_TX_TCP_SEG &&
3398 (m->tso_segsz < ICE_MIN_TSO_MSS ||
3399 m->tso_segsz > ICE_MAX_TSO_MSS ||
3400 m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3402 * MSS outside the range are considered malicious
3408 #ifdef RTE_ETHDEV_DEBUG_TX
3409 ret = rte_validate_tx_offload(m);
3415 ret = rte_net_intel_cksum_prepare(m);
3425 ice_set_tx_function(struct rte_eth_dev *dev)
3427 struct ice_adapter *ad =
3428 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3430 struct ice_tx_queue *txq;
3432 int tx_check_ret = -1;
3434 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3435 ad->tx_use_avx2 = false;
3436 ad->tx_use_avx512 = false;
3437 tx_check_ret = ice_tx_vec_dev_check(dev);
3438 if (tx_check_ret >= 0 &&
3439 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3440 ad->tx_vec_allowed = true;
3442 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3443 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3444 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3445 #ifdef CC_AVX512_SUPPORT
3446 ad->tx_use_avx512 = true;
3449 "AVX512 is not supported in build env");
3451 if (!ad->tx_use_avx512 &&
3452 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3453 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3454 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3455 ad->tx_use_avx2 = true;
3457 if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3458 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3459 ad->tx_vec_allowed = false;
3461 if (ad->tx_vec_allowed) {
3462 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3463 txq = dev->data->tx_queues[i];
3464 if (txq && ice_txq_vec_setup(txq)) {
3465 ad->tx_vec_allowed = false;
3471 ad->tx_vec_allowed = false;
3475 if (ad->tx_vec_allowed) {
3476 dev->tx_pkt_prepare = NULL;
3477 if (ad->tx_use_avx512) {
3478 #ifdef CC_AVX512_SUPPORT
3479 if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3481 "Using AVX512 OFFLOAD Vector Tx (port %d).",
3482 dev->data->port_id);
3484 ice_xmit_pkts_vec_avx512_offload;
3485 dev->tx_pkt_prepare = ice_prep_pkts;
3488 "Using AVX512 Vector Tx (port %d).",
3489 dev->data->port_id);
3490 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3494 if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3496 "Using AVX2 OFFLOAD Vector Tx (port %d).",
3497 dev->data->port_id);
3499 ice_xmit_pkts_vec_avx2_offload;
3500 dev->tx_pkt_prepare = ice_prep_pkts;
3502 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3503 ad->tx_use_avx2 ? "avx2 " : "",
3504 dev->data->port_id);
3505 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3506 ice_xmit_pkts_vec_avx2 :
3515 if (ad->tx_simple_allowed) {
3516 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3517 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3518 dev->tx_pkt_prepare = NULL;
3520 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3521 dev->tx_pkt_burst = ice_xmit_pkts;
3522 dev->tx_pkt_prepare = ice_prep_pkts;
3526 static const struct {
3527 eth_tx_burst_t pkt_burst;
3529 } ice_tx_burst_infos[] = {
3530 { ice_xmit_pkts_simple, "Scalar Simple" },
3531 { ice_xmit_pkts, "Scalar" },
3533 #ifdef CC_AVX512_SUPPORT
3534 { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3535 { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3537 { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3538 { ice_xmit_pkts_vec, "Vector SSE" },
3543 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3544 struct rte_eth_burst_mode *mode)
3546 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3550 for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3551 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3552 snprintf(mode->info, sizeof(mode->info), "%s",
3553 ice_tx_burst_infos[i].info);
3562 /* For each value it means, datasheet of hardware can tell more details
3564 * @note: fix ice_dev_supported_ptypes_get() if any change here.
3566 static inline uint32_t
3567 ice_get_default_pkt_type(uint16_t ptype)
3569 static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3570 __rte_cache_aligned = {
3573 [1] = RTE_PTYPE_L2_ETHER,
3574 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3575 /* [3] - [5] reserved */
3576 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3577 /* [7] - [10] reserved */
3578 [11] = RTE_PTYPE_L2_ETHER_ARP,
3579 /* [12] - [21] reserved */
3581 /* Non tunneled IPv4 */
3582 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3584 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3585 RTE_PTYPE_L4_NONFRAG,
3586 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3589 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3591 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3593 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3597 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3598 RTE_PTYPE_TUNNEL_IP |
3599 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3600 RTE_PTYPE_INNER_L4_FRAG,
3601 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3602 RTE_PTYPE_TUNNEL_IP |
3603 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3604 RTE_PTYPE_INNER_L4_NONFRAG,
3605 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3606 RTE_PTYPE_TUNNEL_IP |
3607 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3608 RTE_PTYPE_INNER_L4_UDP,
3610 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3611 RTE_PTYPE_TUNNEL_IP |
3612 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3613 RTE_PTYPE_INNER_L4_TCP,
3614 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3615 RTE_PTYPE_TUNNEL_IP |
3616 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3617 RTE_PTYPE_INNER_L4_SCTP,
3618 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3619 RTE_PTYPE_TUNNEL_IP |
3620 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3621 RTE_PTYPE_INNER_L4_ICMP,
3624 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3625 RTE_PTYPE_TUNNEL_IP |
3626 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3627 RTE_PTYPE_INNER_L4_FRAG,
3628 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3629 RTE_PTYPE_TUNNEL_IP |
3630 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3631 RTE_PTYPE_INNER_L4_NONFRAG,
3632 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3633 RTE_PTYPE_TUNNEL_IP |
3634 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3635 RTE_PTYPE_INNER_L4_UDP,
3637 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3638 RTE_PTYPE_TUNNEL_IP |
3639 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3640 RTE_PTYPE_INNER_L4_TCP,
3641 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3642 RTE_PTYPE_TUNNEL_IP |
3643 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3644 RTE_PTYPE_INNER_L4_SCTP,
3645 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3646 RTE_PTYPE_TUNNEL_IP |
3647 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3648 RTE_PTYPE_INNER_L4_ICMP,
3650 /* IPv4 --> GRE/Teredo/VXLAN */
3651 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3652 RTE_PTYPE_TUNNEL_GRENAT,
3654 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3655 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3656 RTE_PTYPE_TUNNEL_GRENAT |
3657 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3658 RTE_PTYPE_INNER_L4_FRAG,
3659 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3660 RTE_PTYPE_TUNNEL_GRENAT |
3661 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3662 RTE_PTYPE_INNER_L4_NONFRAG,
3663 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3664 RTE_PTYPE_TUNNEL_GRENAT |
3665 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3666 RTE_PTYPE_INNER_L4_UDP,
3668 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3669 RTE_PTYPE_TUNNEL_GRENAT |
3670 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3671 RTE_PTYPE_INNER_L4_TCP,
3672 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3673 RTE_PTYPE_TUNNEL_GRENAT |
3674 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3675 RTE_PTYPE_INNER_L4_SCTP,
3676 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3677 RTE_PTYPE_TUNNEL_GRENAT |
3678 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3679 RTE_PTYPE_INNER_L4_ICMP,
3681 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3682 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3683 RTE_PTYPE_TUNNEL_GRENAT |
3684 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3685 RTE_PTYPE_INNER_L4_FRAG,
3686 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3687 RTE_PTYPE_TUNNEL_GRENAT |
3688 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3689 RTE_PTYPE_INNER_L4_NONFRAG,
3690 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3691 RTE_PTYPE_TUNNEL_GRENAT |
3692 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3693 RTE_PTYPE_INNER_L4_UDP,
3695 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3696 RTE_PTYPE_TUNNEL_GRENAT |
3697 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3698 RTE_PTYPE_INNER_L4_TCP,
3699 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3700 RTE_PTYPE_TUNNEL_GRENAT |
3701 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3702 RTE_PTYPE_INNER_L4_SCTP,
3703 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3704 RTE_PTYPE_TUNNEL_GRENAT |
3705 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3706 RTE_PTYPE_INNER_L4_ICMP,
3708 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3709 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3710 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3712 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3713 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3714 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3715 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3716 RTE_PTYPE_INNER_L4_FRAG,
3717 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3718 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3719 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3720 RTE_PTYPE_INNER_L4_NONFRAG,
3721 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3722 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3723 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3724 RTE_PTYPE_INNER_L4_UDP,
3726 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3727 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3728 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3729 RTE_PTYPE_INNER_L4_TCP,
3730 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3731 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3732 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3733 RTE_PTYPE_INNER_L4_SCTP,
3734 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3735 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3736 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3737 RTE_PTYPE_INNER_L4_ICMP,
3739 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3740 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3741 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3742 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3743 RTE_PTYPE_INNER_L4_FRAG,
3744 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3745 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3746 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3747 RTE_PTYPE_INNER_L4_NONFRAG,
3748 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3749 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3750 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3751 RTE_PTYPE_INNER_L4_UDP,
3753 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3754 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3755 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3756 RTE_PTYPE_INNER_L4_TCP,
3757 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3758 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3759 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3760 RTE_PTYPE_INNER_L4_SCTP,
3761 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3762 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3763 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3764 RTE_PTYPE_INNER_L4_ICMP,
3765 /* [73] - [87] reserved */
3767 /* Non tunneled IPv6 */
3768 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3770 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3771 RTE_PTYPE_L4_NONFRAG,
3772 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3775 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3777 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3779 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3783 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3784 RTE_PTYPE_TUNNEL_IP |
3785 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3786 RTE_PTYPE_INNER_L4_FRAG,
3787 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3788 RTE_PTYPE_TUNNEL_IP |
3789 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3790 RTE_PTYPE_INNER_L4_NONFRAG,
3791 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3792 RTE_PTYPE_TUNNEL_IP |
3793 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3794 RTE_PTYPE_INNER_L4_UDP,
3796 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3797 RTE_PTYPE_TUNNEL_IP |
3798 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3799 RTE_PTYPE_INNER_L4_TCP,
3800 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3801 RTE_PTYPE_TUNNEL_IP |
3802 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3803 RTE_PTYPE_INNER_L4_SCTP,
3804 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3805 RTE_PTYPE_TUNNEL_IP |
3806 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3807 RTE_PTYPE_INNER_L4_ICMP,
3810 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3811 RTE_PTYPE_TUNNEL_IP |
3812 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3813 RTE_PTYPE_INNER_L4_FRAG,
3814 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3815 RTE_PTYPE_TUNNEL_IP |
3816 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3817 RTE_PTYPE_INNER_L4_NONFRAG,
3818 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3819 RTE_PTYPE_TUNNEL_IP |
3820 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3821 RTE_PTYPE_INNER_L4_UDP,
3822 /* [105] reserved */
3823 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3824 RTE_PTYPE_TUNNEL_IP |
3825 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3826 RTE_PTYPE_INNER_L4_TCP,
3827 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3828 RTE_PTYPE_TUNNEL_IP |
3829 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3830 RTE_PTYPE_INNER_L4_SCTP,
3831 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3832 RTE_PTYPE_TUNNEL_IP |
3833 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3834 RTE_PTYPE_INNER_L4_ICMP,
3836 /* IPv6 --> GRE/Teredo/VXLAN */
3837 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3838 RTE_PTYPE_TUNNEL_GRENAT,
3840 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3841 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3842 RTE_PTYPE_TUNNEL_GRENAT |
3843 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3844 RTE_PTYPE_INNER_L4_FRAG,
3845 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3846 RTE_PTYPE_TUNNEL_GRENAT |
3847 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3848 RTE_PTYPE_INNER_L4_NONFRAG,
3849 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3850 RTE_PTYPE_TUNNEL_GRENAT |
3851 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3852 RTE_PTYPE_INNER_L4_UDP,
3853 /* [113] reserved */
3854 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3855 RTE_PTYPE_TUNNEL_GRENAT |
3856 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3857 RTE_PTYPE_INNER_L4_TCP,
3858 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3859 RTE_PTYPE_TUNNEL_GRENAT |
3860 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3861 RTE_PTYPE_INNER_L4_SCTP,
3862 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3863 RTE_PTYPE_TUNNEL_GRENAT |
3864 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3865 RTE_PTYPE_INNER_L4_ICMP,
3867 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3868 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3869 RTE_PTYPE_TUNNEL_GRENAT |
3870 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3871 RTE_PTYPE_INNER_L4_FRAG,
3872 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3873 RTE_PTYPE_TUNNEL_GRENAT |
3874 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3875 RTE_PTYPE_INNER_L4_NONFRAG,
3876 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3877 RTE_PTYPE_TUNNEL_GRENAT |
3878 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3879 RTE_PTYPE_INNER_L4_UDP,
3880 /* [120] reserved */
3881 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3882 RTE_PTYPE_TUNNEL_GRENAT |
3883 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3884 RTE_PTYPE_INNER_L4_TCP,
3885 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3886 RTE_PTYPE_TUNNEL_GRENAT |
3887 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3888 RTE_PTYPE_INNER_L4_SCTP,
3889 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3890 RTE_PTYPE_TUNNEL_GRENAT |
3891 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3892 RTE_PTYPE_INNER_L4_ICMP,
3894 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3895 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3896 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3898 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3899 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3900 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3901 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3902 RTE_PTYPE_INNER_L4_FRAG,
3903 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3904 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3905 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3906 RTE_PTYPE_INNER_L4_NONFRAG,
3907 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3908 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3909 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3910 RTE_PTYPE_INNER_L4_UDP,
3911 /* [128] reserved */
3912 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3913 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3914 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3915 RTE_PTYPE_INNER_L4_TCP,
3916 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3917 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3918 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3919 RTE_PTYPE_INNER_L4_SCTP,
3920 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3921 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3922 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3923 RTE_PTYPE_INNER_L4_ICMP,
3925 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3926 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3927 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3928 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3929 RTE_PTYPE_INNER_L4_FRAG,
3930 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3931 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3932 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3933 RTE_PTYPE_INNER_L4_NONFRAG,
3934 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3935 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3936 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3937 RTE_PTYPE_INNER_L4_UDP,
3938 /* [135] reserved */
3939 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3940 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3941 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3942 RTE_PTYPE_INNER_L4_TCP,
3943 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3944 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3945 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3946 RTE_PTYPE_INNER_L4_SCTP,
3947 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3948 RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3949 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3950 RTE_PTYPE_INNER_L4_ICMP,
3951 /* [139] - [299] reserved */
3954 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3955 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3957 /* PPPoE --> IPv4 */
3958 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3959 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3961 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3962 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3963 RTE_PTYPE_L4_NONFRAG,
3964 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3965 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3967 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3968 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3970 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3971 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3973 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3974 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3977 /* PPPoE --> IPv6 */
3978 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3979 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3981 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3982 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3983 RTE_PTYPE_L4_NONFRAG,
3984 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3985 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3987 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3988 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3990 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3991 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3993 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3994 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3996 /* [314] - [324] reserved */
3998 /* IPv4/IPv6 --> GTPC/GTPU */
3999 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4000 RTE_PTYPE_TUNNEL_GTPC,
4001 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4002 RTE_PTYPE_TUNNEL_GTPC,
4003 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4004 RTE_PTYPE_TUNNEL_GTPC,
4005 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4006 RTE_PTYPE_TUNNEL_GTPC,
4007 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4008 RTE_PTYPE_TUNNEL_GTPU,
4009 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4010 RTE_PTYPE_TUNNEL_GTPU,
4012 /* IPv4 --> GTPU --> IPv4 */
4013 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4014 RTE_PTYPE_TUNNEL_GTPU |
4015 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4016 RTE_PTYPE_INNER_L4_FRAG,
4017 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4018 RTE_PTYPE_TUNNEL_GTPU |
4019 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4020 RTE_PTYPE_INNER_L4_NONFRAG,
4021 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4022 RTE_PTYPE_TUNNEL_GTPU |
4023 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4024 RTE_PTYPE_INNER_L4_UDP,
4025 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4026 RTE_PTYPE_TUNNEL_GTPU |
4027 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4028 RTE_PTYPE_INNER_L4_TCP,
4029 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4030 RTE_PTYPE_TUNNEL_GTPU |
4031 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4032 RTE_PTYPE_INNER_L4_ICMP,
4034 /* IPv6 --> GTPU --> IPv4 */
4035 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4036 RTE_PTYPE_TUNNEL_GTPU |
4037 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4038 RTE_PTYPE_INNER_L4_FRAG,
4039 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4040 RTE_PTYPE_TUNNEL_GTPU |
4041 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4042 RTE_PTYPE_INNER_L4_NONFRAG,
4043 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4044 RTE_PTYPE_TUNNEL_GTPU |
4045 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4046 RTE_PTYPE_INNER_L4_UDP,
4047 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4048 RTE_PTYPE_TUNNEL_GTPU |
4049 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4050 RTE_PTYPE_INNER_L4_TCP,
4051 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4052 RTE_PTYPE_TUNNEL_GTPU |
4053 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4054 RTE_PTYPE_INNER_L4_ICMP,
4056 /* IPv4 --> GTPU --> IPv6 */
4057 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4058 RTE_PTYPE_TUNNEL_GTPU |
4059 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4060 RTE_PTYPE_INNER_L4_FRAG,
4061 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4062 RTE_PTYPE_TUNNEL_GTPU |
4063 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4064 RTE_PTYPE_INNER_L4_NONFRAG,
4065 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4066 RTE_PTYPE_TUNNEL_GTPU |
4067 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4068 RTE_PTYPE_INNER_L4_UDP,
4069 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4070 RTE_PTYPE_TUNNEL_GTPU |
4071 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4072 RTE_PTYPE_INNER_L4_TCP,
4073 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4074 RTE_PTYPE_TUNNEL_GTPU |
4075 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4076 RTE_PTYPE_INNER_L4_ICMP,
4078 /* IPv6 --> GTPU --> IPv6 */
4079 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4080 RTE_PTYPE_TUNNEL_GTPU |
4081 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4082 RTE_PTYPE_INNER_L4_FRAG,
4083 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4084 RTE_PTYPE_TUNNEL_GTPU |
4085 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4086 RTE_PTYPE_INNER_L4_NONFRAG,
4087 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4088 RTE_PTYPE_TUNNEL_GTPU |
4089 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4090 RTE_PTYPE_INNER_L4_UDP,
4091 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4092 RTE_PTYPE_TUNNEL_GTPU |
4093 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4094 RTE_PTYPE_INNER_L4_TCP,
4095 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4096 RTE_PTYPE_TUNNEL_GTPU |
4097 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4098 RTE_PTYPE_INNER_L4_ICMP,
4100 /* IPv4 --> UDP ECPRI */
4101 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4103 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4105 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4107 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4109 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4111 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4113 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4115 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4117 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4119 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4122 /* IPV6 --> UDP ECPRI */
4123 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4125 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4127 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4129 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4131 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4133 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4135 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4137 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4139 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4141 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4143 /* All others reserved */
4146 return type_table[ptype];
4150 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4152 struct ice_adapter *ad =
4153 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4156 for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4157 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4160 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4161 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4162 (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4163 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4164 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4166 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S 4
4167 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M \
4168 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4169 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S 5
4170 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M \
4171 (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4174 * check the programming status descriptor in rx queue.
4175 * done after Programming Flow Director is programmed on
4179 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4181 volatile union ice_32byte_rx_desc *rxdp;
4188 rxdp = (volatile union ice_32byte_rx_desc *)
4189 (&rxq->rx_ring[rxq->rx_tail]);
4190 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4191 rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4192 >> ICE_RXD_QW1_STATUS_S;
4194 if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4196 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4197 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4198 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4199 ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4201 if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4202 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4203 else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4204 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4208 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4209 ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4211 PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4215 rxdp->wb.qword1.status_error_len = 0;
4217 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4219 if (rxq->rx_tail == 0)
4220 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4222 ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4228 #define ICE_FDIR_MAX_WAIT_US 10000
4231 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4233 struct ice_tx_queue *txq = pf->fdir.txq;
4234 struct ice_rx_queue *rxq = pf->fdir.rxq;
4235 volatile struct ice_fltr_desc *fdirdp;
4236 volatile struct ice_tx_desc *txdp;
4240 fdirdp = (volatile struct ice_fltr_desc *)
4241 (&txq->tx_ring[txq->tx_tail]);
4242 fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4243 fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4245 txdp = &txq->tx_ring[txq->tx_tail + 1];
4246 txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4247 td_cmd = ICE_TX_DESC_CMD_EOP |
4248 ICE_TX_DESC_CMD_RS |
4249 ICE_TX_DESC_CMD_DUMMY;
4251 txdp->cmd_type_offset_bsz =
4252 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4255 if (txq->tx_tail >= txq->nb_tx_desc)
4257 /* Update the tx tail register */
4258 ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4259 for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4260 if ((txdp->cmd_type_offset_bsz &
4261 rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4262 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4266 if (i >= ICE_FDIR_MAX_WAIT_US) {
4268 "Failed to program FDIR filter: time out to get DD on tx queue.");
4272 for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4275 ret = ice_check_fdir_programming_status(rxq);
4283 "Failed to program FDIR filter: programming status reported.");