drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <ethdev_driver.h>
   6 #include <rte_net.h>
   7 #include <rte_vect.h>
   8
   9 #include "rte_pmd_ice.h"
  10 #include "ice_rxtx.h"
  11 #include "ice_rxtx_vec_common.h"
  12
  13 #define ICE_TX_CKSUM_OFFLOAD_MASK (              \
  14                 PKT_TX_IP_CKSUM |                \
  15                 PKT_TX_L4_MASK |                 \
  16                 PKT_TX_TCP_SEG |                 \
  17                 PKT_TX_OUTER_IP_CKSUM)
  18
  19 /* Offset of mbuf dynamic field for protocol extraction data */
  20 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  21
  22 /* Mask of mbuf dynamic flags for protocol extraction type */
  23 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  27 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  28 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  29
  30 static int
  31 ice_monitor_callback(const uint64_t value,
  32                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  33 {
  34         const uint64_t m = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
  35         /*
  36          * we expect the DD bit to be set to 1 if this descriptor was already
  37          * written to.
  38          */
  39         return (value & m) == m ? -1 : 0;
  40 }
  41
  42 int
  43 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  44 {
  45         volatile union ice_rx_flex_desc *rxdp;
  46         struct ice_rx_queue *rxq = rx_queue;
  47         uint16_t desc;
  48
  49         desc = rxq->rx_tail;
  50         rxdp = &rxq->rx_ring[desc];
  51         /* watch for changes in status bit */
  52         pmc->addr = &rxdp->wb.status_error0;
  53
  54         /* comparison callback */
  55         pmc->fn = ice_monitor_callback;
  56
  57         /* register is 16-bit */
  58         pmc->size = sizeof(uint16_t);
  59
  60         return 0;
  61 }
  62
  63
  64 static inline uint8_t
  65 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  66 {
  67         static uint8_t rxdid_map[] = {
  68                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_OVS,
  69                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  70                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  71                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  72                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  73                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  74                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  75         };
  76
  77         return xtr_type < RTE_DIM(rxdid_map) ?
  78                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
  79 }
  80
  81 static inline void
  82 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
  83                                        struct rte_mbuf *mb,
  84                                        volatile union ice_rx_flex_desc *rxdp)
  85 {
  86         volatile struct ice_32b_rx_flex_desc_comms *desc =
  87                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
  88         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
  89
  90         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  91                 mb->ol_flags |= PKT_RX_RSS_HASH;
  92                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  93         }
  94
  95 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  96         if (desc->flow_id != 0xFFFFFFFF) {
  97                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
  98                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  99         }
 100 #endif
 101 }
 102
 103 static inline void
 104 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
 105                                    struct rte_mbuf *mb,
 106                                    volatile union ice_rx_flex_desc *rxdp)
 107 {
 108         volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
 109                         (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
 110 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 111         uint16_t stat_err;
 112 #endif
 113
 114         if (desc->flow_id != 0xFFFFFFFF) {
 115                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 116                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 117         }
 118
 119 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 120         stat_err = rte_le_to_cpu_16(desc->status_error0);
 121         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 122                 mb->ol_flags |= PKT_RX_RSS_HASH;
 123                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 124         }
 125 #endif
 126 }
 127
 128 static inline void
 129 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
 130                                       struct rte_mbuf *mb,
 131                                       volatile union ice_rx_flex_desc *rxdp)
 132 {
 133         volatile struct ice_32b_rx_flex_desc_comms *desc =
 134                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 135         uint16_t stat_err;
 136
 137         stat_err = rte_le_to_cpu_16(desc->status_error0);
 138         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 139                 mb->ol_flags |= PKT_RX_RSS_HASH;
 140                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 141         }
 142
 143 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 144         if (desc->flow_id != 0xFFFFFFFF) {
 145                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 146                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 147         }
 148
 149         if (rxq->xtr_ol_flag) {
 150                 uint32_t metadata = 0;
 151
 152                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 153
 154                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 155                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 156
 157                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 158                         metadata |=
 159                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 160
 161                 if (metadata) {
 162                         mb->ol_flags |= rxq->xtr_ol_flag;
 163
 164                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 165                 }
 166         }
 167 #endif
 168 }
 169
 170 static inline void
 171 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
 172                                       struct rte_mbuf *mb,
 173                                       volatile union ice_rx_flex_desc *rxdp)
 174 {
 175         volatile struct ice_32b_rx_flex_desc_comms *desc =
 176                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 177         uint16_t stat_err;
 178
 179         stat_err = rte_le_to_cpu_16(desc->status_error0);
 180         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 181                 mb->ol_flags |= PKT_RX_RSS_HASH;
 182                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 183         }
 184
 185 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 186         if (desc->flow_id != 0xFFFFFFFF) {
 187                 mb->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
 188                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 189         }
 190
 191         if (rxq->xtr_ol_flag) {
 192                 uint32_t metadata = 0;
 193
 194                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 195                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 196                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 197                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 198
 199                 if (metadata) {
 200                         mb->ol_flags |= rxq->xtr_ol_flag;
 201
 202                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 203                 }
 204         }
 205 #endif
 206 }
 207
 208 void
 209 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
 210 {
 211         switch (rxdid) {
 212         case ICE_RXDID_COMMS_AUX_VLAN:
 213                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
 214                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 215                 break;
 216
 217         case ICE_RXDID_COMMS_AUX_IPV4:
 218                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
 219                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 220                 break;
 221
 222         case ICE_RXDID_COMMS_AUX_IPV6:
 223                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
 224                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 225                 break;
 226
 227         case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
 228                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
 229                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 230                 break;
 231
 232         case ICE_RXDID_COMMS_AUX_TCP:
 233                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
 234                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v1;
 235                 break;
 236
 237         case ICE_RXDID_COMMS_AUX_IP_OFFSET:
 238                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
 239                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_aux_v2;
 240                 break;
 241
 242         case ICE_RXDID_COMMS_GENERIC:
 243                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_generic;
 244                 break;
 245
 246         case ICE_RXDID_COMMS_OVS:
 247                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 248                 break;
 249
 250         default:
 251                 /* update this according to the RXDID for PROTO_XTR_NONE */
 252                 rxq->rxd_to_pkt_fields = ice_rxd_to_pkt_fields_by_comms_ovs;
 253                 break;
 254         }
 255
 256         if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
 257                 rxq->xtr_ol_flag = 0;
 258 }
 259
 260 static enum ice_status
 261 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
 262 {
 263         struct ice_vsi *vsi = rxq->vsi;
 264         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 265         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
 266         struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
 267         struct ice_rlan_ctx rx_ctx;
 268         enum ice_status err;
 269         uint16_t buf_size;
 270         struct rte_eth_rxmode *rxmode = &dev_data->dev_conf.rxmode;
 271         uint32_t rxdid = ICE_RXDID_COMMS_OVS;
 272         uint32_t regval;
 273
 274         /* Set buffer size as the head split is disabled. */
 275         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 276                               RTE_PKTMBUF_HEADROOM);
 277         rxq->rx_hdr_len = 0;
 278         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
 279         rxq->max_pkt_len = RTE_MIN((uint32_t)
 280                                    ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
 281                                    dev_data->dev_conf.rxmode.max_rx_pkt_len);
 282
 283         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
 284                 if (rxq->max_pkt_len <= ICE_ETH_MAX_LEN ||
 285                     rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 286                         PMD_DRV_LOG(ERR, "maximum packet length must "
 287                                     "be larger than %u and smaller than %u,"
 288                                     "as jumbo frame is enabled",
 289                                     (uint32_t)ICE_ETH_MAX_LEN,
 290                                     (uint32_t)ICE_FRAME_SIZE_MAX);
 291                         return -EINVAL;
 292                 }
 293         } else {
 294                 if (rxq->max_pkt_len < RTE_ETHER_MIN_LEN ||
 295                     rxq->max_pkt_len > ICE_ETH_MAX_LEN) {
 296                         PMD_DRV_LOG(ERR, "maximum packet length must be "
 297                                     "larger than %u and smaller than %u, "
 298                                     "as jumbo frame is disabled",
 299                                     (uint32_t)RTE_ETHER_MIN_LEN,
 300                                     (uint32_t)ICE_ETH_MAX_LEN);
 301                         return -EINVAL;
 302                 }
 303         }
 304
 305         if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
 306                 /* Register mbuf field and flag for Rx timestamp */
 307                 err = rte_mbuf_dyn_rx_timestamp_register(
 308                                 &ice_timestamp_dynfield_offset,
 309                                 &ice_timestamp_dynflag);
 310                 if (err) {
 311                         PMD_DRV_LOG(ERR,
 312                                 "Cannot register mbuf field/flag for timestamp");
 313                         return -EINVAL;
 314                 }
 315         }
 316
 317         memset(&rx_ctx, 0, sizeof(rx_ctx));
 318
 319         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 320         rx_ctx.qlen = rxq->nb_rx_desc;
 321         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 322         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 323         rx_ctx.dtype = 0; /* No Header Split mode */
 324 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 325         rx_ctx.dsize = 1; /* 32B descriptors */
 326 #endif
 327         rx_ctx.rxmax = rxq->max_pkt_len;
 328         /* TPH: Transaction Layer Packet (TLP) processing hints */
 329         rx_ctx.tphrdesc_ena = 1;
 330         rx_ctx.tphwdesc_ena = 1;
 331         rx_ctx.tphdata_ena = 1;
 332         rx_ctx.tphhead_ena = 1;
 333         /* Low Receive Queue Threshold defined in 64 descriptors units.
 334          * When the number of free descriptors goes below the lrxqthresh,
 335          * an immediate interrupt is triggered.
 336          */
 337         rx_ctx.lrxqthresh = 2;
 338         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 339         rx_ctx.l2tsel = 1;
 340         rx_ctx.showiv = 0;
 341         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 342
 343         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 344
 345         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 346                     rxq->port_id, rxq->queue_id, rxdid);
 347
 348         if (!(pf->supported_rxdid & BIT(rxdid))) {
 349                 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
 350                             rxdid);
 351                 return -EINVAL;
 352         }
 353
 354         ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
 355
 356         /* Enable Flexible Descriptors in the queue context which
 357          * allows this driver to select a specific receive descriptor format
 358          */
 359         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 360                 QRXFLXP_CNTXT_RXDID_IDX_M;
 361
 362         /* increasing context priority to pick up profile ID;
 363          * default is 0x01; setting to 0x03 to ensure profile
 364          * is programming if prev context is of same priority
 365          */
 366         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 367                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 368
 369         if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP)
 370                 regval |= QRXFLXP_CNTXT_TS_M;
 371
 372         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 373
 374         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 375         if (err) {
 376                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 377                             rxq->queue_id);
 378                 return -EINVAL;
 379         }
 380         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 381         if (err) {
 382                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 383                             rxq->queue_id);
 384                 return -EINVAL;
 385         }
 386
 387         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 388                               RTE_PKTMBUF_HEADROOM);
 389
 390         /* Check if scattered RX needs to be used. */
 391         if (rxq->max_pkt_len > buf_size)
 392                 dev_data->scattered_rx = 1;
 393
 394         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 395
 396         /* Init the Rx tail register*/
 397         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 398
 399         return 0;
 400 }
 401
 402 /* Allocate mbufs for all descriptors in rx queue */
 403 static int
 404 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 405 {
 406         struct ice_rx_entry *rxe = rxq->sw_ring;
 407         uint64_t dma_addr;
 408         uint16_t i;
 409
 410         for (i = 0; i < rxq->nb_rx_desc; i++) {
 411                 volatile union ice_rx_flex_desc *rxd;
 412                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 413
 414                 if (unlikely(!mbuf)) {
 415                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 416                         return -ENOMEM;
 417                 }
 418
 419                 rte_mbuf_refcnt_set(mbuf, 1);
 420                 mbuf->next = NULL;
 421                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 422                 mbuf->nb_segs = 1;
 423                 mbuf->port = rxq->port_id;
 424
 425                 dma_addr =
 426                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 427
 428                 rxd = &rxq->rx_ring[i];
 429                 rxd->read.pkt_addr = dma_addr;
 430                 rxd->read.hdr_addr = 0;
 431 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 432                 rxd->read.rsvd1 = 0;
 433                 rxd->read.rsvd2 = 0;
 434 #endif
 435                 rxe[i].mbuf = mbuf;
 436         }
 437
 438         return 0;
 439 }
 440
 441 /* Free all mbufs for descriptors in rx queue */
 442 static void
 443 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 444 {
 445         uint16_t i;
 446
 447         if (!rxq || !rxq->sw_ring) {
 448                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 449                 return;
 450         }
 451
 452         for (i = 0; i < rxq->nb_rx_desc; i++) {
 453                 if (rxq->sw_ring[i].mbuf) {
 454                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 455                         rxq->sw_ring[i].mbuf = NULL;
 456                 }
 457         }
 458         if (rxq->rx_nb_avail == 0)
 459                 return;
 460         for (i = 0; i < rxq->rx_nb_avail; i++)
 461                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 462
 463         rxq->rx_nb_avail = 0;
 464 }
 465
 466 /* turn on or off rx queue
 467  * @q_idx: queue index in pf scope
 468  * @on: turn on or off the queue
 469  */
 470 static int
 471 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 472 {
 473         uint32_t reg;
 474         uint16_t j;
 475
 476         /* QRX_CTRL = QRX_ENA */
 477         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 478
 479         if (on) {
 480                 if (reg & QRX_CTRL_QENA_STAT_M)
 481                         return 0; /* Already on, skip */
 482                 reg |= QRX_CTRL_QENA_REQ_M;
 483         } else {
 484                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 485                         return 0; /* Already off, skip */
 486                 reg &= ~QRX_CTRL_QENA_REQ_M;
 487         }
 488
 489         /* Write the register */
 490         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 491         /* Check the result. It is said that QENA_STAT
 492          * follows the QENA_REQ not more than 10 use.
 493          * TODO: need to change the wait counter later
 494          */
 495         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 496                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 497                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 498                 if (on) {
 499                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 500                             (reg & QRX_CTRL_QENA_STAT_M))
 501                                 break;
 502                 } else {
 503                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 504                             !(reg & QRX_CTRL_QENA_STAT_M))
 505                                 break;
 506                 }
 507         }
 508
 509         /* Check if it is timeout */
 510         if (j >= ICE_CHK_Q_ENA_COUNT) {
 511                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 512                             (on ? "enable" : "disable"), q_idx);
 513                 return -ETIMEDOUT;
 514         }
 515
 516         return 0;
 517 }
 518
 519 static inline int
 520 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 521 {
 522         int ret = 0;
 523
 524         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 525                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 526                              "rxq->rx_free_thresh=%d, "
 527                              "ICE_RX_MAX_BURST=%d",
 528                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 529                 ret = -EINVAL;
 530         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 531                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 532                              "rxq->rx_free_thresh=%d, "
 533                              "rxq->nb_rx_desc=%d",
 534                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 535                 ret = -EINVAL;
 536         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 537                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 538                              "rxq->nb_rx_desc=%d, "
 539                              "rxq->rx_free_thresh=%d",
 540                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 541                 ret = -EINVAL;
 542         }
 543
 544         return ret;
 545 }
 546
 547 /* reset fields in ice_rx_queue back to default */
 548 static void
 549 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 550 {
 551         unsigned int i;
 552         uint16_t len;
 553
 554         if (!rxq) {
 555                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 556                 return;
 557         }
 558
 559         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 560
 561         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 562                 ((volatile char *)rxq->rx_ring)[i] = 0;
 563
 564         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 565         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 566                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 567
 568         rxq->rx_nb_avail = 0;
 569         rxq->rx_next_avail = 0;
 570         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 571
 572         rxq->rx_tail = 0;
 573         rxq->nb_rx_hold = 0;
 574         rxq->pkt_first_seg = NULL;
 575         rxq->pkt_last_seg = NULL;
 576
 577         rxq->rxrearm_start = 0;
 578         rxq->rxrearm_nb = 0;
 579 }
 580
 581 int
 582 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 583 {
 584         struct ice_rx_queue *rxq;
 585         int err;
 586         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 587
 588         PMD_INIT_FUNC_TRACE();
 589
 590         if (rx_queue_id >= dev->data->nb_rx_queues) {
 591                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 592                             rx_queue_id, dev->data->nb_rx_queues);
 593                 return -EINVAL;
 594         }
 595
 596         rxq = dev->data->rx_queues[rx_queue_id];
 597         if (!rxq || !rxq->q_set) {
 598                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 599                             rx_queue_id);
 600                 return -EINVAL;
 601         }
 602
 603         err = ice_program_hw_rx_queue(rxq);
 604         if (err) {
 605                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 606                             rx_queue_id);
 607                 return -EIO;
 608         }
 609
 610         err = ice_alloc_rx_queue_mbufs(rxq);
 611         if (err) {
 612                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 613                 return -ENOMEM;
 614         }
 615
 616         /* Init the RX tail register. */
 617         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 618
 619         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 620         if (err) {
 621                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 622                             rx_queue_id);
 623
 624                 rxq->rx_rel_mbufs(rxq);
 625                 ice_reset_rx_queue(rxq);
 626                 return -EINVAL;
 627         }
 628
 629         dev->data->rx_queue_state[rx_queue_id] =
 630                 RTE_ETH_QUEUE_STATE_STARTED;
 631
 632         return 0;
 633 }
 634
 635 int
 636 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 637 {
 638         struct ice_rx_queue *rxq;
 639         int err;
 640         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 641
 642         if (rx_queue_id < dev->data->nb_rx_queues) {
 643                 rxq = dev->data->rx_queues[rx_queue_id];
 644
 645                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 646                 if (err) {
 647                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 648                                     rx_queue_id);
 649                         return -EINVAL;
 650                 }
 651                 rxq->rx_rel_mbufs(rxq);
 652                 ice_reset_rx_queue(rxq);
 653                 dev->data->rx_queue_state[rx_queue_id] =
 654                         RTE_ETH_QUEUE_STATE_STOPPED;
 655         }
 656
 657         return 0;
 658 }
 659
 660 int
 661 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 662 {
 663         struct ice_tx_queue *txq;
 664         int err;
 665         struct ice_vsi *vsi;
 666         struct ice_hw *hw;
 667         struct ice_aqc_add_tx_qgrp *txq_elem;
 668         struct ice_tlan_ctx tx_ctx;
 669         int buf_len;
 670
 671         PMD_INIT_FUNC_TRACE();
 672
 673         if (tx_queue_id >= dev->data->nb_tx_queues) {
 674                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 675                             tx_queue_id, dev->data->nb_tx_queues);
 676                 return -EINVAL;
 677         }
 678
 679         txq = dev->data->tx_queues[tx_queue_id];
 680         if (!txq || !txq->q_set) {
 681                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 682                             tx_queue_id);
 683                 return -EINVAL;
 684         }
 685
 686         buf_len = ice_struct_size(txq_elem, txqs, 1);
 687         txq_elem = ice_malloc(hw, buf_len);
 688         if (!txq_elem)
 689                 return -ENOMEM;
 690
 691         vsi = txq->vsi;
 692         hw = ICE_VSI_TO_HW(vsi);
 693
 694         memset(&tx_ctx, 0, sizeof(tx_ctx));
 695         txq_elem->num_txqs = 1;
 696         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 697
 698         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 699         tx_ctx.qlen = txq->nb_tx_desc;
 700         tx_ctx.pf_num = hw->pf_id;
 701         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 702         tx_ctx.src_vsi = vsi->vsi_id;
 703         tx_ctx.port_num = hw->port_info->lport;
 704         tx_ctx.tso_ena = 1; /* tso enable */
 705         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 706         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 707
 708         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 709                     ice_tlan_ctx_info);
 710
 711         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 712
 713         /* Init the Tx tail register*/
 714         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 715
 716         /* Fix me, we assume TC always 0 here */
 717         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 718                         txq_elem, buf_len, NULL);
 719         if (err) {
 720                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 721                 rte_free(txq_elem);
 722                 return -EIO;
 723         }
 724         /* store the schedule node id */
 725         txq->q_teid = txq_elem->txqs[0].q_teid;
 726
 727         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 728
 729         rte_free(txq_elem);
 730         return 0;
 731 }
 732
 733 static enum ice_status
 734 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 735 {
 736         struct ice_vsi *vsi = rxq->vsi;
 737         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 738         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 739         struct ice_rlan_ctx rx_ctx;
 740         enum ice_status err;
 741         uint32_t regval;
 742
 743         rxq->rx_hdr_len = 0;
 744         rxq->rx_buf_len = 1024;
 745
 746         memset(&rx_ctx, 0, sizeof(rx_ctx));
 747
 748         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 749         rx_ctx.qlen = rxq->nb_rx_desc;
 750         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 751         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 752         rx_ctx.dtype = 0; /* No Header Split mode */
 753         rx_ctx.dsize = 1; /* 32B descriptors */
 754         rx_ctx.rxmax = ICE_ETH_MAX_LEN;
 755         /* TPH: Transaction Layer Packet (TLP) processing hints */
 756         rx_ctx.tphrdesc_ena = 1;
 757         rx_ctx.tphwdesc_ena = 1;
 758         rx_ctx.tphdata_ena = 1;
 759         rx_ctx.tphhead_ena = 1;
 760         /* Low Receive Queue Threshold defined in 64 descriptors units.
 761          * When the number of free descriptors goes below the lrxqthresh,
 762          * an immediate interrupt is triggered.
 763          */
 764         rx_ctx.lrxqthresh = 2;
 765         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 766         rx_ctx.l2tsel = 1;
 767         rx_ctx.showiv = 0;
 768         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 769
 770         /* Enable Flexible Descriptors in the queue context which
 771          * allows this driver to select a specific receive descriptor format
 772          */
 773         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 774                 QRXFLXP_CNTXT_RXDID_IDX_M;
 775
 776         /* increasing context priority to pick up profile ID;
 777          * default is 0x01; setting to 0x03 to ensure profile
 778          * is programming if prev context is of same priority
 779          */
 780         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 781                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 782
 783         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 784
 785         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 786         if (err) {
 787                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 788                             rxq->queue_id);
 789                 return -EINVAL;
 790         }
 791         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 792         if (err) {
 793                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 794                             rxq->queue_id);
 795                 return -EINVAL;
 796         }
 797
 798         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 799
 800         /* Init the Rx tail register*/
 801         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 802
 803         return 0;
 804 }
 805
 806 int
 807 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 808 {
 809         struct ice_rx_queue *rxq;
 810         int err;
 811         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 812         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 813
 814         PMD_INIT_FUNC_TRACE();
 815
 816         rxq = pf->fdir.rxq;
 817         if (!rxq || !rxq->q_set) {
 818                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 819                             rx_queue_id);
 820                 return -EINVAL;
 821         }
 822
 823         err = ice_fdir_program_hw_rx_queue(rxq);
 824         if (err) {
 825                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 826                             rx_queue_id);
 827                 return -EIO;
 828         }
 829
 830         /* Init the RX tail register. */
 831         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 832
 833         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 834         if (err) {
 835                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 836                             rx_queue_id);
 837
 838                 ice_reset_rx_queue(rxq);
 839                 return -EINVAL;
 840         }
 841
 842         return 0;
 843 }
 844
 845 int
 846 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 847 {
 848         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 849         struct ice_tx_queue *txq;
 850         int err;
 851         struct ice_vsi *vsi;
 852         struct ice_hw *hw;
 853         struct ice_aqc_add_tx_qgrp *txq_elem;
 854         struct ice_tlan_ctx tx_ctx;
 855         int buf_len;
 856
 857         PMD_INIT_FUNC_TRACE();
 858
 859         txq = pf->fdir.txq;
 860         if (!txq || !txq->q_set) {
 861                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 862                             tx_queue_id);
 863                 return -EINVAL;
 864         }
 865
 866         buf_len = ice_struct_size(txq_elem, txqs, 1);
 867         txq_elem = ice_malloc(hw, buf_len);
 868         if (!txq_elem)
 869                 return -ENOMEM;
 870
 871         vsi = txq->vsi;
 872         hw = ICE_VSI_TO_HW(vsi);
 873
 874         memset(&tx_ctx, 0, sizeof(tx_ctx));
 875         txq_elem->num_txqs = 1;
 876         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 877
 878         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 879         tx_ctx.qlen = txq->nb_tx_desc;
 880         tx_ctx.pf_num = hw->pf_id;
 881         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 882         tx_ctx.src_vsi = vsi->vsi_id;
 883         tx_ctx.port_num = hw->port_info->lport;
 884         tx_ctx.tso_ena = 1; /* tso enable */
 885         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 886         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 887
 888         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 889                     ice_tlan_ctx_info);
 890
 891         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 892
 893         /* Init the Tx tail register*/
 894         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 895
 896         /* Fix me, we assume TC always 0 here */
 897         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 898                               txq_elem, buf_len, NULL);
 899         if (err) {
 900                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 901                 rte_free(txq_elem);
 902                 return -EIO;
 903         }
 904         /* store the schedule node id */
 905         txq->q_teid = txq_elem->txqs[0].q_teid;
 906
 907         rte_free(txq_elem);
 908         return 0;
 909 }
 910
 911 /* Free all mbufs for descriptors in tx queue */
 912 static void
 913 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 914 {
 915         uint16_t i;
 916
 917         if (!txq || !txq->sw_ring) {
 918                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 919                 return;
 920         }
 921
 922         for (i = 0; i < txq->nb_tx_desc; i++) {
 923                 if (txq->sw_ring[i].mbuf) {
 924                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 925                         txq->sw_ring[i].mbuf = NULL;
 926                 }
 927         }
 928 }
 929
 930 static void
 931 ice_reset_tx_queue(struct ice_tx_queue *txq)
 932 {
 933         struct ice_tx_entry *txe;
 934         uint16_t i, prev, size;
 935
 936         if (!txq) {
 937                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 938                 return;
 939         }
 940
 941         txe = txq->sw_ring;
 942         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 943         for (i = 0; i < size; i++)
 944                 ((volatile char *)txq->tx_ring)[i] = 0;
 945
 946         prev = (uint16_t)(txq->nb_tx_desc - 1);
 947         for (i = 0; i < txq->nb_tx_desc; i++) {
 948                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 949
 950                 txd->cmd_type_offset_bsz =
 951                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 952                 txe[i].mbuf =  NULL;
 953                 txe[i].last_id = i;
 954                 txe[prev].next_id = i;
 955                 prev = i;
 956         }
 957
 958         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 959         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 960
 961         txq->tx_tail = 0;
 962         txq->nb_tx_used = 0;
 963
 964         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 965         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 966 }
 967
 968 int
 969 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 970 {
 971         struct ice_tx_queue *txq;
 972         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 973         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 974         struct ice_vsi *vsi = pf->main_vsi;
 975         enum ice_status status;
 976         uint16_t q_ids[1];
 977         uint32_t q_teids[1];
 978         uint16_t q_handle = tx_queue_id;
 979
 980         if (tx_queue_id >= dev->data->nb_tx_queues) {
 981                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 982                             tx_queue_id, dev->data->nb_tx_queues);
 983                 return -EINVAL;
 984         }
 985
 986         txq = dev->data->tx_queues[tx_queue_id];
 987         if (!txq) {
 988                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 989                             tx_queue_id);
 990                 return -EINVAL;
 991         }
 992
 993         q_ids[0] = txq->reg_idx;
 994         q_teids[0] = txq->q_teid;
 995
 996         /* Fix me, we assume TC always 0 here */
 997         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 998                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 999         if (status != ICE_SUCCESS) {
1000                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1001                 return -EINVAL;
1002         }
1003
1004         txq->tx_rel_mbufs(txq);
1005         ice_reset_tx_queue(txq);
1006         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1007
1008         return 0;
1009 }
1010
1011 int
1012 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1013 {
1014         struct ice_rx_queue *rxq;
1015         int err;
1016         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1017         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1018
1019         rxq = pf->fdir.rxq;
1020
1021         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1022         if (err) {
1023                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1024                             rx_queue_id);
1025                 return -EINVAL;
1026         }
1027         rxq->rx_rel_mbufs(rxq);
1028
1029         return 0;
1030 }
1031
1032 int
1033 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1034 {
1035         struct ice_tx_queue *txq;
1036         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1038         struct ice_vsi *vsi = pf->main_vsi;
1039         enum ice_status status;
1040         uint16_t q_ids[1];
1041         uint32_t q_teids[1];
1042         uint16_t q_handle = tx_queue_id;
1043
1044         txq = pf->fdir.txq;
1045         if (!txq) {
1046                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1047                             tx_queue_id);
1048                 return -EINVAL;
1049         }
1050         vsi = txq->vsi;
1051
1052         q_ids[0] = txq->reg_idx;
1053         q_teids[0] = txq->q_teid;
1054
1055         /* Fix me, we assume TC always 0 here */
1056         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1057                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1058         if (status != ICE_SUCCESS) {
1059                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1060                 return -EINVAL;
1061         }
1062
1063         txq->tx_rel_mbufs(txq);
1064
1065         return 0;
1066 }
1067
1068 int
1069 ice_rx_queue_setup(struct rte_eth_dev *dev,
1070                    uint16_t queue_idx,
1071                    uint16_t nb_desc,
1072                    unsigned int socket_id,
1073                    const struct rte_eth_rxconf *rx_conf,
1074                    struct rte_mempool *mp)
1075 {
1076         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1077         struct ice_adapter *ad =
1078                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1079         struct ice_vsi *vsi = pf->main_vsi;
1080         struct ice_rx_queue *rxq;
1081         const struct rte_memzone *rz;
1082         uint32_t ring_size;
1083         uint16_t len;
1084         int use_def_burst_func = 1;
1085         uint64_t offloads;
1086
1087         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1088             nb_desc > ICE_MAX_RING_DESC ||
1089             nb_desc < ICE_MIN_RING_DESC) {
1090                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1091                              "invalid", nb_desc);
1092                 return -EINVAL;
1093         }
1094
1095         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1096
1097         /* Free memory if needed */
1098         if (dev->data->rx_queues[queue_idx]) {
1099                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1100                 dev->data->rx_queues[queue_idx] = NULL;
1101         }
1102
1103         /* Allocate the rx queue data structure */
1104         rxq = rte_zmalloc_socket(NULL,
1105                                  sizeof(struct ice_rx_queue),
1106                                  RTE_CACHE_LINE_SIZE,
1107                                  socket_id);
1108         if (!rxq) {
1109                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1110                              "rx queue data structure");
1111                 return -ENOMEM;
1112         }
1113         rxq->mp = mp;
1114         rxq->nb_rx_desc = nb_desc;
1115         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1116         rxq->queue_id = queue_idx;
1117         rxq->offloads = offloads;
1118
1119         rxq->reg_idx = vsi->base_queue + queue_idx;
1120         rxq->port_id = dev->data->port_id;
1121         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1122                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1123         else
1124                 rxq->crc_len = 0;
1125
1126         rxq->drop_en = rx_conf->rx_drop_en;
1127         rxq->vsi = vsi;
1128         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1129         rxq->proto_xtr = pf->proto_xtr != NULL ?
1130                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1131
1132         /* Allocate the maximun number of RX ring hardware descriptor. */
1133         len = ICE_MAX_RING_DESC;
1134
1135         /**
1136          * Allocating a little more memory because vectorized/bulk_alloc Rx
1137          * functions doesn't check boundaries each time.
1138          */
1139         len += ICE_RX_MAX_BURST;
1140
1141         /* Allocate the maximum number of RX ring hardware descriptor. */
1142         ring_size = sizeof(union ice_rx_flex_desc) * len;
1143         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1144         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1145                                       ring_size, ICE_RING_BASE_ALIGN,
1146                                       socket_id);
1147         if (!rz) {
1148                 ice_rx_queue_release(rxq);
1149                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1150                 return -ENOMEM;
1151         }
1152
1153         /* Zero all the descriptors in the ring. */
1154         memset(rz->addr, 0, ring_size);
1155
1156         rxq->rx_ring_dma = rz->iova;
1157         rxq->rx_ring = rz->addr;
1158
1159         /* always reserve more for bulk alloc */
1160         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1161
1162         /* Allocate the software ring. */
1163         rxq->sw_ring = rte_zmalloc_socket(NULL,
1164                                           sizeof(struct ice_rx_entry) * len,
1165                                           RTE_CACHE_LINE_SIZE,
1166                                           socket_id);
1167         if (!rxq->sw_ring) {
1168                 ice_rx_queue_release(rxq);
1169                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1170                 return -ENOMEM;
1171         }
1172
1173         ice_reset_rx_queue(rxq);
1174         rxq->q_set = true;
1175         dev->data->rx_queues[queue_idx] = rxq;
1176         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1177
1178         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1179
1180         if (!use_def_burst_func) {
1181                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1182                              "satisfied. Rx Burst Bulk Alloc function will be "
1183                              "used on port=%d, queue=%d.",
1184                              rxq->port_id, rxq->queue_id);
1185         } else {
1186                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1187                              "not satisfied, Scattered Rx is requested. "
1188                              "on port=%d, queue=%d.",
1189                              rxq->port_id, rxq->queue_id);
1190                 ad->rx_bulk_alloc_allowed = false;
1191         }
1192
1193         return 0;
1194 }
1195
1196 void
1197 ice_rx_queue_release(void *rxq)
1198 {
1199         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1200
1201         if (!q) {
1202                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1203                 return;
1204         }
1205
1206         q->rx_rel_mbufs(q);
1207         rte_free(q->sw_ring);
1208         rte_free(q);
1209 }
1210
1211 int
1212 ice_tx_queue_setup(struct rte_eth_dev *dev,
1213                    uint16_t queue_idx,
1214                    uint16_t nb_desc,
1215                    unsigned int socket_id,
1216                    const struct rte_eth_txconf *tx_conf)
1217 {
1218         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1219         struct ice_vsi *vsi = pf->main_vsi;
1220         struct ice_tx_queue *txq;
1221         const struct rte_memzone *tz;
1222         uint32_t ring_size;
1223         uint16_t tx_rs_thresh, tx_free_thresh;
1224         uint64_t offloads;
1225
1226         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1227
1228         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1229             nb_desc > ICE_MAX_RING_DESC ||
1230             nb_desc < ICE_MIN_RING_DESC) {
1231                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1232                              "invalid", nb_desc);
1233                 return -EINVAL;
1234         }
1235
1236         /**
1237          * The following two parameters control the setting of the RS bit on
1238          * transmit descriptors. TX descriptors will have their RS bit set
1239          * after txq->tx_rs_thresh descriptors have been used. The TX
1240          * descriptor ring will be cleaned after txq->tx_free_thresh
1241          * descriptors are used or if the number of descriptors required to
1242          * transmit a packet is greater than the number of free TX descriptors.
1243          *
1244          * The following constraints must be satisfied:
1245          *  - tx_rs_thresh must be greater than 0.
1246          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1247          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1248          *  - tx_rs_thresh must be a divisor of the ring size.
1249          *  - tx_free_thresh must be greater than 0.
1250          *  - tx_free_thresh must be less than the size of the ring minus 3.
1251          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1252          *
1253          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1254          * race condition, hence the maximum threshold constraints. When set
1255          * to zero use default values.
1256          */
1257         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1258                                     tx_conf->tx_free_thresh :
1259                                     ICE_DEFAULT_TX_FREE_THRESH);
1260         /* force tx_rs_thresh to adapt an aggresive tx_free_thresh */
1261         tx_rs_thresh =
1262                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1263                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1264         if (tx_conf->tx_rs_thresh)
1265                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1266         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1267                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1268                                 "exceed nb_desc. (tx_rs_thresh=%u "
1269                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1270                                 (unsigned int)tx_rs_thresh,
1271                                 (unsigned int)tx_free_thresh,
1272                                 (unsigned int)nb_desc,
1273                                 (int)dev->data->port_id,
1274                                 (int)queue_idx);
1275                 return -EINVAL;
1276         }
1277         if (tx_rs_thresh >= (nb_desc - 2)) {
1278                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1279                              "number of TX descriptors minus 2. "
1280                              "(tx_rs_thresh=%u port=%d queue=%d)",
1281                              (unsigned int)tx_rs_thresh,
1282                              (int)dev->data->port_id,
1283                              (int)queue_idx);
1284                 return -EINVAL;
1285         }
1286         if (tx_free_thresh >= (nb_desc - 3)) {
1287                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1288                              "tx_free_thresh must be less than the "
1289                              "number of TX descriptors minus 3. "
1290                              "(tx_free_thresh=%u port=%d queue=%d)",
1291                              (unsigned int)tx_free_thresh,
1292                              (int)dev->data->port_id,
1293                              (int)queue_idx);
1294                 return -EINVAL;
1295         }
1296         if (tx_rs_thresh > tx_free_thresh) {
1297                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1298                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1299                              " tx_rs_thresh=%u port=%d queue=%d)",
1300                              (unsigned int)tx_free_thresh,
1301                              (unsigned int)tx_rs_thresh,
1302                              (int)dev->data->port_id,
1303                              (int)queue_idx);
1304                 return -EINVAL;
1305         }
1306         if ((nb_desc % tx_rs_thresh) != 0) {
1307                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1308                              "number of TX descriptors. (tx_rs_thresh=%u"
1309                              " port=%d queue=%d)",
1310                              (unsigned int)tx_rs_thresh,
1311                              (int)dev->data->port_id,
1312                              (int)queue_idx);
1313                 return -EINVAL;
1314         }
1315         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1316                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1317                              "tx_rs_thresh is greater than 1. "
1318                              "(tx_rs_thresh=%u port=%d queue=%d)",
1319                              (unsigned int)tx_rs_thresh,
1320                              (int)dev->data->port_id,
1321                              (int)queue_idx);
1322                 return -EINVAL;
1323         }
1324
1325         /* Free memory if needed. */
1326         if (dev->data->tx_queues[queue_idx]) {
1327                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1328                 dev->data->tx_queues[queue_idx] = NULL;
1329         }
1330
1331         /* Allocate the TX queue data structure. */
1332         txq = rte_zmalloc_socket(NULL,
1333                                  sizeof(struct ice_tx_queue),
1334                                  RTE_CACHE_LINE_SIZE,
1335                                  socket_id);
1336         if (!txq) {
1337                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1338                              "tx queue structure");
1339                 return -ENOMEM;
1340         }
1341
1342         /* Allocate TX hardware ring descriptors. */
1343         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1344         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1345         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1346                                       ring_size, ICE_RING_BASE_ALIGN,
1347                                       socket_id);
1348         if (!tz) {
1349                 ice_tx_queue_release(txq);
1350                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1351                 return -ENOMEM;
1352         }
1353
1354         txq->nb_tx_desc = nb_desc;
1355         txq->tx_rs_thresh = tx_rs_thresh;
1356         txq->tx_free_thresh = tx_free_thresh;
1357         txq->pthresh = tx_conf->tx_thresh.pthresh;
1358         txq->hthresh = tx_conf->tx_thresh.hthresh;
1359         txq->wthresh = tx_conf->tx_thresh.wthresh;
1360         txq->queue_id = queue_idx;
1361
1362         txq->reg_idx = vsi->base_queue + queue_idx;
1363         txq->port_id = dev->data->port_id;
1364         txq->offloads = offloads;
1365         txq->vsi = vsi;
1366         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1367
1368         txq->tx_ring_dma = tz->iova;
1369         txq->tx_ring = tz->addr;
1370
1371         /* Allocate software ring */
1372         txq->sw_ring =
1373                 rte_zmalloc_socket(NULL,
1374                                    sizeof(struct ice_tx_entry) * nb_desc,
1375                                    RTE_CACHE_LINE_SIZE,
1376                                    socket_id);
1377         if (!txq->sw_ring) {
1378                 ice_tx_queue_release(txq);
1379                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1380                 return -ENOMEM;
1381         }
1382
1383         ice_reset_tx_queue(txq);
1384         txq->q_set = true;
1385         dev->data->tx_queues[queue_idx] = txq;
1386         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1387         ice_set_tx_function_flag(dev, txq);
1388
1389         return 0;
1390 }
1391
1392 void
1393 ice_tx_queue_release(void *txq)
1394 {
1395         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1396
1397         if (!q) {
1398                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1399                 return;
1400         }
1401
1402         q->tx_rel_mbufs(q);
1403         rte_free(q->sw_ring);
1404         rte_free(q);
1405 }
1406
1407 void
1408 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1409                  struct rte_eth_rxq_info *qinfo)
1410 {
1411         struct ice_rx_queue *rxq;
1412
1413         rxq = dev->data->rx_queues[queue_id];
1414
1415         qinfo->mp = rxq->mp;
1416         qinfo->scattered_rx = dev->data->scattered_rx;
1417         qinfo->nb_desc = rxq->nb_rx_desc;
1418
1419         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1420         qinfo->conf.rx_drop_en = rxq->drop_en;
1421         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1422 }
1423
1424 void
1425 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1426                  struct rte_eth_txq_info *qinfo)
1427 {
1428         struct ice_tx_queue *txq;
1429
1430         txq = dev->data->tx_queues[queue_id];
1431
1432         qinfo->nb_desc = txq->nb_tx_desc;
1433
1434         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1435         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1436         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1437
1438         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1439         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1440         qinfo->conf.offloads = txq->offloads;
1441         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1442 }
1443
1444 uint32_t
1445 ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1446 {
1447 #define ICE_RXQ_SCAN_INTERVAL 4
1448         volatile union ice_rx_flex_desc *rxdp;
1449         struct ice_rx_queue *rxq;
1450         uint16_t desc = 0;
1451
1452         rxq = dev->data->rx_queues[rx_queue_id];
1453         rxdp = &rxq->rx_ring[rxq->rx_tail];
1454         while ((desc < rxq->nb_rx_desc) &&
1455                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1456                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1457                 /**
1458                  * Check the DD bit of a rx descriptor of each 4 in a group,
1459                  * to avoid checking too frequently and downgrading performance
1460                  * too much.
1461                  */
1462                 desc += ICE_RXQ_SCAN_INTERVAL;
1463                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1464                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1465                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1466                                  desc - rxq->nb_rx_desc]);
1467         }
1468
1469         return desc;
1470 }
1471
1472 #define ICE_RX_FLEX_ERR0_BITS   \
1473         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1474          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1475          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1476          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1477          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1478          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1479
1480 /* Rx L3/L4 checksum */
1481 static inline uint64_t
1482 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1483 {
1484         uint64_t flags = 0;
1485
1486         /* check if HW has decoded the packet and checksum */
1487         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1488                 return 0;
1489
1490         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1491                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
1492                 return flags;
1493         }
1494
1495         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1496                 flags |= PKT_RX_IP_CKSUM_BAD;
1497         else
1498                 flags |= PKT_RX_IP_CKSUM_GOOD;
1499
1500         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1501                 flags |= PKT_RX_L4_CKSUM_BAD;
1502         else
1503                 flags |= PKT_RX_L4_CKSUM_GOOD;
1504
1505         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1506                 flags |= PKT_RX_OUTER_IP_CKSUM_BAD;
1507
1508         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1509                 flags |= PKT_RX_OUTER_L4_CKSUM_BAD;
1510         else
1511                 flags |= PKT_RX_OUTER_L4_CKSUM_GOOD;
1512
1513         return flags;
1514 }
1515
1516 static inline void
1517 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1518 {
1519         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1520             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1521                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1522                 mb->vlan_tci =
1523                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1524                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1525                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1526         } else {
1527                 mb->vlan_tci = 0;
1528         }
1529
1530 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1531         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1532             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1533                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
1534                                 PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
1535                 mb->vlan_tci_outer = mb->vlan_tci;
1536                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1537                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1538                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1539                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1540         } else {
1541                 mb->vlan_tci_outer = 0;
1542         }
1543 #endif
1544         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1545                    mb->vlan_tci, mb->vlan_tci_outer);
1546 }
1547
1548 #define ICE_LOOK_AHEAD 8
1549 #if (ICE_LOOK_AHEAD != 8)
1550 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1551 #endif
1552 static inline int
1553 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1554 {
1555         volatile union ice_rx_flex_desc *rxdp;
1556         struct ice_rx_entry *rxep;
1557         struct rte_mbuf *mb;
1558         uint16_t stat_err0;
1559         uint16_t pkt_len;
1560         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1561         int32_t i, j, nb_rx = 0;
1562         uint64_t pkt_flags = 0;
1563         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1564         struct ice_vsi *vsi = rxq->vsi;
1565         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1566         uint64_t ts_ns;
1567
1568         rxdp = &rxq->rx_ring[rxq->rx_tail];
1569         rxep = &rxq->sw_ring[rxq->rx_tail];
1570
1571         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1572
1573         /* Make sure there is at least 1 packet to receive */
1574         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1575                 return 0;
1576
1577         /**
1578          * Scan LOOK_AHEAD descriptors at a time to determine which
1579          * descriptors reference packets that are ready to be received.
1580          */
1581         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1582              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1583                 /* Read desc statuses backwards to avoid race condition */
1584                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1585                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1586
1587                 rte_smp_rmb();
1588
1589                 /* Compute how many status bits were set */
1590                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1591                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1592
1593                 nb_rx += nb_dd;
1594
1595                 /* Translate descriptor info to mbuf parameters */
1596                 for (j = 0; j < nb_dd; j++) {
1597                         mb = rxep[j].mbuf;
1598                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1599                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1600                         mb->data_len = pkt_len;
1601                         mb->pkt_len = pkt_len;
1602                         mb->ol_flags = 0;
1603                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1604                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1605                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1606                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1607                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1608                         rxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);
1609
1610                         if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
1611                                 ts_ns = ice_tstamp_convert_32b_64b(hw,
1612                                         rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high));
1613                                 if (ice_timestamp_dynflag > 0) {
1614                                         *RTE_MBUF_DYNFIELD(mb,
1615                                                 ice_timestamp_dynfield_offset,
1616                                                 rte_mbuf_timestamp_t *) = ts_ns;
1617                                         mb->ol_flags |= ice_timestamp_dynflag;
1618                                 }
1619                         }
1620
1621                         mb->ol_flags |= pkt_flags;
1622                 }
1623
1624                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1625                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1626
1627                 if (nb_dd != ICE_LOOK_AHEAD)
1628                         break;
1629         }
1630
1631         /* Clear software ring entries */
1632         for (i = 0; i < nb_rx; i++)
1633                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1634
1635         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1636                    "port_id=%u, queue_id=%u, nb_rx=%d",
1637                    rxq->port_id, rxq->queue_id, nb_rx);
1638
1639         return nb_rx;
1640 }
1641
1642 static inline uint16_t
1643 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1644                        struct rte_mbuf **rx_pkts,
1645                        uint16_t nb_pkts)
1646 {
1647         uint16_t i;
1648         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1649
1650         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1651
1652         for (i = 0; i < nb_pkts; i++)
1653                 rx_pkts[i] = stage[i];
1654
1655         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1656         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1657
1658         return nb_pkts;
1659 }
1660
1661 static inline int
1662 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1663 {
1664         volatile union ice_rx_flex_desc *rxdp;
1665         struct ice_rx_entry *rxep;
1666         struct rte_mbuf *mb;
1667         uint16_t alloc_idx, i;
1668         uint64_t dma_addr;
1669         int diag;
1670
1671         /* Allocate buffers in bulk */
1672         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1673                                (rxq->rx_free_thresh - 1));
1674         rxep = &rxq->sw_ring[alloc_idx];
1675         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1676                                     rxq->rx_free_thresh);
1677         if (unlikely(diag != 0)) {
1678                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1679                 return -ENOMEM;
1680         }
1681
1682         rxdp = &rxq->rx_ring[alloc_idx];
1683         for (i = 0; i < rxq->rx_free_thresh; i++) {
1684                 if (likely(i < (rxq->rx_free_thresh - 1)))
1685                         /* Prefetch next mbuf */
1686                         rte_prefetch0(rxep[i + 1].mbuf);
1687
1688                 mb = rxep[i].mbuf;
1689                 rte_mbuf_refcnt_set(mb, 1);
1690                 mb->next = NULL;
1691                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1692                 mb->nb_segs = 1;
1693                 mb->port = rxq->port_id;
1694                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1695                 rxdp[i].read.hdr_addr = 0;
1696                 rxdp[i].read.pkt_addr = dma_addr;
1697         }
1698
1699         /* Update rx tail regsiter */
1700         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1701
1702         rxq->rx_free_trigger =
1703                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1704         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1705                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1706
1707         return 0;
1708 }
1709
1710 static inline uint16_t
1711 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1712 {
1713         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1714         uint16_t nb_rx = 0;
1715
1716         if (!nb_pkts)
1717                 return 0;
1718
1719         if (rxq->rx_nb_avail)
1720                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1721
1722         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1723         rxq->rx_next_avail = 0;
1724         rxq->rx_nb_avail = nb_rx;
1725         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1726
1727         if (rxq->rx_tail > rxq->rx_free_trigger) {
1728                 if (ice_rx_alloc_bufs(rxq) != 0) {
1729                         uint16_t i, j;
1730
1731                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1732                                 rxq->rx_free_thresh;
1733                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1734                                    "port_id=%u, queue_id=%u",
1735                                    rxq->port_id, rxq->queue_id);
1736                         rxq->rx_nb_avail = 0;
1737                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1738                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1739                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1740
1741                         return 0;
1742                 }
1743         }
1744
1745         if (rxq->rx_tail >= rxq->nb_rx_desc)
1746                 rxq->rx_tail = 0;
1747
1748         if (rxq->rx_nb_avail)
1749                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1750
1751         return 0;
1752 }
1753
1754 static uint16_t
1755 ice_recv_pkts_bulk_alloc(void *rx_queue,
1756                          struct rte_mbuf **rx_pkts,
1757                          uint16_t nb_pkts)
1758 {
1759         uint16_t nb_rx = 0;
1760         uint16_t n;
1761         uint16_t count;
1762
1763         if (unlikely(nb_pkts == 0))
1764                 return nb_rx;
1765
1766         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1767                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1768
1769         while (nb_pkts) {
1770                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1771                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1772                 nb_rx = (uint16_t)(nb_rx + count);
1773                 nb_pkts = (uint16_t)(nb_pkts - count);
1774                 if (count < n)
1775                         break;
1776         }
1777
1778         return nb_rx;
1779 }
1780
1781 static uint16_t
1782 ice_recv_scattered_pkts(void *rx_queue,
1783                         struct rte_mbuf **rx_pkts,
1784                         uint16_t nb_pkts)
1785 {
1786         struct ice_rx_queue *rxq = rx_queue;
1787         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1788         volatile union ice_rx_flex_desc *rxdp;
1789         union ice_rx_flex_desc rxd;
1790         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1791         struct ice_rx_entry *rxe;
1792         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1793         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1794         struct rte_mbuf *nmb; /* new allocated mbuf */
1795         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1796         uint16_t rx_id = rxq->rx_tail;
1797         uint16_t nb_rx = 0;
1798         uint16_t nb_hold = 0;
1799         uint16_t rx_packet_len;
1800         uint16_t rx_stat_err0;
1801         uint64_t dma_addr;
1802         uint64_t pkt_flags;
1803         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1804         struct ice_vsi *vsi = rxq->vsi;
1805         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1806         uint64_t ts_ns;
1807
1808         while (nb_rx < nb_pkts) {
1809                 rxdp = &rx_ring[rx_id];
1810                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1811
1812                 /* Check the DD bit first */
1813                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1814                         break;
1815
1816                 /* allocate mbuf */
1817                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1818                 if (unlikely(!nmb)) {
1819                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1820                         break;
1821                 }
1822                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1823
1824                 nb_hold++;
1825                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1826                 rx_id++;
1827                 if (unlikely(rx_id == rxq->nb_rx_desc))
1828                         rx_id = 0;
1829
1830                 /* Prefetch next mbuf */
1831                 rte_prefetch0(sw_ring[rx_id].mbuf);
1832
1833                 /**
1834                  * When next RX descriptor is on a cache line boundary,
1835                  * prefetch the next 4 RX descriptors and next 8 pointers
1836                  * to mbufs.
1837                  */
1838                 if ((rx_id & 0x3) == 0) {
1839                         rte_prefetch0(&rx_ring[rx_id]);
1840                         rte_prefetch0(&sw_ring[rx_id]);
1841                 }
1842
1843                 rxm = rxe->mbuf;
1844                 rxe->mbuf = nmb;
1845                 dma_addr =
1846                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1847
1848                 /* Set data buffer address and data length of the mbuf */
1849                 rxdp->read.hdr_addr = 0;
1850                 rxdp->read.pkt_addr = dma_addr;
1851                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1852                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1853                 rxm->data_len = rx_packet_len;
1854                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1855
1856                 /**
1857                  * If this is the first buffer of the received packet, set the
1858                  * pointer to the first mbuf of the packet and initialize its
1859                  * context. Otherwise, update the total length and the number
1860                  * of segments of the current scattered packet, and update the
1861                  * pointer to the last mbuf of the current packet.
1862                  */
1863                 if (!first_seg) {
1864                         first_seg = rxm;
1865                         first_seg->nb_segs = 1;
1866                         first_seg->pkt_len = rx_packet_len;
1867                 } else {
1868                         first_seg->pkt_len =
1869                                 (uint16_t)(first_seg->pkt_len +
1870                                            rx_packet_len);
1871                         first_seg->nb_segs++;
1872                         last_seg->next = rxm;
1873                 }
1874
1875                 /**
1876                  * If this is not the last buffer of the received packet,
1877                  * update the pointer to the last mbuf of the current scattered
1878                  * packet and continue to parse the RX ring.
1879                  */
1880                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1881                         last_seg = rxm;
1882                         continue;
1883                 }
1884
1885                 /**
1886                  * This is the last buffer of the received packet. If the CRC
1887                  * is not stripped by the hardware:
1888                  *  - Subtract the CRC length from the total packet length.
1889                  *  - If the last buffer only contains the whole CRC or a part
1890                  *  of it, free the mbuf associated to the last buffer. If part
1891                  *  of the CRC is also contained in the previous mbuf, subtract
1892                  *  the length of that CRC part from the data length of the
1893                  *  previous mbuf.
1894                  */
1895                 rxm->next = NULL;
1896                 if (unlikely(rxq->crc_len > 0)) {
1897                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1898                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1899                                 rte_pktmbuf_free_seg(rxm);
1900                                 first_seg->nb_segs--;
1901                                 last_seg->data_len =
1902                                         (uint16_t)(last_seg->data_len -
1903                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1904                                 last_seg->next = NULL;
1905                         } else
1906                                 rxm->data_len = (uint16_t)(rx_packet_len -
1907                                                            RTE_ETHER_CRC_LEN);
1908                 }
1909
1910                 first_seg->port = rxq->port_id;
1911                 first_seg->ol_flags = 0;
1912                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1913                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1914                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1915                 rxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);
1916                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1917
1918                 if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
1919                         ts_ns = ice_tstamp_convert_32b_64b(hw,
1920                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1921                         if (ice_timestamp_dynflag > 0) {
1922                                 *RTE_MBUF_DYNFIELD(first_seg,
1923                                         ice_timestamp_dynfield_offset,
1924                                         rte_mbuf_timestamp_t *) = ts_ns;
1925                                 first_seg->ol_flags |= ice_timestamp_dynflag;
1926                         }
1927                 }
1928
1929                 first_seg->ol_flags |= pkt_flags;
1930                 /* Prefetch data of first segment, if configured to do so. */
1931                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1932                                           first_seg->data_off));
1933                 rx_pkts[nb_rx++] = first_seg;
1934                 first_seg = NULL;
1935         }
1936
1937         /* Record index of the next RX descriptor to probe. */
1938         rxq->rx_tail = rx_id;
1939         rxq->pkt_first_seg = first_seg;
1940         rxq->pkt_last_seg = last_seg;
1941
1942         /**
1943          * If the number of free RX descriptors is greater than the RX free
1944          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1945          * register. Update the RDT with the value of the last processed RX
1946          * descriptor minus 1, to guarantee that the RDT register is never
1947          * equal to the RDH register, which creates a "full" ring situtation
1948          * from the hardware point of view.
1949          */
1950         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1951         if (nb_hold > rxq->rx_free_thresh) {
1952                 rx_id = (uint16_t)(rx_id == 0 ?
1953                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1954                 /* write TAIL register */
1955                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1956                 nb_hold = 0;
1957         }
1958         rxq->nb_rx_hold = nb_hold;
1959
1960         /* return received packet in the burst */
1961         return nb_rx;
1962 }
1963
1964 const uint32_t *
1965 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1966 {
1967         struct ice_adapter *ad =
1968                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1969         const uint32_t *ptypes;
1970
1971         static const uint32_t ptypes_os[] = {
1972                 /* refers to ice_get_default_pkt_type() */
1973                 RTE_PTYPE_L2_ETHER,
1974                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1975                 RTE_PTYPE_L2_ETHER_LLDP,
1976                 RTE_PTYPE_L2_ETHER_ARP,
1977                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1978                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1979                 RTE_PTYPE_L4_FRAG,
1980                 RTE_PTYPE_L4_ICMP,
1981                 RTE_PTYPE_L4_NONFRAG,
1982                 RTE_PTYPE_L4_SCTP,
1983                 RTE_PTYPE_L4_TCP,
1984                 RTE_PTYPE_L4_UDP,
1985                 RTE_PTYPE_TUNNEL_GRENAT,
1986                 RTE_PTYPE_TUNNEL_IP,
1987                 RTE_PTYPE_INNER_L2_ETHER,
1988                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1989                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1990                 RTE_PTYPE_INNER_L4_FRAG,
1991                 RTE_PTYPE_INNER_L4_ICMP,
1992                 RTE_PTYPE_INNER_L4_NONFRAG,
1993                 RTE_PTYPE_INNER_L4_SCTP,
1994                 RTE_PTYPE_INNER_L4_TCP,
1995                 RTE_PTYPE_INNER_L4_UDP,
1996                 RTE_PTYPE_UNKNOWN
1997         };
1998
1999         static const uint32_t ptypes_comms[] = {
2000                 /* refers to ice_get_default_pkt_type() */
2001                 RTE_PTYPE_L2_ETHER,
2002                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2003                 RTE_PTYPE_L2_ETHER_LLDP,
2004                 RTE_PTYPE_L2_ETHER_ARP,
2005                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2006                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2007                 RTE_PTYPE_L4_FRAG,
2008                 RTE_PTYPE_L4_ICMP,
2009                 RTE_PTYPE_L4_NONFRAG,
2010                 RTE_PTYPE_L4_SCTP,
2011                 RTE_PTYPE_L4_TCP,
2012                 RTE_PTYPE_L4_UDP,
2013                 RTE_PTYPE_TUNNEL_GRENAT,
2014                 RTE_PTYPE_TUNNEL_IP,
2015                 RTE_PTYPE_INNER_L2_ETHER,
2016                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2017                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2018                 RTE_PTYPE_INNER_L4_FRAG,
2019                 RTE_PTYPE_INNER_L4_ICMP,
2020                 RTE_PTYPE_INNER_L4_NONFRAG,
2021                 RTE_PTYPE_INNER_L4_SCTP,
2022                 RTE_PTYPE_INNER_L4_TCP,
2023                 RTE_PTYPE_INNER_L4_UDP,
2024                 RTE_PTYPE_TUNNEL_GTPC,
2025                 RTE_PTYPE_TUNNEL_GTPU,
2026                 RTE_PTYPE_L2_ETHER_PPPOE,
2027                 RTE_PTYPE_UNKNOWN
2028         };
2029
2030         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
2031                 ptypes = ptypes_comms;
2032         else
2033                 ptypes = ptypes_os;
2034
2035         if (dev->rx_pkt_burst == ice_recv_pkts ||
2036             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
2037             dev->rx_pkt_burst == ice_recv_scattered_pkts)
2038                 return ptypes;
2039
2040 #ifdef RTE_ARCH_X86
2041         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
2042             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
2043 #ifdef CC_AVX512_SUPPORT
2044             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
2045             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
2046             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
2047             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
2048 #endif
2049             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
2050             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
2051             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2052             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2053                 return ptypes;
2054 #endif
2055
2056         return NULL;
2057 }
2058
2059 int
2060 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2061 {
2062         volatile union ice_rx_flex_desc *rxdp;
2063         struct ice_rx_queue *rxq = rx_queue;
2064         uint32_t desc;
2065
2066         if (unlikely(offset >= rxq->nb_rx_desc))
2067                 return -EINVAL;
2068
2069         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2070                 return RTE_ETH_RX_DESC_UNAVAIL;
2071
2072         desc = rxq->rx_tail + offset;
2073         if (desc >= rxq->nb_rx_desc)
2074                 desc -= rxq->nb_rx_desc;
2075
2076         rxdp = &rxq->rx_ring[desc];
2077         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2078             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2079                 return RTE_ETH_RX_DESC_DONE;
2080
2081         return RTE_ETH_RX_DESC_AVAIL;
2082 }
2083
2084 int
2085 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2086 {
2087         struct ice_tx_queue *txq = tx_queue;
2088         volatile uint64_t *status;
2089         uint64_t mask, expect;
2090         uint32_t desc;
2091
2092         if (unlikely(offset >= txq->nb_tx_desc))
2093                 return -EINVAL;
2094
2095         desc = txq->tx_tail + offset;
2096         /* go to next desc that has the RS bit */
2097         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2098                 txq->tx_rs_thresh;
2099         if (desc >= txq->nb_tx_desc) {
2100                 desc -= txq->nb_tx_desc;
2101                 if (desc >= txq->nb_tx_desc)
2102                         desc -= txq->nb_tx_desc;
2103         }
2104
2105         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2106         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2107         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2108                                   ICE_TXD_QW1_DTYPE_S);
2109         if ((*status & mask) == expect)
2110                 return RTE_ETH_TX_DESC_DONE;
2111
2112         return RTE_ETH_TX_DESC_FULL;
2113 }
2114
2115 void
2116 ice_free_queues(struct rte_eth_dev *dev)
2117 {
2118         uint16_t i;
2119
2120         PMD_INIT_FUNC_TRACE();
2121
2122         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2123                 if (!dev->data->rx_queues[i])
2124                         continue;
2125                 ice_rx_queue_release(dev->data->rx_queues[i]);
2126                 dev->data->rx_queues[i] = NULL;
2127                 rte_eth_dma_zone_free(dev, "rx_ring", i);
2128         }
2129         dev->data->nb_rx_queues = 0;
2130
2131         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2132                 if (!dev->data->tx_queues[i])
2133                         continue;
2134                 ice_tx_queue_release(dev->data->tx_queues[i]);
2135                 dev->data->tx_queues[i] = NULL;
2136                 rte_eth_dma_zone_free(dev, "tx_ring", i);
2137         }
2138         dev->data->nb_tx_queues = 0;
2139 }
2140
2141 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
2142 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
2143
2144 int
2145 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2146 {
2147         struct ice_tx_queue *txq;
2148         const struct rte_memzone *tz = NULL;
2149         uint32_t ring_size;
2150         struct rte_eth_dev *dev;
2151
2152         if (!pf) {
2153                 PMD_DRV_LOG(ERR, "PF is not available");
2154                 return -EINVAL;
2155         }
2156
2157         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2158
2159         /* Allocate the TX queue data structure. */
2160         txq = rte_zmalloc_socket("ice fdir tx queue",
2161                                  sizeof(struct ice_tx_queue),
2162                                  RTE_CACHE_LINE_SIZE,
2163                                  SOCKET_ID_ANY);
2164         if (!txq) {
2165                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2166                             "tx queue structure.");
2167                 return -ENOMEM;
2168         }
2169
2170         /* Allocate TX hardware ring descriptors. */
2171         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2172         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2173
2174         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2175                                       ICE_FDIR_QUEUE_ID, ring_size,
2176                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2177         if (!tz) {
2178                 ice_tx_queue_release(txq);
2179                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2180                 return -ENOMEM;
2181         }
2182
2183         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2184         txq->queue_id = ICE_FDIR_QUEUE_ID;
2185         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2186         txq->vsi = pf->fdir.fdir_vsi;
2187
2188         txq->tx_ring_dma = tz->iova;
2189         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2190         /*
2191          * don't need to allocate software ring and reset for the fdir
2192          * program queue just set the queue has been configured.
2193          */
2194         txq->q_set = true;
2195         pf->fdir.txq = txq;
2196
2197         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2198
2199         return ICE_SUCCESS;
2200 }
2201
2202 int
2203 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2204 {
2205         struct ice_rx_queue *rxq;
2206         const struct rte_memzone *rz = NULL;
2207         uint32_t ring_size;
2208         struct rte_eth_dev *dev;
2209
2210         if (!pf) {
2211                 PMD_DRV_LOG(ERR, "PF is not available");
2212                 return -EINVAL;
2213         }
2214
2215         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2216
2217         /* Allocate the RX queue data structure. */
2218         rxq = rte_zmalloc_socket("ice fdir rx queue",
2219                                  sizeof(struct ice_rx_queue),
2220                                  RTE_CACHE_LINE_SIZE,
2221                                  SOCKET_ID_ANY);
2222         if (!rxq) {
2223                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2224                             "rx queue structure.");
2225                 return -ENOMEM;
2226         }
2227
2228         /* Allocate RX hardware ring descriptors. */
2229         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2230         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2231
2232         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2233                                       ICE_FDIR_QUEUE_ID, ring_size,
2234                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2235         if (!rz) {
2236                 ice_rx_queue_release(rxq);
2237                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2238                 return -ENOMEM;
2239         }
2240
2241         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2242         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2243         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2244         rxq->vsi = pf->fdir.fdir_vsi;
2245
2246         rxq->rx_ring_dma = rz->iova;
2247         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2248                sizeof(union ice_32byte_rx_desc));
2249         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2250
2251         /*
2252          * Don't need to allocate software ring and reset for the fdir
2253          * rx queue, just set the queue has been configured.
2254          */
2255         rxq->q_set = true;
2256         pf->fdir.rxq = rxq;
2257
2258         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2259
2260         return ICE_SUCCESS;
2261 }
2262
2263 uint16_t
2264 ice_recv_pkts(void *rx_queue,
2265               struct rte_mbuf **rx_pkts,
2266               uint16_t nb_pkts)
2267 {
2268         struct ice_rx_queue *rxq = rx_queue;
2269         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2270         volatile union ice_rx_flex_desc *rxdp;
2271         union ice_rx_flex_desc rxd;
2272         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2273         struct ice_rx_entry *rxe;
2274         struct rte_mbuf *nmb; /* new allocated mbuf */
2275         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2276         uint16_t rx_id = rxq->rx_tail;
2277         uint16_t nb_rx = 0;
2278         uint16_t nb_hold = 0;
2279         uint16_t rx_packet_len;
2280         uint16_t rx_stat_err0;
2281         uint64_t dma_addr;
2282         uint64_t pkt_flags;
2283         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2284         struct ice_vsi *vsi = rxq->vsi;
2285         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2286         uint64_t ts_ns;
2287
2288         while (nb_rx < nb_pkts) {
2289                 rxdp = &rx_ring[rx_id];
2290                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2291
2292                 /* Check the DD bit first */
2293                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2294                         break;
2295
2296                 /* allocate mbuf */
2297                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2298                 if (unlikely(!nmb)) {
2299                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2300                         break;
2301                 }
2302                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2303
2304                 nb_hold++;
2305                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2306                 rx_id++;
2307                 if (unlikely(rx_id == rxq->nb_rx_desc))
2308                         rx_id = 0;
2309                 rxm = rxe->mbuf;
2310                 rxe->mbuf = nmb;
2311                 dma_addr =
2312                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2313
2314                 /**
2315                  * fill the read format of descriptor with physic address in
2316                  * new allocated mbuf: nmb
2317                  */
2318                 rxdp->read.hdr_addr = 0;
2319                 rxdp->read.pkt_addr = dma_addr;
2320
2321                 /* calculate rx_packet_len of the received pkt */
2322                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2323                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2324
2325                 /* fill old mbuf with received descriptor: rxd */
2326                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2327                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2328                 rxm->nb_segs = 1;
2329                 rxm->next = NULL;
2330                 rxm->pkt_len = rx_packet_len;
2331                 rxm->data_len = rx_packet_len;
2332                 rxm->port = rxq->port_id;
2333                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2334                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2335                 ice_rxd_to_vlan_tci(rxm, &rxd);
2336                 rxq->rxd_to_pkt_fields(rxq, rxm, &rxd);
2337                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2338
2339                 if (rxq->offloads & DEV_RX_OFFLOAD_TIMESTAMP) {
2340                         ts_ns = ice_tstamp_convert_32b_64b(hw,
2341                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
2342                         if (ice_timestamp_dynflag > 0) {
2343                                 *RTE_MBUF_DYNFIELD(rxm,
2344                                         ice_timestamp_dynfield_offset,
2345                                         rte_mbuf_timestamp_t *) = ts_ns;
2346                                 rxm->ol_flags |= ice_timestamp_dynflag;
2347                         }
2348                 }
2349
2350                 rxm->ol_flags |= pkt_flags;
2351                 /* copy old mbuf to rx_pkts */
2352                 rx_pkts[nb_rx++] = rxm;
2353         }
2354         rxq->rx_tail = rx_id;
2355         /**
2356          * If the number of free RX descriptors is greater than the RX free
2357          * threshold of the queue, advance the receive tail register of queue.
2358          * Update that register with the value of the last processed RX
2359          * descriptor minus 1.
2360          */
2361         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2362         if (nb_hold > rxq->rx_free_thresh) {
2363                 rx_id = (uint16_t)(rx_id == 0 ?
2364                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2365                 /* write TAIL register */
2366                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2367                 nb_hold = 0;
2368         }
2369         rxq->nb_rx_hold = nb_hold;
2370
2371         /* return received packet in the burst */
2372         return nb_rx;
2373 }
2374
2375 static inline void
2376 ice_parse_tunneling_params(uint64_t ol_flags,
2377                             union ice_tx_offload tx_offload,
2378                             uint32_t *cd_tunneling)
2379 {
2380         /* EIPT: External (outer) IP header type */
2381         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
2382                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2383         else if (ol_flags & PKT_TX_OUTER_IPV4)
2384                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2385         else if (ol_flags & PKT_TX_OUTER_IPV6)
2386                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2387
2388         /* EIPLEN: External (outer) IP header length, in DWords */
2389         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2390                 ICE_TXD_CTX_QW0_EIPLEN_S;
2391
2392         /* L4TUNT: L4 Tunneling Type */
2393         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
2394         case PKT_TX_TUNNEL_IPIP:
2395                 /* for non UDP / GRE tunneling, set to 00b */
2396                 break;
2397         case PKT_TX_TUNNEL_VXLAN:
2398         case PKT_TX_TUNNEL_GTP:
2399         case PKT_TX_TUNNEL_GENEVE:
2400                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2401                 break;
2402         case PKT_TX_TUNNEL_GRE:
2403                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2404                 break;
2405         default:
2406                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2407                 return;
2408         }
2409
2410         /* L4TUNLEN: L4 Tunneling Length, in Words
2411          *
2412          * We depend on app to set rte_mbuf.l2_len correctly.
2413          * For IP in GRE it should be set to the length of the GRE
2414          * header;
2415          * For MAC in GRE or MAC in UDP it should be set to the length
2416          * of the GRE or UDP headers plus the inner MAC up to including
2417          * its last Ethertype.
2418          * If MPLS labels exists, it should include them as well.
2419          */
2420         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2421                 ICE_TXD_CTX_QW0_NATLEN_S;
2422
2423         /**
2424          * Calculate the tunneling UDP checksum.
2425          * Shall be set only if L4TUNT = 01b and EIPT is not zero
2426          */
2427         if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2428             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2429                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2430 }
2431
2432 static inline void
2433 ice_txd_enable_checksum(uint64_t ol_flags,
2434                         uint32_t *td_cmd,
2435                         uint32_t *td_offset,
2436                         union ice_tx_offload tx_offload)
2437 {
2438         /* Set MACLEN */
2439         if (ol_flags & PKT_TX_TUNNEL_MASK)
2440                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2441                         << ICE_TX_DESC_LEN_MACLEN_S;
2442         else
2443                 *td_offset |= (tx_offload.l2_len >> 1)
2444                         << ICE_TX_DESC_LEN_MACLEN_S;
2445
2446         /* Enable L3 checksum offloads */
2447         if (ol_flags & PKT_TX_IP_CKSUM) {
2448                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2449                 *td_offset |= (tx_offload.l3_len >> 2) <<
2450                               ICE_TX_DESC_LEN_IPLEN_S;
2451         } else if (ol_flags & PKT_TX_IPV4) {
2452                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2453                 *td_offset |= (tx_offload.l3_len >> 2) <<
2454                               ICE_TX_DESC_LEN_IPLEN_S;
2455         } else if (ol_flags & PKT_TX_IPV6) {
2456                 *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2457                 *td_offset |= (tx_offload.l3_len >> 2) <<
2458                               ICE_TX_DESC_LEN_IPLEN_S;
2459         }
2460
2461         if (ol_flags & PKT_TX_TCP_SEG) {
2462                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2463                 *td_offset |= (tx_offload.l4_len >> 2) <<
2464                               ICE_TX_DESC_LEN_L4_LEN_S;
2465                 return;
2466         }
2467
2468         /* Enable L4 checksum offloads */
2469         switch (ol_flags & PKT_TX_L4_MASK) {
2470         case PKT_TX_TCP_CKSUM:
2471                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2472                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2473                               ICE_TX_DESC_LEN_L4_LEN_S;
2474                 break;
2475         case PKT_TX_SCTP_CKSUM:
2476                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2477                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2478                               ICE_TX_DESC_LEN_L4_LEN_S;
2479                 break;
2480         case PKT_TX_UDP_CKSUM:
2481                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2482                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2483                               ICE_TX_DESC_LEN_L4_LEN_S;
2484                 break;
2485         default:
2486                 break;
2487         }
2488 }
2489
2490 static inline int
2491 ice_xmit_cleanup(struct ice_tx_queue *txq)
2492 {
2493         struct ice_tx_entry *sw_ring = txq->sw_ring;
2494         volatile struct ice_tx_desc *txd = txq->tx_ring;
2495         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2496         uint16_t nb_tx_desc = txq->nb_tx_desc;
2497         uint16_t desc_to_clean_to;
2498         uint16_t nb_tx_to_clean;
2499
2500         /* Determine the last descriptor needing to be cleaned */
2501         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2502         if (desc_to_clean_to >= nb_tx_desc)
2503                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2504
2505         /* Check to make sure the last descriptor to clean is done */
2506         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2507         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2508             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2509                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2510                            "(port=%d queue=%d) value=0x%"PRIx64"\n",
2511                            desc_to_clean_to,
2512                            txq->port_id, txq->queue_id,
2513                            txd[desc_to_clean_to].cmd_type_offset_bsz);
2514                 /* Failed to clean any descriptors */
2515                 return -1;
2516         }
2517
2518         /* Figure out how many descriptors will be cleaned */
2519         if (last_desc_cleaned > desc_to_clean_to)
2520                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2521                                             desc_to_clean_to);
2522         else
2523                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2524                                             last_desc_cleaned);
2525
2526         /* The last descriptor to clean is done, so that means all the
2527          * descriptors from the last descriptor that was cleaned
2528          * up to the last descriptor with the RS bit set
2529          * are done. Only reset the threshold descriptor.
2530          */
2531         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2532
2533         /* Update the txq to reflect the last descriptor that was cleaned */
2534         txq->last_desc_cleaned = desc_to_clean_to;
2535         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2536
2537         return 0;
2538 }
2539
2540 /* Construct the tx flags */
2541 static inline uint64_t
2542 ice_build_ctob(uint32_t td_cmd,
2543                uint32_t td_offset,
2544                uint16_t size,
2545                uint32_t td_tag)
2546 {
2547         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2548                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2549                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2550                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2551                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2552 }
2553
2554 /* Check if the context descriptor is needed for TX offloading */
2555 static inline uint16_t
2556 ice_calc_context_desc(uint64_t flags)
2557 {
2558         static uint64_t mask = PKT_TX_TCP_SEG |
2559                 PKT_TX_QINQ |
2560                 PKT_TX_OUTER_IP_CKSUM |
2561                 PKT_TX_TUNNEL_MASK;
2562
2563         return (flags & mask) ? 1 : 0;
2564 }
2565
2566 /* set ice TSO context descriptor */
2567 static inline uint64_t
2568 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2569 {
2570         uint64_t ctx_desc = 0;
2571         uint32_t cd_cmd, hdr_len, cd_tso_len;
2572
2573         if (!tx_offload.l4_len) {
2574                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2575                 return ctx_desc;
2576         }
2577
2578         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2579         hdr_len += (mbuf->ol_flags & PKT_TX_TUNNEL_MASK) ?
2580                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2581
2582         cd_cmd = ICE_TX_CTX_DESC_TSO;
2583         cd_tso_len = mbuf->pkt_len - hdr_len;
2584         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2585                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2586                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2587
2588         return ctx_desc;
2589 }
2590
2591 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2592 #define ICE_MAX_DATA_PER_TXD \
2593         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2594 /* Calculate the number of TX descriptors needed for each pkt */
2595 static inline uint16_t
2596 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2597 {
2598         struct rte_mbuf *txd = tx_pkt;
2599         uint16_t count = 0;
2600
2601         while (txd != NULL) {
2602                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2603                 txd = txd->next;
2604         }
2605
2606         return count;
2607 }
2608
2609 uint16_t
2610 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2611 {
2612         struct ice_tx_queue *txq;
2613         volatile struct ice_tx_desc *tx_ring;
2614         volatile struct ice_tx_desc *txd;
2615         struct ice_tx_entry *sw_ring;
2616         struct ice_tx_entry *txe, *txn;
2617         struct rte_mbuf *tx_pkt;
2618         struct rte_mbuf *m_seg;
2619         uint32_t cd_tunneling_params;
2620         uint16_t tx_id;
2621         uint16_t nb_tx;
2622         uint16_t nb_used;
2623         uint16_t nb_ctx;
2624         uint32_t td_cmd = 0;
2625         uint32_t td_offset = 0;
2626         uint32_t td_tag = 0;
2627         uint16_t tx_last;
2628         uint16_t slen;
2629         uint64_t buf_dma_addr;
2630         uint64_t ol_flags;
2631         union ice_tx_offload tx_offload = {0};
2632
2633         txq = tx_queue;
2634         sw_ring = txq->sw_ring;
2635         tx_ring = txq->tx_ring;
2636         tx_id = txq->tx_tail;
2637         txe = &sw_ring[tx_id];
2638
2639         /* Check if the descriptor ring needs to be cleaned. */
2640         if (txq->nb_tx_free < txq->tx_free_thresh)
2641                 (void)ice_xmit_cleanup(txq);
2642
2643         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2644                 tx_pkt = *tx_pkts++;
2645
2646                 td_cmd = 0;
2647                 td_tag = 0;
2648                 td_offset = 0;
2649                 ol_flags = tx_pkt->ol_flags;
2650                 tx_offload.l2_len = tx_pkt->l2_len;
2651                 tx_offload.l3_len = tx_pkt->l3_len;
2652                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2653                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2654                 tx_offload.l4_len = tx_pkt->l4_len;
2655                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2656                 /* Calculate the number of context descriptors needed. */
2657                 nb_ctx = ice_calc_context_desc(ol_flags);
2658
2659                 /* The number of descriptors that must be allocated for
2660                  * a packet equals to the number of the segments of that
2661                  * packet plus the number of context descriptor if needed.
2662                  * Recalculate the needed tx descs when TSO enabled in case
2663                  * the mbuf data size exceeds max data size that hw allows
2664                  * per tx desc.
2665                  */
2666                 if (ol_flags & PKT_TX_TCP_SEG)
2667                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2668                                              nb_ctx);
2669                 else
2670                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2671                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2672
2673                 /* Circular ring */
2674                 if (tx_last >= txq->nb_tx_desc)
2675                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2676
2677                 if (nb_used > txq->nb_tx_free) {
2678                         if (ice_xmit_cleanup(txq) != 0) {
2679                                 if (nb_tx == 0)
2680                                         return 0;
2681                                 goto end_of_tx;
2682                         }
2683                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2684                                 while (nb_used > txq->nb_tx_free) {
2685                                         if (ice_xmit_cleanup(txq) != 0) {
2686                                                 if (nb_tx == 0)
2687                                                         return 0;
2688                                                 goto end_of_tx;
2689                                         }
2690                                 }
2691                         }
2692                 }
2693
2694                 /* Descriptor based VLAN insertion */
2695                 if (ol_flags & (PKT_TX_VLAN | PKT_TX_QINQ)) {
2696                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2697                         td_tag = tx_pkt->vlan_tci;
2698                 }
2699
2700                 /* Fill in tunneling parameters if necessary */
2701                 cd_tunneling_params = 0;
2702                 if (ol_flags & PKT_TX_TUNNEL_MASK)
2703                         ice_parse_tunneling_params(ol_flags, tx_offload,
2704                                                    &cd_tunneling_params);
2705
2706                 /* Enable checksum offloading */
2707                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2708                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2709                                                 &td_offset, tx_offload);
2710
2711                 if (nb_ctx) {
2712                         /* Setup TX context descriptor if required */
2713                         volatile struct ice_tx_ctx_desc *ctx_txd =
2714                                 (volatile struct ice_tx_ctx_desc *)
2715                                         &tx_ring[tx_id];
2716                         uint16_t cd_l2tag2 = 0;
2717                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2718
2719                         txn = &sw_ring[txe->next_id];
2720                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2721                         if (txe->mbuf) {
2722                                 rte_pktmbuf_free_seg(txe->mbuf);
2723                                 txe->mbuf = NULL;
2724                         }
2725
2726                         if (ol_flags & PKT_TX_TCP_SEG)
2727                                 cd_type_cmd_tso_mss |=
2728                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2729
2730                         ctx_txd->tunneling_params =
2731                                 rte_cpu_to_le_32(cd_tunneling_params);
2732
2733                         /* TX context descriptor based double VLAN insert */
2734                         if (ol_flags & PKT_TX_QINQ) {
2735                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2736                                 cd_type_cmd_tso_mss |=
2737                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2738                                          ICE_TXD_CTX_QW1_CMD_S);
2739                         }
2740                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2741                         ctx_txd->qw1 =
2742                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2743
2744                         txe->last_id = tx_last;
2745                         tx_id = txe->next_id;
2746                         txe = txn;
2747                 }
2748                 m_seg = tx_pkt;
2749
2750                 do {
2751                         txd = &tx_ring[tx_id];
2752                         txn = &sw_ring[txe->next_id];
2753
2754                         if (txe->mbuf)
2755                                 rte_pktmbuf_free_seg(txe->mbuf);
2756                         txe->mbuf = m_seg;
2757
2758                         /* Setup TX Descriptor */
2759                         slen = m_seg->data_len;
2760                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2761
2762                         while ((ol_flags & PKT_TX_TCP_SEG) &&
2763                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2764                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2765                                 txd->cmd_type_offset_bsz =
2766                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2767                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2768                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2769                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2770                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2771                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2772
2773                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2774                                 slen -= ICE_MAX_DATA_PER_TXD;
2775
2776                                 txe->last_id = tx_last;
2777                                 tx_id = txe->next_id;
2778                                 txe = txn;
2779                                 txd = &tx_ring[tx_id];
2780                                 txn = &sw_ring[txe->next_id];
2781                         }
2782
2783                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2784                         txd->cmd_type_offset_bsz =
2785                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2786                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2787                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2788                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2789                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2790
2791                         txe->last_id = tx_last;
2792                         tx_id = txe->next_id;
2793                         txe = txn;
2794                         m_seg = m_seg->next;
2795                 } while (m_seg);
2796
2797                 /* fill the last descriptor with End of Packet (EOP) bit */
2798                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2799                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2800                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2801
2802                 /* set RS bit on the last descriptor of one packet */
2803                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2804                         PMD_TX_LOG(DEBUG,
2805                                    "Setting RS bit on TXD id="
2806                                    "%4u (port=%d queue=%d)",
2807                                    tx_last, txq->port_id, txq->queue_id);
2808
2809                         td_cmd |= ICE_TX_DESC_CMD_RS;
2810
2811                         /* Update txq RS bit counters */
2812                         txq->nb_tx_used = 0;
2813                 }
2814                 txd->cmd_type_offset_bsz |=
2815                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2816                                          ICE_TXD_QW1_CMD_S);
2817         }
2818 end_of_tx:
2819         /* update Tail register */
2820         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2821         txq->tx_tail = tx_id;
2822
2823         return nb_tx;
2824 }
2825
2826 static __rte_always_inline int
2827 ice_tx_free_bufs(struct ice_tx_queue *txq)
2828 {
2829         struct ice_tx_entry *txep;
2830         uint16_t i;
2831
2832         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2833              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2834             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2835                 return 0;
2836
2837         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2838
2839         for (i = 0; i < txq->tx_rs_thresh; i++)
2840                 rte_prefetch0((txep + i)->mbuf);
2841
2842         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
2843                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2844                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2845                         txep->mbuf = NULL;
2846                 }
2847         } else {
2848                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2849                         rte_pktmbuf_free_seg(txep->mbuf);
2850                         txep->mbuf = NULL;
2851                 }
2852         }
2853
2854         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2855         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2856         if (txq->tx_next_dd >= txq->nb_tx_desc)
2857                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2858
2859         return txq->tx_rs_thresh;
2860 }
2861
2862 static int
2863 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2864                         uint32_t free_cnt)
2865 {
2866         struct ice_tx_entry *swr_ring = txq->sw_ring;
2867         uint16_t i, tx_last, tx_id;
2868         uint16_t nb_tx_free_last;
2869         uint16_t nb_tx_to_clean;
2870         uint32_t pkt_cnt;
2871
2872         /* Start free mbuf from the next of tx_tail */
2873         tx_last = txq->tx_tail;
2874         tx_id  = swr_ring[tx_last].next_id;
2875
2876         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2877                 return 0;
2878
2879         nb_tx_to_clean = txq->nb_tx_free;
2880         nb_tx_free_last = txq->nb_tx_free;
2881         if (!free_cnt)
2882                 free_cnt = txq->nb_tx_desc;
2883
2884         /* Loop through swr_ring to count the amount of
2885          * freeable mubfs and packets.
2886          */
2887         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2888                 for (i = 0; i < nb_tx_to_clean &&
2889                         pkt_cnt < free_cnt &&
2890                         tx_id != tx_last; i++) {
2891                         if (swr_ring[tx_id].mbuf != NULL) {
2892                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2893                                 swr_ring[tx_id].mbuf = NULL;
2894
2895                                 /*
2896                                  * last segment in the packet,
2897                                  * increment packet count
2898                                  */
2899                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2900                         }
2901
2902                         tx_id = swr_ring[tx_id].next_id;
2903                 }
2904
2905                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2906                         txq->nb_tx_free || tx_id == tx_last)
2907                         break;
2908
2909                 if (pkt_cnt < free_cnt) {
2910                         if (ice_xmit_cleanup(txq))
2911                                 break;
2912
2913                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2914                         nb_tx_free_last = txq->nb_tx_free;
2915                 }
2916         }
2917
2918         return (int)pkt_cnt;
2919 }
2920
2921 #ifdef RTE_ARCH_X86
2922 static int
2923 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2924                         uint32_t free_cnt __rte_unused)
2925 {
2926         return -ENOTSUP;
2927 }
2928 #endif
2929
2930 static int
2931 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
2932                         uint32_t free_cnt)
2933 {
2934         int i, n, cnt;
2935
2936         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
2937                 free_cnt = txq->nb_tx_desc;
2938
2939         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
2940
2941         for (i = 0; i < cnt; i += n) {
2942                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
2943                         break;
2944
2945                 n = ice_tx_free_bufs(txq);
2946
2947                 if (n == 0)
2948                         break;
2949         }
2950
2951         return i;
2952 }
2953
2954 int
2955 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
2956 {
2957         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
2958         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
2959         struct ice_adapter *ad =
2960                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2961
2962 #ifdef RTE_ARCH_X86
2963         if (ad->tx_vec_allowed)
2964                 return ice_tx_done_cleanup_vec(q, free_cnt);
2965 #endif
2966         if (ad->tx_simple_allowed)
2967                 return ice_tx_done_cleanup_simple(q, free_cnt);
2968         else
2969                 return ice_tx_done_cleanup_full(q, free_cnt);
2970 }
2971
2972 /* Populate 4 descriptors with data from 4 mbufs */
2973 static inline void
2974 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2975 {
2976         uint64_t dma_addr;
2977         uint32_t i;
2978
2979         for (i = 0; i < 4; i++, txdp++, pkts++) {
2980                 dma_addr = rte_mbuf_data_iova(*pkts);
2981                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2982                 txdp->cmd_type_offset_bsz =
2983                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2984                                        (*pkts)->data_len, 0);
2985         }
2986 }
2987
2988 /* Populate 1 descriptor with data from 1 mbuf */
2989 static inline void
2990 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
2991 {
2992         uint64_t dma_addr;
2993
2994         dma_addr = rte_mbuf_data_iova(*pkts);
2995         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
2996         txdp->cmd_type_offset_bsz =
2997                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
2998                                (*pkts)->data_len, 0);
2999 }
3000
3001 static inline void
3002 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
3003                     uint16_t nb_pkts)
3004 {
3005         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
3006         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
3007         const int N_PER_LOOP = 4;
3008         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
3009         int mainpart, leftover;
3010         int i, j;
3011
3012         /**
3013          * Process most of the packets in chunks of N pkts.  Any
3014          * leftover packets will get processed one at a time.
3015          */
3016         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
3017         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
3018         for (i = 0; i < mainpart; i += N_PER_LOOP) {
3019                 /* Copy N mbuf pointers to the S/W ring */
3020                 for (j = 0; j < N_PER_LOOP; ++j)
3021                         (txep + i + j)->mbuf = *(pkts + i + j);
3022                 tx4(txdp + i, pkts + i);
3023         }
3024
3025         if (unlikely(leftover > 0)) {
3026                 for (i = 0; i < leftover; ++i) {
3027                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
3028                         tx1(txdp + mainpart + i, pkts + mainpart + i);
3029                 }
3030         }
3031 }
3032
3033 static inline uint16_t
3034 tx_xmit_pkts(struct ice_tx_queue *txq,
3035              struct rte_mbuf **tx_pkts,
3036              uint16_t nb_pkts)
3037 {
3038         volatile struct ice_tx_desc *txr = txq->tx_ring;
3039         uint16_t n = 0;
3040
3041         /**
3042          * Begin scanning the H/W ring for done descriptors when the number
3043          * of available descriptors drops below tx_free_thresh. For each done
3044          * descriptor, free the associated buffer.
3045          */
3046         if (txq->nb_tx_free < txq->tx_free_thresh)
3047                 ice_tx_free_bufs(txq);
3048
3049         /* Use available descriptor only */
3050         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
3051         if (unlikely(!nb_pkts))
3052                 return 0;
3053
3054         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
3055         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
3056                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
3057                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
3058                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3059                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3060                                          ICE_TXD_QW1_CMD_S);
3061                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3062                 txq->tx_tail = 0;
3063         }
3064
3065         /* Fill hardware descriptor ring with mbuf data */
3066         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3067         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3068
3069         /* Determin if RS bit needs to be set */
3070         if (txq->tx_tail > txq->tx_next_rs) {
3071                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3072                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3073                                          ICE_TXD_QW1_CMD_S);
3074                 txq->tx_next_rs =
3075                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3076                 if (txq->tx_next_rs >= txq->nb_tx_desc)
3077                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3078         }
3079
3080         if (txq->tx_tail >= txq->nb_tx_desc)
3081                 txq->tx_tail = 0;
3082
3083         /* Update the tx tail register */
3084         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3085
3086         return nb_pkts;
3087 }
3088
3089 static uint16_t
3090 ice_xmit_pkts_simple(void *tx_queue,
3091                      struct rte_mbuf **tx_pkts,
3092                      uint16_t nb_pkts)
3093 {
3094         uint16_t nb_tx = 0;
3095
3096         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3097                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3098                                     tx_pkts, nb_pkts);
3099
3100         while (nb_pkts) {
3101                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3102                                                       ICE_TX_MAX_BURST);
3103
3104                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3105                                    &tx_pkts[nb_tx], num);
3106                 nb_tx = (uint16_t)(nb_tx + ret);
3107                 nb_pkts = (uint16_t)(nb_pkts - ret);
3108                 if (ret < num)
3109                         break;
3110         }
3111
3112         return nb_tx;
3113 }
3114
3115 void __rte_cold
3116 ice_set_rx_function(struct rte_eth_dev *dev)
3117 {
3118         PMD_INIT_FUNC_TRACE();
3119         struct ice_adapter *ad =
3120                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3121 #ifdef RTE_ARCH_X86
3122         struct ice_rx_queue *rxq;
3123         int i;
3124         int rx_check_ret = -1;
3125
3126         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3127                 ad->rx_use_avx512 = false;
3128                 ad->rx_use_avx2 = false;
3129                 rx_check_ret = ice_rx_vec_dev_check(dev);
3130                 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3131                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3132                         ad->rx_vec_allowed = true;
3133                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3134                                 rxq = dev->data->rx_queues[i];
3135                                 if (rxq && ice_rxq_vec_setup(rxq)) {
3136                                         ad->rx_vec_allowed = false;
3137                                         break;
3138                                 }
3139                         }
3140
3141                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3142                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3143                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3144 #ifdef CC_AVX512_SUPPORT
3145                                 ad->rx_use_avx512 = true;
3146 #else
3147                         PMD_DRV_LOG(NOTICE,
3148                                 "AVX512 is not supported in build env");
3149 #endif
3150                         if (!ad->rx_use_avx512 &&
3151                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3152                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3153                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3154                                 ad->rx_use_avx2 = true;
3155
3156                 } else {
3157                         ad->rx_vec_allowed = false;
3158                 }
3159         }
3160
3161         if (ad->rx_vec_allowed) {
3162                 if (dev->data->scattered_rx) {
3163                         if (ad->rx_use_avx512) {
3164 #ifdef CC_AVX512_SUPPORT
3165                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3166                                         PMD_DRV_LOG(NOTICE,
3167                                                 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3168                                                 dev->data->port_id);
3169                                         dev->rx_pkt_burst =
3170                                                 ice_recv_scattered_pkts_vec_avx512_offload;
3171                                 } else {
3172                                         PMD_DRV_LOG(NOTICE,
3173                                                 "Using AVX512 Vector Scattered Rx (port %d).",
3174                                                 dev->data->port_id);
3175                                         dev->rx_pkt_burst =
3176                                                 ice_recv_scattered_pkts_vec_avx512;
3177                                 }
3178 #endif
3179                         } else if (ad->rx_use_avx2) {
3180                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3181                                         PMD_DRV_LOG(NOTICE,
3182                                                     "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3183                                                     dev->data->port_id);
3184                                         dev->rx_pkt_burst =
3185                                                 ice_recv_scattered_pkts_vec_avx2_offload;
3186                                 } else {
3187                                         PMD_DRV_LOG(NOTICE,
3188                                                     "Using AVX2 Vector Scattered Rx (port %d).",
3189                                                     dev->data->port_id);
3190                                         dev->rx_pkt_burst =
3191                                                 ice_recv_scattered_pkts_vec_avx2;
3192                                 }
3193                         } else {
3194                                 PMD_DRV_LOG(DEBUG,
3195                                         "Using Vector Scattered Rx (port %d).",
3196                                         dev->data->port_id);
3197                                 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3198                         }
3199                 } else {
3200                         if (ad->rx_use_avx512) {
3201 #ifdef CC_AVX512_SUPPORT
3202                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3203                                         PMD_DRV_LOG(NOTICE,
3204                                                 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3205                                                 dev->data->port_id);
3206                                         dev->rx_pkt_burst =
3207                                                 ice_recv_pkts_vec_avx512_offload;
3208                                 } else {
3209                                         PMD_DRV_LOG(NOTICE,
3210                                                 "Using AVX512 Vector Rx (port %d).",
3211                                                 dev->data->port_id);
3212                                         dev->rx_pkt_burst =
3213                                                 ice_recv_pkts_vec_avx512;
3214                                 }
3215 #endif
3216                         } else if (ad->rx_use_avx2) {
3217                                 if (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3218                                         PMD_DRV_LOG(NOTICE,
3219                                                     "Using AVX2 OFFLOAD Vector Rx (port %d).",
3220                                                     dev->data->port_id);
3221                                         dev->rx_pkt_burst =
3222                                                 ice_recv_pkts_vec_avx2_offload;
3223                                 } else {
3224                                         PMD_DRV_LOG(NOTICE,
3225                                                     "Using AVX2 Vector Rx (port %d).",
3226                                                     dev->data->port_id);
3227                                         dev->rx_pkt_burst =
3228                                                 ice_recv_pkts_vec_avx2;
3229                                 }
3230                         } else {
3231                                 PMD_DRV_LOG(DEBUG,
3232                                         "Using Vector Rx (port %d).",
3233                                         dev->data->port_id);
3234                                 dev->rx_pkt_burst = ice_recv_pkts_vec;
3235                         }
3236                 }
3237                 return;
3238         }
3239
3240 #endif
3241
3242         if (dev->data->scattered_rx) {
3243                 /* Set the non-LRO scattered function */
3244                 PMD_INIT_LOG(DEBUG,
3245                              "Using a Scattered function on port %d.",
3246                              dev->data->port_id);
3247                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3248         } else if (ad->rx_bulk_alloc_allowed) {
3249                 PMD_INIT_LOG(DEBUG,
3250                              "Rx Burst Bulk Alloc Preconditions are "
3251                              "satisfied. Rx Burst Bulk Alloc function "
3252                              "will be used on port %d.",
3253                              dev->data->port_id);
3254                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3255         } else {
3256                 PMD_INIT_LOG(DEBUG,
3257                              "Rx Burst Bulk Alloc Preconditions are not "
3258                              "satisfied, Normal Rx will be used on port %d.",
3259                              dev->data->port_id);
3260                 dev->rx_pkt_burst = ice_recv_pkts;
3261         }
3262 }
3263
3264 static const struct {
3265         eth_rx_burst_t pkt_burst;
3266         const char *info;
3267 } ice_rx_burst_infos[] = {
3268         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3269         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3270         { ice_recv_pkts,                    "Scalar" },
3271 #ifdef RTE_ARCH_X86
3272 #ifdef CC_AVX512_SUPPORT
3273         { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3274         { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3275         { ice_recv_pkts_vec_avx512,           "Vector AVX512" },
3276         { ice_recv_pkts_vec_avx512_offload,   "Offload Vector AVX512" },
3277 #endif
3278         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3279         { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3280         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3281         { ice_recv_pkts_vec_avx2_offload,   "Offload Vector AVX2" },
3282         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3283         { ice_recv_pkts_vec,                "Vector SSE" },
3284 #endif
3285 };
3286
3287 int
3288 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3289                       struct rte_eth_burst_mode *mode)
3290 {
3291         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3292         int ret = -EINVAL;
3293         unsigned int i;
3294
3295         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3296                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3297                         snprintf(mode->info, sizeof(mode->info), "%s",
3298                                  ice_rx_burst_infos[i].info);
3299                         ret = 0;
3300                         break;
3301                 }
3302         }
3303
3304         return ret;
3305 }
3306
3307 void __rte_cold
3308 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3309 {
3310         struct ice_adapter *ad =
3311                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3312
3313         /* Use a simple Tx queue if possible (only fast free is allowed) */
3314         ad->tx_simple_allowed =
3315                 (txq->offloads ==
3316                 (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3317                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3318
3319         if (ad->tx_simple_allowed)
3320                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3321                              txq->queue_id);
3322         else
3323                 PMD_INIT_LOG(DEBUG,
3324                              "Simple Tx can NOT be enabled on Tx queue %u.",
3325                              txq->queue_id);
3326 }
3327
3328 /*********************************************************************
3329  *
3330  *  TX prep functions
3331  *
3332  **********************************************************************/
3333 /* The default values of TSO MSS */
3334 #define ICE_MIN_TSO_MSS            64
3335 #define ICE_MAX_TSO_MSS            9728
3336 #define ICE_MAX_TSO_FRAME_SIZE     262144
3337 uint16_t
3338 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3339               uint16_t nb_pkts)
3340 {
3341         int i, ret;
3342         uint64_t ol_flags;
3343         struct rte_mbuf *m;
3344
3345         for (i = 0; i < nb_pkts; i++) {
3346                 m = tx_pkts[i];
3347                 ol_flags = m->ol_flags;
3348
3349                 if (ol_flags & PKT_TX_TCP_SEG &&
3350                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3351                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3352                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3353                         /**
3354                          * MSS outside the range are considered malicious
3355                          */
3356                         rte_errno = EINVAL;
3357                         return i;
3358                 }
3359
3360 #ifdef RTE_ETHDEV_DEBUG_TX
3361                 ret = rte_validate_tx_offload(m);
3362                 if (ret != 0) {
3363                         rte_errno = -ret;
3364                         return i;
3365                 }
3366 #endif
3367                 ret = rte_net_intel_cksum_prepare(m);
3368                 if (ret != 0) {
3369                         rte_errno = -ret;
3370                         return i;
3371                 }
3372         }
3373         return i;
3374 }
3375
3376 void __rte_cold
3377 ice_set_tx_function(struct rte_eth_dev *dev)
3378 {
3379         struct ice_adapter *ad =
3380                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3381 #ifdef RTE_ARCH_X86
3382         struct ice_tx_queue *txq;
3383         int i;
3384         int tx_check_ret = -1;
3385
3386         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3387                 ad->tx_use_avx2 = false;
3388                 ad->tx_use_avx512 = false;
3389                 tx_check_ret = ice_tx_vec_dev_check(dev);
3390                 if (tx_check_ret >= 0 &&
3391                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3392                         ad->tx_vec_allowed = true;
3393
3394                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3395                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3396                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3397 #ifdef CC_AVX512_SUPPORT
3398                                 ad->tx_use_avx512 = true;
3399 #else
3400                         PMD_DRV_LOG(NOTICE,
3401                                 "AVX512 is not supported in build env");
3402 #endif
3403                         if (!ad->tx_use_avx512 &&
3404                                 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3405                                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3406                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3407                                 ad->tx_use_avx2 = true;
3408
3409                         if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3410                                 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3411                                 ad->tx_vec_allowed = false;
3412
3413                         if (ad->tx_vec_allowed) {
3414                                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3415                                         txq = dev->data->tx_queues[i];
3416                                         if (txq && ice_txq_vec_setup(txq)) {
3417                                                 ad->tx_vec_allowed = false;
3418                                                 break;
3419                                         }
3420                                 }
3421                         }
3422                 } else {
3423                         ad->tx_vec_allowed = false;
3424                 }
3425         }
3426
3427         if (ad->tx_vec_allowed) {
3428                 dev->tx_pkt_prepare = NULL;
3429                 if (ad->tx_use_avx512) {
3430 #ifdef CC_AVX512_SUPPORT
3431                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3432                                 PMD_DRV_LOG(NOTICE,
3433                                             "Using AVX512 OFFLOAD Vector Tx (port %d).",
3434                                             dev->data->port_id);
3435                                 dev->tx_pkt_burst =
3436                                         ice_xmit_pkts_vec_avx512_offload;
3437                                 dev->tx_pkt_prepare = ice_prep_pkts;
3438                         } else {
3439                                 PMD_DRV_LOG(NOTICE,
3440                                             "Using AVX512 Vector Tx (port %d).",
3441                                             dev->data->port_id);
3442                                 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3443                         }
3444 #endif
3445                 } else {
3446                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3447                                 PMD_DRV_LOG(NOTICE,
3448                                             "Using AVX2 OFFLOAD Vector Tx (port %d).",
3449                                             dev->data->port_id);
3450                                 dev->tx_pkt_burst =
3451                                         ice_xmit_pkts_vec_avx2_offload;
3452                                 dev->tx_pkt_prepare = ice_prep_pkts;
3453                         } else {
3454                                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3455                                             ad->tx_use_avx2 ? "avx2 " : "",
3456                                             dev->data->port_id);
3457                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3458                                                     ice_xmit_pkts_vec_avx2 :
3459                                                     ice_xmit_pkts_vec;
3460                         }
3461                 }
3462
3463                 return;
3464         }
3465 #endif
3466
3467         if (ad->tx_simple_allowed) {
3468                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3469                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3470                 dev->tx_pkt_prepare = NULL;
3471         } else {
3472                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3473                 dev->tx_pkt_burst = ice_xmit_pkts;
3474                 dev->tx_pkt_prepare = ice_prep_pkts;
3475         }
3476 }
3477
3478 static const struct {
3479         eth_tx_burst_t pkt_burst;
3480         const char *info;
3481 } ice_tx_burst_infos[] = {
3482         { ice_xmit_pkts_simple,   "Scalar Simple" },
3483         { ice_xmit_pkts,          "Scalar" },
3484 #ifdef RTE_ARCH_X86
3485 #ifdef CC_AVX512_SUPPORT
3486         { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3487         { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3488 #endif
3489         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3490         { ice_xmit_pkts_vec,      "Vector SSE" },
3491 #endif
3492 };
3493
3494 int
3495 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3496                       struct rte_eth_burst_mode *mode)
3497 {
3498         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3499         int ret = -EINVAL;
3500         unsigned int i;
3501
3502         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3503                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3504                         snprintf(mode->info, sizeof(mode->info), "%s",
3505                                  ice_tx_burst_infos[i].info);
3506                         ret = 0;
3507                         break;
3508                 }
3509         }
3510
3511         return ret;
3512 }
3513
3514 /* For each value it means, datasheet of hardware can tell more details
3515  *
3516  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3517  */
3518 static inline uint32_t
3519 ice_get_default_pkt_type(uint16_t ptype)
3520 {
3521         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3522                 __rte_cache_aligned = {
3523                 /* L2 types */
3524                 /* [0] reserved */
3525                 [1] = RTE_PTYPE_L2_ETHER,
3526                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3527                 /* [3] - [5] reserved */
3528                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3529                 /* [7] - [10] reserved */
3530                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3531                 /* [12] - [21] reserved */
3532
3533                 /* Non tunneled IPv4 */
3534                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3535                        RTE_PTYPE_L4_FRAG,
3536                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3537                        RTE_PTYPE_L4_NONFRAG,
3538                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3539                        RTE_PTYPE_L4_UDP,
3540                 /* [25] reserved */
3541                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3542                        RTE_PTYPE_L4_TCP,
3543                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3544                        RTE_PTYPE_L4_SCTP,
3545                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3546                        RTE_PTYPE_L4_ICMP,
3547
3548                 /* IPv4 --> IPv4 */
3549                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3550                        RTE_PTYPE_TUNNEL_IP |
3551                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3552                        RTE_PTYPE_INNER_L4_FRAG,
3553                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3554                        RTE_PTYPE_TUNNEL_IP |
3555                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3556                        RTE_PTYPE_INNER_L4_NONFRAG,
3557                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3558                        RTE_PTYPE_TUNNEL_IP |
3559                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3560                        RTE_PTYPE_INNER_L4_UDP,
3561                 /* [32] reserved */
3562                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3563                        RTE_PTYPE_TUNNEL_IP |
3564                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3565                        RTE_PTYPE_INNER_L4_TCP,
3566                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3567                        RTE_PTYPE_TUNNEL_IP |
3568                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3569                        RTE_PTYPE_INNER_L4_SCTP,
3570                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3571                        RTE_PTYPE_TUNNEL_IP |
3572                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3573                        RTE_PTYPE_INNER_L4_ICMP,
3574
3575                 /* IPv4 --> IPv6 */
3576                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3577                        RTE_PTYPE_TUNNEL_IP |
3578                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3579                        RTE_PTYPE_INNER_L4_FRAG,
3580                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3581                        RTE_PTYPE_TUNNEL_IP |
3582                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3583                        RTE_PTYPE_INNER_L4_NONFRAG,
3584                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3585                        RTE_PTYPE_TUNNEL_IP |
3586                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3587                        RTE_PTYPE_INNER_L4_UDP,
3588                 /* [39] reserved */
3589                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3590                        RTE_PTYPE_TUNNEL_IP |
3591                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3592                        RTE_PTYPE_INNER_L4_TCP,
3593                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3594                        RTE_PTYPE_TUNNEL_IP |
3595                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3596                        RTE_PTYPE_INNER_L4_SCTP,
3597                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3598                        RTE_PTYPE_TUNNEL_IP |
3599                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3600                        RTE_PTYPE_INNER_L4_ICMP,
3601
3602                 /* IPv4 --> GRE/Teredo/VXLAN */
3603                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3604                        RTE_PTYPE_TUNNEL_GRENAT,
3605
3606                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3607                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3608                        RTE_PTYPE_TUNNEL_GRENAT |
3609                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3610                        RTE_PTYPE_INNER_L4_FRAG,
3611                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3612                        RTE_PTYPE_TUNNEL_GRENAT |
3613                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3614                        RTE_PTYPE_INNER_L4_NONFRAG,
3615                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3616                        RTE_PTYPE_TUNNEL_GRENAT |
3617                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3618                        RTE_PTYPE_INNER_L4_UDP,
3619                 /* [47] reserved */
3620                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3621                        RTE_PTYPE_TUNNEL_GRENAT |
3622                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3623                        RTE_PTYPE_INNER_L4_TCP,
3624                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3625                        RTE_PTYPE_TUNNEL_GRENAT |
3626                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3627                        RTE_PTYPE_INNER_L4_SCTP,
3628                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3629                        RTE_PTYPE_TUNNEL_GRENAT |
3630                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3631                        RTE_PTYPE_INNER_L4_ICMP,
3632
3633                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3634                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3635                        RTE_PTYPE_TUNNEL_GRENAT |
3636                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3637                        RTE_PTYPE_INNER_L4_FRAG,
3638                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3639                        RTE_PTYPE_TUNNEL_GRENAT |
3640                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3641                        RTE_PTYPE_INNER_L4_NONFRAG,
3642                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3643                        RTE_PTYPE_TUNNEL_GRENAT |
3644                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3645                        RTE_PTYPE_INNER_L4_UDP,
3646                 /* [54] reserved */
3647                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3648                        RTE_PTYPE_TUNNEL_GRENAT |
3649                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3650                        RTE_PTYPE_INNER_L4_TCP,
3651                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3652                        RTE_PTYPE_TUNNEL_GRENAT |
3653                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3654                        RTE_PTYPE_INNER_L4_SCTP,
3655                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3656                        RTE_PTYPE_TUNNEL_GRENAT |
3657                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3658                        RTE_PTYPE_INNER_L4_ICMP,
3659
3660                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3661                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3662                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3663
3664                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3665                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3666                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3667                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3668                        RTE_PTYPE_INNER_L4_FRAG,
3669                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3670                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3671                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3672                        RTE_PTYPE_INNER_L4_NONFRAG,
3673                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3674                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3675                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3676                        RTE_PTYPE_INNER_L4_UDP,
3677                 /* [62] reserved */
3678                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3679                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3680                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3681                        RTE_PTYPE_INNER_L4_TCP,
3682                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3683                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3684                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3685                        RTE_PTYPE_INNER_L4_SCTP,
3686                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3687                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3688                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3689                        RTE_PTYPE_INNER_L4_ICMP,
3690
3691                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3692                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3693                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3694                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3695                        RTE_PTYPE_INNER_L4_FRAG,
3696                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3697                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3698                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3699                        RTE_PTYPE_INNER_L4_NONFRAG,
3700                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3701                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3702                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3703                        RTE_PTYPE_INNER_L4_UDP,
3704                 /* [69] reserved */
3705                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3706                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3707                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3708                        RTE_PTYPE_INNER_L4_TCP,
3709                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3710                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3711                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3712                        RTE_PTYPE_INNER_L4_SCTP,
3713                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3714                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3715                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3716                        RTE_PTYPE_INNER_L4_ICMP,
3717                 /* [73] - [87] reserved */
3718
3719                 /* Non tunneled IPv6 */
3720                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3721                        RTE_PTYPE_L4_FRAG,
3722                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3723                        RTE_PTYPE_L4_NONFRAG,
3724                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3725                        RTE_PTYPE_L4_UDP,
3726                 /* [91] reserved */
3727                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3728                        RTE_PTYPE_L4_TCP,
3729                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3730                        RTE_PTYPE_L4_SCTP,
3731                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3732                        RTE_PTYPE_L4_ICMP,
3733
3734                 /* IPv6 --> IPv4 */
3735                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3736                        RTE_PTYPE_TUNNEL_IP |
3737                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3738                        RTE_PTYPE_INNER_L4_FRAG,
3739                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3740                        RTE_PTYPE_TUNNEL_IP |
3741                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3742                        RTE_PTYPE_INNER_L4_NONFRAG,
3743                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3744                        RTE_PTYPE_TUNNEL_IP |
3745                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3746                        RTE_PTYPE_INNER_L4_UDP,
3747                 /* [98] reserved */
3748                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3749                        RTE_PTYPE_TUNNEL_IP |
3750                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3751                        RTE_PTYPE_INNER_L4_TCP,
3752                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3753                         RTE_PTYPE_TUNNEL_IP |
3754                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3755                         RTE_PTYPE_INNER_L4_SCTP,
3756                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3757                         RTE_PTYPE_TUNNEL_IP |
3758                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3759                         RTE_PTYPE_INNER_L4_ICMP,
3760
3761                 /* IPv6 --> IPv6 */
3762                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3763                         RTE_PTYPE_TUNNEL_IP |
3764                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3765                         RTE_PTYPE_INNER_L4_FRAG,
3766                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3767                         RTE_PTYPE_TUNNEL_IP |
3768                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3769                         RTE_PTYPE_INNER_L4_NONFRAG,
3770                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3771                         RTE_PTYPE_TUNNEL_IP |
3772                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3773                         RTE_PTYPE_INNER_L4_UDP,
3774                 /* [105] reserved */
3775                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3776                         RTE_PTYPE_TUNNEL_IP |
3777                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3778                         RTE_PTYPE_INNER_L4_TCP,
3779                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3780                         RTE_PTYPE_TUNNEL_IP |
3781                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3782                         RTE_PTYPE_INNER_L4_SCTP,
3783                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3784                         RTE_PTYPE_TUNNEL_IP |
3785                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3786                         RTE_PTYPE_INNER_L4_ICMP,
3787
3788                 /* IPv6 --> GRE/Teredo/VXLAN */
3789                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3790                         RTE_PTYPE_TUNNEL_GRENAT,
3791
3792                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3793                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3794                         RTE_PTYPE_TUNNEL_GRENAT |
3795                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3796                         RTE_PTYPE_INNER_L4_FRAG,
3797                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3798                         RTE_PTYPE_TUNNEL_GRENAT |
3799                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3800                         RTE_PTYPE_INNER_L4_NONFRAG,
3801                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3802                         RTE_PTYPE_TUNNEL_GRENAT |
3803                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3804                         RTE_PTYPE_INNER_L4_UDP,
3805                 /* [113] reserved */
3806                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3807                         RTE_PTYPE_TUNNEL_GRENAT |
3808                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3809                         RTE_PTYPE_INNER_L4_TCP,
3810                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3811                         RTE_PTYPE_TUNNEL_GRENAT |
3812                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3813                         RTE_PTYPE_INNER_L4_SCTP,
3814                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3815                         RTE_PTYPE_TUNNEL_GRENAT |
3816                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3817                         RTE_PTYPE_INNER_L4_ICMP,
3818
3819                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3820                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3821                         RTE_PTYPE_TUNNEL_GRENAT |
3822                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3823                         RTE_PTYPE_INNER_L4_FRAG,
3824                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3825                         RTE_PTYPE_TUNNEL_GRENAT |
3826                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3827                         RTE_PTYPE_INNER_L4_NONFRAG,
3828                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3829                         RTE_PTYPE_TUNNEL_GRENAT |
3830                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3831                         RTE_PTYPE_INNER_L4_UDP,
3832                 /* [120] reserved */
3833                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3834                         RTE_PTYPE_TUNNEL_GRENAT |
3835                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3836                         RTE_PTYPE_INNER_L4_TCP,
3837                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3838                         RTE_PTYPE_TUNNEL_GRENAT |
3839                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3840                         RTE_PTYPE_INNER_L4_SCTP,
3841                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3842                         RTE_PTYPE_TUNNEL_GRENAT |
3843                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3844                         RTE_PTYPE_INNER_L4_ICMP,
3845
3846                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3847                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3848                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3849
3850                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3851                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3852                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3853                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3854                         RTE_PTYPE_INNER_L4_FRAG,
3855                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3856                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3857                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3858                         RTE_PTYPE_INNER_L4_NONFRAG,
3859                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3860                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3861                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3862                         RTE_PTYPE_INNER_L4_UDP,
3863                 /* [128] reserved */
3864                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3865                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3866                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3867                         RTE_PTYPE_INNER_L4_TCP,
3868                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3869                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3870                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3871                         RTE_PTYPE_INNER_L4_SCTP,
3872                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3873                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3874                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3875                         RTE_PTYPE_INNER_L4_ICMP,
3876
3877                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3878                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3879                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3880                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3881                         RTE_PTYPE_INNER_L4_FRAG,
3882                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3883                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3884                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3885                         RTE_PTYPE_INNER_L4_NONFRAG,
3886                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3887                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3888                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3889                         RTE_PTYPE_INNER_L4_UDP,
3890                 /* [135] reserved */
3891                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3892                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3893                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3894                         RTE_PTYPE_INNER_L4_TCP,
3895                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3896                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3897                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3898                         RTE_PTYPE_INNER_L4_SCTP,
3899                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3900                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3901                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3902                         RTE_PTYPE_INNER_L4_ICMP,
3903                 /* [139] - [299] reserved */
3904
3905                 /* PPPoE */
3906                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3907                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3908
3909                 /* PPPoE --> IPv4 */
3910                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3911                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3912                         RTE_PTYPE_L4_FRAG,
3913                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3914                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3915                         RTE_PTYPE_L4_NONFRAG,
3916                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3917                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3918                         RTE_PTYPE_L4_UDP,
3919                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3920                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3921                         RTE_PTYPE_L4_TCP,
3922                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
3923                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3924                         RTE_PTYPE_L4_SCTP,
3925                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
3926                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3927                         RTE_PTYPE_L4_ICMP,
3928
3929                 /* PPPoE --> IPv6 */
3930                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
3931                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3932                         RTE_PTYPE_L4_FRAG,
3933                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
3934                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3935                         RTE_PTYPE_L4_NONFRAG,
3936                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
3937                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3938                         RTE_PTYPE_L4_UDP,
3939                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
3940                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3941                         RTE_PTYPE_L4_TCP,
3942                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
3943                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3944                         RTE_PTYPE_L4_SCTP,
3945                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
3946                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3947                         RTE_PTYPE_L4_ICMP,
3948                 /* [314] - [324] reserved */
3949
3950                 /* IPv4/IPv6 --> GTPC/GTPU */
3951                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3952                         RTE_PTYPE_TUNNEL_GTPC,
3953                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3954                         RTE_PTYPE_TUNNEL_GTPC,
3955                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3956                         RTE_PTYPE_TUNNEL_GTPC,
3957                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3958                         RTE_PTYPE_TUNNEL_GTPC,
3959                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3960                         RTE_PTYPE_TUNNEL_GTPU,
3961                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3962                         RTE_PTYPE_TUNNEL_GTPU,
3963
3964                 /* IPv4 --> GTPU --> IPv4 */
3965                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3966                         RTE_PTYPE_TUNNEL_GTPU |
3967                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3968                         RTE_PTYPE_INNER_L4_FRAG,
3969                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3970                         RTE_PTYPE_TUNNEL_GTPU |
3971                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3972                         RTE_PTYPE_INNER_L4_NONFRAG,
3973                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3974                         RTE_PTYPE_TUNNEL_GTPU |
3975                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3976                         RTE_PTYPE_INNER_L4_UDP,
3977                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3978                         RTE_PTYPE_TUNNEL_GTPU |
3979                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3980                         RTE_PTYPE_INNER_L4_TCP,
3981                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3982                         RTE_PTYPE_TUNNEL_GTPU |
3983                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3984                         RTE_PTYPE_INNER_L4_ICMP,
3985
3986                 /* IPv6 --> GTPU --> IPv4 */
3987                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3988                         RTE_PTYPE_TUNNEL_GTPU |
3989                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3990                         RTE_PTYPE_INNER_L4_FRAG,
3991                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3992                         RTE_PTYPE_TUNNEL_GTPU |
3993                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3994                         RTE_PTYPE_INNER_L4_NONFRAG,
3995                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3996                         RTE_PTYPE_TUNNEL_GTPU |
3997                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3998                         RTE_PTYPE_INNER_L4_UDP,
3999                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4000                         RTE_PTYPE_TUNNEL_GTPU |
4001                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4002                         RTE_PTYPE_INNER_L4_TCP,
4003                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4004                         RTE_PTYPE_TUNNEL_GTPU |
4005                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4006                         RTE_PTYPE_INNER_L4_ICMP,
4007
4008                 /* IPv4 --> GTPU --> IPv6 */
4009                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4010                         RTE_PTYPE_TUNNEL_GTPU |
4011                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4012                         RTE_PTYPE_INNER_L4_FRAG,
4013                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4014                         RTE_PTYPE_TUNNEL_GTPU |
4015                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4016                         RTE_PTYPE_INNER_L4_NONFRAG,
4017                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4018                         RTE_PTYPE_TUNNEL_GTPU |
4019                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4020                         RTE_PTYPE_INNER_L4_UDP,
4021                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4022                         RTE_PTYPE_TUNNEL_GTPU |
4023                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4024                         RTE_PTYPE_INNER_L4_TCP,
4025                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4026                         RTE_PTYPE_TUNNEL_GTPU |
4027                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4028                         RTE_PTYPE_INNER_L4_ICMP,
4029
4030                 /* IPv6 --> GTPU --> IPv6 */
4031                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4032                         RTE_PTYPE_TUNNEL_GTPU |
4033                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4034                         RTE_PTYPE_INNER_L4_FRAG,
4035                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4036                         RTE_PTYPE_TUNNEL_GTPU |
4037                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4038                         RTE_PTYPE_INNER_L4_NONFRAG,
4039                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4040                         RTE_PTYPE_TUNNEL_GTPU |
4041                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4042                         RTE_PTYPE_INNER_L4_UDP,
4043                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4044                         RTE_PTYPE_TUNNEL_GTPU |
4045                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4046                         RTE_PTYPE_INNER_L4_TCP,
4047                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4048                         RTE_PTYPE_TUNNEL_GTPU |
4049                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4050                         RTE_PTYPE_INNER_L4_ICMP,
4051
4052                 /* IPv4 --> UDP ECPRI */
4053                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4054                         RTE_PTYPE_L4_UDP,
4055                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4056                         RTE_PTYPE_L4_UDP,
4057                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4058                         RTE_PTYPE_L4_UDP,
4059                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4060                         RTE_PTYPE_L4_UDP,
4061                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4062                         RTE_PTYPE_L4_UDP,
4063                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4064                         RTE_PTYPE_L4_UDP,
4065                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4066                         RTE_PTYPE_L4_UDP,
4067                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4068                         RTE_PTYPE_L4_UDP,
4069                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4070                         RTE_PTYPE_L4_UDP,
4071                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4072                         RTE_PTYPE_L4_UDP,
4073
4074                 /* IPV6 --> UDP ECPRI */
4075                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4076                         RTE_PTYPE_L4_UDP,
4077                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4078                         RTE_PTYPE_L4_UDP,
4079                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4080                         RTE_PTYPE_L4_UDP,
4081                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4082                         RTE_PTYPE_L4_UDP,
4083                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4084                         RTE_PTYPE_L4_UDP,
4085                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4086                         RTE_PTYPE_L4_UDP,
4087                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4088                         RTE_PTYPE_L4_UDP,
4089                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4090                         RTE_PTYPE_L4_UDP,
4091                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4092                         RTE_PTYPE_L4_UDP,
4093                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4094                         RTE_PTYPE_L4_UDP,
4095                 /* All others reserved */
4096         };
4097
4098         return type_table[ptype];
4099 }
4100
4101 void __rte_cold
4102 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4103 {
4104         struct ice_adapter *ad =
4105                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4106         int i;
4107
4108         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4109                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4110 }
4111
4112 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4113 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4114                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4115 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4116 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4117
4118 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
4119 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
4120         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4121 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
4122 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
4123         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4124
4125 /*
4126  * check the programming status descriptor in rx queue.
4127  * done after Programming Flow Director is programmed on
4128  * tx queue
4129  */
4130 static inline int
4131 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4132 {
4133         volatile union ice_32byte_rx_desc *rxdp;
4134         uint64_t qword1;
4135         uint32_t rx_status;
4136         uint32_t error;
4137         uint32_t id;
4138         int ret = -EAGAIN;
4139
4140         rxdp = (volatile union ice_32byte_rx_desc *)
4141                 (&rxq->rx_ring[rxq->rx_tail]);
4142         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4143         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4144                         >> ICE_RXD_QW1_STATUS_S;
4145
4146         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4147                 ret = 0;
4148                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4149                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4150                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4151                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4152                 if (error) {
4153                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4154                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4155                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4156                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4157                         ret = -EINVAL;
4158                         goto err;
4159                 }
4160                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4161                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4162                 if (error) {
4163                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4164                         ret = -EINVAL;
4165                 }
4166 err:
4167                 rxdp->wb.qword1.status_error_len = 0;
4168                 rxq->rx_tail++;
4169                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4170                         rxq->rx_tail = 0;
4171                 if (rxq->rx_tail == 0)
4172                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4173                 else
4174                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4175         }
4176
4177         return ret;
4178 }
4179
4180 #define ICE_FDIR_MAX_WAIT_US 10000
4181
4182 int
4183 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4184 {
4185         struct ice_tx_queue *txq = pf->fdir.txq;
4186         struct ice_rx_queue *rxq = pf->fdir.rxq;
4187         volatile struct ice_fltr_desc *fdirdp;
4188         volatile struct ice_tx_desc *txdp;
4189         uint32_t td_cmd;
4190         uint16_t i;
4191
4192         fdirdp = (volatile struct ice_fltr_desc *)
4193                 (&txq->tx_ring[txq->tx_tail]);
4194         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4195         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4196
4197         txdp = &txq->tx_ring[txq->tx_tail + 1];
4198         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4199         td_cmd = ICE_TX_DESC_CMD_EOP |
4200                 ICE_TX_DESC_CMD_RS  |
4201                 ICE_TX_DESC_CMD_DUMMY;
4202
4203         txdp->cmd_type_offset_bsz =
4204                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4205
4206         txq->tx_tail += 2;
4207         if (txq->tx_tail >= txq->nb_tx_desc)
4208                 txq->tx_tail = 0;
4209         /* Update the tx tail register */
4210         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4211         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4212                 if ((txdp->cmd_type_offset_bsz &
4213                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4214                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4215                         break;
4216                 rte_delay_us(1);
4217         }
4218         if (i >= ICE_FDIR_MAX_WAIT_US) {
4219                 PMD_DRV_LOG(ERR,
4220                             "Failed to program FDIR filter: time out to get DD on tx queue.");
4221                 return -ETIMEDOUT;
4222         }
4223
4224         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4225                 int ret;
4226
4227                 ret = ice_check_fdir_programming_status(rxq);
4228                 if (ret == -EAGAIN)
4229                         rte_delay_us(1);
4230                 else
4231                         return ret;
4232         }
4233
4234         PMD_DRV_LOG(ERR,
4235                     "Failed to program FDIR filter: programming status reported.");
4236         return -ETIMEDOUT;
4237
4238
4239 }