drivers/net/ice/ice_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <ethdev_driver.h>
   6 #include <rte_net.h>
   7 #include <rte_vect.h>
   8
   9 #include "rte_pmd_ice.h"
  10 #include "ice_rxtx.h"
  11 #include "ice_rxtx_vec_common.h"
  12
  13 #define ICE_TX_CKSUM_OFFLOAD_MASK (RTE_MBUF_F_TX_IP_CKSUM |              \
  14                 RTE_MBUF_F_TX_L4_MASK |          \
  15                 RTE_MBUF_F_TX_TCP_SEG |          \
  16                 RTE_MBUF_F_TX_OUTER_IP_CKSUM)
  17
  18 /* Offset of mbuf dynamic field for protocol extraction data */
  19 int rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
  20
  21 /* Mask of mbuf dynamic flags for protocol extraction type */
  22 uint64_t rte_net_ice_dynflag_proto_xtr_vlan_mask;
  23 uint64_t rte_net_ice_dynflag_proto_xtr_ipv4_mask;
  24 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_mask;
  25 uint64_t rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
  26 uint64_t rte_net_ice_dynflag_proto_xtr_tcp_mask;
  27 uint64_t rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
  28
  29 static int
  30 ice_monitor_callback(const uint64_t value,
  31                 const uint64_t arg[RTE_POWER_MONITOR_OPAQUE_SZ] __rte_unused)
  32 {
  33         const uint64_t m = rte_cpu_to_le_16(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
  34         /*
  35          * we expect the DD bit to be set to 1 if this descriptor was already
  36          * written to.
  37          */
  38         return (value & m) == m ? -1 : 0;
  39 }
  40
  41 int
  42 ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc)
  43 {
  44         volatile union ice_rx_flex_desc *rxdp;
  45         struct ice_rx_queue *rxq = rx_queue;
  46         uint16_t desc;
  47
  48         desc = rxq->rx_tail;
  49         rxdp = &rxq->rx_ring[desc];
  50         /* watch for changes in status bit */
  51         pmc->addr = &rxdp->wb.status_error0;
  52
  53         /* comparison callback */
  54         pmc->fn = ice_monitor_callback;
  55
  56         /* register is 16-bit */
  57         pmc->size = sizeof(uint16_t);
  58
  59         return 0;
  60 }
  61
  62
  63 static inline uint8_t
  64 ice_proto_xtr_type_to_rxdid(uint8_t xtr_type)
  65 {
  66         static uint8_t rxdid_map[] = {
  67                 [PROTO_XTR_NONE]      = ICE_RXDID_COMMS_OVS,
  68                 [PROTO_XTR_VLAN]      = ICE_RXDID_COMMS_AUX_VLAN,
  69                 [PROTO_XTR_IPV4]      = ICE_RXDID_COMMS_AUX_IPV4,
  70                 [PROTO_XTR_IPV6]      = ICE_RXDID_COMMS_AUX_IPV6,
  71                 [PROTO_XTR_IPV6_FLOW] = ICE_RXDID_COMMS_AUX_IPV6_FLOW,
  72                 [PROTO_XTR_TCP]       = ICE_RXDID_COMMS_AUX_TCP,
  73                 [PROTO_XTR_IP_OFFSET] = ICE_RXDID_COMMS_AUX_IP_OFFSET,
  74         };
  75
  76         return xtr_type < RTE_DIM(rxdid_map) ?
  77                                 rxdid_map[xtr_type] : ICE_RXDID_COMMS_OVS;
  78 }
  79
  80 static inline void
  81 ice_rxd_to_pkt_fields_by_comms_generic(__rte_unused struct ice_rx_queue *rxq,
  82                                        struct rte_mbuf *mb,
  83                                        volatile union ice_rx_flex_desc *rxdp)
  84 {
  85         volatile struct ice_32b_rx_flex_desc_comms *desc =
  86                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
  87         uint16_t stat_err = rte_le_to_cpu_16(desc->status_error0);
  88
  89         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
  90                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
  91                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
  92         }
  93
  94 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  95         if (desc->flow_id != 0xFFFFFFFF) {
  96                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
  97                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
  98         }
  99 #endif
 100 }
 101
 102 static inline void
 103 ice_rxd_to_pkt_fields_by_comms_ovs(__rte_unused struct ice_rx_queue *rxq,
 104                                    struct rte_mbuf *mb,
 105                                    volatile union ice_rx_flex_desc *rxdp)
 106 {
 107         volatile struct ice_32b_rx_flex_desc_comms_ovs *desc =
 108                         (volatile struct ice_32b_rx_flex_desc_comms_ovs *)rxdp;
 109 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 110         uint16_t stat_err;
 111 #endif
 112
 113         if (desc->flow_id != 0xFFFFFFFF) {
 114                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 115                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 116         }
 117
 118 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 119         stat_err = rte_le_to_cpu_16(desc->status_error0);
 120         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 121                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 122                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 123         }
 124 #endif
 125 }
 126
 127 static inline void
 128 ice_rxd_to_pkt_fields_by_comms_aux_v1(struct ice_rx_queue *rxq,
 129                                       struct rte_mbuf *mb,
 130                                       volatile union ice_rx_flex_desc *rxdp)
 131 {
 132         volatile struct ice_32b_rx_flex_desc_comms *desc =
 133                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 134         uint16_t stat_err;
 135
 136         stat_err = rte_le_to_cpu_16(desc->status_error0);
 137         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 138                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 139                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 140         }
 141
 142 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 143         if (desc->flow_id != 0xFFFFFFFF) {
 144                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 145                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 146         }
 147
 148         if (rxq->xtr_ol_flag) {
 149                 uint32_t metadata = 0;
 150
 151                 stat_err = rte_le_to_cpu_16(desc->status_error1);
 152
 153                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S))
 154                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 155
 156                 if (stat_err & (1 << ICE_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S))
 157                         metadata |=
 158                                 rte_le_to_cpu_16(desc->flex_ts.flex.aux1) << 16;
 159
 160                 if (metadata) {
 161                         mb->ol_flags |= rxq->xtr_ol_flag;
 162
 163                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 164                 }
 165         }
 166 #endif
 167 }
 168
 169 static inline void
 170 ice_rxd_to_pkt_fields_by_comms_aux_v2(struct ice_rx_queue *rxq,
 171                                       struct rte_mbuf *mb,
 172                                       volatile union ice_rx_flex_desc *rxdp)
 173 {
 174         volatile struct ice_32b_rx_flex_desc_comms *desc =
 175                         (volatile struct ice_32b_rx_flex_desc_comms *)rxdp;
 176         uint16_t stat_err;
 177
 178         stat_err = rte_le_to_cpu_16(desc->status_error0);
 179         if (likely(stat_err & (1 << ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 180                 mb->ol_flags |= RTE_MBUF_F_RX_RSS_HASH;
 181                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 182         }
 183
 184 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 185         if (desc->flow_id != 0xFFFFFFFF) {
 186                 mb->ol_flags |= RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID;
 187                 mb->hash.fdir.hi = rte_le_to_cpu_32(desc->flow_id);
 188         }
 189
 190         if (rxq->xtr_ol_flag) {
 191                 uint32_t metadata = 0;
 192
 193                 if (desc->flex_ts.flex.aux0 != 0xFFFF)
 194                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux0);
 195                 else if (desc->flex_ts.flex.aux1 != 0xFFFF)
 196                         metadata = rte_le_to_cpu_16(desc->flex_ts.flex.aux1);
 197
 198                 if (metadata) {
 199                         mb->ol_flags |= rxq->xtr_ol_flag;
 200
 201                         *RTE_NET_ICE_DYNF_PROTO_XTR_METADATA(mb) = metadata;
 202                 }
 203         }
 204 #endif
 205 }
 206
 207 static const ice_rxd_to_pkt_fields_t rxd_to_pkt_fields_ops[] = {
 208         [ICE_RXDID_COMMS_AUX_VLAN] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 209         [ICE_RXDID_COMMS_AUX_IPV4] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 210         [ICE_RXDID_COMMS_AUX_IPV6] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 211         [ICE_RXDID_COMMS_AUX_IPV6_FLOW] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 212         [ICE_RXDID_COMMS_AUX_TCP] = ice_rxd_to_pkt_fields_by_comms_aux_v1,
 213         [ICE_RXDID_COMMS_AUX_IP_OFFSET] = ice_rxd_to_pkt_fields_by_comms_aux_v2,
 214         [ICE_RXDID_COMMS_GENERIC] = ice_rxd_to_pkt_fields_by_comms_generic,
 215         [ICE_RXDID_COMMS_OVS] = ice_rxd_to_pkt_fields_by_comms_ovs,
 216 };
 217
 218 void
 219 ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq, uint32_t rxdid)
 220 {
 221         rxq->rxdid = rxdid;
 222
 223         switch (rxdid) {
 224         case ICE_RXDID_COMMS_AUX_VLAN:
 225                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_vlan_mask;
 226                 break;
 227
 228         case ICE_RXDID_COMMS_AUX_IPV4:
 229                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv4_mask;
 230                 break;
 231
 232         case ICE_RXDID_COMMS_AUX_IPV6:
 233                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_mask;
 234                 break;
 235
 236         case ICE_RXDID_COMMS_AUX_IPV6_FLOW:
 237                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask;
 238                 break;
 239
 240         case ICE_RXDID_COMMS_AUX_TCP:
 241                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_tcp_mask;
 242                 break;
 243
 244         case ICE_RXDID_COMMS_AUX_IP_OFFSET:
 245                 rxq->xtr_ol_flag = rte_net_ice_dynflag_proto_xtr_ip_offset_mask;
 246                 break;
 247
 248         case ICE_RXDID_COMMS_GENERIC:
 249                 /* fallthrough */
 250         case ICE_RXDID_COMMS_OVS:
 251                 break;
 252
 253         default:
 254                 /* update this according to the RXDID for PROTO_XTR_NONE */
 255                 rxq->rxdid = ICE_RXDID_COMMS_OVS;
 256                 break;
 257         }
 258
 259         if (!rte_net_ice_dynf_proto_xtr_metadata_avail())
 260                 rxq->xtr_ol_flag = 0;
 261 }
 262
 263 static enum ice_status
 264 ice_program_hw_rx_queue(struct ice_rx_queue *rxq)
 265 {
 266         struct ice_vsi *vsi = rxq->vsi;
 267         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 268         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
 269         struct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;
 270         struct ice_rlan_ctx rx_ctx;
 271         enum ice_status err;
 272         uint16_t buf_size;
 273         uint32_t rxdid = ICE_RXDID_COMMS_OVS;
 274         uint32_t regval;
 275         struct ice_adapter *ad = rxq->vsi->adapter;
 276         uint32_t frame_size = dev_data->mtu + ICE_ETH_OVERHEAD;
 277
 278         /* Set buffer size as the head split is disabled. */
 279         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
 280                               RTE_PKTMBUF_HEADROOM);
 281         rxq->rx_hdr_len = 0;
 282         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << ICE_RLAN_CTX_DBUF_S));
 283         rxq->max_pkt_len =
 284                 RTE_MIN((uint32_t)ICE_SUPPORT_CHAIN_NUM * rxq->rx_buf_len,
 285                         frame_size);
 286
 287         if (rxq->max_pkt_len <= RTE_ETHER_MIN_LEN ||
 288             rxq->max_pkt_len > ICE_FRAME_SIZE_MAX) {
 289                 PMD_DRV_LOG(ERR, "maximum packet length must "
 290                             "be larger than %u and smaller than %u",
 291                             (uint32_t)RTE_ETHER_MIN_LEN,
 292                             (uint32_t)ICE_FRAME_SIZE_MAX);
 293                 return -EINVAL;
 294         }
 295
 296         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) {
 297                 /* Register mbuf field and flag for Rx timestamp */
 298                 err = rte_mbuf_dyn_rx_timestamp_register(
 299                                 &ice_timestamp_dynfield_offset,
 300                                 &ice_timestamp_dynflag);
 301                 if (err) {
 302                         PMD_DRV_LOG(ERR,
 303                                 "Cannot register mbuf field/flag for timestamp");
 304                         return -EINVAL;
 305                 }
 306         }
 307
 308         memset(&rx_ctx, 0, sizeof(rx_ctx));
 309
 310         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 311         rx_ctx.qlen = rxq->nb_rx_desc;
 312         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 313         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 314         rx_ctx.dtype = 0; /* No Header Split mode */
 315 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 316         rx_ctx.dsize = 1; /* 32B descriptors */
 317 #endif
 318         rx_ctx.rxmax = rxq->max_pkt_len;
 319         /* TPH: Transaction Layer Packet (TLP) processing hints */
 320         rx_ctx.tphrdesc_ena = 1;
 321         rx_ctx.tphwdesc_ena = 1;
 322         rx_ctx.tphdata_ena = 1;
 323         rx_ctx.tphhead_ena = 1;
 324         /* Low Receive Queue Threshold defined in 64 descriptors units.
 325          * When the number of free descriptors goes below the lrxqthresh,
 326          * an immediate interrupt is triggered.
 327          */
 328         rx_ctx.lrxqthresh = 2;
 329         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 330         rx_ctx.l2tsel = 1;
 331         rx_ctx.showiv = 0;
 332         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 333
 334         rxdid = ice_proto_xtr_type_to_rxdid(rxq->proto_xtr);
 335
 336         PMD_DRV_LOG(DEBUG, "Port (%u) - Rx queue (%u) is set with RXDID : %u",
 337                     rxq->port_id, rxq->queue_id, rxdid);
 338
 339         if (!(pf->supported_rxdid & BIT(rxdid))) {
 340                 PMD_DRV_LOG(ERR, "currently package doesn't support RXDID (%u)",
 341                             rxdid);
 342                 return -EINVAL;
 343         }
 344
 345         ice_select_rxd_to_pkt_fields_handler(rxq, rxdid);
 346
 347         /* Enable Flexible Descriptors in the queue context which
 348          * allows this driver to select a specific receive descriptor format
 349          */
 350         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 351                 QRXFLXP_CNTXT_RXDID_IDX_M;
 352
 353         /* increasing context priority to pick up profile ID;
 354          * default is 0x01; setting to 0x03 to ensure profile
 355          * is programming if prev context is of same priority
 356          */
 357         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 358                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 359
 360         if (ad->ptp_ena || rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
 361                 regval |= QRXFLXP_CNTXT_TS_M;
 362
 363         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 364
 365         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 366         if (err) {
 367                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 368                             rxq->queue_id);
 369                 return -EINVAL;
 370         }
 371         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 372         if (err) {
 373                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 374                             rxq->queue_id);
 375                 return -EINVAL;
 376         }
 377
 378         /* Check if scattered RX needs to be used. */
 379         if (frame_size > buf_size)
 380                 dev_data->scattered_rx = 1;
 381
 382         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 383
 384         /* Init the Rx tail register*/
 385         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 386
 387         return 0;
 388 }
 389
 390 /* Allocate mbufs for all descriptors in rx queue */
 391 static int
 392 ice_alloc_rx_queue_mbufs(struct ice_rx_queue *rxq)
 393 {
 394         struct ice_rx_entry *rxe = rxq->sw_ring;
 395         uint64_t dma_addr;
 396         uint16_t i;
 397
 398         for (i = 0; i < rxq->nb_rx_desc; i++) {
 399                 volatile union ice_rx_flex_desc *rxd;
 400                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
 401
 402                 if (unlikely(!mbuf)) {
 403                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 404                         return -ENOMEM;
 405                 }
 406
 407                 rte_mbuf_refcnt_set(mbuf, 1);
 408                 mbuf->next = NULL;
 409                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 410                 mbuf->nb_segs = 1;
 411                 mbuf->port = rxq->port_id;
 412
 413                 dma_addr =
 414                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 415
 416                 rxd = &rxq->rx_ring[i];
 417                 rxd->read.pkt_addr = dma_addr;
 418                 rxd->read.hdr_addr = 0;
 419 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 420                 rxd->read.rsvd1 = 0;
 421                 rxd->read.rsvd2 = 0;
 422 #endif
 423                 rxe[i].mbuf = mbuf;
 424         }
 425
 426         return 0;
 427 }
 428
 429 /* Free all mbufs for descriptors in rx queue */
 430 static void
 431 _ice_rx_queue_release_mbufs(struct ice_rx_queue *rxq)
 432 {
 433         uint16_t i;
 434
 435         if (!rxq || !rxq->sw_ring) {
 436                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
 437                 return;
 438         }
 439
 440         for (i = 0; i < rxq->nb_rx_desc; i++) {
 441                 if (rxq->sw_ring[i].mbuf) {
 442                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
 443                         rxq->sw_ring[i].mbuf = NULL;
 444                 }
 445         }
 446         if (rxq->rx_nb_avail == 0)
 447                 return;
 448         for (i = 0; i < rxq->rx_nb_avail; i++)
 449                 rte_pktmbuf_free_seg(rxq->rx_stage[rxq->rx_next_avail + i]);
 450
 451         rxq->rx_nb_avail = 0;
 452 }
 453
 454 /* turn on or off rx queue
 455  * @q_idx: queue index in pf scope
 456  * @on: turn on or off the queue
 457  */
 458 static int
 459 ice_switch_rx_queue(struct ice_hw *hw, uint16_t q_idx, bool on)
 460 {
 461         uint32_t reg;
 462         uint16_t j;
 463
 464         /* QRX_CTRL = QRX_ENA */
 465         reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 466
 467         if (on) {
 468                 if (reg & QRX_CTRL_QENA_STAT_M)
 469                         return 0; /* Already on, skip */
 470                 reg |= QRX_CTRL_QENA_REQ_M;
 471         } else {
 472                 if (!(reg & QRX_CTRL_QENA_STAT_M))
 473                         return 0; /* Already off, skip */
 474                 reg &= ~QRX_CTRL_QENA_REQ_M;
 475         }
 476
 477         /* Write the register */
 478         ICE_WRITE_REG(hw, QRX_CTRL(q_idx), reg);
 479         /* Check the result. It is said that QENA_STAT
 480          * follows the QENA_REQ not more than 10 use.
 481          * TODO: need to change the wait counter later
 482          */
 483         for (j = 0; j < ICE_CHK_Q_ENA_COUNT; j++) {
 484                 rte_delay_us(ICE_CHK_Q_ENA_INTERVAL_US);
 485                 reg = ICE_READ_REG(hw, QRX_CTRL(q_idx));
 486                 if (on) {
 487                         if ((reg & QRX_CTRL_QENA_REQ_M) &&
 488                             (reg & QRX_CTRL_QENA_STAT_M))
 489                                 break;
 490                 } else {
 491                         if (!(reg & QRX_CTRL_QENA_REQ_M) &&
 492                             !(reg & QRX_CTRL_QENA_STAT_M))
 493                                 break;
 494                 }
 495         }
 496
 497         /* Check if it is timeout */
 498         if (j >= ICE_CHK_Q_ENA_COUNT) {
 499                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
 500                             (on ? "enable" : "disable"), q_idx);
 501                 return -ETIMEDOUT;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static inline int
 508 ice_check_rx_burst_bulk_alloc_preconditions(struct ice_rx_queue *rxq)
 509 {
 510         int ret = 0;
 511
 512         if (!(rxq->rx_free_thresh >= ICE_RX_MAX_BURST)) {
 513                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 514                              "rxq->rx_free_thresh=%d, "
 515                              "ICE_RX_MAX_BURST=%d",
 516                              rxq->rx_free_thresh, ICE_RX_MAX_BURST);
 517                 ret = -EINVAL;
 518         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 519                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 520                              "rxq->rx_free_thresh=%d, "
 521                              "rxq->nb_rx_desc=%d",
 522                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 523                 ret = -EINVAL;
 524         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 525                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 526                              "rxq->nb_rx_desc=%d, "
 527                              "rxq->rx_free_thresh=%d",
 528                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 529                 ret = -EINVAL;
 530         }
 531
 532         return ret;
 533 }
 534
 535 /* reset fields in ice_rx_queue back to default */
 536 static void
 537 ice_reset_rx_queue(struct ice_rx_queue *rxq)
 538 {
 539         unsigned int i;
 540         uint16_t len;
 541
 542         if (!rxq) {
 543                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
 544                 return;
 545         }
 546
 547         len = (uint16_t)(rxq->nb_rx_desc + ICE_RX_MAX_BURST);
 548
 549         for (i = 0; i < len * sizeof(union ice_rx_flex_desc); i++)
 550                 ((volatile char *)rxq->rx_ring)[i] = 0;
 551
 552         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 553         for (i = 0; i < ICE_RX_MAX_BURST; ++i)
 554                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
 555
 556         rxq->rx_nb_avail = 0;
 557         rxq->rx_next_avail = 0;
 558         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 559
 560         rxq->rx_tail = 0;
 561         rxq->nb_rx_hold = 0;
 562         rxq->pkt_first_seg = NULL;
 563         rxq->pkt_last_seg = NULL;
 564
 565         rxq->rxrearm_start = 0;
 566         rxq->rxrearm_nb = 0;
 567 }
 568
 569 int
 570 ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 571 {
 572         struct ice_rx_queue *rxq;
 573         int err;
 574         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 575
 576         PMD_INIT_FUNC_TRACE();
 577
 578         if (rx_queue_id >= dev->data->nb_rx_queues) {
 579                 PMD_DRV_LOG(ERR, "RX queue %u is out of range %u",
 580                             rx_queue_id, dev->data->nb_rx_queues);
 581                 return -EINVAL;
 582         }
 583
 584         rxq = dev->data->rx_queues[rx_queue_id];
 585         if (!rxq || !rxq->q_set) {
 586                 PMD_DRV_LOG(ERR, "RX queue %u not available or setup",
 587                             rx_queue_id);
 588                 return -EINVAL;
 589         }
 590
 591         err = ice_program_hw_rx_queue(rxq);
 592         if (err) {
 593                 PMD_DRV_LOG(ERR, "fail to program RX queue %u",
 594                             rx_queue_id);
 595                 return -EIO;
 596         }
 597
 598         err = ice_alloc_rx_queue_mbufs(rxq);
 599         if (err) {
 600                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 601                 return -ENOMEM;
 602         }
 603
 604         /* Init the RX tail register. */
 605         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 606
 607         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 608         if (err) {
 609                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 610                             rx_queue_id);
 611
 612                 rxq->rx_rel_mbufs(rxq);
 613                 ice_reset_rx_queue(rxq);
 614                 return -EINVAL;
 615         }
 616
 617         dev->data->rx_queue_state[rx_queue_id] =
 618                 RTE_ETH_QUEUE_STATE_STARTED;
 619
 620         return 0;
 621 }
 622
 623 int
 624 ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 625 {
 626         struct ice_rx_queue *rxq;
 627         int err;
 628         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 629
 630         if (rx_queue_id < dev->data->nb_rx_queues) {
 631                 rxq = dev->data->rx_queues[rx_queue_id];
 632
 633                 err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
 634                 if (err) {
 635                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 636                                     rx_queue_id);
 637                         return -EINVAL;
 638                 }
 639                 rxq->rx_rel_mbufs(rxq);
 640                 ice_reset_rx_queue(rxq);
 641                 dev->data->rx_queue_state[rx_queue_id] =
 642                         RTE_ETH_QUEUE_STATE_STOPPED;
 643         }
 644
 645         return 0;
 646 }
 647
 648 int
 649 ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 650 {
 651         struct ice_tx_queue *txq;
 652         int err;
 653         struct ice_vsi *vsi;
 654         struct ice_hw *hw;
 655         struct ice_aqc_add_tx_qgrp *txq_elem;
 656         struct ice_tlan_ctx tx_ctx;
 657         int buf_len;
 658
 659         PMD_INIT_FUNC_TRACE();
 660
 661         if (tx_queue_id >= dev->data->nb_tx_queues) {
 662                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 663                             tx_queue_id, dev->data->nb_tx_queues);
 664                 return -EINVAL;
 665         }
 666
 667         txq = dev->data->tx_queues[tx_queue_id];
 668         if (!txq || !txq->q_set) {
 669                 PMD_DRV_LOG(ERR, "TX queue %u is not available or setup",
 670                             tx_queue_id);
 671                 return -EINVAL;
 672         }
 673
 674         buf_len = ice_struct_size(txq_elem, txqs, 1);
 675         txq_elem = ice_malloc(hw, buf_len);
 676         if (!txq_elem)
 677                 return -ENOMEM;
 678
 679         vsi = txq->vsi;
 680         hw = ICE_VSI_TO_HW(vsi);
 681
 682         memset(&tx_ctx, 0, sizeof(tx_ctx));
 683         txq_elem->num_txqs = 1;
 684         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 685
 686         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 687         tx_ctx.qlen = txq->nb_tx_desc;
 688         tx_ctx.pf_num = hw->pf_id;
 689         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 690         tx_ctx.src_vsi = vsi->vsi_id;
 691         tx_ctx.port_num = hw->port_info->lport;
 692         tx_ctx.tso_ena = 1; /* tso enable */
 693         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 694         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 695         tx_ctx.tsyn_ena = 1;
 696
 697         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 698                     ice_tlan_ctx_info);
 699
 700         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 701
 702         /* Init the Tx tail register*/
 703         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 704
 705         /* Fix me, we assume TC always 0 here */
 706         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 707                         txq_elem, buf_len, NULL);
 708         if (err) {
 709                 PMD_DRV_LOG(ERR, "Failed to add lan txq");
 710                 rte_free(txq_elem);
 711                 return -EIO;
 712         }
 713         /* store the schedule node id */
 714         txq->q_teid = txq_elem->txqs[0].q_teid;
 715
 716         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
 717
 718         rte_free(txq_elem);
 719         return 0;
 720 }
 721
 722 static enum ice_status
 723 ice_fdir_program_hw_rx_queue(struct ice_rx_queue *rxq)
 724 {
 725         struct ice_vsi *vsi = rxq->vsi;
 726         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 727         uint32_t rxdid = ICE_RXDID_LEGACY_1;
 728         struct ice_rlan_ctx rx_ctx;
 729         enum ice_status err;
 730         uint32_t regval;
 731
 732         rxq->rx_hdr_len = 0;
 733         rxq->rx_buf_len = 1024;
 734
 735         memset(&rx_ctx, 0, sizeof(rx_ctx));
 736
 737         rx_ctx.base = rxq->rx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 738         rx_ctx.qlen = rxq->nb_rx_desc;
 739         rx_ctx.dbuf = rxq->rx_buf_len >> ICE_RLAN_CTX_DBUF_S;
 740         rx_ctx.hbuf = rxq->rx_hdr_len >> ICE_RLAN_CTX_HBUF_S;
 741         rx_ctx.dtype = 0; /* No Header Split mode */
 742         rx_ctx.dsize = 1; /* 32B descriptors */
 743         rx_ctx.rxmax = ICE_ETH_MAX_LEN;
 744         /* TPH: Transaction Layer Packet (TLP) processing hints */
 745         rx_ctx.tphrdesc_ena = 1;
 746         rx_ctx.tphwdesc_ena = 1;
 747         rx_ctx.tphdata_ena = 1;
 748         rx_ctx.tphhead_ena = 1;
 749         /* Low Receive Queue Threshold defined in 64 descriptors units.
 750          * When the number of free descriptors goes below the lrxqthresh,
 751          * an immediate interrupt is triggered.
 752          */
 753         rx_ctx.lrxqthresh = 2;
 754         /*default use 32 byte descriptor, vlan tag extract to L2TAG2(1st)*/
 755         rx_ctx.l2tsel = 1;
 756         rx_ctx.showiv = 0;
 757         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
 758
 759         /* Enable Flexible Descriptors in the queue context which
 760          * allows this driver to select a specific receive descriptor format
 761          */
 762         regval = (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
 763                 QRXFLXP_CNTXT_RXDID_IDX_M;
 764
 765         /* increasing context priority to pick up profile ID;
 766          * default is 0x01; setting to 0x03 to ensure profile
 767          * is programming if prev context is of same priority
 768          */
 769         regval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &
 770                 QRXFLXP_CNTXT_RXDID_PRIO_M;
 771
 772         ICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);
 773
 774         err = ice_clear_rxq_ctx(hw, rxq->reg_idx);
 775         if (err) {
 776                 PMD_DRV_LOG(ERR, "Failed to clear Lan Rx queue (%u) context",
 777                             rxq->queue_id);
 778                 return -EINVAL;
 779         }
 780         err = ice_write_rxq_ctx(hw, &rx_ctx, rxq->reg_idx);
 781         if (err) {
 782                 PMD_DRV_LOG(ERR, "Failed to write Lan Rx queue (%u) context",
 783                             rxq->queue_id);
 784                 return -EINVAL;
 785         }
 786
 787         rxq->qrx_tail = hw->hw_addr + QRX_TAIL(rxq->reg_idx);
 788
 789         /* Init the Rx tail register*/
 790         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 791
 792         return 0;
 793 }
 794
 795 int
 796 ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 797 {
 798         struct ice_rx_queue *rxq;
 799         int err;
 800         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 801         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 802
 803         PMD_INIT_FUNC_TRACE();
 804
 805         rxq = pf->fdir.rxq;
 806         if (!rxq || !rxq->q_set) {
 807                 PMD_DRV_LOG(ERR, "FDIR RX queue %u not available or setup",
 808                             rx_queue_id);
 809                 return -EINVAL;
 810         }
 811
 812         err = ice_fdir_program_hw_rx_queue(rxq);
 813         if (err) {
 814                 PMD_DRV_LOG(ERR, "fail to program FDIR RX queue %u",
 815                             rx_queue_id);
 816                 return -EIO;
 817         }
 818
 819         /* Init the RX tail register. */
 820         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 821
 822         err = ice_switch_rx_queue(hw, rxq->reg_idx, true);
 823         if (err) {
 824                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u on",
 825                             rx_queue_id);
 826
 827                 ice_reset_rx_queue(rxq);
 828                 return -EINVAL;
 829         }
 830
 831         return 0;
 832 }
 833
 834 int
 835 ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 836 {
 837         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 838         struct ice_tx_queue *txq;
 839         int err;
 840         struct ice_vsi *vsi;
 841         struct ice_hw *hw;
 842         struct ice_aqc_add_tx_qgrp *txq_elem;
 843         struct ice_tlan_ctx tx_ctx;
 844         int buf_len;
 845
 846         PMD_INIT_FUNC_TRACE();
 847
 848         txq = pf->fdir.txq;
 849         if (!txq || !txq->q_set) {
 850                 PMD_DRV_LOG(ERR, "FDIR TX queue %u is not available or setup",
 851                             tx_queue_id);
 852                 return -EINVAL;
 853         }
 854
 855         buf_len = ice_struct_size(txq_elem, txqs, 1);
 856         txq_elem = ice_malloc(hw, buf_len);
 857         if (!txq_elem)
 858                 return -ENOMEM;
 859
 860         vsi = txq->vsi;
 861         hw = ICE_VSI_TO_HW(vsi);
 862
 863         memset(&tx_ctx, 0, sizeof(tx_ctx));
 864         txq_elem->num_txqs = 1;
 865         txq_elem->txqs[0].txq_id = rte_cpu_to_le_16(txq->reg_idx);
 866
 867         tx_ctx.base = txq->tx_ring_dma / ICE_QUEUE_BASE_ADDR_UNIT;
 868         tx_ctx.qlen = txq->nb_tx_desc;
 869         tx_ctx.pf_num = hw->pf_id;
 870         tx_ctx.vmvf_type = ICE_TLAN_CTX_VMVF_TYPE_PF;
 871         tx_ctx.src_vsi = vsi->vsi_id;
 872         tx_ctx.port_num = hw->port_info->lport;
 873         tx_ctx.tso_ena = 1; /* tso enable */
 874         tx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */
 875         tx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */
 876
 877         ice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,
 878                     ice_tlan_ctx_info);
 879
 880         txq->qtx_tail = hw->hw_addr + QTX_COMM_DBELL(txq->reg_idx);
 881
 882         /* Init the Tx tail register*/
 883         ICE_PCI_REG_WRITE(txq->qtx_tail, 0);
 884
 885         /* Fix me, we assume TC always 0 here */
 886         err = ice_ena_vsi_txq(hw->port_info, vsi->idx, 0, tx_queue_id, 1,
 887                               txq_elem, buf_len, NULL);
 888         if (err) {
 889                 PMD_DRV_LOG(ERR, "Failed to add FDIR txq");
 890                 rte_free(txq_elem);
 891                 return -EIO;
 892         }
 893         /* store the schedule node id */
 894         txq->q_teid = txq_elem->txqs[0].q_teid;
 895
 896         rte_free(txq_elem);
 897         return 0;
 898 }
 899
 900 /* Free all mbufs for descriptors in tx queue */
 901 static void
 902 _ice_tx_queue_release_mbufs(struct ice_tx_queue *txq)
 903 {
 904         uint16_t i;
 905
 906         if (!txq || !txq->sw_ring) {
 907                 PMD_DRV_LOG(DEBUG, "Pointer to txq or sw_ring is NULL");
 908                 return;
 909         }
 910
 911         for (i = 0; i < txq->nb_tx_desc; i++) {
 912                 if (txq->sw_ring[i].mbuf) {
 913                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 914                         txq->sw_ring[i].mbuf = NULL;
 915                 }
 916         }
 917 }
 918
 919 static void
 920 ice_reset_tx_queue(struct ice_tx_queue *txq)
 921 {
 922         struct ice_tx_entry *txe;
 923         uint16_t i, prev, size;
 924
 925         if (!txq) {
 926                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 927                 return;
 928         }
 929
 930         txe = txq->sw_ring;
 931         size = sizeof(struct ice_tx_desc) * txq->nb_tx_desc;
 932         for (i = 0; i < size; i++)
 933                 ((volatile char *)txq->tx_ring)[i] = 0;
 934
 935         prev = (uint16_t)(txq->nb_tx_desc - 1);
 936         for (i = 0; i < txq->nb_tx_desc; i++) {
 937                 volatile struct ice_tx_desc *txd = &txq->tx_ring[i];
 938
 939                 txd->cmd_type_offset_bsz =
 940                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE);
 941                 txe[i].mbuf =  NULL;
 942                 txe[i].last_id = i;
 943                 txe[prev].next_id = i;
 944                 prev = i;
 945         }
 946
 947         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
 948         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 949
 950         txq->tx_tail = 0;
 951         txq->nb_tx_used = 0;
 952
 953         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
 954         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
 955 }
 956
 957 int
 958 ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 959 {
 960         struct ice_tx_queue *txq;
 961         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 962         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 963         struct ice_vsi *vsi = pf->main_vsi;
 964         enum ice_status status;
 965         uint16_t q_ids[1];
 966         uint32_t q_teids[1];
 967         uint16_t q_handle = tx_queue_id;
 968
 969         if (tx_queue_id >= dev->data->nb_tx_queues) {
 970                 PMD_DRV_LOG(ERR, "TX queue %u is out of range %u",
 971                             tx_queue_id, dev->data->nb_tx_queues);
 972                 return -EINVAL;
 973         }
 974
 975         txq = dev->data->tx_queues[tx_queue_id];
 976         if (!txq) {
 977                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
 978                             tx_queue_id);
 979                 return -EINVAL;
 980         }
 981
 982         q_ids[0] = txq->reg_idx;
 983         q_teids[0] = txq->q_teid;
 984
 985         /* Fix me, we assume TC always 0 here */
 986         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
 987                                 q_ids, q_teids, ICE_NO_RESET, 0, NULL);
 988         if (status != ICE_SUCCESS) {
 989                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
 990                 return -EINVAL;
 991         }
 992
 993         txq->tx_rel_mbufs(txq);
 994         ice_reset_tx_queue(txq);
 995         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 996
 997         return 0;
 998 }
 999
1000 int
1001 ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1002 {
1003         struct ice_rx_queue *rxq;
1004         int err;
1005         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1006         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1007
1008         rxq = pf->fdir.rxq;
1009
1010         err = ice_switch_rx_queue(hw, rxq->reg_idx, false);
1011         if (err) {
1012                 PMD_DRV_LOG(ERR, "Failed to switch FDIR RX queue %u off",
1013                             rx_queue_id);
1014                 return -EINVAL;
1015         }
1016         rxq->rx_rel_mbufs(rxq);
1017
1018         return 0;
1019 }
1020
1021 int
1022 ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1023 {
1024         struct ice_tx_queue *txq;
1025         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1026         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1027         struct ice_vsi *vsi = pf->main_vsi;
1028         enum ice_status status;
1029         uint16_t q_ids[1];
1030         uint32_t q_teids[1];
1031         uint16_t q_handle = tx_queue_id;
1032
1033         txq = pf->fdir.txq;
1034         if (!txq) {
1035                 PMD_DRV_LOG(ERR, "TX queue %u is not available",
1036                             tx_queue_id);
1037                 return -EINVAL;
1038         }
1039         vsi = txq->vsi;
1040
1041         q_ids[0] = txq->reg_idx;
1042         q_teids[0] = txq->q_teid;
1043
1044         /* Fix me, we assume TC always 0 here */
1045         status = ice_dis_vsi_txq(hw->port_info, vsi->idx, 0, 1, &q_handle,
1046                                  q_ids, q_teids, ICE_NO_RESET, 0, NULL);
1047         if (status != ICE_SUCCESS) {
1048                 PMD_DRV_LOG(DEBUG, "Failed to disable Lan Tx queue");
1049                 return -EINVAL;
1050         }
1051
1052         txq->tx_rel_mbufs(txq);
1053
1054         return 0;
1055 }
1056
1057 int
1058 ice_rx_queue_setup(struct rte_eth_dev *dev,
1059                    uint16_t queue_idx,
1060                    uint16_t nb_desc,
1061                    unsigned int socket_id,
1062                    const struct rte_eth_rxconf *rx_conf,
1063                    struct rte_mempool *mp)
1064 {
1065         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1066         struct ice_adapter *ad =
1067                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1068         struct ice_vsi *vsi = pf->main_vsi;
1069         struct ice_rx_queue *rxq;
1070         const struct rte_memzone *rz;
1071         uint32_t ring_size;
1072         uint16_t len;
1073         int use_def_burst_func = 1;
1074         uint64_t offloads;
1075
1076         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1077             nb_desc > ICE_MAX_RING_DESC ||
1078             nb_desc < ICE_MIN_RING_DESC) {
1079                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
1080                              "invalid", nb_desc);
1081                 return -EINVAL;
1082         }
1083
1084         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1085
1086         /* Free memory if needed */
1087         if (dev->data->rx_queues[queue_idx]) {
1088                 ice_rx_queue_release(dev->data->rx_queues[queue_idx]);
1089                 dev->data->rx_queues[queue_idx] = NULL;
1090         }
1091
1092         /* Allocate the rx queue data structure */
1093         rxq = rte_zmalloc_socket(NULL,
1094                                  sizeof(struct ice_rx_queue),
1095                                  RTE_CACHE_LINE_SIZE,
1096                                  socket_id);
1097         if (!rxq) {
1098                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1099                              "rx queue data structure");
1100                 return -ENOMEM;
1101         }
1102         rxq->mp = mp;
1103         rxq->nb_rx_desc = nb_desc;
1104         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1105         rxq->queue_id = queue_idx;
1106         rxq->offloads = offloads;
1107
1108         rxq->reg_idx = vsi->base_queue + queue_idx;
1109         rxq->port_id = dev->data->port_id;
1110         if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC)
1111                 rxq->crc_len = RTE_ETHER_CRC_LEN;
1112         else
1113                 rxq->crc_len = 0;
1114
1115         rxq->drop_en = rx_conf->rx_drop_en;
1116         rxq->vsi = vsi;
1117         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1118         rxq->proto_xtr = pf->proto_xtr != NULL ?
1119                          pf->proto_xtr[queue_idx] : PROTO_XTR_NONE;
1120
1121         /* Allocate the maximum number of RX ring hardware descriptor. */
1122         len = ICE_MAX_RING_DESC;
1123
1124         /**
1125          * Allocating a little more memory because vectorized/bulk_alloc Rx
1126          * functions doesn't check boundaries each time.
1127          */
1128         len += ICE_RX_MAX_BURST;
1129
1130         /* Allocate the maximum number of RX ring hardware descriptor. */
1131         ring_size = sizeof(union ice_rx_flex_desc) * len;
1132         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1133         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1134                                       ring_size, ICE_RING_BASE_ALIGN,
1135                                       socket_id);
1136         if (!rz) {
1137                 ice_rx_queue_release(rxq);
1138                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
1139                 return -ENOMEM;
1140         }
1141
1142         rxq->mz = rz;
1143         /* Zero all the descriptors in the ring. */
1144         memset(rz->addr, 0, ring_size);
1145
1146         rxq->rx_ring_dma = rz->iova;
1147         rxq->rx_ring = rz->addr;
1148
1149         /* always reserve more for bulk alloc */
1150         len = (uint16_t)(nb_desc + ICE_RX_MAX_BURST);
1151
1152         /* Allocate the software ring. */
1153         rxq->sw_ring = rte_zmalloc_socket(NULL,
1154                                           sizeof(struct ice_rx_entry) * len,
1155                                           RTE_CACHE_LINE_SIZE,
1156                                           socket_id);
1157         if (!rxq->sw_ring) {
1158                 ice_rx_queue_release(rxq);
1159                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
1160                 return -ENOMEM;
1161         }
1162
1163         ice_reset_rx_queue(rxq);
1164         rxq->q_set = true;
1165         dev->data->rx_queues[queue_idx] = rxq;
1166         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
1167
1168         use_def_burst_func = ice_check_rx_burst_bulk_alloc_preconditions(rxq);
1169
1170         if (!use_def_burst_func) {
1171                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1172                              "satisfied. Rx Burst Bulk Alloc function will be "
1173                              "used on port=%d, queue=%d.",
1174                              rxq->port_id, rxq->queue_id);
1175         } else {
1176                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1177                              "not satisfied, Scattered Rx is requested. "
1178                              "on port=%d, queue=%d.",
1179                              rxq->port_id, rxq->queue_id);
1180                 ad->rx_bulk_alloc_allowed = false;
1181         }
1182
1183         return 0;
1184 }
1185
1186 void
1187 ice_rx_queue_release(void *rxq)
1188 {
1189         struct ice_rx_queue *q = (struct ice_rx_queue *)rxq;
1190
1191         if (!q) {
1192                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1193                 return;
1194         }
1195
1196         q->rx_rel_mbufs(q);
1197         rte_free(q->sw_ring);
1198         rte_memzone_free(q->mz);
1199         rte_free(q);
1200 }
1201
1202 int
1203 ice_tx_queue_setup(struct rte_eth_dev *dev,
1204                    uint16_t queue_idx,
1205                    uint16_t nb_desc,
1206                    unsigned int socket_id,
1207                    const struct rte_eth_txconf *tx_conf)
1208 {
1209         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1210         struct ice_vsi *vsi = pf->main_vsi;
1211         struct ice_tx_queue *txq;
1212         const struct rte_memzone *tz;
1213         uint32_t ring_size;
1214         uint16_t tx_rs_thresh, tx_free_thresh;
1215         uint64_t offloads;
1216
1217         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1218
1219         if (nb_desc % ICE_ALIGN_RING_DESC != 0 ||
1220             nb_desc > ICE_MAX_RING_DESC ||
1221             nb_desc < ICE_MIN_RING_DESC) {
1222                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
1223                              "invalid", nb_desc);
1224                 return -EINVAL;
1225         }
1226
1227         /**
1228          * The following two parameters control the setting of the RS bit on
1229          * transmit descriptors. TX descriptors will have their RS bit set
1230          * after txq->tx_rs_thresh descriptors have been used. The TX
1231          * descriptor ring will be cleaned after txq->tx_free_thresh
1232          * descriptors are used or if the number of descriptors required to
1233          * transmit a packet is greater than the number of free TX descriptors.
1234          *
1235          * The following constraints must be satisfied:
1236          *  - tx_rs_thresh must be greater than 0.
1237          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1238          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1239          *  - tx_rs_thresh must be a divisor of the ring size.
1240          *  - tx_free_thresh must be greater than 0.
1241          *  - tx_free_thresh must be less than the size of the ring minus 3.
1242          *  - tx_free_thresh + tx_rs_thresh must not exceed nb_desc.
1243          *
1244          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1245          * race condition, hence the maximum threshold constraints. When set
1246          * to zero use default values.
1247          */
1248         tx_free_thresh = (uint16_t)(tx_conf->tx_free_thresh ?
1249                                     tx_conf->tx_free_thresh :
1250                                     ICE_DEFAULT_TX_FREE_THRESH);
1251         /* force tx_rs_thresh to adapt an aggressive tx_free_thresh */
1252         tx_rs_thresh =
1253                 (ICE_DEFAULT_TX_RSBIT_THRESH + tx_free_thresh > nb_desc) ?
1254                         nb_desc - tx_free_thresh : ICE_DEFAULT_TX_RSBIT_THRESH;
1255         if (tx_conf->tx_rs_thresh)
1256                 tx_rs_thresh = tx_conf->tx_rs_thresh;
1257         if (tx_rs_thresh + tx_free_thresh > nb_desc) {
1258                 PMD_INIT_LOG(ERR, "tx_rs_thresh + tx_free_thresh must not "
1259                                 "exceed nb_desc. (tx_rs_thresh=%u "
1260                                 "tx_free_thresh=%u nb_desc=%u port = %d queue=%d)",
1261                                 (unsigned int)tx_rs_thresh,
1262                                 (unsigned int)tx_free_thresh,
1263                                 (unsigned int)nb_desc,
1264                                 (int)dev->data->port_id,
1265                                 (int)queue_idx);
1266                 return -EINVAL;
1267         }
1268         if (tx_rs_thresh >= (nb_desc - 2)) {
1269                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1270                              "number of TX descriptors minus 2. "
1271                              "(tx_rs_thresh=%u port=%d queue=%d)",
1272                              (unsigned int)tx_rs_thresh,
1273                              (int)dev->data->port_id,
1274                              (int)queue_idx);
1275                 return -EINVAL;
1276         }
1277         if (tx_free_thresh >= (nb_desc - 3)) {
1278                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1279                              "tx_free_thresh must be less than the "
1280                              "number of TX descriptors minus 3. "
1281                              "(tx_free_thresh=%u port=%d queue=%d)",
1282                              (unsigned int)tx_free_thresh,
1283                              (int)dev->data->port_id,
1284                              (int)queue_idx);
1285                 return -EINVAL;
1286         }
1287         if (tx_rs_thresh > tx_free_thresh) {
1288                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1289                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1290                              " tx_rs_thresh=%u port=%d queue=%d)",
1291                              (unsigned int)tx_free_thresh,
1292                              (unsigned int)tx_rs_thresh,
1293                              (int)dev->data->port_id,
1294                              (int)queue_idx);
1295                 return -EINVAL;
1296         }
1297         if ((nb_desc % tx_rs_thresh) != 0) {
1298                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1299                              "number of TX descriptors. (tx_rs_thresh=%u"
1300                              " port=%d queue=%d)",
1301                              (unsigned int)tx_rs_thresh,
1302                              (int)dev->data->port_id,
1303                              (int)queue_idx);
1304                 return -EINVAL;
1305         }
1306         if (tx_rs_thresh > 1 && tx_conf->tx_thresh.wthresh != 0) {
1307                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1308                              "tx_rs_thresh is greater than 1. "
1309                              "(tx_rs_thresh=%u port=%d queue=%d)",
1310                              (unsigned int)tx_rs_thresh,
1311                              (int)dev->data->port_id,
1312                              (int)queue_idx);
1313                 return -EINVAL;
1314         }
1315
1316         /* Free memory if needed. */
1317         if (dev->data->tx_queues[queue_idx]) {
1318                 ice_tx_queue_release(dev->data->tx_queues[queue_idx]);
1319                 dev->data->tx_queues[queue_idx] = NULL;
1320         }
1321
1322         /* Allocate the TX queue data structure. */
1323         txq = rte_zmalloc_socket(NULL,
1324                                  sizeof(struct ice_tx_queue),
1325                                  RTE_CACHE_LINE_SIZE,
1326                                  socket_id);
1327         if (!txq) {
1328                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
1329                              "tx queue structure");
1330                 return -ENOMEM;
1331         }
1332
1333         /* Allocate TX hardware ring descriptors. */
1334         ring_size = sizeof(struct ice_tx_desc) * ICE_MAX_RING_DESC;
1335         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
1336         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
1337                                       ring_size, ICE_RING_BASE_ALIGN,
1338                                       socket_id);
1339         if (!tz) {
1340                 ice_tx_queue_release(txq);
1341                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
1342                 return -ENOMEM;
1343         }
1344
1345         txq->mz = tz;
1346         txq->nb_tx_desc = nb_desc;
1347         txq->tx_rs_thresh = tx_rs_thresh;
1348         txq->tx_free_thresh = tx_free_thresh;
1349         txq->pthresh = tx_conf->tx_thresh.pthresh;
1350         txq->hthresh = tx_conf->tx_thresh.hthresh;
1351         txq->wthresh = tx_conf->tx_thresh.wthresh;
1352         txq->queue_id = queue_idx;
1353
1354         txq->reg_idx = vsi->base_queue + queue_idx;
1355         txq->port_id = dev->data->port_id;
1356         txq->offloads = offloads;
1357         txq->vsi = vsi;
1358         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1359
1360         txq->tx_ring_dma = tz->iova;
1361         txq->tx_ring = tz->addr;
1362
1363         /* Allocate software ring */
1364         txq->sw_ring =
1365                 rte_zmalloc_socket(NULL,
1366                                    sizeof(struct ice_tx_entry) * nb_desc,
1367                                    RTE_CACHE_LINE_SIZE,
1368                                    socket_id);
1369         if (!txq->sw_ring) {
1370                 ice_tx_queue_release(txq);
1371                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
1372                 return -ENOMEM;
1373         }
1374
1375         ice_reset_tx_queue(txq);
1376         txq->q_set = true;
1377         dev->data->tx_queues[queue_idx] = txq;
1378         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
1379         ice_set_tx_function_flag(dev, txq);
1380
1381         return 0;
1382 }
1383
1384 void
1385 ice_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1386 {
1387         ice_rx_queue_release(dev->data->rx_queues[qid]);
1388 }
1389
1390 void
1391 ice_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)
1392 {
1393         ice_tx_queue_release(dev->data->tx_queues[qid]);
1394 }
1395
1396 void
1397 ice_tx_queue_release(void *txq)
1398 {
1399         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
1400
1401         if (!q) {
1402                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1403                 return;
1404         }
1405
1406         q->tx_rel_mbufs(q);
1407         rte_free(q->sw_ring);
1408         rte_memzone_free(q->mz);
1409         rte_free(q);
1410 }
1411
1412 void
1413 ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1414                  struct rte_eth_rxq_info *qinfo)
1415 {
1416         struct ice_rx_queue *rxq;
1417
1418         rxq = dev->data->rx_queues[queue_id];
1419
1420         qinfo->mp = rxq->mp;
1421         qinfo->scattered_rx = dev->data->scattered_rx;
1422         qinfo->nb_desc = rxq->nb_rx_desc;
1423
1424         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
1425         qinfo->conf.rx_drop_en = rxq->drop_en;
1426         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
1427 }
1428
1429 void
1430 ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1431                  struct rte_eth_txq_info *qinfo)
1432 {
1433         struct ice_tx_queue *txq;
1434
1435         txq = dev->data->tx_queues[queue_id];
1436
1437         qinfo->nb_desc = txq->nb_tx_desc;
1438
1439         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
1440         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
1441         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
1442
1443         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
1444         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
1445         qinfo->conf.offloads = txq->offloads;
1446         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
1447 }
1448
1449 uint32_t
1450 ice_rx_queue_count(void *rx_queue)
1451 {
1452 #define ICE_RXQ_SCAN_INTERVAL 4
1453         volatile union ice_rx_flex_desc *rxdp;
1454         struct ice_rx_queue *rxq;
1455         uint16_t desc = 0;
1456
1457         rxq = rx_queue;
1458         rxdp = &rxq->rx_ring[rxq->rx_tail];
1459         while ((desc < rxq->nb_rx_desc) &&
1460                rte_le_to_cpu_16(rxdp->wb.status_error0) &
1461                (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)) {
1462                 /**
1463                  * Check the DD bit of a rx descriptor of each 4 in a group,
1464                  * to avoid checking too frequently and downgrading performance
1465                  * too much.
1466                  */
1467                 desc += ICE_RXQ_SCAN_INTERVAL;
1468                 rxdp += ICE_RXQ_SCAN_INTERVAL;
1469                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1470                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1471                                  desc - rxq->nb_rx_desc]);
1472         }
1473
1474         return desc;
1475 }
1476
1477 #define ICE_RX_FLEX_ERR0_BITS   \
1478         ((1 << ICE_RX_FLEX_DESC_STATUS0_HBO_S) |        \
1479          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |   \
1480          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |   \
1481          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) |  \
1482          (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) | \
1483          (1 << ICE_RX_FLEX_DESC_STATUS0_RXE_S))
1484
1485 /* Rx L3/L4 checksum */
1486 static inline uint64_t
1487 ice_rxd_error_to_pkt_flags(uint16_t stat_err0)
1488 {
1489         uint64_t flags = 0;
1490
1491         /* check if HW has decoded the packet and checksum */
1492         if (unlikely(!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_L3L4P_S))))
1493                 return 0;
1494
1495         if (likely(!(stat_err0 & ICE_RX_FLEX_ERR0_BITS))) {
1496                 flags |= (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD);
1497                 return flags;
1498         }
1499
1500         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
1501                 flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD;
1502         else
1503                 flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD;
1504
1505         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
1506                 flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD;
1507         else
1508                 flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD;
1509
1510         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
1511                 flags |= RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD;
1512
1513         if (unlikely(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S)))
1514                 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_BAD;
1515         else
1516                 flags |= RTE_MBUF_F_RX_OUTER_L4_CKSUM_GOOD;
1517
1518         return flags;
1519 }
1520
1521 static inline void
1522 ice_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union ice_rx_flex_desc *rxdp)
1523 {
1524         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
1525             (1 << ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
1526                 mb->ol_flags |= RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1527                 mb->vlan_tci =
1528                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
1529                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
1530                            rte_le_to_cpu_16(rxdp->wb.l2tag1));
1531         } else {
1532                 mb->vlan_tci = 0;
1533         }
1534
1535 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1536         if (rte_le_to_cpu_16(rxdp->wb.status_error1) &
1537             (1 << ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S)) {
1538                 mb->ol_flags |= RTE_MBUF_F_RX_QINQ_STRIPPED | RTE_MBUF_F_RX_QINQ |
1539                                 RTE_MBUF_F_RX_VLAN_STRIPPED | RTE_MBUF_F_RX_VLAN;
1540                 mb->vlan_tci_outer = mb->vlan_tci;
1541                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd);
1542                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
1543                            rte_le_to_cpu_16(rxdp->wb.l2tag2_1st),
1544                            rte_le_to_cpu_16(rxdp->wb.l2tag2_2nd));
1545         } else {
1546                 mb->vlan_tci_outer = 0;
1547         }
1548 #endif
1549         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
1550                    mb->vlan_tci, mb->vlan_tci_outer);
1551 }
1552
1553 #define ICE_LOOK_AHEAD 8
1554 #if (ICE_LOOK_AHEAD != 8)
1555 #error "PMD ICE: ICE_LOOK_AHEAD must be 8\n"
1556 #endif
1557
1558 #define ICE_PTP_TS_VALID 0x1
1559
1560 static inline int
1561 ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)
1562 {
1563         volatile union ice_rx_flex_desc *rxdp;
1564         struct ice_rx_entry *rxep;
1565         struct rte_mbuf *mb;
1566         uint16_t stat_err0;
1567         uint16_t pkt_len;
1568         int32_t s[ICE_LOOK_AHEAD], nb_dd;
1569         int32_t i, j, nb_rx = 0;
1570         uint64_t pkt_flags = 0;
1571         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1572 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1573         struct ice_vsi *vsi = rxq->vsi;
1574         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1575         uint64_t ts_ns;
1576         struct ice_adapter *ad = rxq->vsi->adapter;
1577 #endif
1578         rxdp = &rxq->rx_ring[rxq->rx_tail];
1579         rxep = &rxq->sw_ring[rxq->rx_tail];
1580
1581         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1582
1583         /* Make sure there is at least 1 packet to receive */
1584         if (!(stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1585                 return 0;
1586
1587         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
1588                 rxq->hw_register_set = 1;
1589
1590         /**
1591          * Scan LOOK_AHEAD descriptors at a time to determine which
1592          * descriptors reference packets that are ready to be received.
1593          */
1594         for (i = 0; i < ICE_RX_MAX_BURST; i += ICE_LOOK_AHEAD,
1595              rxdp += ICE_LOOK_AHEAD, rxep += ICE_LOOK_AHEAD) {
1596                 /* Read desc statuses backwards to avoid race condition */
1597                 for (j = ICE_LOOK_AHEAD - 1; j >= 0; j--)
1598                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1599
1600                 rte_smp_rmb();
1601
1602                 /* Compute how many status bits were set */
1603                 for (j = 0, nb_dd = 0; j < ICE_LOOK_AHEAD; j++)
1604                         nb_dd += s[j] & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S);
1605
1606                 nb_rx += nb_dd;
1607
1608                 /* Translate descriptor info to mbuf parameters */
1609                 for (j = 0; j < nb_dd; j++) {
1610                         mb = rxep[j].mbuf;
1611                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1612                                    ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1613                         mb->data_len = pkt_len;
1614                         mb->pkt_len = pkt_len;
1615                         mb->ol_flags = 0;
1616                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1617                         pkt_flags = ice_rxd_error_to_pkt_flags(stat_err0);
1618                         mb->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1619                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1620                         ice_rxd_to_vlan_tci(mb, &rxdp[j]);
1621                         rxd_to_pkt_fields_ops[rxq->rxdid](rxq, mb, &rxdp[j]);
1622 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1623                         if (ice_timestamp_dynflag > 0) {
1624                                 ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
1625                                         rxq->hw_register_set,
1626                                         rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high));
1627                                 rxq->hw_register_set = 0;
1628                                 *RTE_MBUF_DYNFIELD(mb,
1629                                         ice_timestamp_dynfield_offset,
1630                                         rte_mbuf_timestamp_t *) = ts_ns;
1631                                 mb->ol_flags |= ice_timestamp_dynflag;
1632                         }
1633
1634                         if (ad->ptp_ena && ((mb->packet_type &
1635                             RTE_PTYPE_L2_MASK) == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1636                                 rxq->time_high =
1637                                    rte_le_to_cpu_32(rxdp[j].wb.flex_ts.ts_high);
1638                                 mb->timesync = rxq->queue_id;
1639                                 pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1640                                 if (rxdp[j].wb.time_stamp_low &
1641                                     ICE_PTP_TS_VALID)
1642                                         pkt_flags |=
1643                                                 RTE_MBUF_F_RX_IEEE1588_TMST;
1644                         }
1645 #endif
1646                         mb->ol_flags |= pkt_flags;
1647                 }
1648
1649                 for (j = 0; j < ICE_LOOK_AHEAD; j++)
1650                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1651
1652                 if (nb_dd != ICE_LOOK_AHEAD)
1653                         break;
1654         }
1655
1656         /* Clear software ring entries */
1657         for (i = 0; i < nb_rx; i++)
1658                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1659
1660         PMD_RX_LOG(DEBUG, "ice_rx_scan_hw_ring: "
1661                    "port_id=%u, queue_id=%u, nb_rx=%d",
1662                    rxq->port_id, rxq->queue_id, nb_rx);
1663
1664         return nb_rx;
1665 }
1666
1667 static inline uint16_t
1668 ice_rx_fill_from_stage(struct ice_rx_queue *rxq,
1669                        struct rte_mbuf **rx_pkts,
1670                        uint16_t nb_pkts)
1671 {
1672         uint16_t i;
1673         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1674
1675         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1676
1677         for (i = 0; i < nb_pkts; i++)
1678                 rx_pkts[i] = stage[i];
1679
1680         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1681         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1682
1683         return nb_pkts;
1684 }
1685
1686 static inline int
1687 ice_rx_alloc_bufs(struct ice_rx_queue *rxq)
1688 {
1689         volatile union ice_rx_flex_desc *rxdp;
1690         struct ice_rx_entry *rxep;
1691         struct rte_mbuf *mb;
1692         uint16_t alloc_idx, i;
1693         uint64_t dma_addr;
1694         int diag;
1695
1696         /* Allocate buffers in bulk */
1697         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1698                                (rxq->rx_free_thresh - 1));
1699         rxep = &rxq->sw_ring[alloc_idx];
1700         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1701                                     rxq->rx_free_thresh);
1702         if (unlikely(diag != 0)) {
1703                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1704                 return -ENOMEM;
1705         }
1706
1707         rxdp = &rxq->rx_ring[alloc_idx];
1708         for (i = 0; i < rxq->rx_free_thresh; i++) {
1709                 if (likely(i < (rxq->rx_free_thresh - 1)))
1710                         /* Prefetch next mbuf */
1711                         rte_prefetch0(rxep[i + 1].mbuf);
1712
1713                 mb = rxep[i].mbuf;
1714                 rte_mbuf_refcnt_set(mb, 1);
1715                 mb->next = NULL;
1716                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1717                 mb->nb_segs = 1;
1718                 mb->port = rxq->port_id;
1719                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1720                 rxdp[i].read.hdr_addr = 0;
1721                 rxdp[i].read.pkt_addr = dma_addr;
1722         }
1723
1724         /* Update Rx tail register */
1725         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1726
1727         rxq->rx_free_trigger =
1728                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1729         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1730                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1731
1732         return 0;
1733 }
1734
1735 static inline uint16_t
1736 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1737 {
1738         struct ice_rx_queue *rxq = (struct ice_rx_queue *)rx_queue;
1739         uint16_t nb_rx = 0;
1740
1741         if (!nb_pkts)
1742                 return 0;
1743
1744         if (rxq->rx_nb_avail)
1745                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1746
1747         nb_rx = (uint16_t)ice_rx_scan_hw_ring(rxq);
1748         rxq->rx_next_avail = 0;
1749         rxq->rx_nb_avail = nb_rx;
1750         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1751
1752         if (rxq->rx_tail > rxq->rx_free_trigger) {
1753                 if (ice_rx_alloc_bufs(rxq) != 0) {
1754                         uint16_t i, j;
1755
1756                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed +=
1757                                 rxq->rx_free_thresh;
1758                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1759                                    "port_id=%u, queue_id=%u",
1760                                    rxq->port_id, rxq->queue_id);
1761                         rxq->rx_nb_avail = 0;
1762                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1763                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1764                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1765
1766                         return 0;
1767                 }
1768         }
1769
1770         if (rxq->rx_tail >= rxq->nb_rx_desc)
1771                 rxq->rx_tail = 0;
1772
1773         if (rxq->rx_nb_avail)
1774                 return ice_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1775
1776         return 0;
1777 }
1778
1779 static uint16_t
1780 ice_recv_pkts_bulk_alloc(void *rx_queue,
1781                          struct rte_mbuf **rx_pkts,
1782                          uint16_t nb_pkts)
1783 {
1784         uint16_t nb_rx = 0;
1785         uint16_t n;
1786         uint16_t count;
1787
1788         if (unlikely(nb_pkts == 0))
1789                 return nb_rx;
1790
1791         if (likely(nb_pkts <= ICE_RX_MAX_BURST))
1792                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1793
1794         while (nb_pkts) {
1795                 n = RTE_MIN(nb_pkts, ICE_RX_MAX_BURST);
1796                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1797                 nb_rx = (uint16_t)(nb_rx + count);
1798                 nb_pkts = (uint16_t)(nb_pkts - count);
1799                 if (count < n)
1800                         break;
1801         }
1802
1803         return nb_rx;
1804 }
1805
1806 static uint16_t
1807 ice_recv_scattered_pkts(void *rx_queue,
1808                         struct rte_mbuf **rx_pkts,
1809                         uint16_t nb_pkts)
1810 {
1811         struct ice_rx_queue *rxq = rx_queue;
1812         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
1813         volatile union ice_rx_flex_desc *rxdp;
1814         union ice_rx_flex_desc rxd;
1815         struct ice_rx_entry *sw_ring = rxq->sw_ring;
1816         struct ice_rx_entry *rxe;
1817         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1818         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1819         struct rte_mbuf *nmb; /* new allocated mbuf */
1820         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
1821         uint16_t rx_id = rxq->rx_tail;
1822         uint16_t nb_rx = 0;
1823         uint16_t nb_hold = 0;
1824         uint16_t rx_packet_len;
1825         uint16_t rx_stat_err0;
1826         uint64_t dma_addr;
1827         uint64_t pkt_flags;
1828         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1829 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1830         struct ice_vsi *vsi = rxq->vsi;
1831         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1832         uint64_t ts_ns;
1833         struct ice_adapter *ad = rxq->vsi->adapter;
1834 #endif
1835
1836         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
1837                 rxq->hw_register_set = 1;
1838
1839         while (nb_rx < nb_pkts) {
1840                 rxdp = &rx_ring[rx_id];
1841                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1842
1843                 /* Check the DD bit first */
1844                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
1845                         break;
1846
1847                 /* allocate mbuf */
1848                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1849                 if (unlikely(!nmb)) {
1850                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
1851                         break;
1852                 }
1853                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
1854
1855                 nb_hold++;
1856                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
1857                 rx_id++;
1858                 if (unlikely(rx_id == rxq->nb_rx_desc))
1859                         rx_id = 0;
1860
1861                 /* Prefetch next mbuf */
1862                 rte_prefetch0(sw_ring[rx_id].mbuf);
1863
1864                 /**
1865                  * When next RX descriptor is on a cache line boundary,
1866                  * prefetch the next 4 RX descriptors and next 8 pointers
1867                  * to mbufs.
1868                  */
1869                 if ((rx_id & 0x3) == 0) {
1870                         rte_prefetch0(&rx_ring[rx_id]);
1871                         rte_prefetch0(&sw_ring[rx_id]);
1872                 }
1873
1874                 rxm = rxe->mbuf;
1875                 rxe->mbuf = nmb;
1876                 dma_addr =
1877                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1878
1879                 /* Set data buffer address and data length of the mbuf */
1880                 rxdp->read.hdr_addr = 0;
1881                 rxdp->read.pkt_addr = dma_addr;
1882                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1883                                 ICE_RX_FLX_DESC_PKT_LEN_M;
1884                 rxm->data_len = rx_packet_len;
1885                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1886
1887                 /**
1888                  * If this is the first buffer of the received packet, set the
1889                  * pointer to the first mbuf of the packet and initialize its
1890                  * context. Otherwise, update the total length and the number
1891                  * of segments of the current scattered packet, and update the
1892                  * pointer to the last mbuf of the current packet.
1893                  */
1894                 if (!first_seg) {
1895                         first_seg = rxm;
1896                         first_seg->nb_segs = 1;
1897                         first_seg->pkt_len = rx_packet_len;
1898                 } else {
1899                         first_seg->pkt_len =
1900                                 (uint16_t)(first_seg->pkt_len +
1901                                            rx_packet_len);
1902                         first_seg->nb_segs++;
1903                         last_seg->next = rxm;
1904                 }
1905
1906                 /**
1907                  * If this is not the last buffer of the received packet,
1908                  * update the pointer to the last mbuf of the current scattered
1909                  * packet and continue to parse the RX ring.
1910                  */
1911                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_EOF_S))) {
1912                         last_seg = rxm;
1913                         continue;
1914                 }
1915
1916                 /**
1917                  * This is the last buffer of the received packet. If the CRC
1918                  * is not stripped by the hardware:
1919                  *  - Subtract the CRC length from the total packet length.
1920                  *  - If the last buffer only contains the whole CRC or a part
1921                  *  of it, free the mbuf associated to the last buffer. If part
1922                  *  of the CRC is also contained in the previous mbuf, subtract
1923                  *  the length of that CRC part from the data length of the
1924                  *  previous mbuf.
1925                  */
1926                 rxm->next = NULL;
1927                 if (unlikely(rxq->crc_len > 0)) {
1928                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1929                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1930                                 rte_pktmbuf_free_seg(rxm);
1931                                 first_seg->nb_segs--;
1932                                 last_seg->data_len =
1933                                         (uint16_t)(last_seg->data_len -
1934                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1935                                 last_seg->next = NULL;
1936                         } else
1937                                 rxm->data_len = (uint16_t)(rx_packet_len -
1938                                                            RTE_ETHER_CRC_LEN);
1939                 }
1940
1941                 first_seg->port = rxq->port_id;
1942                 first_seg->ol_flags = 0;
1943                 first_seg->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
1944                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1945                 ice_rxd_to_vlan_tci(first_seg, &rxd);
1946                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, first_seg, &rxd);
1947                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
1948 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
1949                 if (ice_timestamp_dynflag > 0) {
1950                         ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
1951                                 rxq->hw_register_set,
1952                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
1953                         rxq->hw_register_set = 0;
1954                         *RTE_MBUF_DYNFIELD(first_seg,
1955                                 ice_timestamp_dynfield_offset,
1956                                 rte_mbuf_timestamp_t *) = ts_ns;
1957                         first_seg->ol_flags |= ice_timestamp_dynflag;
1958                 }
1959
1960                 if (ad->ptp_ena && ((first_seg->packet_type & RTE_PTYPE_L2_MASK)
1961                     == RTE_PTYPE_L2_ETHER_TIMESYNC)) {
1962                         rxq->time_high =
1963                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
1964                         first_seg->timesync = rxq->queue_id;
1965                         pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
1966                 }
1967 #endif
1968                 first_seg->ol_flags |= pkt_flags;
1969                 /* Prefetch data of first segment, if configured to do so. */
1970                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1971                                           first_seg->data_off));
1972                 rx_pkts[nb_rx++] = first_seg;
1973                 first_seg = NULL;
1974         }
1975
1976         /* Record index of the next RX descriptor to probe. */
1977         rxq->rx_tail = rx_id;
1978         rxq->pkt_first_seg = first_seg;
1979         rxq->pkt_last_seg = last_seg;
1980
1981         /**
1982          * If the number of free RX descriptors is greater than the RX free
1983          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1984          * register. Update the RDT with the value of the last processed RX
1985          * descriptor minus 1, to guarantee that the RDT register is never
1986          * equal to the RDH register, which creates a "full" ring situation
1987          * from the hardware point of view.
1988          */
1989         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1990         if (nb_hold > rxq->rx_free_thresh) {
1991                 rx_id = (uint16_t)(rx_id == 0 ?
1992                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
1993                 /* write TAIL register */
1994                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
1995                 nb_hold = 0;
1996         }
1997         rxq->nb_rx_hold = nb_hold;
1998
1999         /* return received packet in the burst */
2000         return nb_rx;
2001 }
2002
2003 const uint32_t *
2004 ice_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2005 {
2006         struct ice_adapter *ad =
2007                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2008         const uint32_t *ptypes;
2009
2010         static const uint32_t ptypes_os[] = {
2011                 /* refers to ice_get_default_pkt_type() */
2012                 RTE_PTYPE_L2_ETHER,
2013                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2014                 RTE_PTYPE_L2_ETHER_LLDP,
2015                 RTE_PTYPE_L2_ETHER_ARP,
2016                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2017                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2018                 RTE_PTYPE_L4_FRAG,
2019                 RTE_PTYPE_L4_ICMP,
2020                 RTE_PTYPE_L4_NONFRAG,
2021                 RTE_PTYPE_L4_SCTP,
2022                 RTE_PTYPE_L4_TCP,
2023                 RTE_PTYPE_L4_UDP,
2024                 RTE_PTYPE_TUNNEL_GRENAT,
2025                 RTE_PTYPE_TUNNEL_IP,
2026                 RTE_PTYPE_INNER_L2_ETHER,
2027                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2028                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2029                 RTE_PTYPE_INNER_L4_FRAG,
2030                 RTE_PTYPE_INNER_L4_ICMP,
2031                 RTE_PTYPE_INNER_L4_NONFRAG,
2032                 RTE_PTYPE_INNER_L4_SCTP,
2033                 RTE_PTYPE_INNER_L4_TCP,
2034                 RTE_PTYPE_INNER_L4_UDP,
2035                 RTE_PTYPE_UNKNOWN
2036         };
2037
2038         static const uint32_t ptypes_comms[] = {
2039                 /* refers to ice_get_default_pkt_type() */
2040                 RTE_PTYPE_L2_ETHER,
2041                 RTE_PTYPE_L2_ETHER_TIMESYNC,
2042                 RTE_PTYPE_L2_ETHER_LLDP,
2043                 RTE_PTYPE_L2_ETHER_ARP,
2044                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
2045                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
2046                 RTE_PTYPE_L4_FRAG,
2047                 RTE_PTYPE_L4_ICMP,
2048                 RTE_PTYPE_L4_NONFRAG,
2049                 RTE_PTYPE_L4_SCTP,
2050                 RTE_PTYPE_L4_TCP,
2051                 RTE_PTYPE_L4_UDP,
2052                 RTE_PTYPE_TUNNEL_GRENAT,
2053                 RTE_PTYPE_TUNNEL_IP,
2054                 RTE_PTYPE_INNER_L2_ETHER,
2055                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
2056                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
2057                 RTE_PTYPE_INNER_L4_FRAG,
2058                 RTE_PTYPE_INNER_L4_ICMP,
2059                 RTE_PTYPE_INNER_L4_NONFRAG,
2060                 RTE_PTYPE_INNER_L4_SCTP,
2061                 RTE_PTYPE_INNER_L4_TCP,
2062                 RTE_PTYPE_INNER_L4_UDP,
2063                 RTE_PTYPE_TUNNEL_GTPC,
2064                 RTE_PTYPE_TUNNEL_GTPU,
2065                 RTE_PTYPE_L2_ETHER_PPPOE,
2066                 RTE_PTYPE_UNKNOWN
2067         };
2068
2069         if (ad->active_pkg_type == ICE_PKG_TYPE_COMMS)
2070                 ptypes = ptypes_comms;
2071         else
2072                 ptypes = ptypes_os;
2073
2074         if (dev->rx_pkt_burst == ice_recv_pkts ||
2075             dev->rx_pkt_burst == ice_recv_pkts_bulk_alloc ||
2076             dev->rx_pkt_burst == ice_recv_scattered_pkts)
2077                 return ptypes;
2078
2079 #ifdef RTE_ARCH_X86
2080         if (dev->rx_pkt_burst == ice_recv_pkts_vec ||
2081             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec ||
2082 #ifdef CC_AVX512_SUPPORT
2083             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512 ||
2084             dev->rx_pkt_burst == ice_recv_pkts_vec_avx512_offload ||
2085             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512 ||
2086             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx512_offload ||
2087 #endif
2088             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2 ||
2089             dev->rx_pkt_burst == ice_recv_pkts_vec_avx2_offload ||
2090             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2 ||
2091             dev->rx_pkt_burst == ice_recv_scattered_pkts_vec_avx2_offload)
2092                 return ptypes;
2093 #endif
2094
2095         return NULL;
2096 }
2097
2098 int
2099 ice_rx_descriptor_status(void *rx_queue, uint16_t offset)
2100 {
2101         volatile union ice_rx_flex_desc *rxdp;
2102         struct ice_rx_queue *rxq = rx_queue;
2103         uint32_t desc;
2104
2105         if (unlikely(offset >= rxq->nb_rx_desc))
2106                 return -EINVAL;
2107
2108         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2109                 return RTE_ETH_RX_DESC_UNAVAIL;
2110
2111         desc = rxq->rx_tail + offset;
2112         if (desc >= rxq->nb_rx_desc)
2113                 desc -= rxq->nb_rx_desc;
2114
2115         rxdp = &rxq->rx_ring[desc];
2116         if (rte_le_to_cpu_16(rxdp->wb.status_error0) &
2117             (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S))
2118                 return RTE_ETH_RX_DESC_DONE;
2119
2120         return RTE_ETH_RX_DESC_AVAIL;
2121 }
2122
2123 int
2124 ice_tx_descriptor_status(void *tx_queue, uint16_t offset)
2125 {
2126         struct ice_tx_queue *txq = tx_queue;
2127         volatile uint64_t *status;
2128         uint64_t mask, expect;
2129         uint32_t desc;
2130
2131         if (unlikely(offset >= txq->nb_tx_desc))
2132                 return -EINVAL;
2133
2134         desc = txq->tx_tail + offset;
2135         /* go to next desc that has the RS bit */
2136         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2137                 txq->tx_rs_thresh;
2138         if (desc >= txq->nb_tx_desc) {
2139                 desc -= txq->nb_tx_desc;
2140                 if (desc >= txq->nb_tx_desc)
2141                         desc -= txq->nb_tx_desc;
2142         }
2143
2144         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2145         mask = rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M);
2146         expect = rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE <<
2147                                   ICE_TXD_QW1_DTYPE_S);
2148         if ((*status & mask) == expect)
2149                 return RTE_ETH_TX_DESC_DONE;
2150
2151         return RTE_ETH_TX_DESC_FULL;
2152 }
2153
2154 void
2155 ice_free_queues(struct rte_eth_dev *dev)
2156 {
2157         uint16_t i;
2158
2159         PMD_INIT_FUNC_TRACE();
2160
2161         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2162                 if (!dev->data->rx_queues[i])
2163                         continue;
2164                 ice_rx_queue_release(dev->data->rx_queues[i]);
2165                 dev->data->rx_queues[i] = NULL;
2166         }
2167         dev->data->nb_rx_queues = 0;
2168
2169         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2170                 if (!dev->data->tx_queues[i])
2171                         continue;
2172                 ice_tx_queue_release(dev->data->tx_queues[i]);
2173                 dev->data->tx_queues[i] = NULL;
2174         }
2175         dev->data->nb_tx_queues = 0;
2176 }
2177
2178 #define ICE_FDIR_NUM_TX_DESC  ICE_MIN_RING_DESC
2179 #define ICE_FDIR_NUM_RX_DESC  ICE_MIN_RING_DESC
2180
2181 int
2182 ice_fdir_setup_tx_resources(struct ice_pf *pf)
2183 {
2184         struct ice_tx_queue *txq;
2185         const struct rte_memzone *tz = NULL;
2186         uint32_t ring_size;
2187         struct rte_eth_dev *dev;
2188
2189         if (!pf) {
2190                 PMD_DRV_LOG(ERR, "PF is not available");
2191                 return -EINVAL;
2192         }
2193
2194         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2195
2196         /* Allocate the TX queue data structure. */
2197         txq = rte_zmalloc_socket("ice fdir tx queue",
2198                                  sizeof(struct ice_tx_queue),
2199                                  RTE_CACHE_LINE_SIZE,
2200                                  SOCKET_ID_ANY);
2201         if (!txq) {
2202                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2203                             "tx queue structure.");
2204                 return -ENOMEM;
2205         }
2206
2207         /* Allocate TX hardware ring descriptors. */
2208         ring_size = sizeof(struct ice_tx_desc) * ICE_FDIR_NUM_TX_DESC;
2209         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2210
2211         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2212                                       ICE_FDIR_QUEUE_ID, ring_size,
2213                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2214         if (!tz) {
2215                 ice_tx_queue_release(txq);
2216                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2217                 return -ENOMEM;
2218         }
2219
2220         txq->mz = tz;
2221         txq->nb_tx_desc = ICE_FDIR_NUM_TX_DESC;
2222         txq->queue_id = ICE_FDIR_QUEUE_ID;
2223         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2224         txq->vsi = pf->fdir.fdir_vsi;
2225
2226         txq->tx_ring_dma = tz->iova;
2227         txq->tx_ring = (struct ice_tx_desc *)tz->addr;
2228         /*
2229          * don't need to allocate software ring and reset for the fdir
2230          * program queue just set the queue has been configured.
2231          */
2232         txq->q_set = true;
2233         pf->fdir.txq = txq;
2234
2235         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs;
2236
2237         return ICE_SUCCESS;
2238 }
2239
2240 int
2241 ice_fdir_setup_rx_resources(struct ice_pf *pf)
2242 {
2243         struct ice_rx_queue *rxq;
2244         const struct rte_memzone *rz = NULL;
2245         uint32_t ring_size;
2246         struct rte_eth_dev *dev;
2247
2248         if (!pf) {
2249                 PMD_DRV_LOG(ERR, "PF is not available");
2250                 return -EINVAL;
2251         }
2252
2253         dev = &rte_eth_devices[pf->adapter->pf.dev_data->port_id];
2254
2255         /* Allocate the RX queue data structure. */
2256         rxq = rte_zmalloc_socket("ice fdir rx queue",
2257                                  sizeof(struct ice_rx_queue),
2258                                  RTE_CACHE_LINE_SIZE,
2259                                  SOCKET_ID_ANY);
2260         if (!rxq) {
2261                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2262                             "rx queue structure.");
2263                 return -ENOMEM;
2264         }
2265
2266         /* Allocate RX hardware ring descriptors. */
2267         ring_size = sizeof(union ice_32byte_rx_desc) * ICE_FDIR_NUM_RX_DESC;
2268         ring_size = RTE_ALIGN(ring_size, ICE_DMA_MEM_ALIGN);
2269
2270         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2271                                       ICE_FDIR_QUEUE_ID, ring_size,
2272                                       ICE_RING_BASE_ALIGN, SOCKET_ID_ANY);
2273         if (!rz) {
2274                 ice_rx_queue_release(rxq);
2275                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2276                 return -ENOMEM;
2277         }
2278
2279         rxq->mz = rz;
2280         rxq->nb_rx_desc = ICE_FDIR_NUM_RX_DESC;
2281         rxq->queue_id = ICE_FDIR_QUEUE_ID;
2282         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2283         rxq->vsi = pf->fdir.fdir_vsi;
2284
2285         rxq->rx_ring_dma = rz->iova;
2286         memset(rz->addr, 0, ICE_FDIR_NUM_RX_DESC *
2287                sizeof(union ice_32byte_rx_desc));
2288         rxq->rx_ring = (union ice_rx_flex_desc *)rz->addr;
2289
2290         /*
2291          * Don't need to allocate software ring and reset for the fdir
2292          * rx queue, just set the queue has been configured.
2293          */
2294         rxq->q_set = true;
2295         pf->fdir.rxq = rxq;
2296
2297         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs;
2298
2299         return ICE_SUCCESS;
2300 }
2301
2302 uint16_t
2303 ice_recv_pkts(void *rx_queue,
2304               struct rte_mbuf **rx_pkts,
2305               uint16_t nb_pkts)
2306 {
2307         struct ice_rx_queue *rxq = rx_queue;
2308         volatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;
2309         volatile union ice_rx_flex_desc *rxdp;
2310         union ice_rx_flex_desc rxd;
2311         struct ice_rx_entry *sw_ring = rxq->sw_ring;
2312         struct ice_rx_entry *rxe;
2313         struct rte_mbuf *nmb; /* new allocated mbuf */
2314         struct rte_mbuf *rxm; /* pointer to store old mbuf in SW ring */
2315         uint16_t rx_id = rxq->rx_tail;
2316         uint16_t nb_rx = 0;
2317         uint16_t nb_hold = 0;
2318         uint16_t rx_packet_len;
2319         uint16_t rx_stat_err0;
2320         uint64_t dma_addr;
2321         uint64_t pkt_flags;
2322         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
2323 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2324         struct ice_vsi *vsi = rxq->vsi;
2325         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2326         uint64_t ts_ns;
2327         struct ice_adapter *ad = rxq->vsi->adapter;
2328 #endif
2329
2330         if (rxq->offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP)
2331                 rxq->hw_register_set = 1;
2332
2333         while (nb_rx < nb_pkts) {
2334                 rxdp = &rx_ring[rx_id];
2335                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
2336
2337                 /* Check the DD bit first */
2338                 if (!(rx_stat_err0 & (1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
2339                         break;
2340
2341                 /* allocate mbuf */
2342                 nmb = rte_mbuf_raw_alloc(rxq->mp);
2343                 if (unlikely(!nmb)) {
2344                         rxq->vsi->adapter->pf.dev_data->rx_mbuf_alloc_failed++;
2345                         break;
2346                 }
2347                 rxd = *rxdp; /* copy descriptor in ring to temp variable*/
2348
2349                 nb_hold++;
2350                 rxe = &sw_ring[rx_id]; /* get corresponding mbuf in SW ring */
2351                 rx_id++;
2352                 if (unlikely(rx_id == rxq->nb_rx_desc))
2353                         rx_id = 0;
2354                 rxm = rxe->mbuf;
2355                 rxe->mbuf = nmb;
2356                 dma_addr =
2357                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
2358
2359                 /**
2360                  * fill the read format of descriptor with physic address in
2361                  * new allocated mbuf: nmb
2362                  */
2363                 rxdp->read.hdr_addr = 0;
2364                 rxdp->read.pkt_addr = dma_addr;
2365
2366                 /* calculate rx_packet_len of the received pkt */
2367                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
2368                                  ICE_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
2369
2370                 /* fill old mbuf with received descriptor: rxd */
2371                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
2372                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
2373                 rxm->nb_segs = 1;
2374                 rxm->next = NULL;
2375                 rxm->pkt_len = rx_packet_len;
2376                 rxm->data_len = rx_packet_len;
2377                 rxm->port = rxq->port_id;
2378                 rxm->packet_type = ptype_tbl[ICE_RX_FLEX_DESC_PTYPE_M &
2379                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
2380                 ice_rxd_to_vlan_tci(rxm, &rxd);
2381                 rxd_to_pkt_fields_ops[rxq->rxdid](rxq, rxm, &rxd);
2382                 pkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);
2383 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
2384                 if (ice_timestamp_dynflag > 0) {
2385                         ts_ns = ice_tstamp_convert_32b_64b(hw, ad,
2386                                 rxq->hw_register_set,
2387                                 rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high));
2388                         rxq->hw_register_set = 0;
2389                         *RTE_MBUF_DYNFIELD(rxm,
2390                                 ice_timestamp_dynfield_offset,
2391                                 rte_mbuf_timestamp_t *) = ts_ns;
2392                         rxm->ol_flags |= ice_timestamp_dynflag;
2393                 }
2394
2395                 if (ad->ptp_ena && ((rxm->packet_type & RTE_PTYPE_L2_MASK) ==
2396                     RTE_PTYPE_L2_ETHER_TIMESYNC)) {
2397                         rxq->time_high =
2398                            rte_le_to_cpu_32(rxd.wb.flex_ts.ts_high);
2399                         rxm->timesync = rxq->queue_id;
2400                         pkt_flags |= RTE_MBUF_F_RX_IEEE1588_PTP;
2401                 }
2402 #endif
2403                 rxm->ol_flags |= pkt_flags;
2404                 /* copy old mbuf to rx_pkts */
2405                 rx_pkts[nb_rx++] = rxm;
2406         }
2407         rxq->rx_tail = rx_id;
2408         /**
2409          * If the number of free RX descriptors is greater than the RX free
2410          * threshold of the queue, advance the receive tail register of queue.
2411          * Update that register with the value of the last processed RX
2412          * descriptor minus 1.
2413          */
2414         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
2415         if (nb_hold > rxq->rx_free_thresh) {
2416                 rx_id = (uint16_t)(rx_id == 0 ?
2417                                    (rxq->nb_rx_desc - 1) : (rx_id - 1));
2418                 /* write TAIL register */
2419                 ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
2420                 nb_hold = 0;
2421         }
2422         rxq->nb_rx_hold = nb_hold;
2423
2424         /* return received packet in the burst */
2425         return nb_rx;
2426 }
2427
2428 static inline void
2429 ice_parse_tunneling_params(uint64_t ol_flags,
2430                             union ice_tx_offload tx_offload,
2431                             uint32_t *cd_tunneling)
2432 {
2433         /* EIPT: External (outer) IP header type */
2434         if (ol_flags & RTE_MBUF_F_TX_OUTER_IP_CKSUM)
2435                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4;
2436         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV4)
2437                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV4_NO_CSUM;
2438         else if (ol_flags & RTE_MBUF_F_TX_OUTER_IPV6)
2439                 *cd_tunneling |= ICE_TX_CTX_EIPT_IPV6;
2440
2441         /* EIPLEN: External (outer) IP header length, in DWords */
2442         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
2443                 ICE_TXD_CTX_QW0_EIPLEN_S;
2444
2445         /* L4TUNT: L4 Tunneling Type */
2446         switch (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
2447         case RTE_MBUF_F_TX_TUNNEL_IPIP:
2448                 /* for non UDP / GRE tunneling, set to 00b */
2449                 break;
2450         case RTE_MBUF_F_TX_TUNNEL_VXLAN:
2451         case RTE_MBUF_F_TX_TUNNEL_GTP:
2452         case RTE_MBUF_F_TX_TUNNEL_GENEVE:
2453                 *cd_tunneling |= ICE_TXD_CTX_UDP_TUNNELING;
2454                 break;
2455         case RTE_MBUF_F_TX_TUNNEL_GRE:
2456                 *cd_tunneling |= ICE_TXD_CTX_GRE_TUNNELING;
2457                 break;
2458         default:
2459                 PMD_TX_LOG(ERR, "Tunnel type not supported");
2460                 return;
2461         }
2462
2463         /* L4TUNLEN: L4 Tunneling Length, in Words
2464          *
2465          * We depend on app to set rte_mbuf.l2_len correctly.
2466          * For IP in GRE it should be set to the length of the GRE
2467          * header;
2468          * For MAC in GRE or MAC in UDP it should be set to the length
2469          * of the GRE or UDP headers plus the inner MAC up to including
2470          * its last Ethertype.
2471          * If MPLS labels exists, it should include them as well.
2472          */
2473         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
2474                 ICE_TXD_CTX_QW0_NATLEN_S;
2475
2476         /**
2477          * Calculate the tunneling UDP checksum.
2478          * Shall be set only if L4TUNT = 01b and EIPT is not zero
2479          */
2480         if (!(*cd_tunneling & ICE_TX_CTX_EIPT_NONE) &&
2481             (*cd_tunneling & ICE_TXD_CTX_UDP_TUNNELING))
2482                 *cd_tunneling |= ICE_TXD_CTX_QW0_L4T_CS_M;
2483 }
2484
2485 static inline void
2486 ice_txd_enable_checksum(uint64_t ol_flags,
2487                         uint32_t *td_cmd,
2488                         uint32_t *td_offset,
2489                         union ice_tx_offload tx_offload)
2490 {
2491         /* Set MACLEN */
2492         if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2493                 *td_offset |= (tx_offload.outer_l2_len >> 1)
2494                         << ICE_TX_DESC_LEN_MACLEN_S;
2495         else
2496                 *td_offset |= (tx_offload.l2_len >> 1)
2497                         << ICE_TX_DESC_LEN_MACLEN_S;
2498
2499         /* Enable L3 checksum offloads */
2500         /*Tunnel package usage outer len enable L3 checksum offload*/
2501         if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) {
2502                 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
2503                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2504                         *td_offset |= (tx_offload.outer_l3_len >> 2) <<
2505                                 ICE_TX_DESC_LEN_IPLEN_S;
2506                 } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2507                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2508                         *td_offset |= (tx_offload.outer_l3_len >> 2) <<
2509                                 ICE_TX_DESC_LEN_IPLEN_S;
2510                 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2511                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2512                         *td_offset |= (tx_offload.outer_l3_len >> 2) <<
2513                                 ICE_TX_DESC_LEN_IPLEN_S;
2514                 }
2515         } else {
2516                 if (ol_flags & RTE_MBUF_F_TX_IP_CKSUM) {
2517                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4_CSUM;
2518                         *td_offset |= (tx_offload.l3_len >> 2) <<
2519                                 ICE_TX_DESC_LEN_IPLEN_S;
2520                 } else if (ol_flags & RTE_MBUF_F_TX_IPV4) {
2521                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV4;
2522                         *td_offset |= (tx_offload.l3_len >> 2) <<
2523                                 ICE_TX_DESC_LEN_IPLEN_S;
2524                 } else if (ol_flags & RTE_MBUF_F_TX_IPV6) {
2525                         *td_cmd |= ICE_TX_DESC_CMD_IIPT_IPV6;
2526                         *td_offset |= (tx_offload.l3_len >> 2) <<
2527                                 ICE_TX_DESC_LEN_IPLEN_S;
2528                 }
2529         }
2530
2531         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG) {
2532                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2533                 *td_offset |= (tx_offload.l4_len >> 2) <<
2534                               ICE_TX_DESC_LEN_L4_LEN_S;
2535                 return;
2536         }
2537
2538         /* Enable L4 checksum offloads */
2539         switch (ol_flags & RTE_MBUF_F_TX_L4_MASK) {
2540         case RTE_MBUF_F_TX_TCP_CKSUM:
2541                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_TCP;
2542                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
2543                               ICE_TX_DESC_LEN_L4_LEN_S;
2544                 break;
2545         case RTE_MBUF_F_TX_SCTP_CKSUM:
2546                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_SCTP;
2547                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
2548                               ICE_TX_DESC_LEN_L4_LEN_S;
2549                 break;
2550         case RTE_MBUF_F_TX_UDP_CKSUM:
2551                 *td_cmd |= ICE_TX_DESC_CMD_L4T_EOFT_UDP;
2552                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
2553                               ICE_TX_DESC_LEN_L4_LEN_S;
2554                 break;
2555         default:
2556                 break;
2557         }
2558 }
2559
2560 static inline int
2561 ice_xmit_cleanup(struct ice_tx_queue *txq)
2562 {
2563         struct ice_tx_entry *sw_ring = txq->sw_ring;
2564         volatile struct ice_tx_desc *txd = txq->tx_ring;
2565         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
2566         uint16_t nb_tx_desc = txq->nb_tx_desc;
2567         uint16_t desc_to_clean_to;
2568         uint16_t nb_tx_to_clean;
2569
2570         /* Determine the last descriptor needing to be cleaned */
2571         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
2572         if (desc_to_clean_to >= nb_tx_desc)
2573                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
2574
2575         /* Check to make sure the last descriptor to clean is done */
2576         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
2577         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
2578             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))) {
2579                 PMD_TX_LOG(DEBUG, "TX descriptor %4u is not done "
2580                            "(port=%d queue=%d) value=0x%"PRIx64"\n",
2581                            desc_to_clean_to,
2582                            txq->port_id, txq->queue_id,
2583                            txd[desc_to_clean_to].cmd_type_offset_bsz);
2584                 /* Failed to clean any descriptors */
2585                 return -1;
2586         }
2587
2588         /* Figure out how many descriptors will be cleaned */
2589         if (last_desc_cleaned > desc_to_clean_to)
2590                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
2591                                             desc_to_clean_to);
2592         else
2593                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
2594                                             last_desc_cleaned);
2595
2596         /* The last descriptor to clean is done, so that means all the
2597          * descriptors from the last descriptor that was cleaned
2598          * up to the last descriptor with the RS bit set
2599          * are done. Only reset the threshold descriptor.
2600          */
2601         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
2602
2603         /* Update the txq to reflect the last descriptor that was cleaned */
2604         txq->last_desc_cleaned = desc_to_clean_to;
2605         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
2606
2607         return 0;
2608 }
2609
2610 /* Construct the tx flags */
2611 static inline uint64_t
2612 ice_build_ctob(uint32_t td_cmd,
2613                uint32_t td_offset,
2614                uint16_t size,
2615                uint32_t td_tag)
2616 {
2617         return rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2618                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2619                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2620                                 ((uint64_t)size << ICE_TXD_QW1_TX_BUF_SZ_S) |
2621                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2622 }
2623
2624 /* Check if the context descriptor is needed for TX offloading */
2625 static inline uint16_t
2626 ice_calc_context_desc(uint64_t flags)
2627 {
2628         static uint64_t mask = RTE_MBUF_F_TX_TCP_SEG |
2629                 RTE_MBUF_F_TX_QINQ |
2630                 RTE_MBUF_F_TX_OUTER_IP_CKSUM |
2631                 RTE_MBUF_F_TX_TUNNEL_MASK |
2632                 RTE_MBUF_F_TX_IEEE1588_TMST;
2633
2634         return (flags & mask) ? 1 : 0;
2635 }
2636
2637 /* set ice TSO context descriptor */
2638 static inline uint64_t
2639 ice_set_tso_ctx(struct rte_mbuf *mbuf, union ice_tx_offload tx_offload)
2640 {
2641         uint64_t ctx_desc = 0;
2642         uint32_t cd_cmd, hdr_len, cd_tso_len;
2643
2644         if (!tx_offload.l4_len) {
2645                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
2646                 return ctx_desc;
2647         }
2648
2649         hdr_len = tx_offload.l2_len + tx_offload.l3_len + tx_offload.l4_len;
2650         hdr_len += (mbuf->ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK) ?
2651                    tx_offload.outer_l2_len + tx_offload.outer_l3_len : 0;
2652
2653         cd_cmd = ICE_TX_CTX_DESC_TSO;
2654         cd_tso_len = mbuf->pkt_len - hdr_len;
2655         ctx_desc |= ((uint64_t)cd_cmd << ICE_TXD_CTX_QW1_CMD_S) |
2656                     ((uint64_t)cd_tso_len << ICE_TXD_CTX_QW1_TSO_LEN_S) |
2657                     ((uint64_t)mbuf->tso_segsz << ICE_TXD_CTX_QW1_MSS_S);
2658
2659         return ctx_desc;
2660 }
2661
2662 /* HW requires that TX buffer size ranges from 1B up to (16K-1)B. */
2663 #define ICE_MAX_DATA_PER_TXD \
2664         (ICE_TXD_QW1_TX_BUF_SZ_M >> ICE_TXD_QW1_TX_BUF_SZ_S)
2665 /* Calculate the number of TX descriptors needed for each pkt */
2666 static inline uint16_t
2667 ice_calc_pkt_desc(struct rte_mbuf *tx_pkt)
2668 {
2669         struct rte_mbuf *txd = tx_pkt;
2670         uint16_t count = 0;
2671
2672         while (txd != NULL) {
2673                 count += DIV_ROUND_UP(txd->data_len, ICE_MAX_DATA_PER_TXD);
2674                 txd = txd->next;
2675         }
2676
2677         return count;
2678 }
2679
2680 uint16_t
2681 ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2682 {
2683         struct ice_tx_queue *txq;
2684         volatile struct ice_tx_desc *tx_ring;
2685         volatile struct ice_tx_desc *txd;
2686         struct ice_tx_entry *sw_ring;
2687         struct ice_tx_entry *txe, *txn;
2688         struct rte_mbuf *tx_pkt;
2689         struct rte_mbuf *m_seg;
2690         uint32_t cd_tunneling_params;
2691         uint16_t tx_id;
2692         uint16_t nb_tx;
2693         uint16_t nb_used;
2694         uint16_t nb_ctx;
2695         uint32_t td_cmd = 0;
2696         uint32_t td_offset = 0;
2697         uint32_t td_tag = 0;
2698         uint16_t tx_last;
2699         uint16_t slen;
2700         uint64_t buf_dma_addr;
2701         uint64_t ol_flags;
2702         union ice_tx_offload tx_offload = {0};
2703
2704         txq = tx_queue;
2705         sw_ring = txq->sw_ring;
2706         tx_ring = txq->tx_ring;
2707         tx_id = txq->tx_tail;
2708         txe = &sw_ring[tx_id];
2709
2710         /* Check if the descriptor ring needs to be cleaned. */
2711         if (txq->nb_tx_free < txq->tx_free_thresh)
2712                 (void)ice_xmit_cleanup(txq);
2713
2714         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
2715                 tx_pkt = *tx_pkts++;
2716
2717                 td_cmd = 0;
2718                 td_tag = 0;
2719                 td_offset = 0;
2720                 ol_flags = tx_pkt->ol_flags;
2721                 tx_offload.l2_len = tx_pkt->l2_len;
2722                 tx_offload.l3_len = tx_pkt->l3_len;
2723                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
2724                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
2725                 tx_offload.l4_len = tx_pkt->l4_len;
2726                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
2727                 /* Calculate the number of context descriptors needed. */
2728                 nb_ctx = ice_calc_context_desc(ol_flags);
2729
2730                 /* The number of descriptors that must be allocated for
2731                  * a packet equals to the number of the segments of that
2732                  * packet plus the number of context descriptor if needed.
2733                  * Recalculate the needed tx descs when TSO enabled in case
2734                  * the mbuf data size exceeds max data size that hw allows
2735                  * per tx desc.
2736                  */
2737                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2738                         nb_used = (uint16_t)(ice_calc_pkt_desc(tx_pkt) +
2739                                              nb_ctx);
2740                 else
2741                         nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
2742                 tx_last = (uint16_t)(tx_id + nb_used - 1);
2743
2744                 /* Circular ring */
2745                 if (tx_last >= txq->nb_tx_desc)
2746                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
2747
2748                 if (nb_used > txq->nb_tx_free) {
2749                         if (ice_xmit_cleanup(txq) != 0) {
2750                                 if (nb_tx == 0)
2751                                         return 0;
2752                                 goto end_of_tx;
2753                         }
2754                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
2755                                 while (nb_used > txq->nb_tx_free) {
2756                                         if (ice_xmit_cleanup(txq) != 0) {
2757                                                 if (nb_tx == 0)
2758                                                         return 0;
2759                                                 goto end_of_tx;
2760                                         }
2761                                 }
2762                         }
2763                 }
2764
2765                 /* Descriptor based VLAN insertion */
2766                 if (ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {
2767                         td_cmd |= ICE_TX_DESC_CMD_IL2TAG1;
2768                         td_tag = tx_pkt->vlan_tci;
2769                 }
2770
2771                 /* Fill in tunneling parameters if necessary */
2772                 cd_tunneling_params = 0;
2773                 if (ol_flags & RTE_MBUF_F_TX_TUNNEL_MASK)
2774                         ice_parse_tunneling_params(ol_flags, tx_offload,
2775                                                    &cd_tunneling_params);
2776
2777                 /* Enable checksum offloading */
2778                 if (ol_flags & ICE_TX_CKSUM_OFFLOAD_MASK)
2779                         ice_txd_enable_checksum(ol_flags, &td_cmd,
2780                                                 &td_offset, tx_offload);
2781
2782                 if (nb_ctx) {
2783                         /* Setup TX context descriptor if required */
2784                         volatile struct ice_tx_ctx_desc *ctx_txd =
2785                                 (volatile struct ice_tx_ctx_desc *)
2786                                         &tx_ring[tx_id];
2787                         uint16_t cd_l2tag2 = 0;
2788                         uint64_t cd_type_cmd_tso_mss = ICE_TX_DESC_DTYPE_CTX;
2789
2790                         txn = &sw_ring[txe->next_id];
2791                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
2792                         if (txe->mbuf) {
2793                                 rte_pktmbuf_free_seg(txe->mbuf);
2794                                 txe->mbuf = NULL;
2795                         }
2796
2797                         if (ol_flags & RTE_MBUF_F_TX_TCP_SEG)
2798                                 cd_type_cmd_tso_mss |=
2799                                         ice_set_tso_ctx(tx_pkt, tx_offload);
2800                         else if (ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)
2801                                 cd_type_cmd_tso_mss |=
2802                                         ((uint64_t)ICE_TX_CTX_DESC_TSYN <<
2803                                         ICE_TXD_CTX_QW1_CMD_S);
2804
2805                         ctx_txd->tunneling_params =
2806                                 rte_cpu_to_le_32(cd_tunneling_params);
2807
2808                         /* TX context descriptor based double VLAN insert */
2809                         if (ol_flags & RTE_MBUF_F_TX_QINQ) {
2810                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
2811                                 cd_type_cmd_tso_mss |=
2812                                         ((uint64_t)ICE_TX_CTX_DESC_IL2TAG2 <<
2813                                          ICE_TXD_CTX_QW1_CMD_S);
2814                         }
2815                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
2816                         ctx_txd->qw1 =
2817                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
2818
2819                         txe->last_id = tx_last;
2820                         tx_id = txe->next_id;
2821                         txe = txn;
2822                 }
2823                 m_seg = tx_pkt;
2824
2825                 do {
2826                         txd = &tx_ring[tx_id];
2827                         txn = &sw_ring[txe->next_id];
2828
2829                         if (txe->mbuf)
2830                                 rte_pktmbuf_free_seg(txe->mbuf);
2831                         txe->mbuf = m_seg;
2832
2833                         /* Setup TX Descriptor */
2834                         slen = m_seg->data_len;
2835                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
2836
2837                         while ((ol_flags & RTE_MBUF_F_TX_TCP_SEG) &&
2838                                 unlikely(slen > ICE_MAX_DATA_PER_TXD)) {
2839                                 txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2840                                 txd->cmd_type_offset_bsz =
2841                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2842                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2843                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2844                                 ((uint64_t)ICE_MAX_DATA_PER_TXD <<
2845                                  ICE_TXD_QW1_TX_BUF_SZ_S) |
2846                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2847
2848                                 buf_dma_addr += ICE_MAX_DATA_PER_TXD;
2849                                 slen -= ICE_MAX_DATA_PER_TXD;
2850
2851                                 txe->last_id = tx_last;
2852                                 tx_id = txe->next_id;
2853                                 txe = txn;
2854                                 txd = &tx_ring[tx_id];
2855                                 txn = &sw_ring[txe->next_id];
2856                         }
2857
2858                         txd->buf_addr = rte_cpu_to_le_64(buf_dma_addr);
2859                         txd->cmd_type_offset_bsz =
2860                                 rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DATA |
2861                                 ((uint64_t)td_cmd << ICE_TXD_QW1_CMD_S) |
2862                                 ((uint64_t)td_offset << ICE_TXD_QW1_OFFSET_S) |
2863                                 ((uint64_t)slen << ICE_TXD_QW1_TX_BUF_SZ_S) |
2864                                 ((uint64_t)td_tag << ICE_TXD_QW1_L2TAG1_S));
2865
2866                         txe->last_id = tx_last;
2867                         tx_id = txe->next_id;
2868                         txe = txn;
2869                         m_seg = m_seg->next;
2870                 } while (m_seg);
2871
2872                 /* fill the last descriptor with End of Packet (EOP) bit */
2873                 td_cmd |= ICE_TX_DESC_CMD_EOP;
2874                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
2875                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
2876
2877                 /* set RS bit on the last descriptor of one packet */
2878                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
2879                         PMD_TX_LOG(DEBUG,
2880                                    "Setting RS bit on TXD id="
2881                                    "%4u (port=%d queue=%d)",
2882                                    tx_last, txq->port_id, txq->queue_id);
2883
2884                         td_cmd |= ICE_TX_DESC_CMD_RS;
2885
2886                         /* Update txq RS bit counters */
2887                         txq->nb_tx_used = 0;
2888                 }
2889                 txd->cmd_type_offset_bsz |=
2890                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
2891                                          ICE_TXD_QW1_CMD_S);
2892         }
2893 end_of_tx:
2894         /* update Tail register */
2895         ICE_PCI_REG_WRITE(txq->qtx_tail, tx_id);
2896         txq->tx_tail = tx_id;
2897
2898         return nb_tx;
2899 }
2900
2901 static __rte_always_inline int
2902 ice_tx_free_bufs(struct ice_tx_queue *txq)
2903 {
2904         struct ice_tx_entry *txep;
2905         uint16_t i;
2906
2907         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
2908              rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
2909             rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
2910                 return 0;
2911
2912         txep = &txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)];
2913
2914         for (i = 0; i < txq->tx_rs_thresh; i++)
2915                 rte_prefetch0((txep + i)->mbuf);
2916
2917         if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {
2918                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2919                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
2920                         txep->mbuf = NULL;
2921                 }
2922         } else {
2923                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
2924                         rte_pktmbuf_free_seg(txep->mbuf);
2925                         txep->mbuf = NULL;
2926                 }
2927         }
2928
2929         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
2930         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
2931         if (txq->tx_next_dd >= txq->nb_tx_desc)
2932                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2933
2934         return txq->tx_rs_thresh;
2935 }
2936
2937 static int
2938 ice_tx_done_cleanup_full(struct ice_tx_queue *txq,
2939                         uint32_t free_cnt)
2940 {
2941         struct ice_tx_entry *swr_ring = txq->sw_ring;
2942         uint16_t i, tx_last, tx_id;
2943         uint16_t nb_tx_free_last;
2944         uint16_t nb_tx_to_clean;
2945         uint32_t pkt_cnt;
2946
2947         /* Start free mbuf from the next of tx_tail */
2948         tx_last = txq->tx_tail;
2949         tx_id  = swr_ring[tx_last].next_id;
2950
2951         if (txq->nb_tx_free == 0 && ice_xmit_cleanup(txq))
2952                 return 0;
2953
2954         nb_tx_to_clean = txq->nb_tx_free;
2955         nb_tx_free_last = txq->nb_tx_free;
2956         if (!free_cnt)
2957                 free_cnt = txq->nb_tx_desc;
2958
2959         /* Loop through swr_ring to count the amount of
2960          * freeable mubfs and packets.
2961          */
2962         for (pkt_cnt = 0; pkt_cnt < free_cnt; ) {
2963                 for (i = 0; i < nb_tx_to_clean &&
2964                         pkt_cnt < free_cnt &&
2965                         tx_id != tx_last; i++) {
2966                         if (swr_ring[tx_id].mbuf != NULL) {
2967                                 rte_pktmbuf_free_seg(swr_ring[tx_id].mbuf);
2968                                 swr_ring[tx_id].mbuf = NULL;
2969
2970                                 /*
2971                                  * last segment in the packet,
2972                                  * increment packet count
2973                                  */
2974                                 pkt_cnt += (swr_ring[tx_id].last_id == tx_id);
2975                         }
2976
2977                         tx_id = swr_ring[tx_id].next_id;
2978                 }
2979
2980                 if (txq->tx_rs_thresh > txq->nb_tx_desc -
2981                         txq->nb_tx_free || tx_id == tx_last)
2982                         break;
2983
2984                 if (pkt_cnt < free_cnt) {
2985                         if (ice_xmit_cleanup(txq))
2986                                 break;
2987
2988                         nb_tx_to_clean = txq->nb_tx_free - nb_tx_free_last;
2989                         nb_tx_free_last = txq->nb_tx_free;
2990                 }
2991         }
2992
2993         return (int)pkt_cnt;
2994 }
2995
2996 #ifdef RTE_ARCH_X86
2997 static int
2998 ice_tx_done_cleanup_vec(struct ice_tx_queue *txq __rte_unused,
2999                         uint32_t free_cnt __rte_unused)
3000 {
3001         return -ENOTSUP;
3002 }
3003 #endif
3004
3005 static int
3006 ice_tx_done_cleanup_simple(struct ice_tx_queue *txq,
3007                         uint32_t free_cnt)
3008 {
3009         int i, n, cnt;
3010
3011         if (free_cnt == 0 || free_cnt > txq->nb_tx_desc)
3012                 free_cnt = txq->nb_tx_desc;
3013
3014         cnt = free_cnt - free_cnt % txq->tx_rs_thresh;
3015
3016         for (i = 0; i < cnt; i += n) {
3017                 if (txq->nb_tx_desc - txq->nb_tx_free < txq->tx_rs_thresh)
3018                         break;
3019
3020                 n = ice_tx_free_bufs(txq);
3021
3022                 if (n == 0)
3023                         break;
3024         }
3025
3026         return i;
3027 }
3028
3029 int
3030 ice_tx_done_cleanup(void *txq, uint32_t free_cnt)
3031 {
3032         struct ice_tx_queue *q = (struct ice_tx_queue *)txq;
3033         struct rte_eth_dev *dev = &rte_eth_devices[q->port_id];
3034         struct ice_adapter *ad =
3035                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3036
3037 #ifdef RTE_ARCH_X86
3038         if (ad->tx_vec_allowed)
3039                 return ice_tx_done_cleanup_vec(q, free_cnt);
3040 #endif
3041         if (ad->tx_simple_allowed)
3042                 return ice_tx_done_cleanup_simple(q, free_cnt);
3043         else
3044                 return ice_tx_done_cleanup_full(q, free_cnt);
3045 }
3046
3047 /* Populate 4 descriptors with data from 4 mbufs */
3048 static inline void
3049 tx4(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3050 {
3051         uint64_t dma_addr;
3052         uint32_t i;
3053
3054         for (i = 0; i < 4; i++, txdp++, pkts++) {
3055                 dma_addr = rte_mbuf_data_iova(*pkts);
3056                 txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3057                 txdp->cmd_type_offset_bsz =
3058                         ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3059                                        (*pkts)->data_len, 0);
3060         }
3061 }
3062
3063 /* Populate 1 descriptor with data from 1 mbuf */
3064 static inline void
3065 tx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkts)
3066 {
3067         uint64_t dma_addr;
3068
3069         dma_addr = rte_mbuf_data_iova(*pkts);
3070         txdp->buf_addr = rte_cpu_to_le_64(dma_addr);
3071         txdp->cmd_type_offset_bsz =
3072                 ice_build_ctob((uint32_t)ICE_TD_CMD, 0,
3073                                (*pkts)->data_len, 0);
3074 }
3075
3076 static inline void
3077 ice_tx_fill_hw_ring(struct ice_tx_queue *txq, struct rte_mbuf **pkts,
3078                     uint16_t nb_pkts)
3079 {
3080         volatile struct ice_tx_desc *txdp = &txq->tx_ring[txq->tx_tail];
3081         struct ice_tx_entry *txep = &txq->sw_ring[txq->tx_tail];
3082         const int N_PER_LOOP = 4;
3083         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
3084         int mainpart, leftover;
3085         int i, j;
3086
3087         /**
3088          * Process most of the packets in chunks of N pkts.  Any
3089          * leftover packets will get processed one at a time.
3090          */
3091         mainpart = nb_pkts & ((uint32_t)~N_PER_LOOP_MASK);
3092         leftover = nb_pkts & ((uint32_t)N_PER_LOOP_MASK);
3093         for (i = 0; i < mainpart; i += N_PER_LOOP) {
3094                 /* Copy N mbuf pointers to the S/W ring */
3095                 for (j = 0; j < N_PER_LOOP; ++j)
3096                         (txep + i + j)->mbuf = *(pkts + i + j);
3097                 tx4(txdp + i, pkts + i);
3098         }
3099
3100         if (unlikely(leftover > 0)) {
3101                 for (i = 0; i < leftover; ++i) {
3102                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
3103                         tx1(txdp + mainpart + i, pkts + mainpart + i);
3104                 }
3105         }
3106 }
3107
3108 static inline uint16_t
3109 tx_xmit_pkts(struct ice_tx_queue *txq,
3110              struct rte_mbuf **tx_pkts,
3111              uint16_t nb_pkts)
3112 {
3113         volatile struct ice_tx_desc *txr = txq->tx_ring;
3114         uint16_t n = 0;
3115
3116         /**
3117          * Begin scanning the H/W ring for done descriptors when the number
3118          * of available descriptors drops below tx_free_thresh. For each done
3119          * descriptor, free the associated buffer.
3120          */
3121         if (txq->nb_tx_free < txq->tx_free_thresh)
3122                 ice_tx_free_bufs(txq);
3123
3124         /* Use available descriptor only */
3125         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
3126         if (unlikely(!nb_pkts))
3127                 return 0;
3128
3129         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
3130         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
3131                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
3132                 ice_tx_fill_hw_ring(txq, tx_pkts, n);
3133                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3134                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3135                                          ICE_TXD_QW1_CMD_S);
3136                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3137                 txq->tx_tail = 0;
3138         }
3139
3140         /* Fill hardware descriptor ring with mbuf data */
3141         ice_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
3142         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
3143
3144         /* Determine if RS bit needs to be set */
3145         if (txq->tx_tail > txq->tx_next_rs) {
3146                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
3147                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
3148                                          ICE_TXD_QW1_CMD_S);
3149                 txq->tx_next_rs =
3150                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
3151                 if (txq->tx_next_rs >= txq->nb_tx_desc)
3152                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
3153         }
3154
3155         if (txq->tx_tail >= txq->nb_tx_desc)
3156                 txq->tx_tail = 0;
3157
3158         /* Update the tx tail register */
3159         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
3160
3161         return nb_pkts;
3162 }
3163
3164 static uint16_t
3165 ice_xmit_pkts_simple(void *tx_queue,
3166                      struct rte_mbuf **tx_pkts,
3167                      uint16_t nb_pkts)
3168 {
3169         uint16_t nb_tx = 0;
3170
3171         if (likely(nb_pkts <= ICE_TX_MAX_BURST))
3172                 return tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3173                                     tx_pkts, nb_pkts);
3174
3175         while (nb_pkts) {
3176                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
3177                                                       ICE_TX_MAX_BURST);
3178
3179                 ret = tx_xmit_pkts((struct ice_tx_queue *)tx_queue,
3180                                    &tx_pkts[nb_tx], num);
3181                 nb_tx = (uint16_t)(nb_tx + ret);
3182                 nb_pkts = (uint16_t)(nb_pkts - ret);
3183                 if (ret < num)
3184                         break;
3185         }
3186
3187         return nb_tx;
3188 }
3189
3190 void __rte_cold
3191 ice_set_rx_function(struct rte_eth_dev *dev)
3192 {
3193         PMD_INIT_FUNC_TRACE();
3194         struct ice_adapter *ad =
3195                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3196 #ifdef RTE_ARCH_X86
3197         struct ice_rx_queue *rxq;
3198         int i;
3199         int rx_check_ret = -1;
3200
3201         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3202                 ad->rx_use_avx512 = false;
3203                 ad->rx_use_avx2 = false;
3204                 rx_check_ret = ice_rx_vec_dev_check(dev);
3205                 if (ad->ptp_ena)
3206                         rx_check_ret = -1;
3207                 ad->rx_vec_offload_support =
3208                                 (rx_check_ret == ICE_VECTOR_OFFLOAD_PATH);
3209                 if (rx_check_ret >= 0 && ad->rx_bulk_alloc_allowed &&
3210                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3211                         ad->rx_vec_allowed = true;
3212                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3213                                 rxq = dev->data->rx_queues[i];
3214                                 if (rxq && ice_rxq_vec_setup(rxq)) {
3215                                         ad->rx_vec_allowed = false;
3216                                         break;
3217                                 }
3218                         }
3219
3220                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3221                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3222                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3223 #ifdef CC_AVX512_SUPPORT
3224                                 ad->rx_use_avx512 = true;
3225 #else
3226                         PMD_DRV_LOG(NOTICE,
3227                                 "AVX512 is not supported in build env");
3228 #endif
3229                         if (!ad->rx_use_avx512 &&
3230                         (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3231                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3232                         rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3233                                 ad->rx_use_avx2 = true;
3234
3235                 } else {
3236                         ad->rx_vec_allowed = false;
3237                 }
3238         }
3239
3240         if (ad->rx_vec_allowed) {
3241                 if (dev->data->scattered_rx) {
3242                         if (ad->rx_use_avx512) {
3243 #ifdef CC_AVX512_SUPPORT
3244                                 if (ad->rx_vec_offload_support) {
3245                                         PMD_DRV_LOG(NOTICE,
3246                                                 "Using AVX512 OFFLOAD Vector Scattered Rx (port %d).",
3247                                                 dev->data->port_id);
3248                                         dev->rx_pkt_burst =
3249                                                 ice_recv_scattered_pkts_vec_avx512_offload;
3250                                 } else {
3251                                         PMD_DRV_LOG(NOTICE,
3252                                                 "Using AVX512 Vector Scattered Rx (port %d).",
3253                                                 dev->data->port_id);
3254                                         dev->rx_pkt_burst =
3255                                                 ice_recv_scattered_pkts_vec_avx512;
3256                                 }
3257 #endif
3258                         } else if (ad->rx_use_avx2) {
3259                                 if (ad->rx_vec_offload_support) {
3260                                         PMD_DRV_LOG(NOTICE,
3261                                                     "Using AVX2 OFFLOAD Vector Scattered Rx (port %d).",
3262                                                     dev->data->port_id);
3263                                         dev->rx_pkt_burst =
3264                                                 ice_recv_scattered_pkts_vec_avx2_offload;
3265                                 } else {
3266                                         PMD_DRV_LOG(NOTICE,
3267                                                     "Using AVX2 Vector Scattered Rx (port %d).",
3268                                                     dev->data->port_id);
3269                                         dev->rx_pkt_burst =
3270                                                 ice_recv_scattered_pkts_vec_avx2;
3271                                 }
3272                         } else {
3273                                 PMD_DRV_LOG(DEBUG,
3274                                         "Using Vector Scattered Rx (port %d).",
3275                                         dev->data->port_id);
3276                                 dev->rx_pkt_burst = ice_recv_scattered_pkts_vec;
3277                         }
3278                 } else {
3279                         if (ad->rx_use_avx512) {
3280 #ifdef CC_AVX512_SUPPORT
3281                                 if (ad->rx_vec_offload_support) {
3282                                         PMD_DRV_LOG(NOTICE,
3283                                                 "Using AVX512 OFFLOAD Vector Rx (port %d).",
3284                                                 dev->data->port_id);
3285                                         dev->rx_pkt_burst =
3286                                                 ice_recv_pkts_vec_avx512_offload;
3287                                 } else {
3288                                         PMD_DRV_LOG(NOTICE,
3289                                                 "Using AVX512 Vector Rx (port %d).",
3290                                                 dev->data->port_id);
3291                                         dev->rx_pkt_burst =
3292                                                 ice_recv_pkts_vec_avx512;
3293                                 }
3294 #endif
3295                         } else if (ad->rx_use_avx2) {
3296                                 if (ad->rx_vec_offload_support) {
3297                                         PMD_DRV_LOG(NOTICE,
3298                                                     "Using AVX2 OFFLOAD Vector Rx (port %d).",
3299                                                     dev->data->port_id);
3300                                         dev->rx_pkt_burst =
3301                                                 ice_recv_pkts_vec_avx2_offload;
3302                                 } else {
3303                                         PMD_DRV_LOG(NOTICE,
3304                                                     "Using AVX2 Vector Rx (port %d).",
3305                                                     dev->data->port_id);
3306                                         dev->rx_pkt_burst =
3307                                                 ice_recv_pkts_vec_avx2;
3308                                 }
3309                         } else {
3310                                 PMD_DRV_LOG(DEBUG,
3311                                         "Using Vector Rx (port %d).",
3312                                         dev->data->port_id);
3313                                 dev->rx_pkt_burst = ice_recv_pkts_vec;
3314                         }
3315                 }
3316                 return;
3317         }
3318
3319 #endif
3320
3321         if (dev->data->scattered_rx) {
3322                 /* Set the non-LRO scattered function */
3323                 PMD_INIT_LOG(DEBUG,
3324                              "Using a Scattered function on port %d.",
3325                              dev->data->port_id);
3326                 dev->rx_pkt_burst = ice_recv_scattered_pkts;
3327         } else if (ad->rx_bulk_alloc_allowed) {
3328                 PMD_INIT_LOG(DEBUG,
3329                              "Rx Burst Bulk Alloc Preconditions are "
3330                              "satisfied. Rx Burst Bulk Alloc function "
3331                              "will be used on port %d.",
3332                              dev->data->port_id);
3333                 dev->rx_pkt_burst = ice_recv_pkts_bulk_alloc;
3334         } else {
3335                 PMD_INIT_LOG(DEBUG,
3336                              "Rx Burst Bulk Alloc Preconditions are not "
3337                              "satisfied, Normal Rx will be used on port %d.",
3338                              dev->data->port_id);
3339                 dev->rx_pkt_burst = ice_recv_pkts;
3340         }
3341 }
3342
3343 static const struct {
3344         eth_rx_burst_t pkt_burst;
3345         const char *info;
3346 } ice_rx_burst_infos[] = {
3347         { ice_recv_scattered_pkts,          "Scalar Scattered" },
3348         { ice_recv_pkts_bulk_alloc,         "Scalar Bulk Alloc" },
3349         { ice_recv_pkts,                    "Scalar" },
3350 #ifdef RTE_ARCH_X86
3351 #ifdef CC_AVX512_SUPPORT
3352         { ice_recv_scattered_pkts_vec_avx512, "Vector AVX512 Scattered" },
3353         { ice_recv_scattered_pkts_vec_avx512_offload, "Offload Vector AVX512 Scattered" },
3354         { ice_recv_pkts_vec_avx512,           "Vector AVX512" },
3355         { ice_recv_pkts_vec_avx512_offload,   "Offload Vector AVX512" },
3356 #endif
3357         { ice_recv_scattered_pkts_vec_avx2, "Vector AVX2 Scattered" },
3358         { ice_recv_scattered_pkts_vec_avx2_offload, "Offload Vector AVX2 Scattered" },
3359         { ice_recv_pkts_vec_avx2,           "Vector AVX2" },
3360         { ice_recv_pkts_vec_avx2_offload,   "Offload Vector AVX2" },
3361         { ice_recv_scattered_pkts_vec,      "Vector SSE Scattered" },
3362         { ice_recv_pkts_vec,                "Vector SSE" },
3363 #endif
3364 };
3365
3366 int
3367 ice_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3368                       struct rte_eth_burst_mode *mode)
3369 {
3370         eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
3371         int ret = -EINVAL;
3372         unsigned int i;
3373
3374         for (i = 0; i < RTE_DIM(ice_rx_burst_infos); ++i) {
3375                 if (pkt_burst == ice_rx_burst_infos[i].pkt_burst) {
3376                         snprintf(mode->info, sizeof(mode->info), "%s",
3377                                  ice_rx_burst_infos[i].info);
3378                         ret = 0;
3379                         break;
3380                 }
3381         }
3382
3383         return ret;
3384 }
3385
3386 void __rte_cold
3387 ice_set_tx_function_flag(struct rte_eth_dev *dev, struct ice_tx_queue *txq)
3388 {
3389         struct ice_adapter *ad =
3390                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3391
3392         /* Use a simple Tx queue if possible (only fast free is allowed) */
3393         ad->tx_simple_allowed =
3394                 (txq->offloads ==
3395                 (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) &&
3396                 txq->tx_rs_thresh >= ICE_TX_MAX_BURST);
3397
3398         if (ad->tx_simple_allowed)
3399                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3400                              txq->queue_id);
3401         else
3402                 PMD_INIT_LOG(DEBUG,
3403                              "Simple Tx can NOT be enabled on Tx queue %u.",
3404                              txq->queue_id);
3405 }
3406
3407 /*********************************************************************
3408  *
3409  *  TX prep functions
3410  *
3411  **********************************************************************/
3412 /* The default values of TSO MSS */
3413 #define ICE_MIN_TSO_MSS            64
3414 #define ICE_MAX_TSO_MSS            9728
3415 #define ICE_MAX_TSO_FRAME_SIZE     262144
3416 uint16_t
3417 ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
3418               uint16_t nb_pkts)
3419 {
3420         int i, ret;
3421         uint64_t ol_flags;
3422         struct rte_mbuf *m;
3423
3424         for (i = 0; i < nb_pkts; i++) {
3425                 m = tx_pkts[i];
3426                 ol_flags = m->ol_flags;
3427
3428                 if (ol_flags & RTE_MBUF_F_TX_TCP_SEG &&
3429                     (m->tso_segsz < ICE_MIN_TSO_MSS ||
3430                      m->tso_segsz > ICE_MAX_TSO_MSS ||
3431                      m->pkt_len > ICE_MAX_TSO_FRAME_SIZE)) {
3432                         /**
3433                          * MSS outside the range are considered malicious
3434                          */
3435                         rte_errno = EINVAL;
3436                         return i;
3437                 }
3438
3439 #ifdef RTE_ETHDEV_DEBUG_TX
3440                 ret = rte_validate_tx_offload(m);
3441                 if (ret != 0) {
3442                         rte_errno = -ret;
3443                         return i;
3444                 }
3445 #endif
3446                 ret = rte_net_intel_cksum_prepare(m);
3447                 if (ret != 0) {
3448                         rte_errno = -ret;
3449                         return i;
3450                 }
3451         }
3452         return i;
3453 }
3454
3455 void __rte_cold
3456 ice_set_tx_function(struct rte_eth_dev *dev)
3457 {
3458         struct ice_adapter *ad =
3459                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3460 #ifdef RTE_ARCH_X86
3461         struct ice_tx_queue *txq;
3462         int i;
3463         int tx_check_ret = -1;
3464
3465         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3466                 ad->tx_use_avx2 = false;
3467                 ad->tx_use_avx512 = false;
3468                 tx_check_ret = ice_tx_vec_dev_check(dev);
3469                 if (tx_check_ret >= 0 &&
3470                     rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) {
3471                         ad->tx_vec_allowed = true;
3472
3473                         if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_512 &&
3474                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1 &&
3475                         rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512BW) == 1)
3476 #ifdef CC_AVX512_SUPPORT
3477                                 ad->tx_use_avx512 = true;
3478 #else
3479                         PMD_DRV_LOG(NOTICE,
3480                                 "AVX512 is not supported in build env");
3481 #endif
3482                         if (!ad->tx_use_avx512 &&
3483                                 (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
3484                                 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) &&
3485                                 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256)
3486                                 ad->tx_use_avx2 = true;
3487
3488                         if (!ad->tx_use_avx2 && !ad->tx_use_avx512 &&
3489                                 tx_check_ret == ICE_VECTOR_OFFLOAD_PATH)
3490                                 ad->tx_vec_allowed = false;
3491
3492                         if (ad->tx_vec_allowed) {
3493                                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
3494                                         txq = dev->data->tx_queues[i];
3495                                         if (txq && ice_txq_vec_setup(txq)) {
3496                                                 ad->tx_vec_allowed = false;
3497                                                 break;
3498                                         }
3499                                 }
3500                         }
3501                 } else {
3502                         ad->tx_vec_allowed = false;
3503                 }
3504         }
3505
3506         if (ad->tx_vec_allowed) {
3507                 dev->tx_pkt_prepare = NULL;
3508                 if (ad->tx_use_avx512) {
3509 #ifdef CC_AVX512_SUPPORT
3510                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3511                                 PMD_DRV_LOG(NOTICE,
3512                                             "Using AVX512 OFFLOAD Vector Tx (port %d).",
3513                                             dev->data->port_id);
3514                                 dev->tx_pkt_burst =
3515                                         ice_xmit_pkts_vec_avx512_offload;
3516                                 dev->tx_pkt_prepare = ice_prep_pkts;
3517                         } else {
3518                                 PMD_DRV_LOG(NOTICE,
3519                                             "Using AVX512 Vector Tx (port %d).",
3520                                             dev->data->port_id);
3521                                 dev->tx_pkt_burst = ice_xmit_pkts_vec_avx512;
3522                         }
3523 #endif
3524                 } else {
3525                         if (tx_check_ret == ICE_VECTOR_OFFLOAD_PATH) {
3526                                 PMD_DRV_LOG(NOTICE,
3527                                             "Using AVX2 OFFLOAD Vector Tx (port %d).",
3528                                             dev->data->port_id);
3529                                 dev->tx_pkt_burst =
3530                                         ice_xmit_pkts_vec_avx2_offload;
3531                                 dev->tx_pkt_prepare = ice_prep_pkts;
3532                         } else {
3533                                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
3534                                             ad->tx_use_avx2 ? "avx2 " : "",
3535                                             dev->data->port_id);
3536                                 dev->tx_pkt_burst = ad->tx_use_avx2 ?
3537                                                     ice_xmit_pkts_vec_avx2 :
3538                                                     ice_xmit_pkts_vec;
3539                         }
3540                 }
3541
3542                 return;
3543         }
3544 #endif
3545
3546         if (ad->tx_simple_allowed) {
3547                 PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3548                 dev->tx_pkt_burst = ice_xmit_pkts_simple;
3549                 dev->tx_pkt_prepare = NULL;
3550         } else {
3551                 PMD_INIT_LOG(DEBUG, "Normal tx finally be used.");
3552                 dev->tx_pkt_burst = ice_xmit_pkts;
3553                 dev->tx_pkt_prepare = ice_prep_pkts;
3554         }
3555 }
3556
3557 static const struct {
3558         eth_tx_burst_t pkt_burst;
3559         const char *info;
3560 } ice_tx_burst_infos[] = {
3561         { ice_xmit_pkts_simple,   "Scalar Simple" },
3562         { ice_xmit_pkts,          "Scalar" },
3563 #ifdef RTE_ARCH_X86
3564 #ifdef CC_AVX512_SUPPORT
3565         { ice_xmit_pkts_vec_avx512, "Vector AVX512" },
3566         { ice_xmit_pkts_vec_avx512_offload, "Offload Vector AVX512" },
3567 #endif
3568         { ice_xmit_pkts_vec_avx2, "Vector AVX2" },
3569         { ice_xmit_pkts_vec,      "Vector SSE" },
3570 #endif
3571 };
3572
3573 int
3574 ice_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id,
3575                       struct rte_eth_burst_mode *mode)
3576 {
3577         eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
3578         int ret = -EINVAL;
3579         unsigned int i;
3580
3581         for (i = 0; i < RTE_DIM(ice_tx_burst_infos); ++i) {
3582                 if (pkt_burst == ice_tx_burst_infos[i].pkt_burst) {
3583                         snprintf(mode->info, sizeof(mode->info), "%s",
3584                                  ice_tx_burst_infos[i].info);
3585                         ret = 0;
3586                         break;
3587                 }
3588         }
3589
3590         return ret;
3591 }
3592
3593 /* For each value it means, datasheet of hardware can tell more details
3594  *
3595  * @note: fix ice_dev_supported_ptypes_get() if any change here.
3596  */
3597 static inline uint32_t
3598 ice_get_default_pkt_type(uint16_t ptype)
3599 {
3600         static const uint32_t type_table[ICE_MAX_PKT_TYPE]
3601                 __rte_cache_aligned = {
3602                 /* L2 types */
3603                 /* [0] reserved */
3604                 [1] = RTE_PTYPE_L2_ETHER,
3605                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
3606                 /* [3] - [5] reserved */
3607                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
3608                 /* [7] - [10] reserved */
3609                 [11] = RTE_PTYPE_L2_ETHER_ARP,
3610                 /* [12] - [21] reserved */
3611
3612                 /* Non tunneled IPv4 */
3613                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3614                        RTE_PTYPE_L4_FRAG,
3615                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3616                        RTE_PTYPE_L4_NONFRAG,
3617                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3618                        RTE_PTYPE_L4_UDP,
3619                 /* [25] reserved */
3620                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3621                        RTE_PTYPE_L4_TCP,
3622                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3623                        RTE_PTYPE_L4_SCTP,
3624                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3625                        RTE_PTYPE_L4_ICMP,
3626
3627                 /* IPv4 --> IPv4 */
3628                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3629                        RTE_PTYPE_TUNNEL_IP |
3630                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3631                        RTE_PTYPE_INNER_L4_FRAG,
3632                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3633                        RTE_PTYPE_TUNNEL_IP |
3634                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3635                        RTE_PTYPE_INNER_L4_NONFRAG,
3636                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3637                        RTE_PTYPE_TUNNEL_IP |
3638                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3639                        RTE_PTYPE_INNER_L4_UDP,
3640                 /* [32] reserved */
3641                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3642                        RTE_PTYPE_TUNNEL_IP |
3643                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3644                        RTE_PTYPE_INNER_L4_TCP,
3645                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3646                        RTE_PTYPE_TUNNEL_IP |
3647                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3648                        RTE_PTYPE_INNER_L4_SCTP,
3649                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3650                        RTE_PTYPE_TUNNEL_IP |
3651                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3652                        RTE_PTYPE_INNER_L4_ICMP,
3653
3654                 /* IPv4 --> IPv6 */
3655                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3656                        RTE_PTYPE_TUNNEL_IP |
3657                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3658                        RTE_PTYPE_INNER_L4_FRAG,
3659                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3660                        RTE_PTYPE_TUNNEL_IP |
3661                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3662                        RTE_PTYPE_INNER_L4_NONFRAG,
3663                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3664                        RTE_PTYPE_TUNNEL_IP |
3665                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3666                        RTE_PTYPE_INNER_L4_UDP,
3667                 /* [39] reserved */
3668                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3669                        RTE_PTYPE_TUNNEL_IP |
3670                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3671                        RTE_PTYPE_INNER_L4_TCP,
3672                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3673                        RTE_PTYPE_TUNNEL_IP |
3674                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3675                        RTE_PTYPE_INNER_L4_SCTP,
3676                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3677                        RTE_PTYPE_TUNNEL_IP |
3678                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3679                        RTE_PTYPE_INNER_L4_ICMP,
3680
3681                 /* IPv4 --> GRE/Teredo/VXLAN */
3682                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3683                        RTE_PTYPE_TUNNEL_GRENAT,
3684
3685                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
3686                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3687                        RTE_PTYPE_TUNNEL_GRENAT |
3688                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3689                        RTE_PTYPE_INNER_L4_FRAG,
3690                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3691                        RTE_PTYPE_TUNNEL_GRENAT |
3692                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3693                        RTE_PTYPE_INNER_L4_NONFRAG,
3694                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3695                        RTE_PTYPE_TUNNEL_GRENAT |
3696                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3697                        RTE_PTYPE_INNER_L4_UDP,
3698                 /* [47] reserved */
3699                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3700                        RTE_PTYPE_TUNNEL_GRENAT |
3701                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3702                        RTE_PTYPE_INNER_L4_TCP,
3703                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3704                        RTE_PTYPE_TUNNEL_GRENAT |
3705                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3706                        RTE_PTYPE_INNER_L4_SCTP,
3707                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3708                        RTE_PTYPE_TUNNEL_GRENAT |
3709                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3710                        RTE_PTYPE_INNER_L4_ICMP,
3711
3712                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
3713                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3714                        RTE_PTYPE_TUNNEL_GRENAT |
3715                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3716                        RTE_PTYPE_INNER_L4_FRAG,
3717                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3718                        RTE_PTYPE_TUNNEL_GRENAT |
3719                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3720                        RTE_PTYPE_INNER_L4_NONFRAG,
3721                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3722                        RTE_PTYPE_TUNNEL_GRENAT |
3723                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3724                        RTE_PTYPE_INNER_L4_UDP,
3725                 /* [54] reserved */
3726                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3727                        RTE_PTYPE_TUNNEL_GRENAT |
3728                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3729                        RTE_PTYPE_INNER_L4_TCP,
3730                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3731                        RTE_PTYPE_TUNNEL_GRENAT |
3732                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3733                        RTE_PTYPE_INNER_L4_SCTP,
3734                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3735                        RTE_PTYPE_TUNNEL_GRENAT |
3736                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3737                        RTE_PTYPE_INNER_L4_ICMP,
3738
3739                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
3740                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3741                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3742
3743                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3744                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3745                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3746                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3747                        RTE_PTYPE_INNER_L4_FRAG,
3748                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3749                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3750                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3751                        RTE_PTYPE_INNER_L4_NONFRAG,
3752                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3753                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3754                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3755                        RTE_PTYPE_INNER_L4_UDP,
3756                 /* [62] reserved */
3757                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3758                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3759                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3760                        RTE_PTYPE_INNER_L4_TCP,
3761                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3762                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3763                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3764                        RTE_PTYPE_INNER_L4_SCTP,
3765                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3766                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3767                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3768                        RTE_PTYPE_INNER_L4_ICMP,
3769
3770                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3771                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3772                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3773                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3774                        RTE_PTYPE_INNER_L4_FRAG,
3775                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3776                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3777                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3778                        RTE_PTYPE_INNER_L4_NONFRAG,
3779                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3780                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3781                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3782                        RTE_PTYPE_INNER_L4_UDP,
3783                 /* [69] reserved */
3784                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3785                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3786                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3787                        RTE_PTYPE_INNER_L4_TCP,
3788                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3789                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3790                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3791                        RTE_PTYPE_INNER_L4_SCTP,
3792                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3793                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3794                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3795                        RTE_PTYPE_INNER_L4_ICMP,
3796                 /* [73] - [87] reserved */
3797
3798                 /* Non tunneled IPv6 */
3799                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3800                        RTE_PTYPE_L4_FRAG,
3801                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3802                        RTE_PTYPE_L4_NONFRAG,
3803                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3804                        RTE_PTYPE_L4_UDP,
3805                 /* [91] reserved */
3806                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3807                        RTE_PTYPE_L4_TCP,
3808                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3809                        RTE_PTYPE_L4_SCTP,
3810                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3811                        RTE_PTYPE_L4_ICMP,
3812
3813                 /* IPv6 --> IPv4 */
3814                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3815                        RTE_PTYPE_TUNNEL_IP |
3816                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3817                        RTE_PTYPE_INNER_L4_FRAG,
3818                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3819                        RTE_PTYPE_TUNNEL_IP |
3820                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3821                        RTE_PTYPE_INNER_L4_NONFRAG,
3822                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3823                        RTE_PTYPE_TUNNEL_IP |
3824                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3825                        RTE_PTYPE_INNER_L4_UDP,
3826                 /* [98] reserved */
3827                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3828                        RTE_PTYPE_TUNNEL_IP |
3829                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3830                        RTE_PTYPE_INNER_L4_TCP,
3831                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3832                         RTE_PTYPE_TUNNEL_IP |
3833                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3834                         RTE_PTYPE_INNER_L4_SCTP,
3835                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3836                         RTE_PTYPE_TUNNEL_IP |
3837                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3838                         RTE_PTYPE_INNER_L4_ICMP,
3839
3840                 /* IPv6 --> IPv6 */
3841                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3842                         RTE_PTYPE_TUNNEL_IP |
3843                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3844                         RTE_PTYPE_INNER_L4_FRAG,
3845                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3846                         RTE_PTYPE_TUNNEL_IP |
3847                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3848                         RTE_PTYPE_INNER_L4_NONFRAG,
3849                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3850                         RTE_PTYPE_TUNNEL_IP |
3851                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3852                         RTE_PTYPE_INNER_L4_UDP,
3853                 /* [105] reserved */
3854                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3855                         RTE_PTYPE_TUNNEL_IP |
3856                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3857                         RTE_PTYPE_INNER_L4_TCP,
3858                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3859                         RTE_PTYPE_TUNNEL_IP |
3860                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3861                         RTE_PTYPE_INNER_L4_SCTP,
3862                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3863                         RTE_PTYPE_TUNNEL_IP |
3864                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3865                         RTE_PTYPE_INNER_L4_ICMP,
3866
3867                 /* IPv6 --> GRE/Teredo/VXLAN */
3868                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3869                         RTE_PTYPE_TUNNEL_GRENAT,
3870
3871                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
3872                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3873                         RTE_PTYPE_TUNNEL_GRENAT |
3874                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3875                         RTE_PTYPE_INNER_L4_FRAG,
3876                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3877                         RTE_PTYPE_TUNNEL_GRENAT |
3878                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3879                         RTE_PTYPE_INNER_L4_NONFRAG,
3880                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3881                         RTE_PTYPE_TUNNEL_GRENAT |
3882                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3883                         RTE_PTYPE_INNER_L4_UDP,
3884                 /* [113] reserved */
3885                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3886                         RTE_PTYPE_TUNNEL_GRENAT |
3887                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3888                         RTE_PTYPE_INNER_L4_TCP,
3889                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3890                         RTE_PTYPE_TUNNEL_GRENAT |
3891                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3892                         RTE_PTYPE_INNER_L4_SCTP,
3893                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3894                         RTE_PTYPE_TUNNEL_GRENAT |
3895                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3896                         RTE_PTYPE_INNER_L4_ICMP,
3897
3898                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
3899                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3900                         RTE_PTYPE_TUNNEL_GRENAT |
3901                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3902                         RTE_PTYPE_INNER_L4_FRAG,
3903                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3904                         RTE_PTYPE_TUNNEL_GRENAT |
3905                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3906                         RTE_PTYPE_INNER_L4_NONFRAG,
3907                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3908                         RTE_PTYPE_TUNNEL_GRENAT |
3909                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3910                         RTE_PTYPE_INNER_L4_UDP,
3911                 /* [120] reserved */
3912                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3913                         RTE_PTYPE_TUNNEL_GRENAT |
3914                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3915                         RTE_PTYPE_INNER_L4_TCP,
3916                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3917                         RTE_PTYPE_TUNNEL_GRENAT |
3918                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3919                         RTE_PTYPE_INNER_L4_SCTP,
3920                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3921                         RTE_PTYPE_TUNNEL_GRENAT |
3922                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3923                         RTE_PTYPE_INNER_L4_ICMP,
3924
3925                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
3926                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3927                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
3928
3929                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
3930                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3931                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3932                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3933                         RTE_PTYPE_INNER_L4_FRAG,
3934                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3935                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3936                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3937                         RTE_PTYPE_INNER_L4_NONFRAG,
3938                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3939                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3940                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3941                         RTE_PTYPE_INNER_L4_UDP,
3942                 /* [128] reserved */
3943                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3944                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3945                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3946                         RTE_PTYPE_INNER_L4_TCP,
3947                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3948                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3949                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3950                         RTE_PTYPE_INNER_L4_SCTP,
3951                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3952                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3953                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
3954                         RTE_PTYPE_INNER_L4_ICMP,
3955
3956                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
3957                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3958                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3959                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3960                         RTE_PTYPE_INNER_L4_FRAG,
3961                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3962                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3963                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3964                         RTE_PTYPE_INNER_L4_NONFRAG,
3965                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3966                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3967                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3968                         RTE_PTYPE_INNER_L4_UDP,
3969                 /* [135] reserved */
3970                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3971                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3972                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3973                         RTE_PTYPE_INNER_L4_TCP,
3974                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3975                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3976                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3977                         RTE_PTYPE_INNER_L4_SCTP,
3978                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
3979                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
3980                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
3981                         RTE_PTYPE_INNER_L4_ICMP,
3982                 /* [139] - [299] reserved */
3983
3984                 /* PPPoE */
3985                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
3986                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
3987
3988                 /* PPPoE --> IPv4 */
3989                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
3990                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3991                         RTE_PTYPE_L4_FRAG,
3992                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
3993                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3994                         RTE_PTYPE_L4_NONFRAG,
3995                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
3996                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
3997                         RTE_PTYPE_L4_UDP,
3998                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
3999                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4000                         RTE_PTYPE_L4_TCP,
4001                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
4002                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4003                         RTE_PTYPE_L4_SCTP,
4004                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
4005                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4006                         RTE_PTYPE_L4_ICMP,
4007
4008                 /* PPPoE --> IPv6 */
4009                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
4010                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4011                         RTE_PTYPE_L4_FRAG,
4012                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
4013                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4014                         RTE_PTYPE_L4_NONFRAG,
4015                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
4016                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4017                         RTE_PTYPE_L4_UDP,
4018                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
4019                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4020                         RTE_PTYPE_L4_TCP,
4021                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
4022                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4023                         RTE_PTYPE_L4_SCTP,
4024                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
4025                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4026                         RTE_PTYPE_L4_ICMP,
4027                 /* [314] - [324] reserved */
4028
4029                 /* IPv4/IPv6 --> GTPC/GTPU */
4030                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4031                         RTE_PTYPE_TUNNEL_GTPC,
4032                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4033                         RTE_PTYPE_TUNNEL_GTPC,
4034                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4035                         RTE_PTYPE_TUNNEL_GTPC,
4036                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4037                         RTE_PTYPE_TUNNEL_GTPC,
4038                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4039                         RTE_PTYPE_TUNNEL_GTPU,
4040                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4041                         RTE_PTYPE_TUNNEL_GTPU,
4042
4043                 /* IPv4 --> GTPU --> IPv4 */
4044                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4045                         RTE_PTYPE_TUNNEL_GTPU |
4046                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4047                         RTE_PTYPE_INNER_L4_FRAG,
4048                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4049                         RTE_PTYPE_TUNNEL_GTPU |
4050                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4051                         RTE_PTYPE_INNER_L4_NONFRAG,
4052                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4053                         RTE_PTYPE_TUNNEL_GTPU |
4054                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4055                         RTE_PTYPE_INNER_L4_UDP,
4056                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4057                         RTE_PTYPE_TUNNEL_GTPU |
4058                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4059                         RTE_PTYPE_INNER_L4_TCP,
4060                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4061                         RTE_PTYPE_TUNNEL_GTPU |
4062                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4063                         RTE_PTYPE_INNER_L4_ICMP,
4064
4065                 /* IPv6 --> GTPU --> IPv4 */
4066                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4067                         RTE_PTYPE_TUNNEL_GTPU |
4068                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4069                         RTE_PTYPE_INNER_L4_FRAG,
4070                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4071                         RTE_PTYPE_TUNNEL_GTPU |
4072                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4073                         RTE_PTYPE_INNER_L4_NONFRAG,
4074                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4075                         RTE_PTYPE_TUNNEL_GTPU |
4076                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4077                         RTE_PTYPE_INNER_L4_UDP,
4078                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4079                         RTE_PTYPE_TUNNEL_GTPU |
4080                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4081                         RTE_PTYPE_INNER_L4_TCP,
4082                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4083                         RTE_PTYPE_TUNNEL_GTPU |
4084                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
4085                         RTE_PTYPE_INNER_L4_ICMP,
4086
4087                 /* IPv4 --> GTPU --> IPv6 */
4088                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4089                         RTE_PTYPE_TUNNEL_GTPU |
4090                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4091                         RTE_PTYPE_INNER_L4_FRAG,
4092                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4093                         RTE_PTYPE_TUNNEL_GTPU |
4094                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4095                         RTE_PTYPE_INNER_L4_NONFRAG,
4096                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4097                         RTE_PTYPE_TUNNEL_GTPU |
4098                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4099                         RTE_PTYPE_INNER_L4_UDP,
4100                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4101                         RTE_PTYPE_TUNNEL_GTPU |
4102                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4103                         RTE_PTYPE_INNER_L4_TCP,
4104                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4105                         RTE_PTYPE_TUNNEL_GTPU |
4106                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4107                         RTE_PTYPE_INNER_L4_ICMP,
4108
4109                 /* IPv6 --> GTPU --> IPv6 */
4110                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4111                         RTE_PTYPE_TUNNEL_GTPU |
4112                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4113                         RTE_PTYPE_INNER_L4_FRAG,
4114                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4115                         RTE_PTYPE_TUNNEL_GTPU |
4116                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4117                         RTE_PTYPE_INNER_L4_NONFRAG,
4118                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4119                         RTE_PTYPE_TUNNEL_GTPU |
4120                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4121                         RTE_PTYPE_INNER_L4_UDP,
4122                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4123                         RTE_PTYPE_TUNNEL_GTPU |
4124                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4125                         RTE_PTYPE_INNER_L4_TCP,
4126                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4127                         RTE_PTYPE_TUNNEL_GTPU |
4128                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
4129                         RTE_PTYPE_INNER_L4_ICMP,
4130
4131                 /* IPv4 --> UDP ECPRI */
4132                 [372] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4133                         RTE_PTYPE_L4_UDP,
4134                 [373] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4135                         RTE_PTYPE_L4_UDP,
4136                 [374] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4137                         RTE_PTYPE_L4_UDP,
4138                 [375] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4139                         RTE_PTYPE_L4_UDP,
4140                 [376] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4141                         RTE_PTYPE_L4_UDP,
4142                 [377] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4143                         RTE_PTYPE_L4_UDP,
4144                 [378] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4145                         RTE_PTYPE_L4_UDP,
4146                 [379] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4147                         RTE_PTYPE_L4_UDP,
4148                 [380] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4149                         RTE_PTYPE_L4_UDP,
4150                 [381] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
4151                         RTE_PTYPE_L4_UDP,
4152
4153                 /* IPV6 --> UDP ECPRI */
4154                 [382] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4155                         RTE_PTYPE_L4_UDP,
4156                 [383] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4157                         RTE_PTYPE_L4_UDP,
4158                 [384] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4159                         RTE_PTYPE_L4_UDP,
4160                 [385] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4161                         RTE_PTYPE_L4_UDP,
4162                 [386] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4163                         RTE_PTYPE_L4_UDP,
4164                 [387] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4165                         RTE_PTYPE_L4_UDP,
4166                 [388] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4167                         RTE_PTYPE_L4_UDP,
4168                 [389] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4169                         RTE_PTYPE_L4_UDP,
4170                 [390] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4171                         RTE_PTYPE_L4_UDP,
4172                 [391] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
4173                         RTE_PTYPE_L4_UDP,
4174                 /* All others reserved */
4175         };
4176
4177         return type_table[ptype];
4178 }
4179
4180 void __rte_cold
4181 ice_set_default_ptype_table(struct rte_eth_dev *dev)
4182 {
4183         struct ice_adapter *ad =
4184                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
4185         int i;
4186
4187         for (i = 0; i < ICE_MAX_PKT_TYPE; i++)
4188                 ad->ptype_tbl[i] = ice_get_default_pkt_type(i);
4189 }
4190
4191 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S 1
4192 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M \
4193                         (0x3UL << ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S)
4194 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD 0
4195 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL 0x1
4196
4197 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S   4
4198 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M   \
4199         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S)
4200 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S      5
4201 #define ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M      \
4202         (1 << ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S)
4203
4204 /*
4205  * check the programming status descriptor in rx queue.
4206  * done after Programming Flow Director is programmed on
4207  * tx queue
4208  */
4209 static inline int
4210 ice_check_fdir_programming_status(struct ice_rx_queue *rxq)
4211 {
4212         volatile union ice_32byte_rx_desc *rxdp;
4213         uint64_t qword1;
4214         uint32_t rx_status;
4215         uint32_t error;
4216         uint32_t id;
4217         int ret = -EAGAIN;
4218
4219         rxdp = (volatile union ice_32byte_rx_desc *)
4220                 (&rxq->rx_ring[rxq->rx_tail]);
4221         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
4222         rx_status = (qword1 & ICE_RXD_QW1_STATUS_M)
4223                         >> ICE_RXD_QW1_STATUS_S;
4224
4225         if (rx_status & (1 << ICE_RX_DESC_STATUS_DD_S)) {
4226                 ret = 0;
4227                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_M) >>
4228                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_S;
4229                 id = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_M) >>
4230                         ICE_RX_PROG_STATUS_DESC_WB_QW1_PROGID_S;
4231                 if (error) {
4232                         if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_ADD)
4233                                 PMD_DRV_LOG(ERR, "Failed to add FDIR rule.");
4234                         else if (id == ICE_RX_PROG_STATUS_DESC_WB_QW1_PROG_DEL)
4235                                 PMD_DRV_LOG(ERR, "Failed to remove FDIR rule.");
4236                         ret = -EINVAL;
4237                         goto err;
4238                 }
4239                 error = (qword1 & ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_M) >>
4240                         ICE_RX_PROG_STATUS_DESC_WB_QW1_FAIL_PROF_S;
4241                 if (error) {
4242                         PMD_DRV_LOG(ERR, "Failed to create FDIR profile.");
4243                         ret = -EINVAL;
4244                 }
4245 err:
4246                 rxdp->wb.qword1.status_error_len = 0;
4247                 rxq->rx_tail++;
4248                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
4249                         rxq->rx_tail = 0;
4250                 if (rxq->rx_tail == 0)
4251                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
4252                 else
4253                         ICE_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
4254         }
4255
4256         return ret;
4257 }
4258
4259 #define ICE_FDIR_MAX_WAIT_US 10000
4260
4261 int
4262 ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc)
4263 {
4264         struct ice_tx_queue *txq = pf->fdir.txq;
4265         struct ice_rx_queue *rxq = pf->fdir.rxq;
4266         volatile struct ice_fltr_desc *fdirdp;
4267         volatile struct ice_tx_desc *txdp;
4268         uint32_t td_cmd;
4269         uint16_t i;
4270
4271         fdirdp = (volatile struct ice_fltr_desc *)
4272                 (&txq->tx_ring[txq->tx_tail]);
4273         fdirdp->qidx_compq_space_stat = fdir_desc->qidx_compq_space_stat;
4274         fdirdp->dtype_cmd_vsi_fdid = fdir_desc->dtype_cmd_vsi_fdid;
4275
4276         txdp = &txq->tx_ring[txq->tx_tail + 1];
4277         txdp->buf_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
4278         td_cmd = ICE_TX_DESC_CMD_EOP |
4279                 ICE_TX_DESC_CMD_RS  |
4280                 ICE_TX_DESC_CMD_DUMMY;
4281
4282         txdp->cmd_type_offset_bsz =
4283                 ice_build_ctob(td_cmd, 0, ICE_FDIR_PKT_LEN, 0);
4284
4285         txq->tx_tail += 2;
4286         if (txq->tx_tail >= txq->nb_tx_desc)
4287                 txq->tx_tail = 0;
4288         /* Update the tx tail register */
4289         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
4290         for (i = 0; i < ICE_FDIR_MAX_WAIT_US; i++) {
4291                 if ((txdp->cmd_type_offset_bsz &
4292                      rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) ==
4293                     rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
4294                         break;
4295                 rte_delay_us(1);
4296         }
4297         if (i >= ICE_FDIR_MAX_WAIT_US) {
4298                 PMD_DRV_LOG(ERR,
4299                             "Failed to program FDIR filter: time out to get DD on tx queue.");
4300                 return -ETIMEDOUT;
4301         }
4302
4303         for (; i < ICE_FDIR_MAX_WAIT_US; i++) {
4304                 int ret;
4305
4306                 ret = ice_check_fdir_programming_status(rxq);
4307                 if (ret == -EAGAIN)
4308                         rte_delay_us(1);
4309                 else
4310                         return ret;
4311         }
4312
4313         PMD_DRV_LOG(ERR,
4314                     "Failed to program FDIR filter: programming status reported.");
4315         return -ETIMEDOUT;
4316
4317
4318 }