1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
8 #include "ice_ethdev.h"
10 #define ICE_ALIGN_RING_DESC 32
11 #define ICE_MIN_RING_DESC 64
12 #define ICE_MAX_RING_DESC 4096
13 #define ICE_DMA_MEM_ALIGN 4096
14 #define ICE_RING_BASE_ALIGN 128
16 #define ICE_RX_MAX_BURST 32
17 #define ICE_TX_MAX_BURST 32
19 #define ICE_CHK_Q_ENA_COUNT 100
20 #define ICE_CHK_Q_ENA_INTERVAL_US 100
22 #ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC
23 #define ice_rx_flex_desc ice_16b_rx_flex_desc
25 #define ice_rx_flex_desc ice_32b_rx_flex_desc
28 #define ICE_SUPPORT_CHAIN_NUM 5
30 #define ICE_TD_CMD ICE_TX_DESC_CMD_EOP
32 #define ICE_VPMD_RX_BURST 32
33 #define ICE_VPMD_TX_BURST 32
34 #define ICE_RXQ_REARM_THRESH 64
35 #define ICE_MAX_RX_BURST ICE_RXQ_REARM_THRESH
36 #define ICE_TX_MAX_FREE_BUF_SZ 64
37 #define ICE_DESCS_PER_LOOP 4
39 #define ICE_FDIR_PKT_LEN 512
41 #define ICE_RXDID_COMMS_OVS 22
43 typedef void (*ice_rx_release_mbufs_t)(struct ice_rx_queue *rxq);
44 typedef void (*ice_tx_release_mbufs_t)(struct ice_tx_queue *txq);
45 typedef void (*ice_rxd_to_pkt_fields_t)(struct ice_rx_queue *rxq,
47 volatile union ice_rx_flex_desc *rxdp);
50 struct rte_mbuf *mbuf;
54 struct rte_mempool *mp; /* mbuf pool to populate RX ring */
55 volatile union ice_rx_flex_desc *rx_ring;/* RX ring virtual address */
56 rte_iova_t rx_ring_dma; /* RX ring DMA address */
57 struct ice_rx_entry *sw_ring; /* address of RX soft ring */
58 uint16_t nb_rx_desc; /* number of RX descriptors */
59 uint16_t rx_free_thresh; /* max free RX desc to hold */
60 uint16_t rx_tail; /* current value of tail */
61 uint16_t nb_rx_hold; /* number of held free RX desc */
62 struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */
63 struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */
64 uint16_t rx_nb_avail; /**< number of staged packets ready */
65 uint16_t rx_next_avail; /**< index of next staged packets */
66 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
67 struct rte_mbuf fake_mbuf; /**< dummy mbuf */
68 struct rte_mbuf *rx_stage[ICE_RX_MAX_BURST * 2];
70 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */
71 uint16_t rxrearm_start; /**< the idx we start the re-arming from */
72 uint64_t mbuf_initializer; /**< value to init mbufs */
74 uint16_t port_id; /* device port ID */
75 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
76 uint8_t fdir_enabled; /* 0 if FDIR disabled, 1 when enabled */
77 uint16_t queue_id; /* RX queue index */
78 uint16_t reg_idx; /* RX queue register index */
79 uint8_t drop_en; /* if not 0, set register bit */
80 volatile uint8_t *qrx_tail; /* register address of tail */
81 struct ice_vsi *vsi; /* the VSI this queue belongs to */
82 uint16_t rx_buf_len; /* The packet buffer size */
83 uint16_t rx_hdr_len; /* The header buffer size */
84 uint16_t max_pkt_len; /* Maximum packet length */
85 bool q_set; /* indicate if rx queue has been configured */
86 bool rx_deferred_start; /* don't start this queue in dev start */
87 uint8_t proto_xtr; /* Protocol extraction from flexible descriptor */
88 uint64_t xtr_ol_flag; /* Protocol extraction offload flag */
89 ice_rxd_to_pkt_fields_t rxd_to_pkt_fields; /* handle FlexiMD by RXDID */
90 ice_rx_release_mbufs_t rx_rel_mbufs;
95 struct rte_mbuf *mbuf;
100 struct ice_vec_tx_entry {
101 struct rte_mbuf *mbuf;
104 struct ice_tx_queue {
105 uint16_t nb_tx_desc; /* number of TX descriptors */
106 rte_iova_t tx_ring_dma; /* TX ring DMA address */
107 volatile struct ice_tx_desc *tx_ring; /* TX ring virtual address */
108 struct ice_tx_entry *sw_ring; /* virtual address of SW ring */
109 uint16_t tx_tail; /* current value of tail register */
110 volatile uint8_t *qtx_tail; /* register address of tail */
111 uint16_t nb_tx_used; /* number of TX desc used since RS bit set */
112 /* index to last TX descriptor to have been cleaned */
113 uint16_t last_desc_cleaned;
114 /* Total number of TX descriptors ready to be allocated. */
116 /* Start freeing TX buffers if there are less free descriptors than
119 uint16_t tx_free_thresh;
120 /* Number of TX descriptors to use before RS bit is set. */
121 uint16_t tx_rs_thresh;
122 uint8_t pthresh; /**< Prefetch threshold register. */
123 uint8_t hthresh; /**< Host threshold register. */
124 uint8_t wthresh; /**< Write-back threshold reg. */
125 uint16_t port_id; /* Device port identifier. */
126 uint16_t queue_id; /* TX queue index. */
127 uint32_t q_teid; /* TX schedule node id. */
130 struct ice_vsi *vsi; /* the VSI this queue belongs to */
133 bool tx_deferred_start; /* don't start this queue in dev start */
134 bool q_set; /* indicate if tx queue has been configured */
135 ice_tx_release_mbufs_t tx_rel_mbufs;
138 /* Offload features */
139 union ice_tx_offload {
142 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
143 uint64_t l3_len:9; /* L3 (IP) Header Length. */
144 uint64_t l4_len:8; /* L4 Header Length. */
145 uint64_t tso_segsz:16; /* TCP TSO segment size */
146 uint64_t outer_l2_len:8; /* outer L2 Header Length */
147 uint64_t outer_l3_len:16; /* outer L3 Header Length */
151 /* Rx Flex Descriptor for Comms Package Profile
152 * RxDID Profile ID 22 (swap Hash and FlowID)
153 * Flex-field 0: Flow ID lower 16-bits
154 * Flex-field 1: Flow ID upper 16-bits
155 * Flex-field 2: RSS hash lower 16-bits
156 * Flex-field 3: RSS hash upper 16-bits
160 struct ice_32b_rx_flex_desc_comms_ovs {
164 __le16 ptype_flexi_flags0;
166 __le16 hdr_len_sph_flex_flags1;
169 __le16 status_error0;
174 __le16 status_error1;
191 int ice_rx_queue_setup(struct rte_eth_dev *dev,
194 unsigned int socket_id,
195 const struct rte_eth_rxconf *rx_conf,
196 struct rte_mempool *mp);
197 int ice_tx_queue_setup(struct rte_eth_dev *dev,
200 unsigned int socket_id,
201 const struct rte_eth_txconf *tx_conf);
202 int ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
203 int ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
204 int ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
205 int ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
206 int ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
207 int ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
208 int ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
209 int ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
210 void ice_rx_queue_release(void *rxq);
211 void ice_tx_queue_release(void *txq);
212 void ice_free_queues(struct rte_eth_dev *dev);
213 int ice_fdir_setup_tx_resources(struct ice_pf *pf);
214 int ice_fdir_setup_rx_resources(struct ice_pf *pf);
215 uint16_t ice_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
217 uint16_t ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
219 void ice_set_rx_function(struct rte_eth_dev *dev);
220 uint16_t ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
222 void ice_set_tx_function_flag(struct rte_eth_dev *dev,
223 struct ice_tx_queue *txq);
224 void ice_set_tx_function(struct rte_eth_dev *dev);
225 uint32_t ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
226 void ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
227 struct rte_eth_rxq_info *qinfo);
228 void ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
229 struct rte_eth_txq_info *qinfo);
230 int ice_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
231 struct rte_eth_burst_mode *mode);
232 int ice_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
233 struct rte_eth_burst_mode *mode);
234 int ice_rx_descriptor_status(void *rx_queue, uint16_t offset);
235 int ice_tx_descriptor_status(void *tx_queue, uint16_t offset);
236 void ice_set_default_ptype_table(struct rte_eth_dev *dev);
237 const uint32_t *ice_dev_supported_ptypes_get(struct rte_eth_dev *dev);
238 void ice_select_rxd_to_pkt_fields_handler(struct ice_rx_queue *rxq,
241 int ice_rx_vec_dev_check(struct rte_eth_dev *dev);
242 int ice_tx_vec_dev_check(struct rte_eth_dev *dev);
243 int ice_rxq_vec_setup(struct ice_rx_queue *rxq);
244 int ice_txq_vec_setup(struct ice_tx_queue *txq);
245 uint16_t ice_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
247 uint16_t ice_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
249 uint16_t ice_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
251 uint16_t ice_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
253 uint16_t ice_recv_scattered_pkts_vec_avx2(void *rx_queue,
254 struct rte_mbuf **rx_pkts,
256 uint16_t ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
258 uint16_t ice_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
260 uint16_t ice_recv_pkts_vec_avx512_offload(void *rx_queue,
261 struct rte_mbuf **rx_pkts,
263 uint16_t ice_recv_scattered_pkts_vec_avx512(void *rx_queue,
264 struct rte_mbuf **rx_pkts,
266 uint16_t ice_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
267 struct rte_mbuf **rx_pkts,
269 uint16_t ice_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
271 uint16_t ice_xmit_pkts_vec_avx512_offload(void *tx_queue,
272 struct rte_mbuf **tx_pkts,
274 int ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc);
275 int ice_tx_done_cleanup(void *txq, uint32_t free_cnt);
276 int ice_get_monitor_addr(void *rx_queue, struct rte_power_monitor_cond *pmc);
278 #define FDIR_PARSING_ENABLE_PER_QUEUE(ad, on) do { \
280 for (i = 0; i < (ad)->pf.dev_data->nb_rx_queues; i++) { \
281 struct ice_rx_queue *rxq = (ad)->pf.dev_data->rx_queues[i]; \
284 rxq->fdir_enabled = on; \
286 PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
289 /* Enable/disable flow director parsing from Rx descriptor in data path. */
291 void ice_fdir_rx_parsing_enable(struct ice_adapter *ad, bool on)
294 /* Enable flow director parsing from Rx descriptor */
295 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on);
298 if (ad->fdir_ref_cnt >= 1) {
301 if (ad->fdir_ref_cnt == 0)
302 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on);
307 #endif /* _ICE_RXTX_H_ */