1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
8 #include "ice_ethdev.h"
10 #define ICE_ALIGN_RING_DESC 32
11 #define ICE_MIN_RING_DESC 64
12 #define ICE_MAX_RING_DESC 4096
13 #define ICE_DMA_MEM_ALIGN 4096
14 #define ICE_RING_BASE_ALIGN 128
16 #define ICE_RX_MAX_BURST 32
17 #define ICE_TX_MAX_BURST 32
19 #define ICE_CHK_Q_ENA_COUNT 100
20 #define ICE_CHK_Q_ENA_INTERVAL_US 100
22 #ifdef RTE_LIBRTE_ICE_16BYTE_RX_DESC
23 #define ice_rx_flex_desc ice_16b_rx_flex_desc
25 #define ice_rx_flex_desc ice_32b_rx_flex_desc
28 #define ICE_SUPPORT_CHAIN_NUM 5
30 #define ICE_TD_CMD ICE_TX_DESC_CMD_EOP
32 #define ICE_VPMD_RX_BURST 32
33 #define ICE_VPMD_TX_BURST 32
34 #define ICE_RXQ_REARM_THRESH 32
35 #define ICE_MAX_RX_BURST ICE_RXQ_REARM_THRESH
36 #define ICE_TX_MAX_FREE_BUF_SZ 64
37 #define ICE_DESCS_PER_LOOP 4
39 #define ICE_FDIR_PKT_LEN 512
41 #define ICE_RXDID_COMMS_OVS 22
43 typedef void (*ice_rx_release_mbufs_t)(struct ice_rx_queue *rxq);
44 typedef void (*ice_tx_release_mbufs_t)(struct ice_tx_queue *txq);
47 struct rte_mbuf *mbuf;
51 struct rte_mempool *mp; /* mbuf pool to populate RX ring */
52 volatile union ice_rx_flex_desc *rx_ring;/* RX ring virtual address */
53 rte_iova_t rx_ring_dma; /* RX ring DMA address */
54 struct ice_rx_entry *sw_ring; /* address of RX soft ring */
55 uint16_t nb_rx_desc; /* number of RX descriptors */
56 uint16_t rx_free_thresh; /* max free RX desc to hold */
57 uint16_t rx_tail; /* current value of tail */
58 uint16_t nb_rx_hold; /* number of held free RX desc */
59 struct rte_mbuf *pkt_first_seg; /**< first segment of current packet */
60 struct rte_mbuf *pkt_last_seg; /**< last segment of current packet */
61 uint16_t rx_nb_avail; /**< number of staged packets ready */
62 uint16_t rx_next_avail; /**< index of next staged packets */
63 uint16_t rx_free_trigger; /**< triggers rx buffer allocation */
64 struct rte_mbuf fake_mbuf; /**< dummy mbuf */
65 struct rte_mbuf *rx_stage[ICE_RX_MAX_BURST * 2];
67 uint16_t rxrearm_nb; /**< number of remaining to be re-armed */
68 uint16_t rxrearm_start; /**< the idx we start the re-arming from */
69 uint64_t mbuf_initializer; /**< value to init mbufs */
71 uint8_t port_id; /* device port ID */
72 uint8_t crc_len; /* 0 if CRC stripped, 4 otherwise */
73 uint8_t fdir_enabled; /* 0 if FDIR disabled, 1 when enabled */
74 uint16_t queue_id; /* RX queue index */
75 uint16_t reg_idx; /* RX queue register index */
76 uint8_t drop_en; /* if not 0, set register bit */
77 volatile uint8_t *qrx_tail; /* register address of tail */
78 struct ice_vsi *vsi; /* the VSI this queue belongs to */
79 uint16_t rx_buf_len; /* The packet buffer size */
80 uint16_t rx_hdr_len; /* The header buffer size */
81 uint16_t max_pkt_len; /* Maximum packet length */
82 bool q_set; /* indicate if rx queue has been configured */
83 bool rx_deferred_start; /* don't start this queue in dev start */
84 uint8_t proto_xtr; /* Protocol extraction from flexible descriptor */
85 ice_rx_release_mbufs_t rx_rel_mbufs;
89 struct rte_mbuf *mbuf;
95 uint16_t nb_tx_desc; /* number of TX descriptors */
96 rte_iova_t tx_ring_dma; /* TX ring DMA address */
97 volatile struct ice_tx_desc *tx_ring; /* TX ring virtual address */
98 struct ice_tx_entry *sw_ring; /* virtual address of SW ring */
99 uint16_t tx_tail; /* current value of tail register */
100 volatile uint8_t *qtx_tail; /* register address of tail */
101 uint16_t nb_tx_used; /* number of TX desc used since RS bit set */
102 /* index to last TX descriptor to have been cleaned */
103 uint16_t last_desc_cleaned;
104 /* Total number of TX descriptors ready to be allocated. */
106 /* Start freeing TX buffers if there are less free descriptors than
109 uint16_t tx_free_thresh;
110 /* Number of TX descriptors to use before RS bit is set. */
111 uint16_t tx_rs_thresh;
112 uint8_t pthresh; /**< Prefetch threshold register. */
113 uint8_t hthresh; /**< Host threshold register. */
114 uint8_t wthresh; /**< Write-back threshold reg. */
115 uint8_t port_id; /* Device port identifier. */
116 uint16_t queue_id; /* TX queue index. */
117 uint32_t q_teid; /* TX schedule node id. */
120 struct ice_vsi *vsi; /* the VSI this queue belongs to */
123 bool tx_deferred_start; /* don't start this queue in dev start */
124 bool q_set; /* indicate if tx queue has been configured */
125 ice_tx_release_mbufs_t tx_rel_mbufs;
128 /* Offload features */
129 union ice_tx_offload {
132 uint64_t l2_len:7; /* L2 (MAC) Header Length. */
133 uint64_t l3_len:9; /* L3 (IP) Header Length. */
134 uint64_t l4_len:8; /* L4 Header Length. */
135 uint64_t tso_segsz:16; /* TCP TSO segment size */
136 uint64_t outer_l2_len:8; /* outer L2 Header Length */
137 uint64_t outer_l3_len:16; /* outer L3 Header Length */
141 /* Rx Flex Descriptor for Comms Package Profile
142 * RxDID Profile ID 22 (swap Hash and FlowID)
143 * Flex-field 0: Flow ID lower 16-bits
144 * Flex-field 1: Flow ID upper 16-bits
145 * Flex-field 2: RSS hash lower 16-bits
146 * Flex-field 3: RSS hash upper 16-bits
150 struct ice_32b_rx_flex_desc_comms_ovs {
154 __le16 ptype_flexi_flags0;
156 __le16 hdr_len_sph_flex_flags1;
159 __le16 status_error0;
164 __le16 status_error1;
181 int ice_rx_queue_setup(struct rte_eth_dev *dev,
184 unsigned int socket_id,
185 const struct rte_eth_rxconf *rx_conf,
186 struct rte_mempool *mp);
187 int ice_tx_queue_setup(struct rte_eth_dev *dev,
190 unsigned int socket_id,
191 const struct rte_eth_txconf *tx_conf);
192 int ice_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
193 int ice_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
194 int ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
195 int ice_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
196 int ice_fdir_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
197 int ice_fdir_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
198 int ice_fdir_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
199 int ice_fdir_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
200 void ice_rx_queue_release(void *rxq);
201 void ice_tx_queue_release(void *txq);
202 void ice_free_queues(struct rte_eth_dev *dev);
203 int ice_fdir_setup_tx_resources(struct ice_pf *pf);
204 int ice_fdir_setup_rx_resources(struct ice_pf *pf);
205 uint16_t ice_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
207 uint16_t ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
209 void ice_set_rx_function(struct rte_eth_dev *dev);
210 uint16_t ice_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
212 void ice_set_tx_function_flag(struct rte_eth_dev *dev,
213 struct ice_tx_queue *txq);
214 void ice_set_tx_function(struct rte_eth_dev *dev);
215 uint32_t ice_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
216 void ice_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
217 struct rte_eth_rxq_info *qinfo);
218 void ice_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
219 struct rte_eth_txq_info *qinfo);
220 int ice_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
221 struct rte_eth_burst_mode *mode);
222 int ice_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,
223 struct rte_eth_burst_mode *mode);
224 int ice_rx_descriptor_status(void *rx_queue, uint16_t offset);
225 int ice_tx_descriptor_status(void *tx_queue, uint16_t offset);
226 void ice_set_default_ptype_table(struct rte_eth_dev *dev);
227 const uint32_t *ice_dev_supported_ptypes_get(struct rte_eth_dev *dev);
229 int ice_rx_vec_dev_check(struct rte_eth_dev *dev);
230 int ice_tx_vec_dev_check(struct rte_eth_dev *dev);
231 int ice_rxq_vec_setup(struct ice_rx_queue *rxq);
232 int ice_txq_vec_setup(struct ice_tx_queue *txq);
233 uint16_t ice_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
235 uint16_t ice_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
237 uint16_t ice_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
239 uint16_t ice_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
241 uint16_t ice_recv_scattered_pkts_vec_avx2(void *rx_queue,
242 struct rte_mbuf **rx_pkts,
244 uint16_t ice_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
246 int ice_fdir_programming(struct ice_pf *pf, struct ice_fltr_desc *fdir_desc);
247 int ice_tx_done_cleanup(void *txq, uint32_t free_cnt);
249 #define FDIR_PARSING_ENABLE_PER_QUEUE(ad, on) do { \
251 for (i = 0; i < (ad)->eth_dev->data->nb_rx_queues; i++) { \
252 struct ice_rx_queue *rxq = (ad)->eth_dev->data->rx_queues[i]; \
255 rxq->fdir_enabled = on; \
257 PMD_DRV_LOG(DEBUG, "FDIR processing on RX set to %d", on); \
260 /* Enable/disable flow director parsing from Rx descriptor in data path. */
262 void ice_fdir_rx_parsing_enable(struct ice_adapter *ad, bool on)
265 /* Enable flow director parsing from Rx descriptor */
266 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on);
269 if (ad->fdir_ref_cnt >= 1) {
272 if (ad->fdir_ref_cnt == 0)
273 FDIR_PARSING_ENABLE_PER_QUEUE(ad, on);
278 #endif /* _ICE_RXTX_H_ */