drivers/net/ice/ice_rxtx_vec_avx512.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #include "ice_rxtx_vec_common.h"
   6
   7 #include <rte_vect.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 #define ICE_DESCS_PER_LOOP_AVX 8
  14
  15 static __rte_always_inline void
  16 ice_rxq_rearm(struct ice_rx_queue *rxq)
  17 {
  18         int i;
  19         uint16_t rx_id;
  20         volatile union ice_rx_flex_desc *rxdp;
  21         struct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  22         struct rte_mempool_cache *cache = rte_mempool_default_cache(rxq->mp,
  23                         rte_lcore_id());
  24
  25         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  26
  27         if (unlikely(!cache))
  28                 return ice_rxq_rearm_common(rxq, true);
  29
  30         /* We need to pull 'n' more MBUFs into the software ring */
  31         if (cache->len < ICE_RXQ_REARM_THRESH) {
  32                 uint32_t req = ICE_RXQ_REARM_THRESH + (cache->size -
  33                                 cache->len);
  34
  35                 int ret = rte_mempool_ops_dequeue_bulk(rxq->mp,
  36                                 &cache->objs[cache->len], req);
  37                 if (ret == 0) {
  38                         cache->len += req;
  39                 } else {
  40                         if (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=
  41                             rxq->nb_rx_desc) {
  42                                 __m128i dma_addr0;
  43
  44                                 dma_addr0 = _mm_setzero_si128();
  45                                 for (i = 0; i < ICE_DESCS_PER_LOOP; i++) {
  46                                         rxep[i].mbuf = &rxq->fake_mbuf;
  47                                         _mm_store_si128
  48                                                 ((__m128i *)&rxdp[i].read,
  49                                                         dma_addr0);
  50                                 }
  51                         }
  52                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  53                                 ICE_RXQ_REARM_THRESH;
  54                         return;
  55                 }
  56         }
  57
  58         const __m512i iova_offsets =  _mm512_set1_epi64
  59                 (offsetof(struct rte_mbuf, buf_iova));
  60         const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
  61
  62 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  63         /* shuffle the iova into correct slots. Values 4-7 will contain
  64          * zeros, so use 7 for a zero-value.
  65          */
  66         const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
  67 #else
  68         const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
  69 #endif
  70
  71         /* fill up the rxd in vector, process 8 mbufs in one loop */
  72         for (i = 0; i < ICE_RXQ_REARM_THRESH / 8; i++) {
  73                 const __m512i mbuf_ptrs = _mm512_loadu_si512
  74                         (&cache->objs[cache->len - 8]);
  75                 _mm512_store_si512(rxep, mbuf_ptrs);
  76
  77                 /* gather iova of mbuf0-7 into one zmm reg */
  78                 const __m512i iova_base_addrs = _mm512_i64gather_epi64
  79                         (_mm512_add_epi64(mbuf_ptrs, iova_offsets),
  80                                 0, /* base */
  81                                 1  /* scale */);
  82                 const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
  83                                 headroom);
  84 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
  85                 const __m512i iovas0 = _mm512_castsi256_si512
  86                         (_mm512_extracti64x4_epi64(iova_addrs, 0));
  87                 const __m512i iovas1 = _mm512_castsi256_si512
  88                         (_mm512_extracti64x4_epi64(iova_addrs, 1));
  89
  90                 /* permute leaves iova 2-3 in hdr_addr of desc 0-1
  91                  * but these are ignored by driver since header split not
  92                  * enabled. Similarly for desc 4 & 5.
  93                  */
  94                 const __m512i desc0_1 = _mm512_permutexvar_epi64
  95                         (permute_idx, iovas0);
  96                 const __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);
  97
  98                 const __m512i desc4_5 = _mm512_permutexvar_epi64
  99                         (permute_idx, iovas1);
 100                 const __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);
 101
 102                 _mm512_store_si512((void *)rxdp, desc0_1);
 103                 _mm512_store_si512((void *)(rxdp + 2), desc2_3);
 104                 _mm512_store_si512((void *)(rxdp + 4), desc4_5);
 105                 _mm512_store_si512((void *)(rxdp + 6), desc6_7);
 106 #else
 107                 /* permute leaves iova 4-7 in hdr_addr of desc 0-3
 108                  * but these are ignored by driver since header split not
 109                  * enabled.
 110                  */
 111                 const __m512i desc0_3 = _mm512_permutexvar_epi64
 112                         (permute_idx, iova_addrs);
 113                 const __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);
 114
 115                 _mm512_store_si512((void *)rxdp, desc0_3);
 116                 _mm512_store_si512((void *)(rxdp + 4), desc4_7);
 117 #endif
 118                 rxep += 8, rxdp += 8, cache->len -= 8;
 119         }
 120
 121         rxq->rxrearm_start += ICE_RXQ_REARM_THRESH;
 122         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 123                 rxq->rxrearm_start = 0;
 124
 125         rxq->rxrearm_nb -= ICE_RXQ_REARM_THRESH;
 126
 127         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 128                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 129
 130         /* Update the tail pointer on the NIC */
 131         ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 132 }
 133
 134 static inline __m256i
 135 ice_flex_rxd_to_fdir_flags_vec_avx512(const __m256i fdir_id0_7)
 136 {
 137 #define FDID_MIS_MAGIC 0xFFFFFFFF
 138         RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));
 139         RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
 140         const __m256i pkt_fdir_bit = _mm256_set1_epi32(PKT_RX_FDIR |
 141                         PKT_RX_FDIR_ID);
 142         /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
 143         const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);
 144         __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,
 145                         fdir_mis_mask);
 146         /* this XOR op results to bit-reverse the fdir_mask */
 147         fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);
 148         const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
 149
 150         return fdir_flags;
 151 }
 152
 153 static __rte_always_inline uint16_t
 154 _ice_recv_raw_pkts_vec_avx512(struct ice_rx_queue *rxq,
 155                               struct rte_mbuf **rx_pkts,
 156                               uint16_t nb_pkts,
 157                               uint8_t *split_packet,
 158                               bool do_offload)
 159 {
 160         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 161         const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
 162                         0, rxq->mbuf_initializer);
 163         struct ice_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail];
 164         volatile union ice_rx_flex_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 165
 166         rte_prefetch0(rxdp);
 167
 168         /* nb_pkts has to be floor-aligned to ICE_DESCS_PER_LOOP_AVX */
 169         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, ICE_DESCS_PER_LOOP_AVX);
 170
 171         /* See if we need to rearm the RX queue - gives the prefetch a bit
 172          * of time to act
 173          */
 174         if (rxq->rxrearm_nb > ICE_RXQ_REARM_THRESH)
 175                 ice_rxq_rearm(rxq);
 176
 177         /* Before we start moving massive data around, check to see if
 178          * there is actually a packet available
 179          */
 180         if (!(rxdp->wb.status_error0 &
 181                         rte_cpu_to_le_32(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
 182                 return 0;
 183
 184         /* constants used in processing loop */
 185         const __m512i crc_adjust =
 186                 _mm512_set4_epi32
 187                         (0,             /* ignore non-length fields */
 188                          -rxq->crc_len, /* sub crc on data_len */
 189                          -rxq->crc_len, /* sub crc on pkt_len */
 190                          0              /* ignore non-length fields */
 191                         );
 192
 193         /* 8 packets DD mask, LSB in each 32-bit value */
 194         const __m256i dd_check = _mm256_set1_epi32(1);
 195
 196         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 197         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 198                         ICE_RX_DESC_STATUS_EOF_S);
 199
 200         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 201         const __m512i shuf_msk =
 202                 _mm512_set4_epi32
 203                         (/* rss hash parsed separately */
 204                          0xFFFFFFFF,
 205                          /* octet 10~11, 16 bits vlan_macip */
 206                          /* octet 4~5, 16 bits data_len */
 207                          11 << 24 | 10 << 16 | 5 << 8 | 4,
 208                          /* skip hi 16 bits pkt_len, zero out */
 209                          /* octet 4~5, 16 bits pkt_len */
 210                          0xFFFF << 16 | 5 << 8 | 4,
 211                          /* pkt_type set as unknown */
 212                          0xFFFFFFFF
 213                         );
 214
 215         /**
 216          * compile-time check the above crc and shuffle layout is correct.
 217          * NOTE: the first field (lowest address) is given last in set_epi
 218          * calls above.
 219          */
 220         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 221                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 222         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 223                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 224         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 225                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 226         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 227                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 228
 229         /* following code block is for Rx Checksum Offload */
 230         /* Status/Error flag masks */
 231         /**
 232          * mask everything except Checksum Reports, RSS indication
 233          * and VLAN indication.
 234          * bit6:4 for IP/L4 checksum errors.
 235          * bit12 is for RSS indication.
 236          * bit13 is for VLAN indication.
 237          */
 238         const __m256i flags_mask =
 239                  _mm256_set1_epi32((0xF << 4) | (1 << 12) | (1 << 13));
 240         /**
 241          * data to be shuffled by the result of the flags mask shifted by 4
 242          * bits.  This gives use the l3_l4 flags.
 243          */
 244         const __m256i l3_l4_flags_shuf =
 245                 _mm256_set_epi8((PKT_RX_OUTER_L4_CKSUM_BAD >> 20 |
 246                  PKT_RX_OUTER_IP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 247                   PKT_RX_IP_CKSUM_BAD) >> 1,
 248                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 249                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 250                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 251                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 252                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 253                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 254                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_BAD  |
 255                  PKT_RX_IP_CKSUM_BAD) >> 1,
 256                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_BAD  |
 257                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 258                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 259                  PKT_RX_IP_CKSUM_BAD) >> 1,
 260                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 261                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 262                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 263                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 264                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 265                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 266                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 267                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 268                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 269                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 270                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_BAD |
 271                  PKT_RX_IP_CKSUM_BAD) >> 1,
 272                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_BAD |
 273                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 274                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 275                  PKT_RX_IP_CKSUM_BAD) >> 1,
 276                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 277                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 278                 /**
 279                  * second 128-bits
 280                  * shift right 20 bits to use the low two bits to indicate
 281                  * outer checksum status
 282                  * shift right 1 bit to make sure it not exceed 255
 283                  */
 284                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 285                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 286                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 287                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 288                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 289                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 290                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 291                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 292                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_BAD  |
 293                  PKT_RX_IP_CKSUM_BAD) >> 1,
 294                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_BAD  |
 295                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 296                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 297                  PKT_RX_IP_CKSUM_BAD) >> 1,
 298                 (PKT_RX_OUTER_L4_CKSUM_BAD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 299                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 300                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 301                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 302                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 303                  PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 304                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 305                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 306                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_OUTER_IP_CKSUM_BAD |
 307                  PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 308                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_BAD |
 309                  PKT_RX_IP_CKSUM_BAD) >> 1,
 310                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_BAD |
 311                  PKT_RX_IP_CKSUM_GOOD) >> 1,
 312                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 313                  PKT_RX_IP_CKSUM_BAD) >> 1,
 314                 (PKT_RX_OUTER_L4_CKSUM_GOOD >> 20 | PKT_RX_L4_CKSUM_GOOD |
 315                  PKT_RX_IP_CKSUM_GOOD) >> 1);
 316         const __m256i cksum_mask =
 317                  _mm256_set1_epi32(PKT_RX_IP_CKSUM_MASK |
 318                                    PKT_RX_L4_CKSUM_MASK |
 319                                    PKT_RX_OUTER_IP_CKSUM_BAD |
 320                                    PKT_RX_OUTER_L4_CKSUM_MASK);
 321         /**
 322          * data to be shuffled by result of flag mask, shifted down 12.
 323          * If RSS(bit12)/VLAN(bit13) are set,
 324          * shuffle moves appropriate flags in place.
 325          */
 326         const __m256i rss_vlan_flags_shuf = _mm256_set_epi8(0, 0, 0, 0,
 327                         0, 0, 0, 0,
 328                         0, 0, 0, 0,
 329                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 330                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 331                         PKT_RX_RSS_HASH, 0,
 332                         /* 2nd 128-bits */
 333                         0, 0, 0, 0,
 334                         0, 0, 0, 0,
 335                         0, 0, 0, 0,
 336                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 337                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 338                         PKT_RX_RSS_HASH, 0);
 339
 340         uint16_t i, received;
 341
 342         for (i = 0, received = 0; i < nb_pkts;
 343              i += ICE_DESCS_PER_LOOP_AVX,
 344              rxdp += ICE_DESCS_PER_LOOP_AVX) {
 345                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 346                 _mm256_storeu_si256((void *)&rx_pkts[i],
 347                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 348 #ifdef RTE_ARCH_X86_64
 349                 _mm256_storeu_si256
 350                         ((void *)&rx_pkts[i + 4],
 351                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 352 #endif
 353
 354                 __m512i raw_desc0_3, raw_desc4_7;
 355                 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
 356
 357                 /* load in descriptors, in reverse order */
 358                 const __m128i raw_desc7 =
 359                         _mm_load_si128((void *)(rxdp + 7));
 360                 rte_compiler_barrier();
 361                 const __m128i raw_desc6 =
 362                         _mm_load_si128((void *)(rxdp + 6));
 363                 rte_compiler_barrier();
 364                 const __m128i raw_desc5 =
 365                         _mm_load_si128((void *)(rxdp + 5));
 366                 rte_compiler_barrier();
 367                 const __m128i raw_desc4 =
 368                         _mm_load_si128((void *)(rxdp + 4));
 369                 rte_compiler_barrier();
 370                 const __m128i raw_desc3 =
 371                         _mm_load_si128((void *)(rxdp + 3));
 372                 rte_compiler_barrier();
 373                 const __m128i raw_desc2 =
 374                         _mm_load_si128((void *)(rxdp + 2));
 375                 rte_compiler_barrier();
 376                 const __m128i raw_desc1 =
 377                         _mm_load_si128((void *)(rxdp + 1));
 378                 rte_compiler_barrier();
 379                 const __m128i raw_desc0 =
 380                         _mm_load_si128((void *)(rxdp + 0));
 381
 382                 raw_desc6_7 =
 383                         _mm256_inserti128_si256
 384                                 (_mm256_castsi128_si256(raw_desc6),
 385                                  raw_desc7, 1);
 386                 raw_desc4_5 =
 387                         _mm256_inserti128_si256
 388                                 (_mm256_castsi128_si256(raw_desc4),
 389                                  raw_desc5, 1);
 390                 raw_desc2_3 =
 391                         _mm256_inserti128_si256
 392                                 (_mm256_castsi128_si256(raw_desc2),
 393                                  raw_desc3, 1);
 394                 raw_desc0_1 =
 395                         _mm256_inserti128_si256
 396                                 (_mm256_castsi128_si256(raw_desc0),
 397                                  raw_desc1, 1);
 398
 399                 raw_desc4_7 =
 400                         _mm512_inserti64x4
 401                                 (_mm512_castsi256_si512(raw_desc4_5),
 402                                  raw_desc6_7, 1);
 403                 raw_desc0_3 =
 404                         _mm512_inserti64x4
 405                                 (_mm512_castsi256_si512(raw_desc0_1),
 406                                  raw_desc2_3, 1);
 407
 408                 if (split_packet) {
 409                         int j;
 410
 411                         for (j = 0; j < ICE_DESCS_PER_LOOP_AVX; j++)
 412                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 413                 }
 414
 415                 /**
 416                  * convert descriptors 0-7 into mbufs, re-arrange fields.
 417                  * Then write into the mbuf.
 418                  */
 419                 __m512i mb4_7 = _mm512_shuffle_epi8(raw_desc4_7, shuf_msk);
 420                 __m512i mb0_3 = _mm512_shuffle_epi8(raw_desc0_3, shuf_msk);
 421
 422                 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
 423                 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
 424
 425                 /**
 426                  * to get packet types, ptype is located in bit16-25
 427                  * of each 128bits
 428                  */
 429                 const __m512i ptype_mask =
 430                         _mm512_set1_epi16(ICE_RX_FLEX_DESC_PTYPE_M);
 431
 432                 /**
 433                  * to get packet types, ptype is located in bit16-25
 434                  * of each 128bits
 435                  */
 436                 const __m512i ptypes4_7 =
 437                         _mm512_and_si512(raw_desc4_7, ptype_mask);
 438                 const __m512i ptypes0_3 =
 439                         _mm512_and_si512(raw_desc0_3, ptype_mask);
 440
 441                 const __m256i ptypes6_7 =
 442                         _mm512_extracti64x4_epi64(ptypes4_7, 1);
 443                 const __m256i ptypes4_5 =
 444                         _mm512_extracti64x4_epi64(ptypes4_7, 0);
 445                 const __m256i ptypes2_3 =
 446                         _mm512_extracti64x4_epi64(ptypes0_3, 1);
 447                 const __m256i ptypes0_1 =
 448                         _mm512_extracti64x4_epi64(ptypes0_3, 0);
 449                 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
 450                 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
 451                 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
 452                 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
 453                 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
 454                 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
 455                 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
 456                 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
 457
 458                 const __m512i ptype4_7 = _mm512_set_epi32
 459                         (0, 0, 0, ptype_tbl[ptype7],
 460                          0, 0, 0, ptype_tbl[ptype6],
 461                          0, 0, 0, ptype_tbl[ptype5],
 462                          0, 0, 0, ptype_tbl[ptype4]);
 463                 const __m512i ptype0_3 = _mm512_set_epi32
 464                         (0, 0, 0, ptype_tbl[ptype3],
 465                          0, 0, 0, ptype_tbl[ptype2],
 466                          0, 0, 0, ptype_tbl[ptype1],
 467                          0, 0, 0, ptype_tbl[ptype0]);
 468
 469                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 470                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 471
 472                 __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
 473                 __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
 474                 __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
 475                 __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
 476
 477                 /**
 478                  * use permute/extract to get status content
 479                  * After the operations, the packets status flags are in the
 480                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 481                  */
 482                 /* merge the status bits into one register */
 483                 const __m512i status_permute_msk = _mm512_set_epi32
 484                         (0, 0, 0, 0,
 485                          0, 0, 0, 0,
 486                          22, 30, 6, 14,
 487                          18, 26, 2, 10);
 488                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
 489                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
 490                 __m256i status0_7 = _mm512_extracti64x4_epi64
 491                         (raw_status0_7, 0);
 492
 493                 __m256i mbuf_flags = _mm256_set1_epi32(0);
 494
 495                 if (do_offload) {
 496                         /* now do flag manipulation */
 497
 498                         /* get only flag/error bits we want */
 499                         const __m256i flag_bits =
 500                                 _mm256_and_si256(status0_7, flags_mask);
 501                         /**
 502                          * l3_l4_error flags, shuffle, then shift to correct adjustment
 503                          * of flags in flags_shuf, and finally mask out extra bits
 504                          */
 505                         __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 506                                         _mm256_srli_epi32(flag_bits, 4));
 507                         l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 508                         __m256i l4_outer_mask = _mm256_set1_epi32(0x6);
 509                         __m256i l4_outer_flags =
 510                                         _mm256_and_si256(l3_l4_flags, l4_outer_mask);
 511                         l4_outer_flags = _mm256_slli_epi32(l4_outer_flags, 20);
 512
 513                         __m256i l3_l4_mask = _mm256_set1_epi32(~0x6);
 514
 515                         l3_l4_flags = _mm256_and_si256(l3_l4_flags, l3_l4_mask);
 516                         l3_l4_flags = _mm256_or_si256(l3_l4_flags, l4_outer_flags);
 517                         l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 518                         /* set rss and vlan flags */
 519                         const __m256i rss_vlan_flag_bits =
 520                                 _mm256_srli_epi32(flag_bits, 12);
 521                         const __m256i rss_vlan_flags =
 522                                 _mm256_shuffle_epi8(rss_vlan_flags_shuf,
 523                                                     rss_vlan_flag_bits);
 524
 525                         /* merge flags */
 526                         mbuf_flags = _mm256_or_si256(l3_l4_flags,
 527                                                      rss_vlan_flags);
 528                 }
 529
 530                 if (rxq->fdir_enabled) {
 531                         const __m256i fdir_id4_7 =
 532                                 _mm256_unpackhi_epi32(raw_desc6_7, raw_desc4_5);
 533
 534                         const __m256i fdir_id0_3 =
 535                                 _mm256_unpackhi_epi32(raw_desc2_3, raw_desc0_1);
 536
 537                         const __m256i fdir_id0_7 =
 538                                 _mm256_unpackhi_epi64(fdir_id4_7, fdir_id0_3);
 539
 540                         if (do_offload) {
 541                                 const __m256i fdir_flags =
 542                                         ice_flex_rxd_to_fdir_flags_vec_avx512
 543                                                 (fdir_id0_7);
 544
 545                                 /* merge with fdir_flags */
 546                                 mbuf_flags = _mm256_or_si256
 547                                                 (mbuf_flags, fdir_flags);
 548                         } else {
 549                                 mbuf_flags =
 550                                         ice_flex_rxd_to_fdir_flags_vec_avx512
 551                                                 (fdir_id0_7);
 552                         }
 553
 554                         /* write to mbuf: have to use scalar store here */
 555                         rx_pkts[i + 0]->hash.fdir.hi =
 556                                 _mm256_extract_epi32(fdir_id0_7, 3);
 557
 558                         rx_pkts[i + 1]->hash.fdir.hi =
 559                                 _mm256_extract_epi32(fdir_id0_7, 7);
 560
 561                         rx_pkts[i + 2]->hash.fdir.hi =
 562                                 _mm256_extract_epi32(fdir_id0_7, 2);
 563
 564                         rx_pkts[i + 3]->hash.fdir.hi =
 565                                 _mm256_extract_epi32(fdir_id0_7, 6);
 566
 567                         rx_pkts[i + 4]->hash.fdir.hi =
 568                                 _mm256_extract_epi32(fdir_id0_7, 1);
 569
 570                         rx_pkts[i + 5]->hash.fdir.hi =
 571                                 _mm256_extract_epi32(fdir_id0_7, 5);
 572
 573                         rx_pkts[i + 6]->hash.fdir.hi =
 574                                 _mm256_extract_epi32(fdir_id0_7, 0);
 575
 576                         rx_pkts[i + 7]->hash.fdir.hi =
 577                                 _mm256_extract_epi32(fdir_id0_7, 4);
 578                 } /* if() on fdir_enabled */
 579
 580                 if (do_offload) {
 581 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 582                         /**
 583                          * needs to load 2nd 16B of each desc for RSS hash parsing,
 584                          * will cause performance drop to get into this context.
 585                          */
 586                         if (rxq->vsi->adapter->pf.dev_data->dev_conf.rxmode.offloads &
 587                                         DEV_RX_OFFLOAD_RSS_HASH) {
 588                                 /* load bottom half of every 32B desc */
 589                                 const __m128i raw_desc_bh7 =
 590                                         _mm_load_si128
 591                                                 ((void *)(&rxdp[7].wb.status_error1));
 592                                 rte_compiler_barrier();
 593                                 const __m128i raw_desc_bh6 =
 594                                         _mm_load_si128
 595                                                 ((void *)(&rxdp[6].wb.status_error1));
 596                                 rte_compiler_barrier();
 597                                 const __m128i raw_desc_bh5 =
 598                                         _mm_load_si128
 599                                                 ((void *)(&rxdp[5].wb.status_error1));
 600                                 rte_compiler_barrier();
 601                                 const __m128i raw_desc_bh4 =
 602                                         _mm_load_si128
 603                                                 ((void *)(&rxdp[4].wb.status_error1));
 604                                 rte_compiler_barrier();
 605                                 const __m128i raw_desc_bh3 =
 606                                         _mm_load_si128
 607                                                 ((void *)(&rxdp[3].wb.status_error1));
 608                                 rte_compiler_barrier();
 609                                 const __m128i raw_desc_bh2 =
 610                                         _mm_load_si128
 611                                                 ((void *)(&rxdp[2].wb.status_error1));
 612                                 rte_compiler_barrier();
 613                                 const __m128i raw_desc_bh1 =
 614                                         _mm_load_si128
 615                                                 ((void *)(&rxdp[1].wb.status_error1));
 616                                 rte_compiler_barrier();
 617                                 const __m128i raw_desc_bh0 =
 618                                         _mm_load_si128
 619                                                 ((void *)(&rxdp[0].wb.status_error1));
 620
 621                                 __m256i raw_desc_bh6_7 =
 622                                         _mm256_inserti128_si256
 623                                                 (_mm256_castsi128_si256(raw_desc_bh6),
 624                                                 raw_desc_bh7, 1);
 625                                 __m256i raw_desc_bh4_5 =
 626                                         _mm256_inserti128_si256
 627                                                 (_mm256_castsi128_si256(raw_desc_bh4),
 628                                                 raw_desc_bh5, 1);
 629                                 __m256i raw_desc_bh2_3 =
 630                                         _mm256_inserti128_si256
 631                                                 (_mm256_castsi128_si256(raw_desc_bh2),
 632                                                 raw_desc_bh3, 1);
 633                                 __m256i raw_desc_bh0_1 =
 634                                         _mm256_inserti128_si256
 635                                                 (_mm256_castsi128_si256(raw_desc_bh0),
 636                                                 raw_desc_bh1, 1);
 637
 638                                 /**
 639                                  * to shift the 32b RSS hash value to the
 640                                  * highest 32b of each 128b before mask
 641                                  */
 642                                 __m256i rss_hash6_7 =
 643                                         _mm256_slli_epi64(raw_desc_bh6_7, 32);
 644                                 __m256i rss_hash4_5 =
 645                                         _mm256_slli_epi64(raw_desc_bh4_5, 32);
 646                                 __m256i rss_hash2_3 =
 647                                         _mm256_slli_epi64(raw_desc_bh2_3, 32);
 648                                 __m256i rss_hash0_1 =
 649                                         _mm256_slli_epi64(raw_desc_bh0_1, 32);
 650
 651                                 __m256i rss_hash_msk =
 652                                         _mm256_set_epi32(0xFFFFFFFF, 0, 0, 0,
 653                                                          0xFFFFFFFF, 0, 0, 0);
 654
 655                                 rss_hash6_7 = _mm256_and_si256
 656                                                 (rss_hash6_7, rss_hash_msk);
 657                                 rss_hash4_5 = _mm256_and_si256
 658                                                 (rss_hash4_5, rss_hash_msk);
 659                                 rss_hash2_3 = _mm256_and_si256
 660                                                 (rss_hash2_3, rss_hash_msk);
 661                                 rss_hash0_1 = _mm256_and_si256
 662                                                 (rss_hash0_1, rss_hash_msk);
 663
 664                                 mb6_7 = _mm256_or_si256(mb6_7, rss_hash6_7);
 665                                 mb4_5 = _mm256_or_si256(mb4_5, rss_hash4_5);
 666                                 mb2_3 = _mm256_or_si256(mb2_3, rss_hash2_3);
 667                                 mb0_1 = _mm256_or_si256(mb0_1, rss_hash0_1);
 668                         } /* if() on RSS hash parsing */
 669 #endif
 670                 }
 671
 672                 /**
 673                  * At this point, we have the 8 sets of flags in the low 16-bits
 674                  * of each 32-bit value in vlan0.
 675                  * We want to extract these, and merge them with the mbuf init
 676                  * data so we can do a single write to the mbuf to set the flags
 677                  * and all the other initialization fields. Extracting the
 678                  * appropriate flags means that we have to do a shift and blend
 679                  * for each mbuf before we do the write. However, we can also
 680                  * add in the previously computed rx_descriptor fields to
 681                  * make a single 256-bit write per mbuf
 682                  */
 683                 /* check the structure matches expectations */
 684                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 685                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 686                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 687                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 688                                                     rearm_data),
 689                                            16));
 690                 /* build up data and do writes */
 691                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 692                         rearm6, rearm7;
 693
 694                 rearm6 = _mm256_blend_epi32(mbuf_init,
 695                                             _mm256_slli_si256(mbuf_flags, 8),
 696                                             0x04);
 697                 rearm4 = _mm256_blend_epi32(mbuf_init,
 698                                             _mm256_slli_si256(mbuf_flags, 4),
 699                                             0x04);
 700                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 701                 rearm0 = _mm256_blend_epi32(mbuf_init,
 702                                             _mm256_srli_si256(mbuf_flags, 4),
 703                                             0x04);
 704
 705                 /* permute to add in the rx_descriptor e.g. rss fields */
 706                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 707                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 708                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 709                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 710
 711                 /* write to mbuf */
 712                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 713                                     rearm6);
 714                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 715                                     rearm4);
 716                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 717                                     rearm2);
 718                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 719                                     rearm0);
 720
 721                 /* repeat for the odd mbufs */
 722                 const __m256i odd_flags =
 723                         _mm256_castsi128_si256
 724                                 (_mm256_extracti128_si256(mbuf_flags, 1));
 725                 rearm7 = _mm256_blend_epi32(mbuf_init,
 726                                             _mm256_slli_si256(odd_flags, 8),
 727                                             0x04);
 728                 rearm5 = _mm256_blend_epi32(mbuf_init,
 729                                             _mm256_slli_si256(odd_flags, 4),
 730                                             0x04);
 731                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 732                 rearm1 = _mm256_blend_epi32(mbuf_init,
 733                                             _mm256_srli_si256(odd_flags, 4),
 734                                             0x04);
 735
 736                 /* since odd mbufs are already in hi 128-bits use blend */
 737                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 738                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 739                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 740                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 741                 /* again write to mbufs */
 742                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 743                                     rearm7);
 744                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 745                                     rearm5);
 746                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 747                                     rearm3);
 748                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 749                                     rearm1);
 750
 751                 /* extract and record EOP bit */
 752                 if (split_packet) {
 753                         const __m128i eop_mask =
 754                                 _mm_set1_epi16(1 << ICE_RX_DESC_STATUS_EOF_S);
 755                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 756                                                                      eop_check);
 757                         /* pack status bits into a single 128-bit register */
 758                         const __m128i eop_bits =
 759                                 _mm_packus_epi32
 760                                         (_mm256_castsi256_si128(eop_bits256),
 761                                          _mm256_extractf128_si256(eop_bits256,
 762                                                                   1));
 763                         /**
 764                          * flip bits, and mask out the EOP bit, which is now
 765                          * a split-packet bit i.e. !EOP, rather than EOP one.
 766                          */
 767                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 768                                         eop_mask);
 769                         /**
 770                          * eop bits are out of order, so we need to shuffle them
 771                          * back into order again. In doing so, only use low 8
 772                          * bits, which acts like another pack instruction
 773                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 774                          * [Since we use epi8, the 16-bit positions are
 775                          * multiplied by 2 in the eop_shuffle value.]
 776                          */
 777                         __m128i eop_shuffle =
 778                                 _mm_set_epi8(/* zero hi 64b */
 779                                              0xFF, 0xFF, 0xFF, 0xFF,
 780                                              0xFF, 0xFF, 0xFF, 0xFF,
 781                                              /* move values to lo 64b */
 782                                              8, 0, 10, 2,
 783                                              12, 4, 14, 6);
 784                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 785                         *(uint64_t *)split_packet =
 786                                 _mm_cvtsi128_si64(split_bits);
 787                         split_packet += ICE_DESCS_PER_LOOP_AVX;
 788                 }
 789
 790                 /* perform dd_check */
 791                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 792                 status0_7 = _mm256_packs_epi32(status0_7,
 793                                                _mm256_setzero_si256());
 794
 795                 uint64_t burst = __builtin_popcountll
 796                                         (_mm_cvtsi128_si64
 797                                                 (_mm256_extracti128_si256
 798                                                         (status0_7, 1)));
 799                 burst += __builtin_popcountll
 800                                 (_mm_cvtsi128_si64
 801                                         (_mm256_castsi256_si128(status0_7)));
 802                 received += burst;
 803                 if (burst != ICE_DESCS_PER_LOOP_AVX)
 804                         break;
 805         }
 806
 807         /* update tail pointers */
 808         rxq->rx_tail += received;
 809         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 810         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
 811                 rxq->rx_tail--;
 812                 received--;
 813         }
 814         rxq->rxrearm_nb += received;
 815         return received;
 816 }
 817
 818 /**
 819  * Notice:
 820  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 821  */
 822 uint16_t
 823 ice_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 824                          uint16_t nb_pkts)
 825 {
 826         return _ice_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts, NULL, false);
 827 }
 828
 829 /**
 830  * Notice:
 831  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 832  */
 833 uint16_t
 834 ice_recv_pkts_vec_avx512_offload(void *rx_queue, struct rte_mbuf **rx_pkts,
 835                                  uint16_t nb_pkts)
 836 {
 837         return _ice_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts,
 838                                              nb_pkts, NULL, true);
 839 }
 840
 841 /**
 842  * vPMD receive routine that reassembles single burst of 32 scattered packets
 843  * Notice:
 844  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 845  */
 846 static uint16_t
 847 ice_recv_scattered_burst_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 848                                     uint16_t nb_pkts)
 849 {
 850         struct ice_rx_queue *rxq = rx_queue;
 851         uint8_t split_flags[ICE_VPMD_RX_BURST] = {0};
 852
 853         /* get some new buffers */
 854         uint16_t nb_bufs = _ice_recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,
 855                                                        split_flags, false);
 856         if (nb_bufs == 0)
 857                 return 0;
 858
 859         /* happy day case, full burst + no packets to be joined */
 860         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 861
 862         if (!rxq->pkt_first_seg &&
 863             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 864             split_fl64[2] == 0 && split_fl64[3] == 0)
 865                 return nb_bufs;
 866
 867         /* reassemble any packets that need reassembly */
 868         unsigned int i = 0;
 869
 870         if (!rxq->pkt_first_seg) {
 871                 /* find the first split flag, and only reassemble then */
 872                 while (i < nb_bufs && !split_flags[i])
 873                         i++;
 874                 if (i == nb_bufs)
 875                         return nb_bufs;
 876                 rxq->pkt_first_seg = rx_pkts[i];
 877         }
 878         return i + ice_rx_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 879                                              &split_flags[i]);
 880 }
 881
 882 /**
 883  * vPMD receive routine that reassembles single burst of 32 scattered packets
 884  * Notice:
 885  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 886  */
 887 static uint16_t
 888 ice_recv_scattered_burst_vec_avx512_offload(void *rx_queue,
 889                                             struct rte_mbuf **rx_pkts,
 890                                             uint16_t nb_pkts)
 891 {
 892         struct ice_rx_queue *rxq = rx_queue;
 893         uint8_t split_flags[ICE_VPMD_RX_BURST] = {0};
 894
 895         /* get some new buffers */
 896         uint16_t nb_bufs = _ice_recv_raw_pkts_vec_avx512(rxq,
 897                                 rx_pkts, nb_pkts, split_flags, true);
 898         if (nb_bufs == 0)
 899                 return 0;
 900
 901         /* happy day case, full burst + no packets to be joined */
 902         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 903
 904         if (!rxq->pkt_first_seg &&
 905             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 906             split_fl64[2] == 0 && split_fl64[3] == 0)
 907                 return nb_bufs;
 908
 909         /* reassemble any packets that need reassembly */
 910         unsigned int i = 0;
 911
 912         if (!rxq->pkt_first_seg) {
 913                 /* find the first split flag, and only reassemble then */
 914                 while (i < nb_bufs && !split_flags[i])
 915                         i++;
 916                 if (i == nb_bufs)
 917                         return nb_bufs;
 918                 rxq->pkt_first_seg = rx_pkts[i];
 919         }
 920         return i + ice_rx_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 921                                              &split_flags[i]);
 922 }
 923
 924 /**
 925  * vPMD receive routine that reassembles scattered packets.
 926  * Main receive routine that can handle arbitrary burst sizes
 927  * Notice:
 928  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 929  */
 930 uint16_t
 931 ice_recv_scattered_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
 932                                    uint16_t nb_pkts)
 933 {
 934         uint16_t retval = 0;
 935
 936         while (nb_pkts > ICE_VPMD_RX_BURST) {
 937                 uint16_t burst = ice_recv_scattered_burst_vec_avx512(rx_queue,
 938                                 rx_pkts + retval, ICE_VPMD_RX_BURST);
 939                 retval += burst;
 940                 nb_pkts -= burst;
 941                 if (burst < ICE_VPMD_RX_BURST)
 942                         return retval;
 943         }
 944         return retval + ice_recv_scattered_burst_vec_avx512(rx_queue,
 945                                 rx_pkts + retval, nb_pkts);
 946 }
 947
 948 /**
 949  * vPMD receive routine that reassembles scattered packets.
 950  * Main receive routine that can handle arbitrary burst sizes
 951  * Notice:
 952  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 953  */
 954 uint16_t
 955 ice_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
 956                                            struct rte_mbuf **rx_pkts,
 957                                            uint16_t nb_pkts)
 958 {
 959         uint16_t retval = 0;
 960
 961         while (nb_pkts > ICE_VPMD_RX_BURST) {
 962                 uint16_t burst =
 963                         ice_recv_scattered_burst_vec_avx512_offload(rx_queue,
 964                                 rx_pkts + retval, ICE_VPMD_RX_BURST);
 965                 retval += burst;
 966                 nb_pkts -= burst;
 967                 if (burst < ICE_VPMD_RX_BURST)
 968                         return retval;
 969         }
 970         return retval + ice_recv_scattered_burst_vec_avx512_offload(rx_queue,
 971                                 rx_pkts + retval, nb_pkts);
 972 }
 973
 974 static __rte_always_inline int
 975 ice_tx_free_bufs_avx512(struct ice_tx_queue *txq)
 976 {
 977         struct ice_vec_tx_entry *txep;
 978         uint32_t n;
 979         uint32_t i;
 980         int nb_free = 0;
 981         struct rte_mbuf *m, *free[ICE_TX_MAX_FREE_BUF_SZ];
 982
 983         /* check DD bits on threshold descriptor */
 984         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
 985                         rte_cpu_to_le_64(ICE_TXD_QW1_DTYPE_M)) !=
 986                         rte_cpu_to_le_64(ICE_TX_DESC_DTYPE_DESC_DONE))
 987                 return 0;
 988
 989         n = txq->tx_rs_thresh;
 990
 991         /* first buffer to free from S/W ring is at index
 992          * tx_next_dd - (tx_rs_thresh - 1)
 993          */
 994         txep = (void *)txq->sw_ring;
 995         txep += txq->tx_next_dd - (n - 1);
 996
 997         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE && (n & 31) == 0) {
 998                 struct rte_mempool *mp = txep[0].mbuf->pool;
 999                 void **cache_objs;
1000                 struct rte_mempool_cache *cache = rte_mempool_default_cache(mp,
1001                                 rte_lcore_id());
1002
1003                 if (!cache || cache->len == 0)
1004                         goto normal;
1005
1006                 cache_objs = &cache->objs[cache->len];
1007
1008                 if (n > RTE_MEMPOOL_CACHE_MAX_SIZE) {
1009                         rte_mempool_ops_enqueue_bulk(mp, (void *)txep, n);
1010                         goto done;
1011                 }
1012
1013                 /* The cache follows the following algorithm
1014                  *   1. Add the objects to the cache
1015                  *   2. Anything greater than the cache min value (if it
1016                  *   crosses the cache flush threshold) is flushed to the ring.
1017                  */
1018                 /* Add elements back into the cache */
1019                 uint32_t copied = 0;
1020                 /* n is multiple of 32 */
1021                 while (copied < n) {
1022                         const __m512i a = _mm512_loadu_si512(&txep[copied]);
1023                         const __m512i b = _mm512_loadu_si512(&txep[copied + 8]);
1024                         const __m512i c = _mm512_loadu_si512(&txep[copied + 16]);
1025                         const __m512i d = _mm512_loadu_si512(&txep[copied + 24]);
1026
1027                         _mm512_storeu_si512(&cache_objs[copied], a);
1028                         _mm512_storeu_si512(&cache_objs[copied + 8], b);
1029                         _mm512_storeu_si512(&cache_objs[copied + 16], c);
1030                         _mm512_storeu_si512(&cache_objs[copied + 24], d);
1031                         copied += 32;
1032                 }
1033                 cache->len += n;
1034
1035                 if (cache->len >= cache->flushthresh) {
1036                         rte_mempool_ops_enqueue_bulk
1037                                 (mp, &cache->objs[cache->size],
1038                                  cache->len - cache->size);
1039                         cache->len = cache->size;
1040                 }
1041                 goto done;
1042         }
1043
1044 normal:
1045         m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
1046         if (likely(m)) {
1047                 free[0] = m;
1048                 nb_free = 1;
1049                 for (i = 1; i < n; i++) {
1050                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1051                         if (likely(m)) {
1052                                 if (likely(m->pool == free[0]->pool)) {
1053                                         free[nb_free++] = m;
1054                                 } else {
1055                                         rte_mempool_put_bulk(free[0]->pool,
1056                                                              (void *)free,
1057                                                              nb_free);
1058                                         free[0] = m;
1059                                         nb_free = 1;
1060                                 }
1061                         }
1062                 }
1063                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
1064         } else {
1065                 for (i = 1; i < n; i++) {
1066                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1067                         if (m)
1068                                 rte_mempool_put(m->pool, m);
1069                 }
1070         }
1071
1072 done:
1073         /* buffers were freed, update counters */
1074         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1075         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1076         if (txq->tx_next_dd >= txq->nb_tx_desc)
1077                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1078
1079         return txq->tx_rs_thresh;
1080 }
1081
1082 static __rte_always_inline void
1083 ice_vtx1(volatile struct ice_tx_desc *txdp,
1084          struct rte_mbuf *pkt, uint64_t flags, bool do_offload)
1085 {
1086         uint64_t high_qw =
1087                 (ICE_TX_DESC_DTYPE_DATA |
1088                  ((uint64_t)flags  << ICE_TXD_QW1_CMD_S) |
1089                  ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));
1090
1091         if (do_offload)
1092                 ice_txd_enable_offload(pkt, &high_qw);
1093
1094         __m128i descriptor = _mm_set_epi64x(high_qw,
1095                                 pkt->buf_iova + pkt->data_off);
1096         _mm_store_si128((__m128i *)txdp, descriptor);
1097 }
1098
1099 static __rte_always_inline void
1100 ice_vtx(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkt,
1101         uint16_t nb_pkts,  uint64_t flags, bool do_offload)
1102 {
1103         const uint64_t hi_qw_tmpl = (ICE_TX_DESC_DTYPE_DATA |
1104                         ((uint64_t)flags  << ICE_TXD_QW1_CMD_S));
1105
1106         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
1107                 uint64_t hi_qw3 =
1108                         hi_qw_tmpl |
1109                         ((uint64_t)pkt[3]->data_len <<
1110                          ICE_TXD_QW1_TX_BUF_SZ_S);
1111                 if (do_offload)
1112                         ice_txd_enable_offload(pkt[3], &hi_qw3);
1113                 uint64_t hi_qw2 =
1114                         hi_qw_tmpl |
1115                         ((uint64_t)pkt[2]->data_len <<
1116                          ICE_TXD_QW1_TX_BUF_SZ_S);
1117                 if (do_offload)
1118                         ice_txd_enable_offload(pkt[2], &hi_qw2);
1119                 uint64_t hi_qw1 =
1120                         hi_qw_tmpl |
1121                         ((uint64_t)pkt[1]->data_len <<
1122                          ICE_TXD_QW1_TX_BUF_SZ_S);
1123                 if (do_offload)
1124                         ice_txd_enable_offload(pkt[1], &hi_qw1);
1125                 uint64_t hi_qw0 =
1126                         hi_qw_tmpl |
1127                         ((uint64_t)pkt[0]->data_len <<
1128                          ICE_TXD_QW1_TX_BUF_SZ_S);
1129                 if (do_offload)
1130                         ice_txd_enable_offload(pkt[0], &hi_qw0);
1131
1132                 __m512i desc0_3 =
1133                         _mm512_set_epi64
1134                                 (hi_qw3,
1135                                  pkt[3]->buf_iova + pkt[3]->data_off,
1136                                  hi_qw2,
1137                                  pkt[2]->buf_iova + pkt[2]->data_off,
1138                                  hi_qw1,
1139                                  pkt[1]->buf_iova + pkt[1]->data_off,
1140                                  hi_qw0,
1141                                  pkt[0]->buf_iova + pkt[0]->data_off);
1142                 _mm512_storeu_si512((void *)txdp, desc0_3);
1143         }
1144
1145         /* do any last ones */
1146         while (nb_pkts) {
1147                 ice_vtx1(txdp, *pkt, flags, do_offload);
1148                 txdp++, pkt++, nb_pkts--;
1149         }
1150 }
1151
1152 static __rte_always_inline void
1153 ice_tx_backlog_entry_avx512(struct ice_vec_tx_entry *txep,
1154                             struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1155 {
1156         int i;
1157
1158         for (i = 0; i < (int)nb_pkts; ++i)
1159                 txep[i].mbuf = tx_pkts[i];
1160 }
1161
1162 static __rte_always_inline uint16_t
1163 ice_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1164                                 uint16_t nb_pkts, bool do_offload)
1165 {
1166         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
1167         volatile struct ice_tx_desc *txdp;
1168         struct ice_vec_tx_entry *txep;
1169         uint16_t n, nb_commit, tx_id;
1170         uint64_t flags = ICE_TD_CMD;
1171         uint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;
1172
1173         /* cross rx_thresh boundary is not allowed */
1174         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1175
1176         if (txq->nb_tx_free < txq->tx_free_thresh)
1177                 ice_tx_free_bufs_avx512(txq);
1178
1179         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1180         if (unlikely(nb_pkts == 0))
1181                 return 0;
1182
1183         tx_id = txq->tx_tail;
1184         txdp = &txq->tx_ring[tx_id];
1185         txep = (void *)txq->sw_ring;
1186         txep += tx_id;
1187
1188         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1189
1190         n = (uint16_t)(txq->nb_tx_desc - tx_id);
1191         if (nb_commit >= n) {
1192                 ice_tx_backlog_entry_avx512(txep, tx_pkts, n);
1193
1194                 ice_vtx(txdp, tx_pkts, n - 1, flags, do_offload);
1195                 tx_pkts += (n - 1);
1196                 txdp += (n - 1);
1197
1198                 ice_vtx1(txdp, *tx_pkts++, rs, do_offload);
1199
1200                 nb_commit = (uint16_t)(nb_commit - n);
1201
1202                 tx_id = 0;
1203                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1204
1205                 /* avoid reach the end of ring */
1206                 txdp = txq->tx_ring;
1207                 txep = (void *)txq->sw_ring;
1208         }
1209
1210         ice_tx_backlog_entry_avx512(txep, tx_pkts, nb_commit);
1211
1212         ice_vtx(txdp, tx_pkts, nb_commit, flags, do_offload);
1213
1214         tx_id = (uint16_t)(tx_id + nb_commit);
1215         if (tx_id > txq->tx_next_rs) {
1216                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
1217                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
1218                                          ICE_TXD_QW1_CMD_S);
1219                 txq->tx_next_rs =
1220                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1221         }
1222
1223         txq->tx_tail = tx_id;
1224
1225         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1226
1227         return nb_pkts;
1228 }
1229
1230 uint16_t
1231 ice_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1232                          uint16_t nb_pkts)
1233 {
1234         uint16_t nb_tx = 0;
1235         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
1236
1237         while (nb_pkts) {
1238                 uint16_t ret, num;
1239
1240                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1241                 ret = ice_xmit_fixed_burst_vec_avx512(tx_queue,
1242                                 &tx_pkts[nb_tx], num, false);
1243                 nb_tx += ret;
1244                 nb_pkts -= ret;
1245                 if (ret < num)
1246                         break;
1247         }
1248
1249         return nb_tx;
1250 }
1251
1252 uint16_t
1253 ice_xmit_pkts_vec_avx512_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
1254                                  uint16_t nb_pkts)
1255 {
1256         uint16_t nb_tx = 0;
1257         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
1258
1259         while (nb_pkts) {
1260                 uint16_t ret, num;
1261
1262                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1263                 ret = ice_xmit_fixed_burst_vec_avx512(tx_queue,
1264                                 &tx_pkts[nb_tx], num, true);
1265
1266                 nb_tx += ret;
1267                 nb_pkts -= ret;
1268                 if (ret < num)
1269                         break;
1270         }
1271
1272         return nb_tx;
1273 }