net/ice: support Tx SSE vector
[dpdk.git] / drivers / net / ice / ice_rxtx_vec_sse.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2019 Intel Corporation
3  */
4
5 #include "ice_rxtx_vec_common.h"
6
7 #include <tmmintrin.h>
8
9 #ifndef __INTEL_COMPILER
10 #pragma GCC diagnostic ignored "-Wcast-qual"
11 #endif
12
13 static inline void
14 ice_rxq_rearm(struct ice_rx_queue *rxq)
15 {
16         int i;
17         uint16_t rx_id;
18         volatile union ice_rx_desc *rxdp;
19         struct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
20         struct rte_mbuf *mb0, *mb1;
21         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
22                                           RTE_PKTMBUF_HEADROOM);
23         __m128i dma_addr0, dma_addr1;
24
25         rxdp = rxq->rx_ring + rxq->rxrearm_start;
26
27         /* Pull 'n' more MBUFs into the software ring */
28         if (rte_mempool_get_bulk(rxq->mp,
29                                  (void *)rxep,
30                                  ICE_RXQ_REARM_THRESH) < 0) {
31                 if (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=
32                     rxq->nb_rx_desc) {
33                         dma_addr0 = _mm_setzero_si128();
34                         for (i = 0; i < ICE_DESCS_PER_LOOP; i++) {
35                                 rxep[i].mbuf = &rxq->fake_mbuf;
36                                 _mm_store_si128((__m128i *)&rxdp[i].read,
37                                                 dma_addr0);
38                         }
39                 }
40                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
41                         ICE_RXQ_REARM_THRESH;
42                 return;
43         }
44
45         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
46         for (i = 0; i < ICE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
47                 __m128i vaddr0, vaddr1;
48
49                 mb0 = rxep[0].mbuf;
50                 mb1 = rxep[1].mbuf;
51
52                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
53                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
54                                  offsetof(struct rte_mbuf, buf_addr) + 8);
55                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
56                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
57
58                 /* convert pa to dma_addr hdr/data */
59                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
60                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
61
62                 /* add headroom to pa values */
63                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
64                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
65
66                 /* flush desc with pa dma_addr */
67                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
68                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
69         }
70
71         rxq->rxrearm_start += ICE_RXQ_REARM_THRESH;
72         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
73                 rxq->rxrearm_start = 0;
74
75         rxq->rxrearm_nb -= ICE_RXQ_REARM_THRESH;
76
77         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
78                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
79
80         /* Update the tail pointer on the NIC */
81         ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
82 }
83
84 static inline void
85 ice_rx_desc_to_olflags_v(struct ice_rx_queue *rxq, __m128i descs[4],
86                          struct rte_mbuf **rx_pkts)
87 {
88         const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
89         __m128i rearm0, rearm1, rearm2, rearm3;
90
91         __m128i vlan0, vlan1, rss, l3_l4e;
92
93         /* mask everything except RSS, flow director and VLAN flags
94          * bit2 is for VLAN tag, bit11 for flow director indication
95          * bit13:12 for RSS indication.
96          */
97         const __m128i rss_vlan_msk = _mm_set_epi32(0x1c03804, 0x1c03804,
98                                                    0x1c03804, 0x1c03804);
99
100         const __m128i cksum_mask = _mm_set_epi32(PKT_RX_IP_CKSUM_GOOD |
101                                                  PKT_RX_IP_CKSUM_BAD |
102                                                  PKT_RX_L4_CKSUM_GOOD |
103                                                  PKT_RX_L4_CKSUM_BAD |
104                                                  PKT_RX_EIP_CKSUM_BAD,
105                                                  PKT_RX_IP_CKSUM_GOOD |
106                                                  PKT_RX_IP_CKSUM_BAD |
107                                                  PKT_RX_L4_CKSUM_GOOD |
108                                                  PKT_RX_L4_CKSUM_BAD |
109                                                  PKT_RX_EIP_CKSUM_BAD,
110                                                  PKT_RX_IP_CKSUM_GOOD |
111                                                  PKT_RX_IP_CKSUM_BAD |
112                                                  PKT_RX_L4_CKSUM_GOOD |
113                                                  PKT_RX_L4_CKSUM_BAD |
114                                                  PKT_RX_EIP_CKSUM_BAD,
115                                                  PKT_RX_IP_CKSUM_GOOD |
116                                                  PKT_RX_IP_CKSUM_BAD |
117                                                  PKT_RX_L4_CKSUM_GOOD |
118                                                  PKT_RX_L4_CKSUM_BAD |
119                                                  PKT_RX_EIP_CKSUM_BAD);
120
121         /* map rss and vlan type to rss hash and vlan flag */
122         const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
123                         0, 0, 0, 0,
124                         0, 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
125                         0, 0, 0, 0);
126
127         const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
128                         0, 0, 0, 0,
129                         PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
130                         0, 0, PKT_RX_FDIR, 0);
131
132         const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
133                         /* shift right 1 bit to make sure it not exceed 255 */
134                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
135                          PKT_RX_IP_CKSUM_BAD) >> 1,
136                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
137                          PKT_RX_L4_CKSUM_BAD) >> 1,
138                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
139                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
140                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
141                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
142                         PKT_RX_IP_CKSUM_BAD >> 1,
143                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
144
145         vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);
146         vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);
147         vlan0 = _mm_unpacklo_epi64(vlan0, vlan1);
148
149         vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
150         vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
151
152         rss = _mm_srli_epi32(vlan1, 11);
153         rss = _mm_shuffle_epi8(rss_flags, rss);
154
155         l3_l4e = _mm_srli_epi32(vlan1, 22);
156         l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);
157         /* then we shift left 1 bit */
158         l3_l4e = _mm_slli_epi32(l3_l4e, 1);
159         /* we need to mask out the reduntant bits */
160         l3_l4e = _mm_and_si128(l3_l4e, cksum_mask);
161
162         vlan0 = _mm_or_si128(vlan0, rss);
163         vlan0 = _mm_or_si128(vlan0, l3_l4e);
164
165         /**
166          * At this point, we have the 4 sets of flags in the low 16-bits
167          * of each 32-bit value in vlan0.
168          * We want to extract these, and merge them with the mbuf init data
169          * so we can do a single 16-byte write to the mbuf to set the flags
170          * and all the other initialization fields. Extracting the
171          * appropriate flags means that we have to do a shift and blend for
172          * each mbuf before we do the write.
173          */
174         rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 8), 0x10);
175         rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 4), 0x10);
176         rearm2 = _mm_blend_epi16(mbuf_init, vlan0, 0x10);
177         rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10);
178
179         /* write the rearm data and the olflags in one write */
180         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
181                          offsetof(struct rte_mbuf, rearm_data) + 8);
182         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
183                          RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
184         _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
185         _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
186         _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
187         _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
188 }
189
190 #define PKTLEN_SHIFT     10
191
192 static inline void
193 ice_rx_desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,
194                        uint32_t *ptype_tbl)
195 {
196         __m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
197         __m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
198
199         ptype0 = _mm_srli_epi64(ptype0, 30);
200         ptype1 = _mm_srli_epi64(ptype1, 30);
201
202         rx_pkts[0]->packet_type = ptype_tbl[_mm_extract_epi8(ptype0, 0)];
203         rx_pkts[1]->packet_type = ptype_tbl[_mm_extract_epi8(ptype0, 8)];
204         rx_pkts[2]->packet_type = ptype_tbl[_mm_extract_epi8(ptype1, 0)];
205         rx_pkts[3]->packet_type = ptype_tbl[_mm_extract_epi8(ptype1, 8)];
206 }
207
208 /**
209  * Notice:
210  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
211  * - nb_pkts > ICE_VPMD_RX_BURST, only scan ICE_VPMD_RX_BURST
212  *   numbers of DD bits
213  */
214 static inline uint16_t
215 _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,
216                        uint16_t nb_pkts, uint8_t *split_packet)
217 {
218         volatile union ice_rx_desc *rxdp;
219         struct ice_rx_entry *sw_ring;
220         uint16_t nb_pkts_recd;
221         int pos;
222         uint64_t var;
223         __m128i shuf_msk;
224         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
225
226         __m128i crc_adjust = _mm_set_epi16
227                                 (0, 0, 0,    /* ignore non-length fields */
228                                  -rxq->crc_len, /* sub crc on data_len */
229                                  0,          /* ignore high-16bits of pkt_len */
230                                  -rxq->crc_len, /* sub crc on pkt_len */
231                                  0, 0            /* ignore pkt_type field */
232                                 );
233         /**
234          * compile-time check the above crc_adjust layout is correct.
235          * NOTE: the first field (lowest address) is given last in set_epi16
236          * call above.
237          */
238         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
239                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
240         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
241                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
242         __m128i dd_check, eop_check;
243
244         /* nb_pkts shall be less equal than ICE_MAX_RX_BURST */
245         nb_pkts = RTE_MIN(nb_pkts, ICE_MAX_RX_BURST);
246
247         /* nb_pkts has to be floor-aligned to ICE_DESCS_PER_LOOP */
248         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, ICE_DESCS_PER_LOOP);
249
250         /* Just the act of getting into the function from the application is
251          * going to cost about 7 cycles
252          */
253         rxdp = rxq->rx_ring + rxq->rx_tail;
254
255         rte_prefetch0(rxdp);
256
257         /* See if we need to rearm the RX queue - gives the prefetch a bit
258          * of time to act
259          */
260         if (rxq->rxrearm_nb > ICE_RXQ_REARM_THRESH)
261                 ice_rxq_rearm(rxq);
262
263         /* Before we start moving massive data around, check to see if
264          * there is actually a packet available
265          */
266         if (!(rxdp->wb.qword1.status_error_len &
267               rte_cpu_to_le_32(1 << ICE_RX_DESC_STATUS_DD_S)))
268                 return 0;
269
270         /* 4 packets DD mask */
271         dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
272
273         /* 4 packets EOP mask */
274         eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
275
276         /* mask to shuffle from desc. to mbuf */
277         shuf_msk = _mm_set_epi8
278                         (7, 6, 5, 4,  /* octet 4~7, 32bits rss */
279                          3, 2,        /* octet 2~3, low 16 bits vlan_macip */
280                          15, 14,      /* octet 15~14, 16 bits data_len */
281                          0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
282                          15, 14,      /* octet 15~14, low 16 bits pkt_len */
283                          0xFF, 0xFF,  /* pkt_type set as unknown */
284                          0xFF, 0xFF  /*pkt_type set as unknown */
285                         );
286         /**
287          * Compile-time verify the shuffle mask
288          * NOTE: some field positions already verified above, but duplicated
289          * here for completeness in case of future modifications.
290          */
291         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
292                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
293         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
294                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
295         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
296                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
297         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
298                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
299
300         /* Cache is empty -> need to scan the buffer rings, but first move
301          * the next 'n' mbufs into the cache
302          */
303         sw_ring = &rxq->sw_ring[rxq->rx_tail];
304
305         /* A. load 4 packet in one loop
306          * [A*. mask out 4 unused dirty field in desc]
307          * B. copy 4 mbuf point from swring to rx_pkts
308          * C. calc the number of DD bits among the 4 packets
309          * [C*. extract the end-of-packet bit, if requested]
310          * D. fill info. from desc to mbuf
311          */
312
313         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
314              pos += ICE_DESCS_PER_LOOP,
315              rxdp += ICE_DESCS_PER_LOOP) {
316                 __m128i descs[ICE_DESCS_PER_LOOP];
317                 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
318                 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
319                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
320                 __m128i mbp1;
321 #if defined(RTE_ARCH_X86_64)
322                 __m128i mbp2;
323 #endif
324
325                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
326                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
327                 /* Read desc statuses backwards to avoid race condition */
328                 /* A.1 load 4 pkts desc */
329                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
330                 rte_compiler_barrier();
331
332                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
333                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
334
335 #if defined(RTE_ARCH_X86_64)
336                 /* B.1 load 2 64 bit mbuf points */
337                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
338 #endif
339
340                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
341                 rte_compiler_barrier();
342                 /* B.1 load 2 mbuf point */
343                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
344                 rte_compiler_barrier();
345                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
346
347 #if defined(RTE_ARCH_X86_64)
348                 /* B.2 copy 2 mbuf point into rx_pkts  */
349                 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
350 #endif
351
352                 if (split_packet) {
353                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
354                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
355                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
356                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
357                 }
358
359                 /* avoid compiler reorder optimization */
360                 rte_compiler_barrier();
361
362                 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
363                 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
364                 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
365
366                 /* merge the now-aligned packet length fields back in */
367                 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
368                 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
369
370                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
371                 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
372                 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
373
374                 /* C.1 4=>2 filter staterr info only */
375                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
376                 /* C.1 4=>2 filter staterr info only */
377                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
378
379                 ice_rx_desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
380
381                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
382                 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
383                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
384
385                 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
386                 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
387                 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
388
389                 /* merge the now-aligned packet length fields back in */
390                 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
391                 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
392
393                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
394                 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
395                 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
396
397                 /* C.2 get 4 pkts staterr value  */
398                 zero = _mm_xor_si128(dd_check, dd_check);
399                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
400
401                 /* D.3 copy final 3,4 data to rx_pkts */
402                 _mm_storeu_si128
403                         ((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
404                          pkt_mb4);
405                 _mm_storeu_si128
406                         ((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
407                          pkt_mb3);
408
409                 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
410                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
411                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
412
413                 /* C* extract and record EOP bit */
414                 if (split_packet) {
415                         __m128i eop_shuf_mask = _mm_set_epi8(0xFF, 0xFF,
416                                                              0xFF, 0xFF,
417                                                              0xFF, 0xFF,
418                                                              0xFF, 0xFF,
419                                                              0xFF, 0xFF,
420                                                              0xFF, 0xFF,
421                                                              0x04, 0x0C,
422                                                              0x00, 0x08);
423
424                         /* and with mask to extract bits, flipping 1-0 */
425                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
426                         /* the staterr values are not in order, as the count
427                          * count of dd bits doesn't care. However, for end of
428                          * packet tracking, we do care, so shuffle. This also
429                          * compresses the 32-bit values to 8-bit
430                          */
431                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
432                         /* store the resulting 32-bit value */
433                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
434                         split_packet += ICE_DESCS_PER_LOOP;
435                 }
436
437                 /* C.3 calc available number of desc */
438                 staterr = _mm_and_si128(staterr, dd_check);
439                 staterr = _mm_packs_epi32(staterr, zero);
440
441                 /* D.3 copy final 1,2 data to rx_pkts */
442                 _mm_storeu_si128
443                         ((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
444                          pkt_mb2);
445                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
446                                  pkt_mb1);
447                 ice_rx_desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
448                 /* C.4 calc avaialbe number of desc */
449                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
450                 nb_pkts_recd += var;
451                 if (likely(var != ICE_DESCS_PER_LOOP))
452                         break;
453         }
454
455         /* Update our internal tail pointer */
456         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
457         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
458         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
459
460         return nb_pkts_recd;
461 }
462
463 /**
464  * Notice:
465  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
466  * - nb_pkts > ICE_VPMD_RX_BURST, only scan ICE_VPMD_RX_BURST
467  *   numbers of DD bits
468  */
469 uint16_t
470 ice_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
471                   uint16_t nb_pkts)
472 {
473         return _ice_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
474 }
475
476 /* vPMD receive routine that reassembles scattered packets
477  * Notice:
478  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
479  * - nb_pkts > ICE_VPMD_RX_BURST, only scan ICE_VPMD_RX_BURST
480  *   numbers of DD bits
481  */
482 uint16_t
483 ice_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
484                             uint16_t nb_pkts)
485 {
486         struct ice_rx_queue *rxq = rx_queue;
487         uint8_t split_flags[ICE_VPMD_RX_BURST] = {0};
488
489         /* get some new buffers */
490         uint16_t nb_bufs = _ice_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
491                                                   split_flags);
492         if (nb_bufs == 0)
493                 return 0;
494
495         /* happy day case, full burst + no packets to be joined */
496         const uint64_t *split_fl64 = (uint64_t *)split_flags;
497
498         if (!rxq->pkt_first_seg &&
499             split_fl64[0] == 0 && split_fl64[1] == 0 &&
500             split_fl64[2] == 0 && split_fl64[3] == 0)
501                 return nb_bufs;
502
503         /* reassemble any packets that need reassembly*/
504         unsigned int i = 0;
505
506         if (!rxq->pkt_first_seg) {
507                 /* find the first split flag, and only reassemble then*/
508                 while (i < nb_bufs && !split_flags[i])
509                         i++;
510                 if (i == nb_bufs)
511                         return nb_bufs;
512         }
513         return i + ice_rx_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
514                                              &split_flags[i]);
515 }
516
517 static inline void
518 ice_vtx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf *pkt,
519          uint64_t flags)
520 {
521         uint64_t high_qw =
522                 (ICE_TX_DESC_DTYPE_DATA |
523                  ((uint64_t)flags  << ICE_TXD_QW1_CMD_S) |
524                  ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));
525
526         __m128i descriptor = _mm_set_epi64x(high_qw,
527                                             pkt->buf_iova + pkt->data_off);
528         _mm_store_si128((__m128i *)txdp, descriptor);
529 }
530
531 static inline void
532 ice_vtx(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkt,
533         uint16_t nb_pkts, uint64_t flags)
534 {
535         int i;
536
537         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
538                 ice_vtx1(txdp, *pkt, flags);
539 }
540
541 static uint16_t
542 ice_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
543                          uint16_t nb_pkts)
544 {
545         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
546         volatile struct ice_tx_desc *txdp;
547         struct ice_tx_entry *txep;
548         uint16_t n, nb_commit, tx_id;
549         uint64_t flags = ICE_TD_CMD;
550         uint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;
551         int i;
552
553         /* cross rx_thresh boundary is not allowed */
554         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
555
556         if (txq->nb_tx_free < txq->tx_free_thresh)
557                 ice_tx_free_bufs(txq);
558
559         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
560         nb_commit = nb_pkts;
561         if (unlikely(nb_pkts == 0))
562                 return 0;
563
564         tx_id = txq->tx_tail;
565         txdp = &txq->tx_ring[tx_id];
566         txep = &txq->sw_ring[tx_id];
567
568         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
569
570         n = (uint16_t)(txq->nb_tx_desc - tx_id);
571         if (nb_commit >= n) {
572                 ice_tx_backlog_entry(txep, tx_pkts, n);
573
574                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
575                         ice_vtx1(txdp, *tx_pkts, flags);
576
577                 ice_vtx1(txdp, *tx_pkts++, rs);
578
579                 nb_commit = (uint16_t)(nb_commit - n);
580
581                 tx_id = 0;
582                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
583
584                 /* avoid reach the end of ring */
585                 txdp = &txq->tx_ring[tx_id];
586                 txep = &txq->sw_ring[tx_id];
587         }
588
589         ice_tx_backlog_entry(txep, tx_pkts, nb_commit);
590
591         ice_vtx(txdp, tx_pkts, nb_commit, flags);
592
593         tx_id = (uint16_t)(tx_id + nb_commit);
594         if (tx_id > txq->tx_next_rs) {
595                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
596                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
597                                          ICE_TXD_QW1_CMD_S);
598                 txq->tx_next_rs =
599                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
600         }
601
602         txq->tx_tail = tx_id;
603
604         ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
605
606         return nb_pkts;
607 }
608
609 uint16_t
610 ice_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
611                   uint16_t nb_pkts)
612 {
613         uint16_t nb_tx = 0;
614         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
615
616         while (nb_pkts) {
617                 uint16_t ret, num;
618
619                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
620                 ret = ice_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);
621                 nb_tx += ret;
622                 nb_pkts -= ret;
623                 if (ret < num)
624                         break;
625         }
626
627         return nb_tx;
628 }
629
630 int __attribute__((cold))
631 ice_rxq_vec_setup(struct ice_rx_queue *rxq)
632 {
633         if (!rxq)
634                 return -1;
635
636         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs_vec;
637         return ice_rxq_vec_setup_default(rxq);
638 }
639
640 int __attribute__((cold))
641 ice_txq_vec_setup(struct ice_tx_queue __rte_unused *txq)
642 {
643         if (!txq)
644                 return -1;
645
646         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs_vec;
647         return 0;
648 }
649
650 int __attribute__((cold))
651 ice_rx_vec_dev_check(struct rte_eth_dev *dev)
652 {
653         return ice_rx_vec_dev_check_default(dev);
654 }
655
656 int __attribute__((cold))
657 ice_tx_vec_dev_check(struct rte_eth_dev *dev)
658 {
659         return ice_tx_vec_dev_check_default(dev);
660 }