drivers/net/ice/ice_rxtx_vec_sse.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #include "ice_rxtx_vec_common.h"
   6
   7 #include <tmmintrin.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 static inline __m128i
  14 ice_flex_rxd_to_fdir_flags_vec(const __m128i fdir_id0_3)
  15 {
  16 #define FDID_MIS_MAGIC 0xFFFFFFFF
  17         RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));
  18         RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
  19         const __m128i pkt_fdir_bit = _mm_set1_epi32(PKT_RX_FDIR |
  20                         PKT_RX_FDIR_ID);
  21         /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
  22         const __m128i fdir_mis_mask = _mm_set1_epi32(FDID_MIS_MAGIC);
  23         __m128i fdir_mask = _mm_cmpeq_epi32(fdir_id0_3,
  24                         fdir_mis_mask);
  25         /* this XOR op results to bit-reverse the fdir_mask */
  26         fdir_mask = _mm_xor_si128(fdir_mask, fdir_mis_mask);
  27         const __m128i fdir_flags = _mm_and_si128(fdir_mask, pkt_fdir_bit);
  28
  29         return fdir_flags;
  30 }
  31
  32 static inline void
  33 ice_rxq_rearm(struct ice_rx_queue *rxq)
  34 {
  35         int i;
  36         uint16_t rx_id;
  37         volatile union ice_rx_flex_desc *rxdp;
  38         struct ice_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
  39         struct rte_mbuf *mb0, *mb1;
  40         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  41                                           RTE_PKTMBUF_HEADROOM);
  42         __m128i dma_addr0, dma_addr1;
  43
  44         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  45
  46         /* Pull 'n' more MBUFs into the software ring */
  47         if (rte_mempool_get_bulk(rxq->mp,
  48                                  (void *)rxep,
  49                                  ICE_RXQ_REARM_THRESH) < 0) {
  50                 if (rxq->rxrearm_nb + ICE_RXQ_REARM_THRESH >=
  51                     rxq->nb_rx_desc) {
  52                         dma_addr0 = _mm_setzero_si128();
  53                         for (i = 0; i < ICE_DESCS_PER_LOOP; i++) {
  54                                 rxep[i].mbuf = &rxq->fake_mbuf;
  55                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  56                                                 dma_addr0);
  57                         }
  58                 }
  59                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  60                         ICE_RXQ_REARM_THRESH;
  61                 return;
  62         }
  63
  64         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  65         for (i = 0; i < ICE_RXQ_REARM_THRESH; i += 2, rxep += 2) {
  66                 __m128i vaddr0, vaddr1;
  67
  68                 mb0 = rxep[0].mbuf;
  69                 mb1 = rxep[1].mbuf;
  70
  71                 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
  72                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
  73                                  offsetof(struct rte_mbuf, buf_addr) + 8);
  74                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  75                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  76
  77                 /* convert pa to dma_addr hdr/data */
  78                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
  79                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
  80
  81                 /* add headroom to pa values */
  82                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
  83                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
  84
  85                 /* flush desc with pa dma_addr */
  86                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
  87                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
  88         }
  89
  90         rxq->rxrearm_start += ICE_RXQ_REARM_THRESH;
  91         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
  92                 rxq->rxrearm_start = 0;
  93
  94         rxq->rxrearm_nb -= ICE_RXQ_REARM_THRESH;
  95
  96         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
  97                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
  98
  99         /* Update the tail pointer on the NIC */
 100         ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 101 }
 102
 103 static inline void
 104 ice_rx_desc_to_olflags_v(struct ice_rx_queue *rxq, __m128i descs[4],
 105                          struct rte_mbuf **rx_pkts)
 106 {
 107         const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
 108         __m128i rearm0, rearm1, rearm2, rearm3;
 109
 110         __m128i tmp_desc, flags, rss_vlan;
 111
 112         /* mask everything except checksum, RSS and VLAN flags.
 113          * bit6:4 for checksum.
 114          * bit12 for RSS indication.
 115          * bit13 for VLAN indication.
 116          */
 117         const __m128i desc_mask = _mm_set_epi32(0x3070, 0x3070,
 118                                                 0x3070, 0x3070);
 119
 120         const __m128i cksum_mask = _mm_set_epi32(PKT_RX_IP_CKSUM_MASK |
 121                                                  PKT_RX_L4_CKSUM_MASK |
 122                                                  PKT_RX_EIP_CKSUM_BAD,
 123                                                  PKT_RX_IP_CKSUM_MASK |
 124                                                  PKT_RX_L4_CKSUM_MASK |
 125                                                  PKT_RX_EIP_CKSUM_BAD,
 126                                                  PKT_RX_IP_CKSUM_MASK |
 127                                                  PKT_RX_L4_CKSUM_MASK |
 128                                                  PKT_RX_EIP_CKSUM_BAD,
 129                                                  PKT_RX_IP_CKSUM_MASK |
 130                                                  PKT_RX_L4_CKSUM_MASK |
 131                                                  PKT_RX_EIP_CKSUM_BAD);
 132
 133         /* map the checksum, rss and vlan fields to the checksum, rss
 134          * and vlan flag
 135          */
 136         const __m128i cksum_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 137                         /* shift right 1 bit to make sure it not exceed 255 */
 138                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 139                          PKT_RX_IP_CKSUM_BAD) >> 1,
 140                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 141                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 142                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 143                          PKT_RX_IP_CKSUM_BAD) >> 1,
 144                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
 145                          PKT_RX_IP_CKSUM_GOOD) >> 1,
 146                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 147                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
 148                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
 149                         (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
 150
 151         const __m128i rss_vlan_flags = _mm_set_epi8(0, 0, 0, 0,
 152                         0, 0, 0, 0,
 153                         0, 0, 0, 0,
 154                         PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 155                         PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
 156                         PKT_RX_RSS_HASH, 0);
 157
 158         /* merge 4 descriptors */
 159         flags = _mm_unpackhi_epi32(descs[0], descs[1]);
 160         tmp_desc = _mm_unpackhi_epi32(descs[2], descs[3]);
 161         tmp_desc = _mm_unpacklo_epi64(flags, tmp_desc);
 162         tmp_desc = _mm_and_si128(tmp_desc, desc_mask);
 163
 164         /* checksum flags */
 165         tmp_desc = _mm_srli_epi32(tmp_desc, 4);
 166         flags = _mm_shuffle_epi8(cksum_flags, tmp_desc);
 167         /* then we shift left 1 bit */
 168         flags = _mm_slli_epi32(flags, 1);
 169         /* we need to mask out the reduntant bits introduced by RSS or
 170          * VLAN fields.
 171          */
 172         flags = _mm_and_si128(flags, cksum_mask);
 173
 174         /* RSS, VLAN flag */
 175         tmp_desc = _mm_srli_epi32(tmp_desc, 8);
 176         rss_vlan = _mm_shuffle_epi8(rss_vlan_flags, tmp_desc);
 177
 178         /* merge the flags */
 179         flags = _mm_or_si128(flags, rss_vlan);
 180
 181         if (rxq->fdir_enabled) {
 182                 const __m128i fdir_id0_1 =
 183                         _mm_unpackhi_epi32(descs[0], descs[1]);
 184
 185                 const __m128i fdir_id2_3 =
 186                         _mm_unpackhi_epi32(descs[2], descs[3]);
 187
 188                 const __m128i fdir_id0_3 =
 189                         _mm_unpackhi_epi64(fdir_id0_1, fdir_id2_3);
 190
 191                 const __m128i fdir_flags =
 192                         ice_flex_rxd_to_fdir_flags_vec(fdir_id0_3);
 193
 194                 /* merge with fdir_flags */
 195                 flags = _mm_or_si128(flags, fdir_flags);
 196
 197                 /* write fdir_id to mbuf */
 198                 rx_pkts[0]->hash.fdir.hi =
 199                         _mm_extract_epi32(fdir_id0_3, 0);
 200
 201                 rx_pkts[1]->hash.fdir.hi =
 202                         _mm_extract_epi32(fdir_id0_3, 1);
 203
 204                 rx_pkts[2]->hash.fdir.hi =
 205                         _mm_extract_epi32(fdir_id0_3, 2);
 206
 207                 rx_pkts[3]->hash.fdir.hi =
 208                         _mm_extract_epi32(fdir_id0_3, 3);
 209         } /* if() on fdir_enabled */
 210
 211         /**
 212          * At this point, we have the 4 sets of flags in the low 16-bits
 213          * of each 32-bit value in flags.
 214          * We want to extract these, and merge them with the mbuf init data
 215          * so we can do a single 16-byte write to the mbuf to set the flags
 216          * and all the other initialization fields. Extracting the
 217          * appropriate flags means that we have to do a shift and blend for
 218          * each mbuf before we do the write.
 219          */
 220         rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 8), 0x10);
 221         rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 4), 0x10);
 222         rearm2 = _mm_blend_epi16(mbuf_init, flags, 0x10);
 223         rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(flags, 4), 0x10);
 224
 225         /* write the rearm data and the olflags in one write */
 226         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 227                          offsetof(struct rte_mbuf, rearm_data) + 8);
 228         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 229                          RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
 230         _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
 231         _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
 232         _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
 233         _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
 234 }
 235
 236 static inline void
 237 ice_rx_desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,
 238                        uint32_t *ptype_tbl)
 239 {
 240         const __m128i ptype_mask = _mm_set_epi16(ICE_RX_FLEX_DESC_PTYPE_M, 0,
 241                                                  ICE_RX_FLEX_DESC_PTYPE_M, 0,
 242                                                  ICE_RX_FLEX_DESC_PTYPE_M, 0,
 243                                                  ICE_RX_FLEX_DESC_PTYPE_M, 0);
 244         __m128i ptype_01 = _mm_unpacklo_epi32(descs[0], descs[1]);
 245         __m128i ptype_23 = _mm_unpacklo_epi32(descs[2], descs[3]);
 246         __m128i ptype_all = _mm_unpacklo_epi64(ptype_01, ptype_23);
 247
 248         ptype_all = _mm_and_si128(ptype_all, ptype_mask);
 249
 250         rx_pkts[0]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 1)];
 251         rx_pkts[1]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 3)];
 252         rx_pkts[2]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 5)];
 253         rx_pkts[3]->packet_type = ptype_tbl[_mm_extract_epi16(ptype_all, 7)];
 254 }
 255
 256 /**
 257  * vPMD raw receive routine, only accept(nb_pkts >= ICE_DESCS_PER_LOOP)
 258  *
 259  * Notice:
 260  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 261  * - floor align nb_pkts to a ICE_DESCS_PER_LOOP power-of-two
 262  */
 263 static inline uint16_t
 264 _ice_recv_raw_pkts_vec(struct ice_rx_queue *rxq, struct rte_mbuf **rx_pkts,
 265                        uint16_t nb_pkts, uint8_t *split_packet)
 266 {
 267         volatile union ice_rx_flex_desc *rxdp;
 268         struct ice_rx_entry *sw_ring;
 269         uint16_t nb_pkts_recd;
 270         int pos;
 271         uint64_t var;
 272         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 273         __m128i crc_adjust = _mm_set_epi16
 274                                 (0, 0, 0,       /* ignore non-length fields */
 275                                  -rxq->crc_len, /* sub crc on data_len */
 276                                  0,          /* ignore high-16bits of pkt_len */
 277                                  -rxq->crc_len, /* sub crc on pkt_len */
 278                                  0, 0           /* ignore pkt_type field */
 279                                 );
 280         const __m128i zero = _mm_setzero_si128();
 281         /* mask to shuffle from desc. to mbuf */
 282         const __m128i shuf_msk = _mm_set_epi8
 283                         (0xFF, 0xFF,
 284                          0xFF, 0xFF,  /* rss hash parsed separately */
 285                          11, 10,      /* octet 10~11, 16 bits vlan_macip */
 286                          5, 4,        /* octet 4~5, 16 bits data_len */
 287                          0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 288                          5, 4,        /* octet 4~5, low 16 bits pkt_len */
 289                          0xFF, 0xFF,  /* pkt_type set as unknown */
 290                          0xFF, 0xFF   /* pkt_type set as unknown */
 291                         );
 292         const __m128i eop_shuf_mask = _mm_set_epi8(0xFF, 0xFF,
 293                                                    0xFF, 0xFF,
 294                                                    0xFF, 0xFF,
 295                                                    0xFF, 0xFF,
 296                                                    0xFF, 0xFF,
 297                                                    0xFF, 0xFF,
 298                                                    0x04, 0x0C,
 299                                                    0x00, 0x08);
 300
 301         /**
 302          * compile-time check the above crc_adjust layout is correct.
 303          * NOTE: the first field (lowest address) is given last in set_epi16
 304          * call above.
 305          */
 306         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 307                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 308         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 309                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 310
 311         /* 4 packets DD mask */
 312         const __m128i dd_check = _mm_set_epi64x(0x0000000100000001LL,
 313                                                 0x0000000100000001LL);
 314         /* 4 packets EOP mask */
 315         const __m128i eop_check = _mm_set_epi64x(0x0000000200000002LL,
 316                                                  0x0000000200000002LL);
 317
 318         /* nb_pkts has to be floor-aligned to ICE_DESCS_PER_LOOP */
 319         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, ICE_DESCS_PER_LOOP);
 320
 321         /* Just the act of getting into the function from the application is
 322          * going to cost about 7 cycles
 323          */
 324         rxdp = rxq->rx_ring + rxq->rx_tail;
 325
 326         rte_prefetch0(rxdp);
 327
 328         /* See if we need to rearm the RX queue - gives the prefetch a bit
 329          * of time to act
 330          */
 331         if (rxq->rxrearm_nb > ICE_RXQ_REARM_THRESH)
 332                 ice_rxq_rearm(rxq);
 333
 334         /* Before we start moving massive data around, check to see if
 335          * there is actually a packet available
 336          */
 337         if (!(rxdp->wb.status_error0 &
 338               rte_cpu_to_le_32(1 << ICE_RX_FLEX_DESC_STATUS0_DD_S)))
 339                 return 0;
 340
 341         /**
 342          * Compile-time verify the shuffle mask
 343          * NOTE: some field positions already verified above, but duplicated
 344          * here for completeness in case of future modifications.
 345          */
 346         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 347                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 348         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 349                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 350         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 351                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 352         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 353                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 354
 355         /* Cache is empty -> need to scan the buffer rings, but first move
 356          * the next 'n' mbufs into the cache
 357          */
 358         sw_ring = &rxq->sw_ring[rxq->rx_tail];
 359
 360         /* A. load 4 packet in one loop
 361          * [A*. mask out 4 unused dirty field in desc]
 362          * B. copy 4 mbuf point from swring to rx_pkts
 363          * C. calc the number of DD bits among the 4 packets
 364          * [C*. extract the end-of-packet bit, if requested]
 365          * D. fill info. from desc to mbuf
 366          */
 367
 368         for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
 369              pos += ICE_DESCS_PER_LOOP,
 370              rxdp += ICE_DESCS_PER_LOOP) {
 371                 __m128i descs[ICE_DESCS_PER_LOOP];
 372                 __m128i pkt_mb0, pkt_mb1, pkt_mb2, pkt_mb3;
 373                 __m128i staterr, sterr_tmp1, sterr_tmp2;
 374                 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
 375                 __m128i mbp1;
 376 #if defined(RTE_ARCH_X86_64)
 377                 __m128i mbp2;
 378 #endif
 379
 380                 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
 381                 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
 382                 /* Read desc statuses backwards to avoid race condition */
 383                 /* A.1 load 4 pkts desc */
 384                 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
 385                 rte_compiler_barrier();
 386
 387                 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
 388                 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
 389
 390 #if defined(RTE_ARCH_X86_64)
 391                 /* B.1 load 2 64 bit mbuf points */
 392                 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
 393 #endif
 394
 395                 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
 396                 rte_compiler_barrier();
 397                 /* B.1 load 2 mbuf point */
 398                 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
 399                 rte_compiler_barrier();
 400                 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
 401
 402 #if defined(RTE_ARCH_X86_64)
 403                 /* B.2 copy 2 mbuf point into rx_pkts  */
 404                 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
 405 #endif
 406
 407                 if (split_packet) {
 408                         rte_mbuf_prefetch_part2(rx_pkts[pos]);
 409                         rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
 410                         rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
 411                         rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
 412                 }
 413
 414                 /* avoid compiler reorder optimization */
 415                 rte_compiler_barrier();
 416
 417                 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
 418                 pkt_mb3 = _mm_shuffle_epi8(descs[3], shuf_msk);
 419                 pkt_mb2 = _mm_shuffle_epi8(descs[2], shuf_msk);
 420
 421                 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
 422                 pkt_mb1 = _mm_shuffle_epi8(descs[1], shuf_msk);
 423                 pkt_mb0 = _mm_shuffle_epi8(descs[0], shuf_msk);
 424
 425                 /* C.1 4=>2 filter staterr info only */
 426                 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
 427                 /* C.1 4=>2 filter staterr info only */
 428                 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
 429
 430                 ice_rx_desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
 431
 432                 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
 433                 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
 434                 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
 435
 436                 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
 437                 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
 438                 pkt_mb0 = _mm_add_epi16(pkt_mb0, crc_adjust);
 439
 440 #ifndef RTE_LIBRTE_ICE_16BYTE_RX_DESC
 441                 /**
 442                  * needs to load 2nd 16B of each desc for RSS hash parsing,
 443                  * will cause performance drop to get into this context.
 444                  */
 445                 if (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &
 446                                 DEV_RX_OFFLOAD_RSS_HASH) {
 447                         /* load bottom half of every 32B desc */
 448                         const __m128i raw_desc_bh3 =
 449                                 _mm_load_si128
 450                                         ((void *)(&rxdp[3].wb.status_error1));
 451                         rte_compiler_barrier();
 452                         const __m128i raw_desc_bh2 =
 453                                 _mm_load_si128
 454                                         ((void *)(&rxdp[2].wb.status_error1));
 455                         rte_compiler_barrier();
 456                         const __m128i raw_desc_bh1 =
 457                                 _mm_load_si128
 458                                         ((void *)(&rxdp[1].wb.status_error1));
 459                         rte_compiler_barrier();
 460                         const __m128i raw_desc_bh0 =
 461                                 _mm_load_si128
 462                                         ((void *)(&rxdp[0].wb.status_error1));
 463
 464                         /**
 465                          * to shift the 32b RSS hash value to the
 466                          * highest 32b of each 128b before mask
 467                          */
 468                         __m128i rss_hash3 =
 469                                 _mm_slli_epi64(raw_desc_bh3, 32);
 470                         __m128i rss_hash2 =
 471                                 _mm_slli_epi64(raw_desc_bh2, 32);
 472                         __m128i rss_hash1 =
 473                                 _mm_slli_epi64(raw_desc_bh1, 32);
 474                         __m128i rss_hash0 =
 475                                 _mm_slli_epi64(raw_desc_bh0, 32);
 476
 477                         __m128i rss_hash_msk =
 478                                 _mm_set_epi32(0xFFFFFFFF, 0, 0, 0);
 479
 480                         rss_hash3 = _mm_and_si128
 481                                         (rss_hash3, rss_hash_msk);
 482                         rss_hash2 = _mm_and_si128
 483                                         (rss_hash2, rss_hash_msk);
 484                         rss_hash1 = _mm_and_si128
 485                                         (rss_hash1, rss_hash_msk);
 486                         rss_hash0 = _mm_and_si128
 487                                         (rss_hash0, rss_hash_msk);
 488
 489                         pkt_mb3 = _mm_or_si128(pkt_mb3, rss_hash3);
 490                         pkt_mb2 = _mm_or_si128(pkt_mb2, rss_hash2);
 491                         pkt_mb1 = _mm_or_si128(pkt_mb1, rss_hash1);
 492                         pkt_mb0 = _mm_or_si128(pkt_mb0, rss_hash0);
 493                 } /* if() on RSS hash parsing */
 494 #endif
 495
 496                 /* C.2 get 4 pkts staterr value  */
 497                 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
 498
 499                 /* D.3 copy final 3,4 data to rx_pkts */
 500                 _mm_storeu_si128
 501                         ((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
 502                          pkt_mb3);
 503                 _mm_storeu_si128
 504                         ((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
 505                          pkt_mb2);
 506
 507                 /* C* extract and record EOP bit */
 508                 if (split_packet) {
 509                         /* and with mask to extract bits, flipping 1-0 */
 510                         __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
 511                         /* the staterr values are not in order, as the count
 512                          * count of dd bits doesn't care. However, for end of
 513                          * packet tracking, we do care, so shuffle. This also
 514                          * compresses the 32-bit values to 8-bit
 515                          */
 516                         eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
 517                         /* store the resulting 32-bit value */
 518                         *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
 519                         split_packet += ICE_DESCS_PER_LOOP;
 520                 }
 521
 522                 /* C.3 calc available number of desc */
 523                 staterr = _mm_and_si128(staterr, dd_check);
 524                 staterr = _mm_packs_epi32(staterr, zero);
 525
 526                 /* D.3 copy final 1,2 data to rx_pkts */
 527                 _mm_storeu_si128
 528                         ((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
 529                          pkt_mb1);
 530                 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
 531                                  pkt_mb0);
 532                 ice_rx_desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
 533                 /* C.4 calc avaialbe number of desc */
 534                 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
 535                 nb_pkts_recd += var;
 536                 if (likely(var != ICE_DESCS_PER_LOOP))
 537                         break;
 538         }
 539
 540         /* Update our internal tail pointer */
 541         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
 542         rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
 543         rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
 544
 545         return nb_pkts_recd;
 546 }
 547
 548 /**
 549  * Notice:
 550  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 551  * - nb_pkts > ICE_VPMD_RX_BURST, only scan ICE_VPMD_RX_BURST
 552  *   numbers of DD bits
 553  */
 554 uint16_t
 555 ice_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 556                   uint16_t nb_pkts)
 557 {
 558         return _ice_recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
 559 }
 560
 561 /**
 562  * vPMD receive routine that reassembles single burst of 32 scattered packets
 563  *
 564  * Notice:
 565  * - nb_pkts < ICE_DESCS_PER_LOOP, just return no packet
 566  */
 567 static uint16_t
 568 ice_recv_scattered_burst_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 569                              uint16_t nb_pkts)
 570 {
 571         struct ice_rx_queue *rxq = rx_queue;
 572         uint8_t split_flags[ICE_VPMD_RX_BURST] = {0};
 573
 574         /* get some new buffers */
 575         uint16_t nb_bufs = _ice_recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
 576                                                   split_flags);
 577         if (nb_bufs == 0)
 578                 return 0;
 579
 580         /* happy day case, full burst + no packets to be joined */
 581         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 582
 583         if (!rxq->pkt_first_seg &&
 584             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 585             split_fl64[2] == 0 && split_fl64[3] == 0)
 586                 return nb_bufs;
 587
 588         /* reassemble any packets that need reassembly*/
 589         unsigned int i = 0;
 590
 591         if (!rxq->pkt_first_seg) {
 592                 /* find the first split flag, and only reassemble then*/
 593                 while (i < nb_bufs && !split_flags[i])
 594                         i++;
 595                 if (i == nb_bufs)
 596                         return nb_bufs;
 597                 rxq->pkt_first_seg = rx_pkts[i];
 598         }
 599         return i + ice_rx_reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 600                                              &split_flags[i]);
 601 }
 602
 603 /**
 604  * vPMD receive routine that reassembles scattered packets.
 605  */
 606 uint16_t
 607 ice_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
 608                             uint16_t nb_pkts)
 609 {
 610         uint16_t retval = 0;
 611
 612         while (nb_pkts > ICE_VPMD_RX_BURST) {
 613                 uint16_t burst;
 614
 615                 burst = ice_recv_scattered_burst_vec(rx_queue,
 616                                                      rx_pkts + retval,
 617                                                      ICE_VPMD_RX_BURST);
 618                 retval += burst;
 619                 nb_pkts -= burst;
 620                 if (burst < ICE_VPMD_RX_BURST)
 621                         return retval;
 622         }
 623
 624         return retval + ice_recv_scattered_burst_vec(rx_queue,
 625                                                      rx_pkts + retval,
 626                                                      nb_pkts);
 627 }
 628
 629 static inline void
 630 ice_vtx1(volatile struct ice_tx_desc *txdp, struct rte_mbuf *pkt,
 631          uint64_t flags)
 632 {
 633         uint64_t high_qw =
 634                 (ICE_TX_DESC_DTYPE_DATA |
 635                  ((uint64_t)flags  << ICE_TXD_QW1_CMD_S) |
 636                  ((uint64_t)pkt->data_len << ICE_TXD_QW1_TX_BUF_SZ_S));
 637
 638         __m128i descriptor = _mm_set_epi64x(high_qw,
 639                                             pkt->buf_iova + pkt->data_off);
 640         _mm_store_si128((__m128i *)txdp, descriptor);
 641 }
 642
 643 static inline void
 644 ice_vtx(volatile struct ice_tx_desc *txdp, struct rte_mbuf **pkt,
 645         uint16_t nb_pkts, uint64_t flags)
 646 {
 647         int i;
 648
 649         for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
 650                 ice_vtx1(txdp, *pkt, flags);
 651 }
 652
 653 static uint16_t
 654 ice_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 655                          uint16_t nb_pkts)
 656 {
 657         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
 658         volatile struct ice_tx_desc *txdp;
 659         struct ice_tx_entry *txep;
 660         uint16_t n, nb_commit, tx_id;
 661         uint64_t flags = ICE_TD_CMD;
 662         uint64_t rs = ICE_TX_DESC_CMD_RS | ICE_TD_CMD;
 663         int i;
 664
 665         /* cross rx_thresh boundary is not allowed */
 666         nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 667
 668         if (txq->nb_tx_free < txq->tx_free_thresh)
 669                 ice_tx_free_bufs(txq);
 670
 671         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
 672         nb_commit = nb_pkts;
 673         if (unlikely(nb_pkts == 0))
 674                 return 0;
 675
 676         tx_id = txq->tx_tail;
 677         txdp = &txq->tx_ring[tx_id];
 678         txep = &txq->sw_ring[tx_id];
 679
 680         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
 681
 682         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 683         if (nb_commit >= n) {
 684                 ice_tx_backlog_entry(txep, tx_pkts, n);
 685
 686                 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
 687                         ice_vtx1(txdp, *tx_pkts, flags);
 688
 689                 ice_vtx1(txdp, *tx_pkts++, rs);
 690
 691                 nb_commit = (uint16_t)(nb_commit - n);
 692
 693                 tx_id = 0;
 694                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
 695
 696                 /* avoid reach the end of ring */
 697                 txdp = &txq->tx_ring[tx_id];
 698                 txep = &txq->sw_ring[tx_id];
 699         }
 700
 701         ice_tx_backlog_entry(txep, tx_pkts, nb_commit);
 702
 703         ice_vtx(txdp, tx_pkts, nb_commit, flags);
 704
 705         tx_id = (uint16_t)(tx_id + nb_commit);
 706         if (tx_id > txq->tx_next_rs) {
 707                 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
 708                         rte_cpu_to_le_64(((uint64_t)ICE_TX_DESC_CMD_RS) <<
 709                                          ICE_TXD_QW1_CMD_S);
 710                 txq->tx_next_rs =
 711                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
 712         }
 713
 714         txq->tx_tail = tx_id;
 715
 716         ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
 717
 718         return nb_pkts;
 719 }
 720
 721 uint16_t
 722 ice_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
 723                   uint16_t nb_pkts)
 724 {
 725         uint16_t nb_tx = 0;
 726         struct ice_tx_queue *txq = (struct ice_tx_queue *)tx_queue;
 727
 728         while (nb_pkts) {
 729                 uint16_t ret, num;
 730
 731                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
 732                 ret = ice_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);
 733                 nb_tx += ret;
 734                 nb_pkts -= ret;
 735                 if (ret < num)
 736                         break;
 737         }
 738
 739         return nb_tx;
 740 }
 741
 742 int __rte_cold
 743 ice_rxq_vec_setup(struct ice_rx_queue *rxq)
 744 {
 745         if (!rxq)
 746                 return -1;
 747
 748         rxq->rx_rel_mbufs = _ice_rx_queue_release_mbufs_vec;
 749         return ice_rxq_vec_setup_default(rxq);
 750 }
 751
 752 int __rte_cold
 753 ice_txq_vec_setup(struct ice_tx_queue __rte_unused *txq)
 754 {
 755         if (!txq)
 756                 return -1;
 757
 758         txq->tx_rel_mbufs = _ice_tx_queue_release_mbufs_vec;
 759         return 0;
 760 }
 761
 762 int __rte_cold
 763 ice_rx_vec_dev_check(struct rte_eth_dev *dev)
 764 {
 765         return ice_rx_vec_dev_check_default(dev);
 766 }
 767
 768 int __rte_cold
 769 ice_tx_vec_dev_check(struct rte_eth_dev *dev)
 770 {
 771         return ice_tx_vec_dev_check_default(dev);
 772 }