1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Intel Corporation
6 #include "ifcvf_osdep.h"
9 get_cap_addr(struct ifcvf_hw *hw, struct ifcvf_pci_cap *cap)
12 u32 length = cap->length;
13 u32 offset = cap->offset;
15 if (bar > IFCVF_PCI_MAX_RESOURCE - 1) {
16 DEBUGOUT("invalid bar: %u\n", bar);
20 if (offset + length < offset) {
21 DEBUGOUT("offset(%u) + length(%u) overflows\n",
26 if (offset + length > hw->mem_resource[cap->bar].len) {
27 DEBUGOUT("offset(%u) + length(%u) overflows bar length(%u)",
28 offset, length, (u32)hw->mem_resource[cap->bar].len);
32 return hw->mem_resource[bar].addr + offset;
36 ifcvf_init_hw(struct ifcvf_hw *hw, PCI_DEV *dev)
40 struct ifcvf_pci_cap cap;
42 ret = PCI_READ_CONFIG_BYTE(dev, &pos, PCI_CAPABILITY_LIST);
44 DEBUGOUT("failed to read pci capability list\n");
49 ret = PCI_READ_CONFIG_RANGE(dev, (u32 *)&cap,
52 DEBUGOUT("failed to read cap at pos: %x", pos);
56 if (cap.cap_vndr != PCI_CAP_ID_VNDR)
59 DEBUGOUT("cfg type: %u, bar: %u, offset: %u, "
60 "len: %u\n", cap.cfg_type, cap.bar,
61 cap.offset, cap.length);
63 switch (cap.cfg_type) {
64 case IFCVF_PCI_CAP_COMMON_CFG:
65 hw->common_cfg = get_cap_addr(hw, &cap);
67 case IFCVF_PCI_CAP_NOTIFY_CFG:
68 PCI_READ_CONFIG_DWORD(dev, &hw->notify_off_multiplier,
70 hw->notify_base = get_cap_addr(hw, &cap);
71 hw->notify_region = cap.bar;
73 case IFCVF_PCI_CAP_ISR_CFG:
74 hw->isr = get_cap_addr(hw, &cap);
76 case IFCVF_PCI_CAP_DEVICE_CFG:
77 hw->dev_cfg = get_cap_addr(hw, &cap);
84 hw->lm_cfg = hw->mem_resource[4].addr;
86 if (hw->common_cfg == NULL || hw->notify_base == NULL ||
87 hw->isr == NULL || hw->dev_cfg == NULL) {
88 DEBUGOUT("capability incomplete\n");
92 DEBUGOUT("capability mapping:\ncommon cfg: %p\n"
93 "notify base: %p\nisr cfg: %p\ndevice cfg: %p\n"
95 hw->common_cfg, hw->dev_cfg,
96 hw->isr, hw->notify_base,
97 hw->notify_off_multiplier);
103 ifcvf_get_status(struct ifcvf_hw *hw)
105 return IFCVF_READ_REG8(&hw->common_cfg->device_status);
109 ifcvf_set_status(struct ifcvf_hw *hw, u8 status)
111 IFCVF_WRITE_REG8(status, &hw->common_cfg->device_status);
115 ifcvf_reset(struct ifcvf_hw *hw)
117 ifcvf_set_status(hw, 0);
119 /* flush status write */
120 while (ifcvf_get_status(hw))
125 ifcvf_add_status(struct ifcvf_hw *hw, u8 status)
128 status |= ifcvf_get_status(hw);
130 ifcvf_set_status(hw, status);
131 ifcvf_get_status(hw);
135 ifcvf_get_features(struct ifcvf_hw *hw)
137 u32 features_lo, features_hi;
138 struct ifcvf_pci_common_cfg *cfg = hw->common_cfg;
140 IFCVF_WRITE_REG32(0, &cfg->device_feature_select);
141 features_lo = IFCVF_READ_REG32(&cfg->device_feature);
143 IFCVF_WRITE_REG32(1, &cfg->device_feature_select);
144 features_hi = IFCVF_READ_REG32(&cfg->device_feature);
146 return ((u64)features_hi << 32) | features_lo;
150 ifcvf_set_features(struct ifcvf_hw *hw, u64 features)
152 struct ifcvf_pci_common_cfg *cfg = hw->common_cfg;
154 IFCVF_WRITE_REG32(0, &cfg->guest_feature_select);
155 IFCVF_WRITE_REG32(features & ((1ULL << 32) - 1), &cfg->guest_feature);
157 IFCVF_WRITE_REG32(1, &cfg->guest_feature_select);
158 IFCVF_WRITE_REG32(features >> 32, &cfg->guest_feature);
162 ifcvf_config_features(struct ifcvf_hw *hw)
166 host_features = ifcvf_get_features(hw);
167 hw->req_features &= host_features;
169 ifcvf_set_features(hw, hw->req_features);
170 ifcvf_add_status(hw, IFCVF_CONFIG_STATUS_FEATURES_OK);
172 if (!(ifcvf_get_status(hw) & IFCVF_CONFIG_STATUS_FEATURES_OK)) {
173 DEBUGOUT("failed to set FEATURES_OK status\n");
181 io_write64_twopart(u64 val, u32 *lo, u32 *hi)
183 IFCVF_WRITE_REG32(val & ((1ULL << 32) - 1), lo);
184 IFCVF_WRITE_REG32(val >> 32, hi);
188 ifcvf_hw_enable(struct ifcvf_hw *hw)
190 struct ifcvf_pci_common_cfg *cfg;
195 cfg = hw->common_cfg;
198 IFCVF_WRITE_REG16(0, &cfg->msix_config);
199 if (IFCVF_READ_REG16(&cfg->msix_config) == IFCVF_MSI_NO_VECTOR) {
200 DEBUGOUT("msix vec alloc failed for device config\n");
204 for (i = 0; i < hw->nr_vring; i++) {
205 IFCVF_WRITE_REG16(i, &cfg->queue_select);
206 io_write64_twopart(hw->vring[i].desc, &cfg->queue_desc_lo,
207 &cfg->queue_desc_hi);
208 io_write64_twopart(hw->vring[i].avail, &cfg->queue_avail_lo,
209 &cfg->queue_avail_hi);
210 io_write64_twopart(hw->vring[i].used, &cfg->queue_used_lo,
211 &cfg->queue_used_hi);
212 IFCVF_WRITE_REG16(hw->vring[i].size, &cfg->queue_size);
214 *(u32 *)(lm_cfg + IFCVF_LM_RING_STATE_OFFSET +
215 (i / 2) * IFCVF_LM_CFG_SIZE + (i % 2) * 4) =
216 (u32)hw->vring[i].last_avail_idx |
217 ((u32)hw->vring[i].last_used_idx << 16);
219 IFCVF_WRITE_REG16(i + 1, &cfg->queue_msix_vector);
220 if (IFCVF_READ_REG16(&cfg->queue_msix_vector) ==
221 IFCVF_MSI_NO_VECTOR) {
222 DEBUGOUT("queue %u, msix vec alloc failed\n",
227 notify_off = IFCVF_READ_REG16(&cfg->queue_notify_off);
228 hw->notify_addr[i] = (void *)((u8 *)hw->notify_base +
229 notify_off * hw->notify_off_multiplier);
230 IFCVF_WRITE_REG16(1, &cfg->queue_enable);
237 ifcvf_hw_disable(struct ifcvf_hw *hw)
240 struct ifcvf_pci_common_cfg *cfg;
243 cfg = hw->common_cfg;
245 IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg->msix_config);
246 for (i = 0; i < hw->nr_vring; i++) {
247 IFCVF_WRITE_REG16(i, &cfg->queue_select);
248 IFCVF_WRITE_REG16(0, &cfg->queue_enable);
249 IFCVF_WRITE_REG16(IFCVF_MSI_NO_VECTOR, &cfg->queue_msix_vector);
250 ring_state = *(u32 *)(hw->lm_cfg + IFCVF_LM_RING_STATE_OFFSET +
251 (i / 2) * IFCVF_LM_CFG_SIZE + (i % 2) * 4);
252 hw->vring[i].last_avail_idx = (u16)ring_state;
253 hw->vring[i].last_used_idx = (u16)(ring_state >> 16);
258 ifcvf_start_hw(struct ifcvf_hw *hw)
261 ifcvf_add_status(hw, IFCVF_CONFIG_STATUS_ACK);
262 ifcvf_add_status(hw, IFCVF_CONFIG_STATUS_DRIVER);
264 if (ifcvf_config_features(hw) < 0)
267 if (ifcvf_hw_enable(hw) < 0)
270 ifcvf_add_status(hw, IFCVF_CONFIG_STATUS_DRIVER_OK);
275 ifcvf_stop_hw(struct ifcvf_hw *hw)
277 ifcvf_hw_disable(hw);
282 ifcvf_notify_queue(struct ifcvf_hw *hw, u16 qid)
284 IFCVF_WRITE_REG16(qid, hw->notify_addr[qid]);
288 ifcvf_get_notify_region(struct ifcvf_hw *hw)
290 return hw->notify_region;
294 ifcvf_get_queue_notify_off(struct ifcvf_hw *hw, int qid)
296 return (u8 *)hw->notify_addr[qid] -
297 (u8 *)hw->mem_resource[hw->notify_region].addr;