drivers/net/igc/base/igc_hw.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2020 Intel Corporation
   3  */
   4
   5 #ifndef _IGC_HW_H_
   6 #define _IGC_HW_H_
   7
   8 #include "igc_osdep.h"
   9 #include "igc_regs.h"
  10 #include "igc_defines.h"
  11
  12 struct igc_hw;
  13
  14 #define IGC_DEV_ID_82542                        0x1000
  15 #define IGC_DEV_ID_82543GC_FIBER                0x1001
  16 #define IGC_DEV_ID_82543GC_COPPER               0x1004
  17 #define IGC_DEV_ID_82544EI_COPPER               0x1008
  18 #define IGC_DEV_ID_82544EI_FIBER                0x1009
  19 #define IGC_DEV_ID_82544GC_COPPER               0x100C
  20 #define IGC_DEV_ID_82544GC_LOM          0x100D
  21 #define IGC_DEV_ID_82540EM                      0x100E
  22 #define IGC_DEV_ID_82540EM_LOM          0x1015
  23 #define IGC_DEV_ID_82540EP_LOM          0x1016
  24 #define IGC_DEV_ID_82540EP                      0x1017
  25 #define IGC_DEV_ID_82540EP_LP                   0x101E
  26 #define IGC_DEV_ID_82545EM_COPPER               0x100F
  27 #define IGC_DEV_ID_82545EM_FIBER                0x1011
  28 #define IGC_DEV_ID_82545GM_COPPER               0x1026
  29 #define IGC_DEV_ID_82545GM_FIBER                0x1027
  30 #define IGC_DEV_ID_82545GM_SERDES               0x1028
  31 #define IGC_DEV_ID_82546EB_COPPER               0x1010
  32 #define IGC_DEV_ID_82546EB_FIBER                0x1012
  33 #define IGC_DEV_ID_82546EB_QUAD_COPPER  0x101D
  34 #define IGC_DEV_ID_82546GB_COPPER               0x1079
  35 #define IGC_DEV_ID_82546GB_FIBER                0x107A
  36 #define IGC_DEV_ID_82546GB_SERDES               0x107B
  37 #define IGC_DEV_ID_82546GB_PCIE         0x108A
  38 #define IGC_DEV_ID_82546GB_QUAD_COPPER  0x1099
  39 #define IGC_DEV_ID_82546GB_QUAD_COPPER_KSP3     0x10B5
  40 #define IGC_DEV_ID_82541EI                      0x1013
  41 #define IGC_DEV_ID_82541EI_MOBILE               0x1018
  42 #define IGC_DEV_ID_82541ER_LOM          0x1014
  43 #define IGC_DEV_ID_82541ER                      0x1078
  44 #define IGC_DEV_ID_82541GI                      0x1076
  45 #define IGC_DEV_ID_82541GI_LF                   0x107C
  46 #define IGC_DEV_ID_82541GI_MOBILE               0x1077
  47 #define IGC_DEV_ID_82547EI                      0x1019
  48 #define IGC_DEV_ID_82547EI_MOBILE               0x101A
  49 #define IGC_DEV_ID_82547GI                      0x1075
  50 #define IGC_DEV_ID_82571EB_COPPER               0x105E
  51 #define IGC_DEV_ID_82571EB_FIBER                0x105F
  52 #define IGC_DEV_ID_82571EB_SERDES               0x1060
  53 #define IGC_DEV_ID_82571EB_SERDES_DUAL  0x10D9
  54 #define IGC_DEV_ID_82571EB_SERDES_QUAD  0x10DA
  55 #define IGC_DEV_ID_82571EB_QUAD_COPPER  0x10A4
  56 #define IGC_DEV_ID_82571PT_QUAD_COPPER  0x10D5
  57 #define IGC_DEV_ID_82571EB_QUAD_FIBER           0x10A5
  58 #define IGC_DEV_ID_82571EB_QUAD_COPPER_LP       0x10BC
  59 #define IGC_DEV_ID_82572EI_COPPER               0x107D
  60 #define IGC_DEV_ID_82572EI_FIBER                0x107E
  61 #define IGC_DEV_ID_82572EI_SERDES               0x107F
  62 #define IGC_DEV_ID_82572EI                      0x10B9
  63 #define IGC_DEV_ID_82573E                       0x108B
  64 #define IGC_DEV_ID_82573E_IAMT          0x108C
  65 #define IGC_DEV_ID_82573L                       0x109A
  66 #define IGC_DEV_ID_82574L                       0x10D3
  67 #define IGC_DEV_ID_82574LA                      0x10F6
  68 #define IGC_DEV_ID_82583V                       0x150C
  69 #define IGC_DEV_ID_80003ES2LAN_COPPER_DPT       0x1096
  70 #define IGC_DEV_ID_80003ES2LAN_SERDES_DPT       0x1098
  71 #define IGC_DEV_ID_80003ES2LAN_COPPER_SPT       0x10BA
  72 #define IGC_DEV_ID_80003ES2LAN_SERDES_SPT       0x10BB
  73 #define IGC_DEV_ID_ICH8_82567V_3                0x1501
  74 #define IGC_DEV_ID_ICH8_IGP_M_AMT               0x1049
  75 #define IGC_DEV_ID_ICH8_IGP_AMT         0x104A
  76 #define IGC_DEV_ID_ICH8_IGP_C                   0x104B
  77 #define IGC_DEV_ID_ICH8_IFE                     0x104C
  78 #define IGC_DEV_ID_ICH8_IFE_GT          0x10C4
  79 #define IGC_DEV_ID_ICH8_IFE_G                   0x10C5
  80 #define IGC_DEV_ID_ICH8_IGP_M                   0x104D
  81 #define IGC_DEV_ID_ICH9_IGP_M                   0x10BF
  82 #define IGC_DEV_ID_ICH9_IGP_M_AMT               0x10F5
  83 #define IGC_DEV_ID_ICH9_IGP_M_V         0x10CB
  84 #define IGC_DEV_ID_ICH9_IGP_AMT         0x10BD
  85 #define IGC_DEV_ID_ICH9_BM                      0x10E5
  86 #define IGC_DEV_ID_ICH9_IGP_C                   0x294C
  87 #define IGC_DEV_ID_ICH9_IFE                     0x10C0
  88 #define IGC_DEV_ID_ICH9_IFE_GT          0x10C3
  89 #define IGC_DEV_ID_ICH9_IFE_G                   0x10C2
  90 #define IGC_DEV_ID_ICH10_R_BM_LM                0x10CC
  91 #define IGC_DEV_ID_ICH10_R_BM_LF                0x10CD
  92 #define IGC_DEV_ID_ICH10_R_BM_V         0x10CE
  93 #define IGC_DEV_ID_ICH10_D_BM_LM                0x10DE
  94 #define IGC_DEV_ID_ICH10_D_BM_LF                0x10DF
  95 #define IGC_DEV_ID_ICH10_D_BM_V         0x1525
  96 #define IGC_DEV_ID_PCH_M_HV_LM          0x10EA
  97 #define IGC_DEV_ID_PCH_M_HV_LC          0x10EB
  98 #define IGC_DEV_ID_PCH_D_HV_DM          0x10EF
  99 #define IGC_DEV_ID_PCH_D_HV_DC          0x10F0
 100 #define IGC_DEV_ID_PCH2_LV_LM                   0x1502
 101 #define IGC_DEV_ID_PCH2_LV_V                    0x1503
 102 #define IGC_DEV_ID_PCH_LPT_I217_LM              0x153A
 103 #define IGC_DEV_ID_PCH_LPT_I217_V               0x153B
 104 #define IGC_DEV_ID_PCH_LPTLP_I218_LM            0x155A
 105 #define IGC_DEV_ID_PCH_LPTLP_I218_V             0x1559
 106 #define IGC_DEV_ID_PCH_I218_LM2         0x15A0
 107 #define IGC_DEV_ID_PCH_I218_V2          0x15A1
 108 #define IGC_DEV_ID_PCH_I218_LM3         0x15A2 /* Wildcat Point PCH */
 109 #define IGC_DEV_ID_PCH_I218_V3          0x15A3 /* Wildcat Point PCH */
 110 #define IGC_DEV_ID_PCH_SPT_I219_LM              0x156F /* Sunrise Point PCH */
 111 #define IGC_DEV_ID_PCH_SPT_I219_V               0x1570 /* Sunrise Point PCH */
 112 #define IGC_DEV_ID_PCH_SPT_I219_LM2             0x15B7 /* Sunrise Point-H PCH */
 113 #define IGC_DEV_ID_PCH_SPT_I219_V2              0x15B8 /* Sunrise Point-H PCH */
 114 #define IGC_DEV_ID_PCH_LBG_I219_LM3             0x15B9 /* LEWISBURG PCH */
 115 #define IGC_DEV_ID_PCH_SPT_I219_LM4             0x15D7
 116 #define IGC_DEV_ID_PCH_SPT_I219_V4              0x15D8
 117 #define IGC_DEV_ID_PCH_SPT_I219_LM5             0x15E3
 118 #define IGC_DEV_ID_PCH_SPT_I219_V5              0x15D6
 119 #define IGC_DEV_ID_PCH_CNP_I219_LM6             0x15BD
 120 #define IGC_DEV_ID_PCH_CNP_I219_V6              0x15BE
 121 #define IGC_DEV_ID_PCH_CNP_I219_LM7             0x15BB
 122 #define IGC_DEV_ID_PCH_CNP_I219_V7              0x15BC
 123 #define IGC_DEV_ID_PCH_ICP_I219_LM8             0x15DF
 124 #define IGC_DEV_ID_PCH_ICP_I219_V8              0x15E0
 125 #define IGC_DEV_ID_PCH_ICP_I219_LM9             0x15E1
 126 #define IGC_DEV_ID_PCH_ICP_I219_V9              0x15E2
 127 #define IGC_DEV_ID_82576                        0x10C9
 128 #define IGC_DEV_ID_82576_FIBER          0x10E6
 129 #define IGC_DEV_ID_82576_SERDES         0x10E7
 130 #define IGC_DEV_ID_82576_QUAD_COPPER            0x10E8
 131 #define IGC_DEV_ID_82576_QUAD_COPPER_ET2        0x1526
 132 #define IGC_DEV_ID_82576_NS                     0x150A
 133 #define IGC_DEV_ID_82576_NS_SERDES              0x1518
 134 #define IGC_DEV_ID_82576_SERDES_QUAD            0x150D
 135 #define IGC_DEV_ID_82576_VF                     0x10CA
 136 #define IGC_DEV_ID_82576_VF_HV          0x152D
 137 #define IGC_DEV_ID_I350_VF                      0x1520
 138 #define IGC_DEV_ID_I350_VF_HV                   0x152F
 139 #define IGC_DEV_ID_82575EB_COPPER               0x10A7
 140 #define IGC_DEV_ID_82575EB_FIBER_SERDES 0x10A9
 141 #define IGC_DEV_ID_82575GB_QUAD_COPPER  0x10D6
 142 #define IGC_DEV_ID_82580_COPPER         0x150E
 143 #define IGC_DEV_ID_82580_FIBER          0x150F
 144 #define IGC_DEV_ID_82580_SERDES         0x1510
 145 #define IGC_DEV_ID_82580_SGMII          0x1511
 146 #define IGC_DEV_ID_82580_COPPER_DUAL            0x1516
 147 #define IGC_DEV_ID_82580_QUAD_FIBER             0x1527
 148 #define IGC_DEV_ID_I350_COPPER          0x1521
 149 #define IGC_DEV_ID_I350_FIBER                   0x1522
 150 #define IGC_DEV_ID_I350_SERDES          0x1523
 151 #define IGC_DEV_ID_I350_SGMII                   0x1524
 152 #define IGC_DEV_ID_I350_DA4                     0x1546
 153 #define IGC_DEV_ID_I210_COPPER          0x1533
 154 #define IGC_DEV_ID_I210_COPPER_OEM1             0x1534
 155 #define IGC_DEV_ID_I210_COPPER_IT               0x1535
 156 #define IGC_DEV_ID_I210_FIBER                   0x1536
 157 #define IGC_DEV_ID_I210_SERDES          0x1537
 158 #define IGC_DEV_ID_I210_SGMII                   0x1538
 159 #define IGC_DEV_ID_I210_COPPER_FLASHLESS        0x157B
 160 #define IGC_DEV_ID_I210_SERDES_FLASHLESS        0x157C
 161 #define IGC_DEV_ID_I210_SGMII_FLASHLESS 0x15F6
 162 #define IGC_DEV_ID_I211_COPPER          0x1539
 163 #define IGC_DEV_ID_I225_LM                      0x15F2
 164 #define IGC_DEV_ID_I225_V                       0x15F3
 165 #define IGC_DEV_ID_I225_K                       0x3100
 166 #define IGC_DEV_ID_I225_I                       0x15F8
 167 #define IGC_DEV_ID_I220_V                       0x15F7
 168 #define IGC_DEV_ID_I225_BLANK_NVM               0x15FD
 169 #define IGC_DEV_ID_I226_K           0x3102
 170 #define IGC_DEV_ID_I226_LMVP        0x5503
 171 #define IGC_DEV_ID_I226_LM          0x125B
 172 #define IGC_DEV_ID_I226_V           0x125C
 173 #define IGC_DEV_ID_I226_IT          0x125D
 174 #define IGC_DEV_ID_I226_BLANK_NVM   0x125F
 175 #define IGC_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
 176 #define IGC_DEV_ID_I354_SGMII                   0x1F41
 177 #define IGC_DEV_ID_I354_BACKPLANE_2_5GBPS       0x1F45
 178 #define IGC_DEV_ID_DH89XXCC_SGMII               0x0438
 179 #define IGC_DEV_ID_DH89XXCC_SERDES              0x043A
 180 #define IGC_DEV_ID_DH89XXCC_BACKPLANE           0x043C
 181 #define IGC_DEV_ID_DH89XXCC_SFP         0x0440
 182
 183 #define IGC_REVISION_0  0
 184 #define IGC_REVISION_1  1
 185 #define IGC_REVISION_2  2
 186 #define IGC_REVISION_3  3
 187 #define IGC_REVISION_4  4
 188
 189 #define IGC_FUNC_0              0
 190 #define IGC_FUNC_1              1
 191 #define IGC_FUNC_2              2
 192 #define IGC_FUNC_3              3
 193
 194 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0
 195 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3
 196 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN2 6
 197 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN3 9
 198
 199 enum igc_mac_type {
 200         igc_undefined = 0,
 201         igc_82542,
 202         igc_82543,
 203         igc_82544,
 204         igc_82540,
 205         igc_82545,
 206         igc_82545_rev_3,
 207         igc_82546,
 208         igc_82546_rev_3,
 209         igc_82541,
 210         igc_82541_rev_2,
 211         igc_82547,
 212         igc_82547_rev_2,
 213         igc_82571,
 214         igc_82572,
 215         igc_82573,
 216         igc_82574,
 217         igc_82583,
 218         igc_80003es2lan,
 219         igc_ich8lan,
 220         igc_ich9lan,
 221         igc_ich10lan,
 222         igc_pchlan,
 223         igc_pch2lan,
 224         igc_pch_lpt,
 225         igc_pch_spt,
 226         igc_pch_cnp,
 227         igc_82575,
 228         igc_82576,
 229         igc_82580,
 230         igc_i350,
 231         igc_i354,
 232         igc_i210,
 233         igc_i211,
 234         igc_i225,
 235         igc_vfadapt,
 236         igc_vfadapt_i350,
 237         igc_num_macs  /* List is 1-based, so subtract 1 for true count. */
 238 };
 239
 240 enum igc_media_type {
 241         igc_media_type_unknown = 0,
 242         igc_media_type_copper = 1,
 243         igc_media_type_fiber = 2,
 244         igc_media_type_internal_serdes = 3,
 245         igc_num_media_types
 246 };
 247
 248 enum igc_nvm_type {
 249         igc_nvm_unknown = 0,
 250         igc_nvm_none,
 251         igc_nvm_eeprom_spi,
 252         igc_nvm_eeprom_microwire,
 253         igc_nvm_flash_hw,
 254         igc_nvm_invm,
 255         igc_nvm_flash_sw
 256 };
 257
 258 enum igc_nvm_override {
 259         igc_nvm_override_none = 0,
 260         igc_nvm_override_spi_small,
 261         igc_nvm_override_spi_large,
 262         igc_nvm_override_microwire_small,
 263         igc_nvm_override_microwire_large
 264 };
 265
 266 enum igc_phy_type {
 267         igc_phy_unknown = 0,
 268         igc_phy_none,
 269         igc_phy_m88,
 270         igc_phy_igp,
 271         igc_phy_igp_2,
 272         igc_phy_gg82563,
 273         igc_phy_igp_3,
 274         igc_phy_ife,
 275         igc_phy_bm,
 276         igc_phy_82578,
 277         igc_phy_82577,
 278         igc_phy_82579,
 279         igc_phy_i217,
 280         igc_phy_82580,
 281         igc_phy_vf,
 282         igc_phy_i210,
 283         igc_phy_i225,
 284 };
 285
 286 enum igc_bus_type {
 287         igc_bus_type_unknown = 0,
 288         igc_bus_type_pci,
 289         igc_bus_type_pcix,
 290         igc_bus_type_pci_express,
 291         igc_bus_type_reserved
 292 };
 293
 294 enum igc_bus_speed {
 295         igc_bus_speed_unknown = 0,
 296         igc_bus_speed_33,
 297         igc_bus_speed_66,
 298         igc_bus_speed_100,
 299         igc_bus_speed_120,
 300         igc_bus_speed_133,
 301         igc_bus_speed_2500,
 302         igc_bus_speed_5000,
 303         igc_bus_speed_reserved
 304 };
 305
 306 enum igc_bus_width {
 307         igc_bus_width_unknown = 0,
 308         igc_bus_width_pcie_x1,
 309         igc_bus_width_pcie_x2,
 310         igc_bus_width_pcie_x4 = 4,
 311         igc_bus_width_pcie_x8 = 8,
 312         igc_bus_width_32,
 313         igc_bus_width_64,
 314         igc_bus_width_reserved
 315 };
 316
 317 enum igc_1000t_rx_status {
 318         igc_1000t_rx_status_not_ok = 0,
 319         igc_1000t_rx_status_ok,
 320         igc_1000t_rx_status_undefined = 0xFF
 321 };
 322
 323 enum igc_rev_polarity {
 324         igc_rev_polarity_normal = 0,
 325         igc_rev_polarity_reversed,
 326         igc_rev_polarity_undefined = 0xFF
 327 };
 328
 329 enum igc_fc_mode {
 330         igc_fc_none = 0,
 331         igc_fc_rx_pause,
 332         igc_fc_tx_pause,
 333         igc_fc_full,
 334         igc_fc_default = 0xFF
 335 };
 336
 337 enum igc_ffe_config {
 338         igc_ffe_config_enabled = 0,
 339         igc_ffe_config_active,
 340         igc_ffe_config_blocked
 341 };
 342
 343 enum igc_dsp_config {
 344         igc_dsp_config_disabled = 0,
 345         igc_dsp_config_enabled,
 346         igc_dsp_config_activated,
 347         igc_dsp_config_undefined = 0xFF
 348 };
 349
 350 enum igc_ms_type {
 351         igc_ms_hw_default = 0,
 352         igc_ms_force_master,
 353         igc_ms_force_slave,
 354         igc_ms_auto
 355 };
 356
 357 enum igc_smart_speed {
 358         igc_smart_speed_default = 0,
 359         igc_smart_speed_on,
 360         igc_smart_speed_off
 361 };
 362
 363 enum igc_serdes_link_state {
 364         igc_serdes_link_down = 0,
 365         igc_serdes_link_autoneg_progress,
 366         igc_serdes_link_autoneg_complete,
 367         igc_serdes_link_forced_up
 368 };
 369
 370 enum igc_invm_structure_type {
 371         igc_invm_uninitialized_structure                = 0x00,
 372         igc_invm_word_autoload_structure                = 0x01,
 373         igc_invm_csr_autoload_structure         = 0x02,
 374         igc_invm_phy_register_autoload_structure        = 0x03,
 375         igc_invm_rsa_key_sha256_structure               = 0x04,
 376         igc_invm_invalidated_structure          = 0x0f,
 377 };
 378
 379 #define __le16 u16
 380 #define __le32 u32
 381 #define __le64 u64
 382 /* Receive Descriptor */
 383 struct igc_rx_desc {
 384         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 385         __le16 length;      /* Length of data DMAed into data buffer */
 386         __le16 csum; /* Packet checksum */
 387         u8  status;  /* Descriptor status */
 388         u8  errors;  /* Descriptor Errors */
 389         __le16 special;
 390 };
 391
 392 /* Receive Descriptor - Extended */
 393 union igc_rx_desc_extended {
 394         struct {
 395                 __le64 buffer_addr;
 396                 __le64 reserved;
 397         } read;
 398         struct {
 399                 struct {
 400                         __le32 mrq; /* Multiple Rx Queues */
 401                         union {
 402                                 __le32 rss; /* RSS Hash */
 403                                 struct {
 404                                         __le16 ip_id;  /* IP id */
 405                                         __le16 csum;   /* Packet Checksum */
 406                                 } csum_ip;
 407                         } hi_dword;
 408                 } lower;
 409                 struct {
 410                         __le32 status_error;  /* ext status/error */
 411                         __le16 length;
 412                         __le16 vlan; /* VLAN tag */
 413                 } upper;
 414         } wb;  /* writeback */
 415 };
 416
 417 #define MAX_PS_BUFFERS 4
 418
 419 /* Number of packet split data buffers (not including the header buffer) */
 420 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 421
 422 /* Receive Descriptor - Packet Split */
 423 union igc_rx_desc_packet_split {
 424         struct {
 425                 /* one buffer for protocol header(s), three data buffers */
 426                 __le64 buffer_addr[MAX_PS_BUFFERS];
 427         } read;
 428         struct {
 429                 struct {
 430                         __le32 mrq;  /* Multiple Rx Queues */
 431                         union {
 432                                 __le32 rss; /* RSS Hash */
 433                                 struct {
 434                                         __le16 ip_id;    /* IP id */
 435                                         __le16 csum;     /* Packet Checksum */
 436                                 } csum_ip;
 437                         } hi_dword;
 438                 } lower;
 439                 struct {
 440                         __le32 status_error;  /* ext status/error */
 441                         __le16 length0;  /* length of buffer 0 */
 442                         __le16 vlan;  /* VLAN tag */
 443                 } middle;
 444                 struct {
 445                         __le16 header_status;
 446                         /* length of buffers 1-3 */
 447                         __le16 length[PS_PAGE_BUFFERS];
 448                 } upper;
 449                 __le64 reserved;
 450         } wb; /* writeback */
 451 };
 452
 453 /* Transmit Descriptor */
 454 struct igc_tx_desc {
 455         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 456         union {
 457                 __le32 data;
 458                 struct {
 459                         __le16 length;  /* Data buffer length */
 460                         u8 cso;  /* Checksum offset */
 461                         u8 cmd;  /* Descriptor control */
 462                 } flags;
 463         } lower;
 464         union {
 465                 __le32 data;
 466                 struct {
 467                         u8 status; /* Descriptor status */
 468                         u8 css;  /* Checksum start */
 469                         __le16 special;
 470                 } fields;
 471         } upper;
 472 };
 473
 474 /* Offload Context Descriptor */
 475 struct igc_context_desc {
 476         union {
 477                 __le32 ip_config;
 478                 struct {
 479                         u8 ipcss;  /* IP checksum start */
 480                         u8 ipcso;  /* IP checksum offset */
 481                         __le16 ipcse;  /* IP checksum end */
 482                 } ip_fields;
 483         } lower_setup;
 484         union {
 485                 __le32 tcp_config;
 486                 struct {
 487                         u8 tucss;  /* TCP checksum start */
 488                         u8 tucso;  /* TCP checksum offset */
 489                         __le16 tucse;  /* TCP checksum end */
 490                 } tcp_fields;
 491         } upper_setup;
 492         __le32 cmd_and_length;
 493         union {
 494                 __le32 data;
 495                 struct {
 496                         u8 status;  /* Descriptor status */
 497                         u8 hdr_len;  /* Header length */
 498                         __le16 mss;  /* Maximum segment size */
 499                 } fields;
 500         } tcp_seg_setup;
 501 };
 502
 503 /* Offload data descriptor */
 504 struct igc_data_desc {
 505         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 506         union {
 507                 __le32 data;
 508                 struct {
 509                         __le16 length;  /* Data buffer length */
 510                         u8 typ_len_ext;
 511                         u8 cmd;
 512                 } flags;
 513         } lower;
 514         union {
 515                 __le32 data;
 516                 struct {
 517                         u8 status;  /* Descriptor status */
 518                         u8 popts;  /* Packet Options */
 519                         __le16 special;
 520                 } fields;
 521         } upper;
 522 };
 523
 524 /* Statistics counters collected by the MAC */
 525 struct igc_hw_stats {
 526         u64 crcerrs;
 527         u64 algnerrc;
 528         u64 symerrs;
 529         u64 rxerrc;
 530         u64 mpc;
 531         u64 scc;
 532         u64 ecol;
 533         u64 mcc;
 534         u64 latecol;
 535         u64 colc;
 536         u64 dc;
 537         u64 tncrs;
 538         u64 sec;
 539         u64 cexterr;
 540         u64 rlec;
 541         u64 xonrxc;
 542         u64 xontxc;
 543         u64 xoffrxc;
 544         u64 xofftxc;
 545         u64 fcruc;
 546         u64 prc64;
 547         u64 prc127;
 548         u64 prc255;
 549         u64 prc511;
 550         u64 prc1023;
 551         u64 prc1522;
 552         u64 gprc;
 553         u64 bprc;
 554         u64 mprc;
 555         u64 gptc;
 556         u64 gorc;
 557         u64 gotc;
 558         u64 rnbc;
 559         u64 ruc;
 560         u64 rfc;
 561         u64 roc;
 562         u64 rjc;
 563         u64 mgprc;
 564         u64 mgpdc;
 565         u64 mgptc;
 566         u64 tor;
 567         u64 tot;
 568         u64 tpr;
 569         u64 tpt;
 570         u64 ptc64;
 571         u64 ptc127;
 572         u64 ptc255;
 573         u64 ptc511;
 574         u64 ptc1023;
 575         u64 ptc1522;
 576         u64 mptc;
 577         u64 bptc;
 578         u64 tsctc;
 579         u64 tsctfc;
 580         u64 iac;
 581         u64 icrxptc;
 582         u64 icrxatc;
 583         u64 ictxptc;
 584         u64 ictxatc;
 585         u64 ictxqec;
 586         u64 ictxqmtc;
 587         u64 icrxdmtc;
 588         u64 icrxoc;
 589         u64 cbtmpc;
 590         u64 htdpmc;
 591         u64 cbrdpc;
 592         u64 cbrmpc;
 593         u64 rpthc;
 594         u64 hgptc;
 595         u64 htcbdpc;
 596         u64 hgorc;
 597         u64 hgotc;
 598         u64 lenerrs;
 599         u64 scvpc;
 600         u64 hrmpc;
 601         u64 doosync;
 602         u64 o2bgptc;
 603         u64 o2bspc;
 604         u64 b2ospc;
 605         u64 b2ogprc;
 606 };
 607
 608 struct igc_vf_stats {
 609         u64 base_gprc;
 610         u64 base_gptc;
 611         u64 base_gorc;
 612         u64 base_gotc;
 613         u64 base_mprc;
 614         u64 base_gotlbc;
 615         u64 base_gptlbc;
 616         u64 base_gorlbc;
 617         u64 base_gprlbc;
 618
 619         u32 last_gprc;
 620         u32 last_gptc;
 621         u32 last_gorc;
 622         u32 last_gotc;
 623         u32 last_mprc;
 624         u32 last_gotlbc;
 625         u32 last_gptlbc;
 626         u32 last_gorlbc;
 627         u32 last_gprlbc;
 628
 629         u64 gprc;
 630         u64 gptc;
 631         u64 gorc;
 632         u64 gotc;
 633         u64 mprc;
 634         u64 gotlbc;
 635         u64 gptlbc;
 636         u64 gorlbc;
 637         u64 gprlbc;
 638 };
 639
 640 struct igc_phy_stats {
 641         u32 idle_errors;
 642         u32 receive_errors;
 643 };
 644
 645 struct igc_host_mng_dhcp_cookie {
 646         u32 signature;
 647         u8  status;
 648         u8  reserved0;
 649         u16 vlan_id;
 650         u32 reserved1;
 651         u16 reserved2;
 652         u8  reserved3;
 653         u8  checksum;
 654 };
 655
 656 /* Host Interface "Rev 1" */
 657 struct igc_host_command_header {
 658         u8 command_id;
 659         u8 command_length;
 660         u8 command_options;
 661         u8 checksum;
 662 };
 663
 664 #define IGC_HI_MAX_DATA_LENGTH  252
 665 struct igc_host_command_info {
 666         struct igc_host_command_header command_header;
 667         u8 command_data[IGC_HI_MAX_DATA_LENGTH];
 668 };
 669
 670 /* Host Interface "Rev 2" */
 671 struct igc_host_mng_command_header {
 672         u8  command_id;
 673         u8  checksum;
 674         u16 reserved1;
 675         u16 reserved2;
 676         u16 command_length;
 677 };
 678
 679 #define IGC_HI_MAX_MNG_DATA_LENGTH      0x6F8
 680 struct igc_host_mng_command_info {
 681         struct igc_host_mng_command_header command_header;
 682         u8 command_data[IGC_HI_MAX_MNG_DATA_LENGTH];
 683 };
 684
 685 #include "igc_mac.h"
 686 #include "igc_phy.h"
 687 #include "igc_nvm.h"
 688 #include "igc_manage.h"
 689
 690 /* Function pointers for the MAC. */
 691 struct igc_mac_operations {
 692         s32  (*init_params)(struct igc_hw *hw);
 693         s32  (*id_led_init)(struct igc_hw *hw);
 694         s32  (*blink_led)(struct igc_hw *hw);
 695         bool (*check_mng_mode)(struct igc_hw *hw);
 696         s32  (*check_for_link)(struct igc_hw *hw);
 697         s32  (*cleanup_led)(struct igc_hw *hw);
 698         void (*clear_hw_cntrs)(struct igc_hw *hw);
 699         void (*clear_vfta)(struct igc_hw *hw);
 700         s32  (*get_bus_info)(struct igc_hw *hw);
 701         void (*set_lan_id)(struct igc_hw *hw);
 702         s32  (*get_link_up_info)(struct igc_hw *hw, u16 *speed, u16 *duplex);
 703         s32  (*led_on)(struct igc_hw *hw);
 704         s32  (*led_off)(struct igc_hw *hw);
 705         void (*update_mc_addr_list)(struct igc_hw *hw,
 706                         u8 *mc_addr_list, u32 count);
 707         s32  (*reset_hw)(struct igc_hw *hw);
 708         s32  (*init_hw)(struct igc_hw *hw);
 709         void (*shutdown_serdes)(struct igc_hw *hw);
 710         void (*power_up_serdes)(struct igc_hw *hw);
 711         s32  (*setup_link)(struct igc_hw *hw);
 712         s32  (*setup_physical_interface)(struct igc_hw *hw);
 713         s32  (*setup_led)(struct igc_hw *hw);
 714         void (*write_vfta)(struct igc_hw *hw, u32 offset, u32 value);
 715         void (*config_collision_dist)(struct igc_hw *hw);
 716         int  (*rar_set)(struct igc_hw *hw, u8 *addr, u32 index);
 717         s32  (*read_mac_addr)(struct igc_hw *hw);
 718         s32  (*validate_mdi_setting)(struct igc_hw *hw);
 719         s32  (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);
 720         void (*release_swfw_sync)(struct igc_hw *hw, u16 mask);
 721 };
 722
 723 /* When to use various PHY register access functions:
 724  *
 725  *                 Func   Caller
 726  *   Function      Does   Does    When to use
 727  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 728  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 729  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 730  *                                on different pages
 731  *   X_reg_page    A      L,P     for multiple accesses of different regs
 732  *                                on the same page
 733  *
 734  * Where X=[read|write], L=locking, P=sets page, A=register access
 735  *
 736  */
 737 struct igc_phy_operations {
 738         s32  (*init_params)(struct igc_hw *hw);
 739         s32  (*acquire)(struct igc_hw *hw);
 740         s32  (*cfg_on_link_up)(struct igc_hw *hw);
 741         s32  (*check_polarity)(struct igc_hw *hw);
 742         s32  (*check_reset_block)(struct igc_hw *hw);
 743         s32  (*commit)(struct igc_hw *hw);
 744         s32  (*force_speed_duplex)(struct igc_hw *hw);
 745         s32  (*get_cfg_done)(struct igc_hw *hw);
 746         s32  (*get_cable_length)(struct igc_hw *hw);
 747         s32  (*get_info)(struct igc_hw *hw);
 748         s32  (*set_page)(struct igc_hw *hw, u16 page);
 749         s32  (*read_reg)(struct igc_hw *hw, u32 offset, u16 *data);
 750         s32  (*read_reg_locked)(struct igc_hw *hw, u32 offset, u16 *data);
 751         s32  (*read_reg_page)(struct igc_hw *hw, u32 offset, u16 *data);
 752         void (*release)(struct igc_hw *hw);
 753         s32  (*reset)(struct igc_hw *hw);
 754         s32  (*set_d0_lplu_state)(struct igc_hw *hw, bool active);
 755         s32  (*set_d3_lplu_state)(struct igc_hw *hw, bool active);
 756         s32  (*write_reg)(struct igc_hw *hw, u32 offset, u16 data);
 757         s32  (*write_reg_locked)(struct igc_hw *hw, u32 offset, u16 data);
 758         s32  (*write_reg_page)(struct igc_hw *hw, u32 offset, u16 data);
 759         void (*power_up)(struct igc_hw *hw);
 760         void (*power_down)(struct igc_hw *hw);
 761         s32 (*read_i2c_byte)(struct igc_hw *hw, u8 byte_offset,
 762                         u8 dev_addr, u8 *data);
 763         s32 (*write_i2c_byte)(struct igc_hw *hw, u8 byte_offset,
 764                         u8 dev_addr, u8 data);
 765 };
 766
 767 /* Function pointers for the NVM. */
 768 struct igc_nvm_operations {
 769         s32  (*init_params)(struct igc_hw *hw);
 770         s32  (*acquire)(struct igc_hw *hw);
 771         s32  (*read)(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
 772         void (*release)(struct igc_hw *hw);
 773         void (*reload)(struct igc_hw *hw);
 774         s32  (*update)(struct igc_hw *hw);
 775         s32  (*valid_led_default)(struct igc_hw *hw, u16 *data);
 776         s32  (*validate)(struct igc_hw *hw);
 777         s32  (*write)(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
 778 };
 779
 780 struct igc_info {
 781         s32 (*get_invariants)(struct igc_hw *hw);
 782         struct igc_mac_operations *mac_ops;
 783         const struct igc_phy_operations *phy_ops;
 784         struct igc_nvm_operations *nvm_ops;
 785 };
 786
 787 extern const struct igc_info igc_i225_info;
 788
 789 struct igc_mac_info {
 790         struct igc_mac_operations ops;
 791         u8 addr[ETH_ADDR_LEN];
 792         u8 perm_addr[ETH_ADDR_LEN];
 793
 794         enum igc_mac_type type;
 795
 796         u32 collision_delta;
 797         u32 ledctl_default;
 798         u32 ledctl_mode1;
 799         u32 ledctl_mode2;
 800         u32 mc_filter_type;
 801         u32 tx_packet_delta;
 802         u32 txcw;
 803
 804         u16 current_ifs_val;
 805         u16 ifs_max_val;
 806         u16 ifs_min_val;
 807         u16 ifs_ratio;
 808         u16 ifs_step_size;
 809         u16 mta_reg_count;
 810         u16 uta_reg_count;
 811
 812         /* Maximum size of the MTA register table in all supported adapters */
 813 #define MAX_MTA_REG 128
 814         u32 mta_shadow[MAX_MTA_REG];
 815         u16 rar_entry_count;
 816
 817         u8  forced_speed_duplex;
 818
 819         bool adaptive_ifs;
 820         bool has_fwsm;
 821         bool arc_subsystem_valid;
 822         bool asf_firmware_present;
 823         bool autoneg;
 824         bool autoneg_failed;
 825         bool get_link_status;
 826         bool in_ifs_mode;
 827         bool report_tx_early;
 828         enum igc_serdes_link_state serdes_link_state;
 829         bool serdes_has_link;
 830         bool tx_pkt_filtering;
 831 };
 832
 833 struct igc_phy_info {
 834         struct igc_phy_operations ops;
 835         enum igc_phy_type type;
 836
 837         enum igc_1000t_rx_status local_rx;
 838         enum igc_1000t_rx_status remote_rx;
 839         enum igc_ms_type ms_type;
 840         enum igc_ms_type original_ms_type;
 841         enum igc_rev_polarity cable_polarity;
 842         enum igc_smart_speed smart_speed;
 843
 844         u32 addr;
 845         u32 id;
 846         u32 reset_delay_us; /* in usec */
 847         u32 revision;
 848
 849         enum igc_media_type media_type;
 850
 851         u16 autoneg_advertised;
 852         u16 autoneg_mask;
 853         u16 cable_length;
 854         u16 max_cable_length;
 855         u16 min_cable_length;
 856
 857         u8 mdix;
 858
 859         bool disable_polarity_correction;
 860         bool is_mdix;
 861         bool polarity_correction;
 862         bool speed_downgraded;
 863         bool autoneg_wait_to_complete;
 864 };
 865
 866 struct igc_nvm_info {
 867         struct igc_nvm_operations ops;
 868         enum igc_nvm_type type;
 869         enum igc_nvm_override override;
 870
 871         u32 flash_bank_size;
 872         u32 flash_base_addr;
 873
 874         u16 word_size;
 875         u16 delay_usec;
 876         u16 address_bits;
 877         u16 opcode_bits;
 878         u16 page_size;
 879 };
 880
 881 struct igc_bus_info {
 882         enum igc_bus_type type;
 883         enum igc_bus_speed speed;
 884         enum igc_bus_width width;
 885
 886         u16 func;
 887         u16 pci_cmd_word;
 888 };
 889
 890 struct igc_fc_info {
 891         u32 high_water;  /* Flow control high-water mark */
 892         u32 low_water;  /* Flow control low-water mark */
 893         u16 pause_time;  /* Flow control pause timer */
 894         u16 refresh_time;  /* Flow control refresh timer */
 895         bool send_xon;  /* Flow control send XON */
 896         bool strict_ieee;  /* Strict IEEE mode */
 897         enum igc_fc_mode current_mode;  /* FC mode in effect */
 898         enum igc_fc_mode requested_mode;  /* FC mode requested by caller */
 899 };
 900
 901 struct igc_mbx_operations {
 902         s32 (*init_params)(struct igc_hw *hw);
 903 };
 904
 905 struct igc_mbx_stats {
 906         u32 msgs_tx;
 907         u32 msgs_rx;
 908
 909         u32 acks;
 910         u32 reqs;
 911         u32 rsts;
 912 };
 913
 914 struct igc_mbx_info {
 915         struct igc_mbx_operations ops;
 916         struct igc_mbx_stats stats;
 917         u32 timeout;
 918         u32 usec_delay;
 919         u16 size;
 920 };
 921
 922 struct igc_dev_spec_82541 {
 923         enum igc_dsp_config dsp_config;
 924         enum igc_ffe_config ffe_config;
 925         u16 spd_default;
 926         bool phy_init_script;
 927 };
 928
 929 struct igc_dev_spec_82542 {
 930         bool dma_fairness;
 931 };
 932
 933 struct igc_dev_spec_82543 {
 934         u32  tbi_compatibility;
 935         bool dma_fairness;
 936         bool init_phy_disabled;
 937 };
 938
 939 struct igc_dev_spec_82571 {
 940         bool laa_is_present;
 941         u32 smb_counter;
 942         IGC_MUTEX swflag_mutex;
 943 };
 944
 945 struct igc_dev_spec_80003es2lan {
 946         bool  mdic_wa_enable;
 947 };
 948
 949 struct igc_shadow_ram {
 950         u16  value;
 951         bool modified;
 952 };
 953
 954 #define IGC_SHADOW_RAM_WORDS            2048
 955
 956 /* I218 PHY Ultra Low Power (ULP) states */
 957 enum igc_ulp_state {
 958         igc_ulp_state_unknown,
 959         igc_ulp_state_off,
 960         igc_ulp_state_on,
 961 };
 962
 963 struct igc_dev_spec_ich8lan {
 964         bool kmrn_lock_loss_workaround_enabled;
 965         struct igc_shadow_ram shadow_ram[IGC_SHADOW_RAM_WORDS];
 966         IGC_MUTEX nvm_mutex;
 967         IGC_MUTEX swflag_mutex;
 968         bool nvm_k1_enabled;
 969         bool disable_k1_off;
 970         bool eee_disable;
 971         u16 eee_lp_ability;
 972         enum igc_ulp_state ulp_state;
 973         bool ulp_capability_disabled;
 974         bool during_suspend_flow;
 975         bool during_dpg_exit;
 976         u16 lat_enc;
 977         u16 max_ltr_enc;
 978         bool smbus_disable;
 979 };
 980
 981 struct igc_dev_spec_82575 {
 982         bool sgmii_active;
 983         bool global_device_reset;
 984         bool eee_disable;
 985         bool module_plugged;
 986         bool clear_semaphore_once;
 987         u32 mtu;
 988         struct sfp_igc_flags eth_flags;
 989         u8 media_port;
 990         bool media_changed;
 991 };
 992
 993 struct igc_dev_spec_vf {
 994         u32 vf_number;
 995         u32 v2p_mailbox;
 996 };
 997
 998 struct igc_dev_spec_i225 {
 999         bool global_device_reset;
1000         bool eee_disable;
1001         bool clear_semaphore_once;
1002         bool module_plugged;
1003         u8 media_port;
1004         bool mas_capable;
1005         u32 mtu;
1006 };
1007
1008 struct igc_hw {
1009         void *back;
1010
1011         u8 *hw_addr;
1012         u8 *flash_address;
1013         unsigned long io_base;
1014
1015         struct igc_mac_info  mac;
1016         struct igc_fc_info   fc;
1017         struct igc_phy_info  phy;
1018         struct igc_nvm_info  nvm;
1019         struct igc_bus_info  bus;
1020         struct igc_mbx_info mbx;
1021         struct igc_host_mng_dhcp_cookie mng_cookie;
1022
1023         union {
1024                 struct igc_dev_spec_82541 _82541;
1025                 struct igc_dev_spec_82542 _82542;
1026                 struct igc_dev_spec_82543 _82543;
1027                 struct igc_dev_spec_82571 _82571;
1028                 struct igc_dev_spec_80003es2lan _80003es2lan;
1029                 struct igc_dev_spec_ich8lan ich8lan;
1030                 struct igc_dev_spec_82575 _82575;
1031                 struct igc_dev_spec_vf vf;
1032                 struct igc_dev_spec_i225 _i225;
1033         } dev_spec;
1034
1035         u16 device_id;
1036         u16 subsystem_vendor_id;
1037         u16 subsystem_device_id;
1038         u16 vendor_id;
1039
1040         u8  revision_id;
1041 };
1042
1043 #include "igc_82571.h"
1044 #include "igc_ich8lan.h"
1045 #include "igc_82575.h"
1046 #include "igc_i225.h"
1047 #include "igc_base.h"
1048
1049 /* These functions must be implemented by drivers */
1050 void igc_pci_clear_mwi(struct igc_hw *hw);
1051 void igc_pci_set_mwi(struct igc_hw *hw);
1052 s32  igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
1053 s32  igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
1054 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
1055 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
1056
1057 #endif