1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
10 #include "igc_defines.h"
14 #define IGC_DEV_ID_82542 0x1000
15 #define IGC_DEV_ID_82543GC_FIBER 0x1001
16 #define IGC_DEV_ID_82543GC_COPPER 0x1004
17 #define IGC_DEV_ID_82544EI_COPPER 0x1008
18 #define IGC_DEV_ID_82544EI_FIBER 0x1009
19 #define IGC_DEV_ID_82544GC_COPPER 0x100C
20 #define IGC_DEV_ID_82544GC_LOM 0x100D
21 #define IGC_DEV_ID_82540EM 0x100E
22 #define IGC_DEV_ID_82540EM_LOM 0x1015
23 #define IGC_DEV_ID_82540EP_LOM 0x1016
24 #define IGC_DEV_ID_82540EP 0x1017
25 #define IGC_DEV_ID_82540EP_LP 0x101E
26 #define IGC_DEV_ID_82545EM_COPPER 0x100F
27 #define IGC_DEV_ID_82545EM_FIBER 0x1011
28 #define IGC_DEV_ID_82545GM_COPPER 0x1026
29 #define IGC_DEV_ID_82545GM_FIBER 0x1027
30 #define IGC_DEV_ID_82545GM_SERDES 0x1028
31 #define IGC_DEV_ID_82546EB_COPPER 0x1010
32 #define IGC_DEV_ID_82546EB_FIBER 0x1012
33 #define IGC_DEV_ID_82546EB_QUAD_COPPER 0x101D
34 #define IGC_DEV_ID_82546GB_COPPER 0x1079
35 #define IGC_DEV_ID_82546GB_FIBER 0x107A
36 #define IGC_DEV_ID_82546GB_SERDES 0x107B
37 #define IGC_DEV_ID_82546GB_PCIE 0x108A
38 #define IGC_DEV_ID_82546GB_QUAD_COPPER 0x1099
39 #define IGC_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
40 #define IGC_DEV_ID_82541EI 0x1013
41 #define IGC_DEV_ID_82541EI_MOBILE 0x1018
42 #define IGC_DEV_ID_82541ER_LOM 0x1014
43 #define IGC_DEV_ID_82541ER 0x1078
44 #define IGC_DEV_ID_82541GI 0x1076
45 #define IGC_DEV_ID_82541GI_LF 0x107C
46 #define IGC_DEV_ID_82541GI_MOBILE 0x1077
47 #define IGC_DEV_ID_82547EI 0x1019
48 #define IGC_DEV_ID_82547EI_MOBILE 0x101A
49 #define IGC_DEV_ID_82547GI 0x1075
50 #define IGC_DEV_ID_82571EB_COPPER 0x105E
51 #define IGC_DEV_ID_82571EB_FIBER 0x105F
52 #define IGC_DEV_ID_82571EB_SERDES 0x1060
53 #define IGC_DEV_ID_82571EB_SERDES_DUAL 0x10D9
54 #define IGC_DEV_ID_82571EB_SERDES_QUAD 0x10DA
55 #define IGC_DEV_ID_82571EB_QUAD_COPPER 0x10A4
56 #define IGC_DEV_ID_82571PT_QUAD_COPPER 0x10D5
57 #define IGC_DEV_ID_82571EB_QUAD_FIBER 0x10A5
58 #define IGC_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC
59 #define IGC_DEV_ID_82572EI_COPPER 0x107D
60 #define IGC_DEV_ID_82572EI_FIBER 0x107E
61 #define IGC_DEV_ID_82572EI_SERDES 0x107F
62 #define IGC_DEV_ID_82572EI 0x10B9
63 #define IGC_DEV_ID_82573E 0x108B
64 #define IGC_DEV_ID_82573E_IAMT 0x108C
65 #define IGC_DEV_ID_82573L 0x109A
66 #define IGC_DEV_ID_82574L 0x10D3
67 #define IGC_DEV_ID_82574LA 0x10F6
68 #define IGC_DEV_ID_82583V 0x150C
69 #define IGC_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096
70 #define IGC_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098
71 #define IGC_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA
72 #define IGC_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB
73 #define IGC_DEV_ID_ICH8_82567V_3 0x1501
74 #define IGC_DEV_ID_ICH8_IGP_M_AMT 0x1049
75 #define IGC_DEV_ID_ICH8_IGP_AMT 0x104A
76 #define IGC_DEV_ID_ICH8_IGP_C 0x104B
77 #define IGC_DEV_ID_ICH8_IFE 0x104C
78 #define IGC_DEV_ID_ICH8_IFE_GT 0x10C4
79 #define IGC_DEV_ID_ICH8_IFE_G 0x10C5
80 #define IGC_DEV_ID_ICH8_IGP_M 0x104D
81 #define IGC_DEV_ID_ICH9_IGP_M 0x10BF
82 #define IGC_DEV_ID_ICH9_IGP_M_AMT 0x10F5
83 #define IGC_DEV_ID_ICH9_IGP_M_V 0x10CB
84 #define IGC_DEV_ID_ICH9_IGP_AMT 0x10BD
85 #define IGC_DEV_ID_ICH9_BM 0x10E5
86 #define IGC_DEV_ID_ICH9_IGP_C 0x294C
87 #define IGC_DEV_ID_ICH9_IFE 0x10C0
88 #define IGC_DEV_ID_ICH9_IFE_GT 0x10C3
89 #define IGC_DEV_ID_ICH9_IFE_G 0x10C2
90 #define IGC_DEV_ID_ICH10_R_BM_LM 0x10CC
91 #define IGC_DEV_ID_ICH10_R_BM_LF 0x10CD
92 #define IGC_DEV_ID_ICH10_R_BM_V 0x10CE
93 #define IGC_DEV_ID_ICH10_D_BM_LM 0x10DE
94 #define IGC_DEV_ID_ICH10_D_BM_LF 0x10DF
95 #define IGC_DEV_ID_ICH10_D_BM_V 0x1525
96 #define IGC_DEV_ID_PCH_M_HV_LM 0x10EA
97 #define IGC_DEV_ID_PCH_M_HV_LC 0x10EB
98 #define IGC_DEV_ID_PCH_D_HV_DM 0x10EF
99 #define IGC_DEV_ID_PCH_D_HV_DC 0x10F0
100 #define IGC_DEV_ID_PCH2_LV_LM 0x1502
101 #define IGC_DEV_ID_PCH2_LV_V 0x1503
102 #define IGC_DEV_ID_PCH_LPT_I217_LM 0x153A
103 #define IGC_DEV_ID_PCH_LPT_I217_V 0x153B
104 #define IGC_DEV_ID_PCH_LPTLP_I218_LM 0x155A
105 #define IGC_DEV_ID_PCH_LPTLP_I218_V 0x1559
106 #define IGC_DEV_ID_PCH_I218_LM2 0x15A0
107 #define IGC_DEV_ID_PCH_I218_V2 0x15A1
108 #define IGC_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
109 #define IGC_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
110 #define IGC_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */
111 #define IGC_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */
112 #define IGC_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */
113 #define IGC_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */
114 #define IGC_DEV_ID_PCH_LBG_I219_LM3 0x15B9 /* LEWISBURG PCH */
115 #define IGC_DEV_ID_PCH_SPT_I219_LM4 0x15D7
116 #define IGC_DEV_ID_PCH_SPT_I219_V4 0x15D8
117 #define IGC_DEV_ID_PCH_SPT_I219_LM5 0x15E3
118 #define IGC_DEV_ID_PCH_SPT_I219_V5 0x15D6
119 #define IGC_DEV_ID_PCH_CNP_I219_LM6 0x15BD
120 #define IGC_DEV_ID_PCH_CNP_I219_V6 0x15BE
121 #define IGC_DEV_ID_PCH_CNP_I219_LM7 0x15BB
122 #define IGC_DEV_ID_PCH_CNP_I219_V7 0x15BC
123 #define IGC_DEV_ID_PCH_ICP_I219_LM8 0x15DF
124 #define IGC_DEV_ID_PCH_ICP_I219_V8 0x15E0
125 #define IGC_DEV_ID_PCH_ICP_I219_LM9 0x15E1
126 #define IGC_DEV_ID_PCH_ICP_I219_V9 0x15E2
127 #define IGC_DEV_ID_82576 0x10C9
128 #define IGC_DEV_ID_82576_FIBER 0x10E6
129 #define IGC_DEV_ID_82576_SERDES 0x10E7
130 #define IGC_DEV_ID_82576_QUAD_COPPER 0x10E8
131 #define IGC_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
132 #define IGC_DEV_ID_82576_NS 0x150A
133 #define IGC_DEV_ID_82576_NS_SERDES 0x1518
134 #define IGC_DEV_ID_82576_SERDES_QUAD 0x150D
135 #define IGC_DEV_ID_82576_VF 0x10CA
136 #define IGC_DEV_ID_82576_VF_HV 0x152D
137 #define IGC_DEV_ID_I350_VF 0x1520
138 #define IGC_DEV_ID_I350_VF_HV 0x152F
139 #define IGC_DEV_ID_82575EB_COPPER 0x10A7
140 #define IGC_DEV_ID_82575EB_FIBER_SERDES 0x10A9
141 #define IGC_DEV_ID_82575GB_QUAD_COPPER 0x10D6
142 #define IGC_DEV_ID_82580_COPPER 0x150E
143 #define IGC_DEV_ID_82580_FIBER 0x150F
144 #define IGC_DEV_ID_82580_SERDES 0x1510
145 #define IGC_DEV_ID_82580_SGMII 0x1511
146 #define IGC_DEV_ID_82580_COPPER_DUAL 0x1516
147 #define IGC_DEV_ID_82580_QUAD_FIBER 0x1527
148 #define IGC_DEV_ID_I350_COPPER 0x1521
149 #define IGC_DEV_ID_I350_FIBER 0x1522
150 #define IGC_DEV_ID_I350_SERDES 0x1523
151 #define IGC_DEV_ID_I350_SGMII 0x1524
152 #define IGC_DEV_ID_I350_DA4 0x1546
153 #define IGC_DEV_ID_I210_COPPER 0x1533
154 #define IGC_DEV_ID_I210_COPPER_OEM1 0x1534
155 #define IGC_DEV_ID_I210_COPPER_IT 0x1535
156 #define IGC_DEV_ID_I210_FIBER 0x1536
157 #define IGC_DEV_ID_I210_SERDES 0x1537
158 #define IGC_DEV_ID_I210_SGMII 0x1538
159 #define IGC_DEV_ID_I210_COPPER_FLASHLESS 0x157B
160 #define IGC_DEV_ID_I210_SERDES_FLASHLESS 0x157C
161 #define IGC_DEV_ID_I210_SGMII_FLASHLESS 0x15F6
162 #define IGC_DEV_ID_I211_COPPER 0x1539
163 #define IGC_DEV_ID_I225_LM 0x15F2
164 #define IGC_DEV_ID_I225_V 0x15F3
165 #define IGC_DEV_ID_I225_K 0x3100
166 #define IGC_DEV_ID_I225_I 0x15F8
167 #define IGC_DEV_ID_I220_V 0x15F7
168 #define IGC_DEV_ID_I225_BLANK_NVM 0x15FD
169 #define IGC_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
170 #define IGC_DEV_ID_I354_SGMII 0x1F41
171 #define IGC_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
172 #define IGC_DEV_ID_DH89XXCC_SGMII 0x0438
173 #define IGC_DEV_ID_DH89XXCC_SERDES 0x043A
174 #define IGC_DEV_ID_DH89XXCC_BACKPLANE 0x043C
175 #define IGC_DEV_ID_DH89XXCC_SFP 0x0440
177 #define IGC_REVISION_0 0
178 #define IGC_REVISION_1 1
179 #define IGC_REVISION_2 2
180 #define IGC_REVISION_3 3
181 #define IGC_REVISION_4 4
188 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0
189 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3
190 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN2 6
191 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN3 9
231 igc_num_macs /* List is 1-based, so subtract 1 for true count. */
234 enum igc_media_type {
235 igc_media_type_unknown = 0,
236 igc_media_type_copper = 1,
237 igc_media_type_fiber = 2,
238 igc_media_type_internal_serdes = 3,
246 igc_nvm_eeprom_microwire,
252 enum igc_nvm_override {
253 igc_nvm_override_none = 0,
254 igc_nvm_override_spi_small,
255 igc_nvm_override_spi_large,
256 igc_nvm_override_microwire_small,
257 igc_nvm_override_microwire_large
281 igc_bus_type_unknown = 0,
284 igc_bus_type_pci_express,
285 igc_bus_type_reserved
289 igc_bus_speed_unknown = 0,
297 igc_bus_speed_reserved
301 igc_bus_width_unknown = 0,
302 igc_bus_width_pcie_x1,
303 igc_bus_width_pcie_x2,
304 igc_bus_width_pcie_x4 = 4,
305 igc_bus_width_pcie_x8 = 8,
308 igc_bus_width_reserved
311 enum igc_1000t_rx_status {
312 igc_1000t_rx_status_not_ok = 0,
313 igc_1000t_rx_status_ok,
314 igc_1000t_rx_status_undefined = 0xFF
317 enum igc_rev_polarity {
318 igc_rev_polarity_normal = 0,
319 igc_rev_polarity_reversed,
320 igc_rev_polarity_undefined = 0xFF
328 igc_fc_default = 0xFF
331 enum igc_ffe_config {
332 igc_ffe_config_enabled = 0,
333 igc_ffe_config_active,
334 igc_ffe_config_blocked
337 enum igc_dsp_config {
338 igc_dsp_config_disabled = 0,
339 igc_dsp_config_enabled,
340 igc_dsp_config_activated,
341 igc_dsp_config_undefined = 0xFF
345 igc_ms_hw_default = 0,
351 enum igc_smart_speed {
352 igc_smart_speed_default = 0,
357 enum igc_serdes_link_state {
358 igc_serdes_link_down = 0,
359 igc_serdes_link_autoneg_progress,
360 igc_serdes_link_autoneg_complete,
361 igc_serdes_link_forced_up
364 enum igc_invm_structure_type {
365 igc_invm_uninitialized_structure = 0x00,
366 igc_invm_word_autoload_structure = 0x01,
367 igc_invm_csr_autoload_structure = 0x02,
368 igc_invm_phy_register_autoload_structure = 0x03,
369 igc_invm_rsa_key_sha256_structure = 0x04,
370 igc_invm_invalidated_structure = 0x0f,
376 /* Receive Descriptor */
378 __le64 buffer_addr; /* Address of the descriptor's data buffer */
379 __le16 length; /* Length of data DMAed into data buffer */
380 __le16 csum; /* Packet checksum */
381 u8 status; /* Descriptor status */
382 u8 errors; /* Descriptor Errors */
386 /* Receive Descriptor - Extended */
387 union igc_rx_desc_extended {
394 __le32 mrq; /* Multiple Rx Queues */
396 __le32 rss; /* RSS Hash */
398 __le16 ip_id; /* IP id */
399 __le16 csum; /* Packet Checksum */
404 __le32 status_error; /* ext status/error */
406 __le16 vlan; /* VLAN tag */
408 } wb; /* writeback */
411 #define MAX_PS_BUFFERS 4
413 /* Number of packet split data buffers (not including the header buffer) */
414 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
416 /* Receive Descriptor - Packet Split */
417 union igc_rx_desc_packet_split {
419 /* one buffer for protocol header(s), three data buffers */
420 __le64 buffer_addr[MAX_PS_BUFFERS];
424 __le32 mrq; /* Multiple Rx Queues */
426 __le32 rss; /* RSS Hash */
428 __le16 ip_id; /* IP id */
429 __le16 csum; /* Packet Checksum */
434 __le32 status_error; /* ext status/error */
435 __le16 length0; /* length of buffer 0 */
436 __le16 vlan; /* VLAN tag */
439 __le16 header_status;
440 /* length of buffers 1-3 */
441 __le16 length[PS_PAGE_BUFFERS];
444 } wb; /* writeback */
447 /* Transmit Descriptor */
449 __le64 buffer_addr; /* Address of the descriptor's data buffer */
453 __le16 length; /* Data buffer length */
454 u8 cso; /* Checksum offset */
455 u8 cmd; /* Descriptor control */
461 u8 status; /* Descriptor status */
462 u8 css; /* Checksum start */
468 /* Offload Context Descriptor */
469 struct igc_context_desc {
473 u8 ipcss; /* IP checksum start */
474 u8 ipcso; /* IP checksum offset */
475 __le16 ipcse; /* IP checksum end */
481 u8 tucss; /* TCP checksum start */
482 u8 tucso; /* TCP checksum offset */
483 __le16 tucse; /* TCP checksum end */
486 __le32 cmd_and_length;
490 u8 status; /* Descriptor status */
491 u8 hdr_len; /* Header length */
492 __le16 mss; /* Maximum segment size */
497 /* Offload data descriptor */
498 struct igc_data_desc {
499 __le64 buffer_addr; /* Address of the descriptor's buffer address */
503 __le16 length; /* Data buffer length */
511 u8 status; /* Descriptor status */
512 u8 popts; /* Packet Options */
518 /* Statistics counters collected by the MAC */
519 struct igc_hw_stats {
602 struct igc_vf_stats {
634 struct igc_phy_stats {
639 struct igc_host_mng_dhcp_cookie {
650 /* Host Interface "Rev 1" */
651 struct igc_host_command_header {
658 #define IGC_HI_MAX_DATA_LENGTH 252
659 struct igc_host_command_info {
660 struct igc_host_command_header command_header;
661 u8 command_data[IGC_HI_MAX_DATA_LENGTH];
664 /* Host Interface "Rev 2" */
665 struct igc_host_mng_command_header {
673 #define IGC_HI_MAX_MNG_DATA_LENGTH 0x6F8
674 struct igc_host_mng_command_info {
675 struct igc_host_mng_command_header command_header;
676 u8 command_data[IGC_HI_MAX_MNG_DATA_LENGTH];
682 #include "igc_manage.h"
684 /* Function pointers for the MAC. */
685 struct igc_mac_operations {
686 s32 (*init_params)(struct igc_hw *hw);
687 s32 (*id_led_init)(struct igc_hw *hw);
688 s32 (*blink_led)(struct igc_hw *hw);
689 bool (*check_mng_mode)(struct igc_hw *hw);
690 s32 (*check_for_link)(struct igc_hw *hw);
691 s32 (*cleanup_led)(struct igc_hw *hw);
692 void (*clear_hw_cntrs)(struct igc_hw *hw);
693 void (*clear_vfta)(struct igc_hw *hw);
694 s32 (*get_bus_info)(struct igc_hw *hw);
695 void (*set_lan_id)(struct igc_hw *hw);
696 s32 (*get_link_up_info)(struct igc_hw *hw, u16 *speed, u16 *duplex);
697 s32 (*led_on)(struct igc_hw *hw);
698 s32 (*led_off)(struct igc_hw *hw);
699 void (*update_mc_addr_list)(struct igc_hw *hw,
700 u8 *mc_addr_list, u32 count);
701 s32 (*reset_hw)(struct igc_hw *hw);
702 s32 (*init_hw)(struct igc_hw *hw);
703 void (*shutdown_serdes)(struct igc_hw *hw);
704 void (*power_up_serdes)(struct igc_hw *hw);
705 s32 (*setup_link)(struct igc_hw *hw);
706 s32 (*setup_physical_interface)(struct igc_hw *hw);
707 s32 (*setup_led)(struct igc_hw *hw);
708 void (*write_vfta)(struct igc_hw *hw, u32 offset, u32 value);
709 void (*config_collision_dist)(struct igc_hw *hw);
710 int (*rar_set)(struct igc_hw *hw, u8 *addr, u32 index);
711 s32 (*read_mac_addr)(struct igc_hw *hw);
712 s32 (*validate_mdi_setting)(struct igc_hw *hw);
713 s32 (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);
714 void (*release_swfw_sync)(struct igc_hw *hw, u16 mask);
717 /* When to use various PHY register access functions:
720 * Function Does Does When to use
721 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
722 * X_reg L,P,A n/a for simple PHY reg accesses
723 * X_reg_locked P,A L for multiple accesses of different regs
725 * X_reg_page A L,P for multiple accesses of different regs
728 * Where X=[read|write], L=locking, P=sets page, A=register access
731 struct igc_phy_operations {
732 s32 (*init_params)(struct igc_hw *hw);
733 s32 (*acquire)(struct igc_hw *hw);
734 s32 (*cfg_on_link_up)(struct igc_hw *hw);
735 s32 (*check_polarity)(struct igc_hw *hw);
736 s32 (*check_reset_block)(struct igc_hw *hw);
737 s32 (*commit)(struct igc_hw *hw);
738 s32 (*force_speed_duplex)(struct igc_hw *hw);
739 s32 (*get_cfg_done)(struct igc_hw *hw);
740 s32 (*get_cable_length)(struct igc_hw *hw);
741 s32 (*get_info)(struct igc_hw *hw);
742 s32 (*set_page)(struct igc_hw *hw, u16 page);
743 s32 (*read_reg)(struct igc_hw *hw, u32 offset, u16 *data);
744 s32 (*read_reg_locked)(struct igc_hw *hw, u32 offset, u16 *data);
745 s32 (*read_reg_page)(struct igc_hw *hw, u32 offset, u16 *data);
746 void (*release)(struct igc_hw *hw);
747 s32 (*reset)(struct igc_hw *hw);
748 s32 (*set_d0_lplu_state)(struct igc_hw *hw, bool active);
749 s32 (*set_d3_lplu_state)(struct igc_hw *hw, bool active);
750 s32 (*write_reg)(struct igc_hw *hw, u32 offset, u16 data);
751 s32 (*write_reg_locked)(struct igc_hw *hw, u32 offset, u16 data);
752 s32 (*write_reg_page)(struct igc_hw *hw, u32 offset, u16 data);
753 void (*power_up)(struct igc_hw *hw);
754 void (*power_down)(struct igc_hw *hw);
755 s32 (*read_i2c_byte)(struct igc_hw *hw, u8 byte_offset,
756 u8 dev_addr, u8 *data);
757 s32 (*write_i2c_byte)(struct igc_hw *hw, u8 byte_offset,
758 u8 dev_addr, u8 data);
761 /* Function pointers for the NVM. */
762 struct igc_nvm_operations {
763 s32 (*init_params)(struct igc_hw *hw);
764 s32 (*acquire)(struct igc_hw *hw);
765 s32 (*read)(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
766 void (*release)(struct igc_hw *hw);
767 void (*reload)(struct igc_hw *hw);
768 s32 (*update)(struct igc_hw *hw);
769 s32 (*valid_led_default)(struct igc_hw *hw, u16 *data);
770 s32 (*validate)(struct igc_hw *hw);
771 s32 (*write)(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
775 s32 (*get_invariants)(struct igc_hw *hw);
776 struct igc_mac_operations *mac_ops;
777 const struct igc_phy_operations *phy_ops;
778 struct igc_nvm_operations *nvm_ops;
781 extern const struct igc_info igc_i225_info;
783 struct igc_mac_info {
784 struct igc_mac_operations ops;
785 u8 addr[ETH_ADDR_LEN];
786 u8 perm_addr[ETH_ADDR_LEN];
788 enum igc_mac_type type;
806 /* Maximum size of the MTA register table in all supported adapters */
807 #define MAX_MTA_REG 128
808 u32 mta_shadow[MAX_MTA_REG];
811 u8 forced_speed_duplex;
815 bool arc_subsystem_valid;
816 bool asf_firmware_present;
819 bool get_link_status;
821 bool report_tx_early;
822 enum igc_serdes_link_state serdes_link_state;
823 bool serdes_has_link;
824 bool tx_pkt_filtering;
827 struct igc_phy_info {
828 struct igc_phy_operations ops;
829 enum igc_phy_type type;
831 enum igc_1000t_rx_status local_rx;
832 enum igc_1000t_rx_status remote_rx;
833 enum igc_ms_type ms_type;
834 enum igc_ms_type original_ms_type;
835 enum igc_rev_polarity cable_polarity;
836 enum igc_smart_speed smart_speed;
840 u32 reset_delay_us; /* in usec */
843 enum igc_media_type media_type;
845 u16 autoneg_advertised;
848 u16 max_cable_length;
849 u16 min_cable_length;
853 bool disable_polarity_correction;
855 bool polarity_correction;
856 bool speed_downgraded;
857 bool autoneg_wait_to_complete;
860 struct igc_nvm_info {
861 struct igc_nvm_operations ops;
862 enum igc_nvm_type type;
863 enum igc_nvm_override override;
875 struct igc_bus_info {
876 enum igc_bus_type type;
877 enum igc_bus_speed speed;
878 enum igc_bus_width width;
885 u32 high_water; /* Flow control high-water mark */
886 u32 low_water; /* Flow control low-water mark */
887 u16 pause_time; /* Flow control pause timer */
888 u16 refresh_time; /* Flow control refresh timer */
889 bool send_xon; /* Flow control send XON */
890 bool strict_ieee; /* Strict IEEE mode */
891 enum igc_fc_mode current_mode; /* FC mode in effect */
892 enum igc_fc_mode requested_mode; /* FC mode requested by caller */
895 struct igc_mbx_operations {
896 s32 (*init_params)(struct igc_hw *hw);
899 struct igc_mbx_stats {
908 struct igc_mbx_info {
909 struct igc_mbx_operations ops;
910 struct igc_mbx_stats stats;
916 struct igc_dev_spec_82541 {
917 enum igc_dsp_config dsp_config;
918 enum igc_ffe_config ffe_config;
920 bool phy_init_script;
923 struct igc_dev_spec_82542 {
927 struct igc_dev_spec_82543 {
928 u32 tbi_compatibility;
930 bool init_phy_disabled;
933 struct igc_dev_spec_82571 {
936 IGC_MUTEX swflag_mutex;
939 struct igc_dev_spec_80003es2lan {
943 struct igc_shadow_ram {
948 #define IGC_SHADOW_RAM_WORDS 2048
950 /* I218 PHY Ultra Low Power (ULP) states */
952 igc_ulp_state_unknown,
957 struct igc_dev_spec_ich8lan {
958 bool kmrn_lock_loss_workaround_enabled;
959 struct igc_shadow_ram shadow_ram[IGC_SHADOW_RAM_WORDS];
961 IGC_MUTEX swflag_mutex;
966 enum igc_ulp_state ulp_state;
967 bool ulp_capability_disabled;
968 bool during_suspend_flow;
969 bool during_dpg_exit;
975 struct igc_dev_spec_82575 {
977 bool global_device_reset;
980 bool clear_semaphore_once;
982 struct sfp_igc_flags eth_flags;
987 struct igc_dev_spec_vf {
992 struct igc_dev_spec_i225 {
993 bool global_device_reset;
995 bool clear_semaphore_once;
1007 unsigned long io_base;
1009 struct igc_mac_info mac;
1010 struct igc_fc_info fc;
1011 struct igc_phy_info phy;
1012 struct igc_nvm_info nvm;
1013 struct igc_bus_info bus;
1014 struct igc_mbx_info mbx;
1015 struct igc_host_mng_dhcp_cookie mng_cookie;
1018 struct igc_dev_spec_82541 _82541;
1019 struct igc_dev_spec_82542 _82542;
1020 struct igc_dev_spec_82543 _82543;
1021 struct igc_dev_spec_82571 _82571;
1022 struct igc_dev_spec_80003es2lan _80003es2lan;
1023 struct igc_dev_spec_ich8lan ich8lan;
1024 struct igc_dev_spec_82575 _82575;
1025 struct igc_dev_spec_vf vf;
1026 struct igc_dev_spec_i225 _i225;
1030 u16 subsystem_vendor_id;
1031 u16 subsystem_device_id;
1037 #include "igc_82571.h"
1038 #include "igc_ich8lan.h"
1039 #include "igc_82575.h"
1040 #include "igc_i225.h"
1041 #include "igc_base.h"
1043 /* These functions must be implemented by drivers */
1044 void igc_pci_clear_mwi(struct igc_hw *hw);
1045 void igc_pci_set_mwi(struct igc_hw *hw);
1046 s32 igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
1047 s32 igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
1048 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
1049 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);