drivers/net/igc/base/igc_hw.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2020 Intel Corporation
   3  */
   4
   5 #ifndef _IGC_HW_H_
   6 #define _IGC_HW_H_
   7
   8 #include "igc_osdep.h"
   9 #include "igc_regs.h"
  10 #include "igc_defines.h"
  11
  12 struct igc_hw;
  13
  14 #define IGC_DEV_ID_82542                        0x1000
  15 #define IGC_DEV_ID_82543GC_FIBER                0x1001
  16 #define IGC_DEV_ID_82543GC_COPPER               0x1004
  17 #define IGC_DEV_ID_82544EI_COPPER               0x1008
  18 #define IGC_DEV_ID_82544EI_FIBER                0x1009
  19 #define IGC_DEV_ID_82544GC_COPPER               0x100C
  20 #define IGC_DEV_ID_82544GC_LOM          0x100D
  21 #define IGC_DEV_ID_82540EM                      0x100E
  22 #define IGC_DEV_ID_82540EM_LOM          0x1015
  23 #define IGC_DEV_ID_82540EP_LOM          0x1016
  24 #define IGC_DEV_ID_82540EP                      0x1017
  25 #define IGC_DEV_ID_82540EP_LP                   0x101E
  26 #define IGC_DEV_ID_82545EM_COPPER               0x100F
  27 #define IGC_DEV_ID_82545EM_FIBER                0x1011
  28 #define IGC_DEV_ID_82545GM_COPPER               0x1026
  29 #define IGC_DEV_ID_82545GM_FIBER                0x1027
  30 #define IGC_DEV_ID_82545GM_SERDES               0x1028
  31 #define IGC_DEV_ID_82546EB_COPPER               0x1010
  32 #define IGC_DEV_ID_82546EB_FIBER                0x1012
  33 #define IGC_DEV_ID_82546EB_QUAD_COPPER  0x101D
  34 #define IGC_DEV_ID_82546GB_COPPER               0x1079
  35 #define IGC_DEV_ID_82546GB_FIBER                0x107A
  36 #define IGC_DEV_ID_82546GB_SERDES               0x107B
  37 #define IGC_DEV_ID_82546GB_PCIE         0x108A
  38 #define IGC_DEV_ID_82546GB_QUAD_COPPER  0x1099
  39 #define IGC_DEV_ID_82546GB_QUAD_COPPER_KSP3     0x10B5
  40 #define IGC_DEV_ID_82541EI                      0x1013
  41 #define IGC_DEV_ID_82541EI_MOBILE               0x1018
  42 #define IGC_DEV_ID_82541ER_LOM          0x1014
  43 #define IGC_DEV_ID_82541ER                      0x1078
  44 #define IGC_DEV_ID_82541GI                      0x1076
  45 #define IGC_DEV_ID_82541GI_LF                   0x107C
  46 #define IGC_DEV_ID_82541GI_MOBILE               0x1077
  47 #define IGC_DEV_ID_82547EI                      0x1019
  48 #define IGC_DEV_ID_82547EI_MOBILE               0x101A
  49 #define IGC_DEV_ID_82547GI                      0x1075
  50 #define IGC_DEV_ID_82571EB_COPPER               0x105E
  51 #define IGC_DEV_ID_82571EB_FIBER                0x105F
  52 #define IGC_DEV_ID_82571EB_SERDES               0x1060
  53 #define IGC_DEV_ID_82571EB_SERDES_DUAL  0x10D9
  54 #define IGC_DEV_ID_82571EB_SERDES_QUAD  0x10DA
  55 #define IGC_DEV_ID_82571EB_QUAD_COPPER  0x10A4
  56 #define IGC_DEV_ID_82571PT_QUAD_COPPER  0x10D5
  57 #define IGC_DEV_ID_82571EB_QUAD_FIBER           0x10A5
  58 #define IGC_DEV_ID_82571EB_QUAD_COPPER_LP       0x10BC
  59 #define IGC_DEV_ID_82572EI_COPPER               0x107D
  60 #define IGC_DEV_ID_82572EI_FIBER                0x107E
  61 #define IGC_DEV_ID_82572EI_SERDES               0x107F
  62 #define IGC_DEV_ID_82572EI                      0x10B9
  63 #define IGC_DEV_ID_82573E                       0x108B
  64 #define IGC_DEV_ID_82573E_IAMT          0x108C
  65 #define IGC_DEV_ID_82573L                       0x109A
  66 #define IGC_DEV_ID_82574L                       0x10D3
  67 #define IGC_DEV_ID_82574LA                      0x10F6
  68 #define IGC_DEV_ID_82583V                       0x150C
  69 #define IGC_DEV_ID_80003ES2LAN_COPPER_DPT       0x1096
  70 #define IGC_DEV_ID_80003ES2LAN_SERDES_DPT       0x1098
  71 #define IGC_DEV_ID_80003ES2LAN_COPPER_SPT       0x10BA
  72 #define IGC_DEV_ID_80003ES2LAN_SERDES_SPT       0x10BB
  73 #define IGC_DEV_ID_ICH8_82567V_3                0x1501
  74 #define IGC_DEV_ID_ICH8_IGP_M_AMT               0x1049
  75 #define IGC_DEV_ID_ICH8_IGP_AMT         0x104A
  76 #define IGC_DEV_ID_ICH8_IGP_C                   0x104B
  77 #define IGC_DEV_ID_ICH8_IFE                     0x104C
  78 #define IGC_DEV_ID_ICH8_IFE_GT          0x10C4
  79 #define IGC_DEV_ID_ICH8_IFE_G                   0x10C5
  80 #define IGC_DEV_ID_ICH8_IGP_M                   0x104D
  81 #define IGC_DEV_ID_ICH9_IGP_M                   0x10BF
  82 #define IGC_DEV_ID_ICH9_IGP_M_AMT               0x10F5
  83 #define IGC_DEV_ID_ICH9_IGP_M_V         0x10CB
  84 #define IGC_DEV_ID_ICH9_IGP_AMT         0x10BD
  85 #define IGC_DEV_ID_ICH9_BM                      0x10E5
  86 #define IGC_DEV_ID_ICH9_IGP_C                   0x294C
  87 #define IGC_DEV_ID_ICH9_IFE                     0x10C0
  88 #define IGC_DEV_ID_ICH9_IFE_GT          0x10C3
  89 #define IGC_DEV_ID_ICH9_IFE_G                   0x10C2
  90 #define IGC_DEV_ID_ICH10_R_BM_LM                0x10CC
  91 #define IGC_DEV_ID_ICH10_R_BM_LF                0x10CD
  92 #define IGC_DEV_ID_ICH10_R_BM_V         0x10CE
  93 #define IGC_DEV_ID_ICH10_D_BM_LM                0x10DE
  94 #define IGC_DEV_ID_ICH10_D_BM_LF                0x10DF
  95 #define IGC_DEV_ID_ICH10_D_BM_V         0x1525
  96 #define IGC_DEV_ID_PCH_M_HV_LM          0x10EA
  97 #define IGC_DEV_ID_PCH_M_HV_LC          0x10EB
  98 #define IGC_DEV_ID_PCH_D_HV_DM          0x10EF
  99 #define IGC_DEV_ID_PCH_D_HV_DC          0x10F0
 100 #define IGC_DEV_ID_PCH2_LV_LM                   0x1502
 101 #define IGC_DEV_ID_PCH2_LV_V                    0x1503
 102 #define IGC_DEV_ID_PCH_LPT_I217_LM              0x153A
 103 #define IGC_DEV_ID_PCH_LPT_I217_V               0x153B
 104 #define IGC_DEV_ID_PCH_LPTLP_I218_LM            0x155A
 105 #define IGC_DEV_ID_PCH_LPTLP_I218_V             0x1559
 106 #define IGC_DEV_ID_PCH_I218_LM2         0x15A0
 107 #define IGC_DEV_ID_PCH_I218_V2          0x15A1
 108 #define IGC_DEV_ID_PCH_I218_LM3         0x15A2 /* Wildcat Point PCH */
 109 #define IGC_DEV_ID_PCH_I218_V3          0x15A3 /* Wildcat Point PCH */
 110 #define IGC_DEV_ID_PCH_SPT_I219_LM              0x156F /* Sunrise Point PCH */
 111 #define IGC_DEV_ID_PCH_SPT_I219_V               0x1570 /* Sunrise Point PCH */
 112 #define IGC_DEV_ID_PCH_SPT_I219_LM2             0x15B7 /* Sunrise Point-H PCH */
 113 #define IGC_DEV_ID_PCH_SPT_I219_V2              0x15B8 /* Sunrise Point-H PCH */
 114 #define IGC_DEV_ID_PCH_LBG_I219_LM3             0x15B9 /* LEWISBURG PCH */
 115 #define IGC_DEV_ID_PCH_SPT_I219_LM4             0x15D7
 116 #define IGC_DEV_ID_PCH_SPT_I219_V4              0x15D8
 117 #define IGC_DEV_ID_PCH_SPT_I219_LM5             0x15E3
 118 #define IGC_DEV_ID_PCH_SPT_I219_V5              0x15D6
 119 #define IGC_DEV_ID_PCH_CNP_I219_LM6             0x15BD
 120 #define IGC_DEV_ID_PCH_CNP_I219_V6              0x15BE
 121 #define IGC_DEV_ID_PCH_CNP_I219_LM7             0x15BB
 122 #define IGC_DEV_ID_PCH_CNP_I219_V7              0x15BC
 123 #define IGC_DEV_ID_PCH_ICP_I219_LM8             0x15DF
 124 #define IGC_DEV_ID_PCH_ICP_I219_V8              0x15E0
 125 #define IGC_DEV_ID_PCH_ICP_I219_LM9             0x15E1
 126 #define IGC_DEV_ID_PCH_ICP_I219_V9              0x15E2
 127 #define IGC_DEV_ID_82576                        0x10C9
 128 #define IGC_DEV_ID_82576_FIBER          0x10E6
 129 #define IGC_DEV_ID_82576_SERDES         0x10E7
 130 #define IGC_DEV_ID_82576_QUAD_COPPER            0x10E8
 131 #define IGC_DEV_ID_82576_QUAD_COPPER_ET2        0x1526
 132 #define IGC_DEV_ID_82576_NS                     0x150A
 133 #define IGC_DEV_ID_82576_NS_SERDES              0x1518
 134 #define IGC_DEV_ID_82576_SERDES_QUAD            0x150D
 135 #define IGC_DEV_ID_82576_VF                     0x10CA
 136 #define IGC_DEV_ID_82576_VF_HV          0x152D
 137 #define IGC_DEV_ID_I350_VF                      0x1520
 138 #define IGC_DEV_ID_I350_VF_HV                   0x152F
 139 #define IGC_DEV_ID_82575EB_COPPER               0x10A7
 140 #define IGC_DEV_ID_82575EB_FIBER_SERDES 0x10A9
 141 #define IGC_DEV_ID_82575GB_QUAD_COPPER  0x10D6
 142 #define IGC_DEV_ID_82580_COPPER         0x150E
 143 #define IGC_DEV_ID_82580_FIBER          0x150F
 144 #define IGC_DEV_ID_82580_SERDES         0x1510
 145 #define IGC_DEV_ID_82580_SGMII          0x1511
 146 #define IGC_DEV_ID_82580_COPPER_DUAL            0x1516
 147 #define IGC_DEV_ID_82580_QUAD_FIBER             0x1527
 148 #define IGC_DEV_ID_I350_COPPER          0x1521
 149 #define IGC_DEV_ID_I350_FIBER                   0x1522
 150 #define IGC_DEV_ID_I350_SERDES          0x1523
 151 #define IGC_DEV_ID_I350_SGMII                   0x1524
 152 #define IGC_DEV_ID_I350_DA4                     0x1546
 153 #define IGC_DEV_ID_I210_COPPER          0x1533
 154 #define IGC_DEV_ID_I210_COPPER_OEM1             0x1534
 155 #define IGC_DEV_ID_I210_COPPER_IT               0x1535
 156 #define IGC_DEV_ID_I210_FIBER                   0x1536
 157 #define IGC_DEV_ID_I210_SERDES          0x1537
 158 #define IGC_DEV_ID_I210_SGMII                   0x1538
 159 #define IGC_DEV_ID_I210_COPPER_FLASHLESS        0x157B
 160 #define IGC_DEV_ID_I210_SERDES_FLASHLESS        0x157C
 161 #define IGC_DEV_ID_I210_SGMII_FLASHLESS 0x15F6
 162 #define IGC_DEV_ID_I211_COPPER          0x1539
 163 #define IGC_DEV_ID_I225_LM                      0x15F2
 164 #define IGC_DEV_ID_I225_V                       0x15F3
 165 #define IGC_DEV_ID_I225_K                       0x3100
 166 #define IGC_DEV_ID_I225_I                       0x15F8
 167 #define IGC_DEV_ID_I220_V                       0x15F7
 168 #define IGC_DEV_ID_I225_BLANK_NVM               0x15FD
 169 #define IGC_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40
 170 #define IGC_DEV_ID_I354_SGMII                   0x1F41
 171 #define IGC_DEV_ID_I354_BACKPLANE_2_5GBPS       0x1F45
 172 #define IGC_DEV_ID_DH89XXCC_SGMII               0x0438
 173 #define IGC_DEV_ID_DH89XXCC_SERDES              0x043A
 174 #define IGC_DEV_ID_DH89XXCC_BACKPLANE           0x043C
 175 #define IGC_DEV_ID_DH89XXCC_SFP         0x0440
 176
 177 #define IGC_REVISION_0  0
 178 #define IGC_REVISION_1  1
 179 #define IGC_REVISION_2  2
 180 #define IGC_REVISION_3  3
 181 #define IGC_REVISION_4  4
 182
 183 #define IGC_FUNC_0              0
 184 #define IGC_FUNC_1              1
 185 #define IGC_FUNC_2              2
 186 #define IGC_FUNC_3              3
 187
 188 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN0 0
 189 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN1 3
 190 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN2 6
 191 #define IGC_ALT_MAC_ADDRESS_OFFSET_LAN3 9
 192
 193 enum igc_mac_type {
 194         igc_undefined = 0,
 195         igc_82542,
 196         igc_82543,
 197         igc_82544,
 198         igc_82540,
 199         igc_82545,
 200         igc_82545_rev_3,
 201         igc_82546,
 202         igc_82546_rev_3,
 203         igc_82541,
 204         igc_82541_rev_2,
 205         igc_82547,
 206         igc_82547_rev_2,
 207         igc_82571,
 208         igc_82572,
 209         igc_82573,
 210         igc_82574,
 211         igc_82583,
 212         igc_80003es2lan,
 213         igc_ich8lan,
 214         igc_ich9lan,
 215         igc_ich10lan,
 216         igc_pchlan,
 217         igc_pch2lan,
 218         igc_pch_lpt,
 219         igc_pch_spt,
 220         igc_pch_cnp,
 221         igc_82575,
 222         igc_82576,
 223         igc_82580,
 224         igc_i350,
 225         igc_i354,
 226         igc_i210,
 227         igc_i211,
 228         igc_i225,
 229         igc_vfadapt,
 230         igc_vfadapt_i350,
 231         igc_num_macs  /* List is 1-based, so subtract 1 for true count. */
 232 };
 233
 234 enum igc_media_type {
 235         igc_media_type_unknown = 0,
 236         igc_media_type_copper = 1,
 237         igc_media_type_fiber = 2,
 238         igc_media_type_internal_serdes = 3,
 239         igc_num_media_types
 240 };
 241
 242 enum igc_nvm_type {
 243         igc_nvm_unknown = 0,
 244         igc_nvm_none,
 245         igc_nvm_eeprom_spi,
 246         igc_nvm_eeprom_microwire,
 247         igc_nvm_flash_hw,
 248         igc_nvm_invm,
 249         igc_nvm_flash_sw
 250 };
 251
 252 enum igc_nvm_override {
 253         igc_nvm_override_none = 0,
 254         igc_nvm_override_spi_small,
 255         igc_nvm_override_spi_large,
 256         igc_nvm_override_microwire_small,
 257         igc_nvm_override_microwire_large
 258 };
 259
 260 enum igc_phy_type {
 261         igc_phy_unknown = 0,
 262         igc_phy_none,
 263         igc_phy_m88,
 264         igc_phy_igp,
 265         igc_phy_igp_2,
 266         igc_phy_gg82563,
 267         igc_phy_igp_3,
 268         igc_phy_ife,
 269         igc_phy_bm,
 270         igc_phy_82578,
 271         igc_phy_82577,
 272         igc_phy_82579,
 273         igc_phy_i217,
 274         igc_phy_82580,
 275         igc_phy_vf,
 276         igc_phy_i210,
 277         igc_phy_i225,
 278 };
 279
 280 enum igc_bus_type {
 281         igc_bus_type_unknown = 0,
 282         igc_bus_type_pci,
 283         igc_bus_type_pcix,
 284         igc_bus_type_pci_express,
 285         igc_bus_type_reserved
 286 };
 287
 288 enum igc_bus_speed {
 289         igc_bus_speed_unknown = 0,
 290         igc_bus_speed_33,
 291         igc_bus_speed_66,
 292         igc_bus_speed_100,
 293         igc_bus_speed_120,
 294         igc_bus_speed_133,
 295         igc_bus_speed_2500,
 296         igc_bus_speed_5000,
 297         igc_bus_speed_reserved
 298 };
 299
 300 enum igc_bus_width {
 301         igc_bus_width_unknown = 0,
 302         igc_bus_width_pcie_x1,
 303         igc_bus_width_pcie_x2,
 304         igc_bus_width_pcie_x4 = 4,
 305         igc_bus_width_pcie_x8 = 8,
 306         igc_bus_width_32,
 307         igc_bus_width_64,
 308         igc_bus_width_reserved
 309 };
 310
 311 enum igc_1000t_rx_status {
 312         igc_1000t_rx_status_not_ok = 0,
 313         igc_1000t_rx_status_ok,
 314         igc_1000t_rx_status_undefined = 0xFF
 315 };
 316
 317 enum igc_rev_polarity {
 318         igc_rev_polarity_normal = 0,
 319         igc_rev_polarity_reversed,
 320         igc_rev_polarity_undefined = 0xFF
 321 };
 322
 323 enum igc_fc_mode {
 324         igc_fc_none = 0,
 325         igc_fc_rx_pause,
 326         igc_fc_tx_pause,
 327         igc_fc_full,
 328         igc_fc_default = 0xFF
 329 };
 330
 331 enum igc_ffe_config {
 332         igc_ffe_config_enabled = 0,
 333         igc_ffe_config_active,
 334         igc_ffe_config_blocked
 335 };
 336
 337 enum igc_dsp_config {
 338         igc_dsp_config_disabled = 0,
 339         igc_dsp_config_enabled,
 340         igc_dsp_config_activated,
 341         igc_dsp_config_undefined = 0xFF
 342 };
 343
 344 enum igc_ms_type {
 345         igc_ms_hw_default = 0,
 346         igc_ms_force_master,
 347         igc_ms_force_slave,
 348         igc_ms_auto
 349 };
 350
 351 enum igc_smart_speed {
 352         igc_smart_speed_default = 0,
 353         igc_smart_speed_on,
 354         igc_smart_speed_off
 355 };
 356
 357 enum igc_serdes_link_state {
 358         igc_serdes_link_down = 0,
 359         igc_serdes_link_autoneg_progress,
 360         igc_serdes_link_autoneg_complete,
 361         igc_serdes_link_forced_up
 362 };
 363
 364 enum igc_invm_structure_type {
 365         igc_invm_uninitialized_structure                = 0x00,
 366         igc_invm_word_autoload_structure                = 0x01,
 367         igc_invm_csr_autoload_structure         = 0x02,
 368         igc_invm_phy_register_autoload_structure        = 0x03,
 369         igc_invm_rsa_key_sha256_structure               = 0x04,
 370         igc_invm_invalidated_structure          = 0x0f,
 371 };
 372
 373 #define __le16 u16
 374 #define __le32 u32
 375 #define __le64 u64
 376 /* Receive Descriptor */
 377 struct igc_rx_desc {
 378         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 379         __le16 length;      /* Length of data DMAed into data buffer */
 380         __le16 csum; /* Packet checksum */
 381         u8  status;  /* Descriptor status */
 382         u8  errors;  /* Descriptor Errors */
 383         __le16 special;
 384 };
 385
 386 /* Receive Descriptor - Extended */
 387 union igc_rx_desc_extended {
 388         struct {
 389                 __le64 buffer_addr;
 390                 __le64 reserved;
 391         } read;
 392         struct {
 393                 struct {
 394                         __le32 mrq; /* Multiple Rx Queues */
 395                         union {
 396                                 __le32 rss; /* RSS Hash */
 397                                 struct {
 398                                         __le16 ip_id;  /* IP id */
 399                                         __le16 csum;   /* Packet Checksum */
 400                                 } csum_ip;
 401                         } hi_dword;
 402                 } lower;
 403                 struct {
 404                         __le32 status_error;  /* ext status/error */
 405                         __le16 length;
 406                         __le16 vlan; /* VLAN tag */
 407                 } upper;
 408         } wb;  /* writeback */
 409 };
 410
 411 #define MAX_PS_BUFFERS 4
 412
 413 /* Number of packet split data buffers (not including the header buffer) */
 414 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 415
 416 /* Receive Descriptor - Packet Split */
 417 union igc_rx_desc_packet_split {
 418         struct {
 419                 /* one buffer for protocol header(s), three data buffers */
 420                 __le64 buffer_addr[MAX_PS_BUFFERS];
 421         } read;
 422         struct {
 423                 struct {
 424                         __le32 mrq;  /* Multiple Rx Queues */
 425                         union {
 426                                 __le32 rss; /* RSS Hash */
 427                                 struct {
 428                                         __le16 ip_id;    /* IP id */
 429                                         __le16 csum;     /* Packet Checksum */
 430                                 } csum_ip;
 431                         } hi_dword;
 432                 } lower;
 433                 struct {
 434                         __le32 status_error;  /* ext status/error */
 435                         __le16 length0;  /* length of buffer 0 */
 436                         __le16 vlan;  /* VLAN tag */
 437                 } middle;
 438                 struct {
 439                         __le16 header_status;
 440                         /* length of buffers 1-3 */
 441                         __le16 length[PS_PAGE_BUFFERS];
 442                 } upper;
 443                 __le64 reserved;
 444         } wb; /* writeback */
 445 };
 446
 447 /* Transmit Descriptor */
 448 struct igc_tx_desc {
 449         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 450         union {
 451                 __le32 data;
 452                 struct {
 453                         __le16 length;  /* Data buffer length */
 454                         u8 cso;  /* Checksum offset */
 455                         u8 cmd;  /* Descriptor control */
 456                 } flags;
 457         } lower;
 458         union {
 459                 __le32 data;
 460                 struct {
 461                         u8 status; /* Descriptor status */
 462                         u8 css;  /* Checksum start */
 463                         __le16 special;
 464                 } fields;
 465         } upper;
 466 };
 467
 468 /* Offload Context Descriptor */
 469 struct igc_context_desc {
 470         union {
 471                 __le32 ip_config;
 472                 struct {
 473                         u8 ipcss;  /* IP checksum start */
 474                         u8 ipcso;  /* IP checksum offset */
 475                         __le16 ipcse;  /* IP checksum end */
 476                 } ip_fields;
 477         } lower_setup;
 478         union {
 479                 __le32 tcp_config;
 480                 struct {
 481                         u8 tucss;  /* TCP checksum start */
 482                         u8 tucso;  /* TCP checksum offset */
 483                         __le16 tucse;  /* TCP checksum end */
 484                 } tcp_fields;
 485         } upper_setup;
 486         __le32 cmd_and_length;
 487         union {
 488                 __le32 data;
 489                 struct {
 490                         u8 status;  /* Descriptor status */
 491                         u8 hdr_len;  /* Header length */
 492                         __le16 mss;  /* Maximum segment size */
 493                 } fields;
 494         } tcp_seg_setup;
 495 };
 496
 497 /* Offload data descriptor */
 498 struct igc_data_desc {
 499         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 500         union {
 501                 __le32 data;
 502                 struct {
 503                         __le16 length;  /* Data buffer length */
 504                         u8 typ_len_ext;
 505                         u8 cmd;
 506                 } flags;
 507         } lower;
 508         union {
 509                 __le32 data;
 510                 struct {
 511                         u8 status;  /* Descriptor status */
 512                         u8 popts;  /* Packet Options */
 513                         __le16 special;
 514                 } fields;
 515         } upper;
 516 };
 517
 518 /* Statistics counters collected by the MAC */
 519 struct igc_hw_stats {
 520         u64 crcerrs;
 521         u64 algnerrc;
 522         u64 symerrs;
 523         u64 rxerrc;
 524         u64 mpc;
 525         u64 scc;
 526         u64 ecol;
 527         u64 mcc;
 528         u64 latecol;
 529         u64 colc;
 530         u64 dc;
 531         u64 tncrs;
 532         u64 sec;
 533         u64 cexterr;
 534         u64 rlec;
 535         u64 xonrxc;
 536         u64 xontxc;
 537         u64 xoffrxc;
 538         u64 xofftxc;
 539         u64 fcruc;
 540         u64 prc64;
 541         u64 prc127;
 542         u64 prc255;
 543         u64 prc511;
 544         u64 prc1023;
 545         u64 prc1522;
 546         u64 gprc;
 547         u64 bprc;
 548         u64 mprc;
 549         u64 gptc;
 550         u64 gorc;
 551         u64 gotc;
 552         u64 rnbc;
 553         u64 ruc;
 554         u64 rfc;
 555         u64 roc;
 556         u64 rjc;
 557         u64 mgprc;
 558         u64 mgpdc;
 559         u64 mgptc;
 560         u64 tor;
 561         u64 tot;
 562         u64 tpr;
 563         u64 tpt;
 564         u64 ptc64;
 565         u64 ptc127;
 566         u64 ptc255;
 567         u64 ptc511;
 568         u64 ptc1023;
 569         u64 ptc1522;
 570         u64 mptc;
 571         u64 bptc;
 572         u64 tsctc;
 573         u64 tsctfc;
 574         u64 iac;
 575         u64 icrxptc;
 576         u64 icrxatc;
 577         u64 ictxptc;
 578         u64 ictxatc;
 579         u64 ictxqec;
 580         u64 ictxqmtc;
 581         u64 icrxdmtc;
 582         u64 icrxoc;
 583         u64 cbtmpc;
 584         u64 htdpmc;
 585         u64 cbrdpc;
 586         u64 cbrmpc;
 587         u64 rpthc;
 588         u64 hgptc;
 589         u64 htcbdpc;
 590         u64 hgorc;
 591         u64 hgotc;
 592         u64 lenerrs;
 593         u64 scvpc;
 594         u64 hrmpc;
 595         u64 doosync;
 596         u64 o2bgptc;
 597         u64 o2bspc;
 598         u64 b2ospc;
 599         u64 b2ogprc;
 600 };
 601
 602 struct igc_vf_stats {
 603         u64 base_gprc;
 604         u64 base_gptc;
 605         u64 base_gorc;
 606         u64 base_gotc;
 607         u64 base_mprc;
 608         u64 base_gotlbc;
 609         u64 base_gptlbc;
 610         u64 base_gorlbc;
 611         u64 base_gprlbc;
 612
 613         u32 last_gprc;
 614         u32 last_gptc;
 615         u32 last_gorc;
 616         u32 last_gotc;
 617         u32 last_mprc;
 618         u32 last_gotlbc;
 619         u32 last_gptlbc;
 620         u32 last_gorlbc;
 621         u32 last_gprlbc;
 622
 623         u64 gprc;
 624         u64 gptc;
 625         u64 gorc;
 626         u64 gotc;
 627         u64 mprc;
 628         u64 gotlbc;
 629         u64 gptlbc;
 630         u64 gorlbc;
 631         u64 gprlbc;
 632 };
 633
 634 struct igc_phy_stats {
 635         u32 idle_errors;
 636         u32 receive_errors;
 637 };
 638
 639 struct igc_host_mng_dhcp_cookie {
 640         u32 signature;
 641         u8  status;
 642         u8  reserved0;
 643         u16 vlan_id;
 644         u32 reserved1;
 645         u16 reserved2;
 646         u8  reserved3;
 647         u8  checksum;
 648 };
 649
 650 /* Host Interface "Rev 1" */
 651 struct igc_host_command_header {
 652         u8 command_id;
 653         u8 command_length;
 654         u8 command_options;
 655         u8 checksum;
 656 };
 657
 658 #define IGC_HI_MAX_DATA_LENGTH  252
 659 struct igc_host_command_info {
 660         struct igc_host_command_header command_header;
 661         u8 command_data[IGC_HI_MAX_DATA_LENGTH];
 662 };
 663
 664 /* Host Interface "Rev 2" */
 665 struct igc_host_mng_command_header {
 666         u8  command_id;
 667         u8  checksum;
 668         u16 reserved1;
 669         u16 reserved2;
 670         u16 command_length;
 671 };
 672
 673 #define IGC_HI_MAX_MNG_DATA_LENGTH      0x6F8
 674 struct igc_host_mng_command_info {
 675         struct igc_host_mng_command_header command_header;
 676         u8 command_data[IGC_HI_MAX_MNG_DATA_LENGTH];
 677 };
 678
 679 #include "igc_mac.h"
 680 #include "igc_phy.h"
 681 #include "igc_nvm.h"
 682 #include "igc_manage.h"
 683
 684 /* Function pointers for the MAC. */
 685 struct igc_mac_operations {
 686         s32  (*init_params)(struct igc_hw *hw);
 687         s32  (*id_led_init)(struct igc_hw *hw);
 688         s32  (*blink_led)(struct igc_hw *hw);
 689         bool (*check_mng_mode)(struct igc_hw *hw);
 690         s32  (*check_for_link)(struct igc_hw *hw);
 691         s32  (*cleanup_led)(struct igc_hw *hw);
 692         void (*clear_hw_cntrs)(struct igc_hw *hw);
 693         void (*clear_vfta)(struct igc_hw *hw);
 694         s32  (*get_bus_info)(struct igc_hw *hw);
 695         void (*set_lan_id)(struct igc_hw *hw);
 696         s32  (*get_link_up_info)(struct igc_hw *hw, u16 *speed, u16 *duplex);
 697         s32  (*led_on)(struct igc_hw *hw);
 698         s32  (*led_off)(struct igc_hw *hw);
 699         void (*update_mc_addr_list)(struct igc_hw *hw,
 700                         u8 *mc_addr_list, u32 count);
 701         s32  (*reset_hw)(struct igc_hw *hw);
 702         s32  (*init_hw)(struct igc_hw *hw);
 703         void (*shutdown_serdes)(struct igc_hw *hw);
 704         void (*power_up_serdes)(struct igc_hw *hw);
 705         s32  (*setup_link)(struct igc_hw *hw);
 706         s32  (*setup_physical_interface)(struct igc_hw *hw);
 707         s32  (*setup_led)(struct igc_hw *hw);
 708         void (*write_vfta)(struct igc_hw *hw, u32 offset, u32 value);
 709         void (*config_collision_dist)(struct igc_hw *hw);
 710         int  (*rar_set)(struct igc_hw *hw, u8 *addr, u32 index);
 711         s32  (*read_mac_addr)(struct igc_hw *hw);
 712         s32  (*validate_mdi_setting)(struct igc_hw *hw);
 713         s32  (*acquire_swfw_sync)(struct igc_hw *hw, u16 mask);
 714         void (*release_swfw_sync)(struct igc_hw *hw, u16 mask);
 715 };
 716
 717 /* When to use various PHY register access functions:
 718  *
 719  *                 Func   Caller
 720  *   Function      Does   Does    When to use
 721  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 722  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 723  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 724  *                                on different pages
 725  *   X_reg_page    A      L,P     for multiple accesses of different regs
 726  *                                on the same page
 727  *
 728  * Where X=[read|write], L=locking, P=sets page, A=register access
 729  *
 730  */
 731 struct igc_phy_operations {
 732         s32  (*init_params)(struct igc_hw *hw);
 733         s32  (*acquire)(struct igc_hw *hw);
 734         s32  (*cfg_on_link_up)(struct igc_hw *hw);
 735         s32  (*check_polarity)(struct igc_hw *hw);
 736         s32  (*check_reset_block)(struct igc_hw *hw);
 737         s32  (*commit)(struct igc_hw *hw);
 738         s32  (*force_speed_duplex)(struct igc_hw *hw);
 739         s32  (*get_cfg_done)(struct igc_hw *hw);
 740         s32  (*get_cable_length)(struct igc_hw *hw);
 741         s32  (*get_info)(struct igc_hw *hw);
 742         s32  (*set_page)(struct igc_hw *hw, u16 page);
 743         s32  (*read_reg)(struct igc_hw *hw, u32 offset, u16 *data);
 744         s32  (*read_reg_locked)(struct igc_hw *hw, u32 offset, u16 *data);
 745         s32  (*read_reg_page)(struct igc_hw *hw, u32 offset, u16 *data);
 746         void (*release)(struct igc_hw *hw);
 747         s32  (*reset)(struct igc_hw *hw);
 748         s32  (*set_d0_lplu_state)(struct igc_hw *hw, bool active);
 749         s32  (*set_d3_lplu_state)(struct igc_hw *hw, bool active);
 750         s32  (*write_reg)(struct igc_hw *hw, u32 offset, u16 data);
 751         s32  (*write_reg_locked)(struct igc_hw *hw, u32 offset, u16 data);
 752         s32  (*write_reg_page)(struct igc_hw *hw, u32 offset, u16 data);
 753         void (*power_up)(struct igc_hw *hw);
 754         void (*power_down)(struct igc_hw *hw);
 755         s32 (*read_i2c_byte)(struct igc_hw *hw, u8 byte_offset,
 756                         u8 dev_addr, u8 *data);
 757         s32 (*write_i2c_byte)(struct igc_hw *hw, u8 byte_offset,
 758                         u8 dev_addr, u8 data);
 759 };
 760
 761 /* Function pointers for the NVM. */
 762 struct igc_nvm_operations {
 763         s32  (*init_params)(struct igc_hw *hw);
 764         s32  (*acquire)(struct igc_hw *hw);
 765         s32  (*read)(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
 766         void (*release)(struct igc_hw *hw);
 767         void (*reload)(struct igc_hw *hw);
 768         s32  (*update)(struct igc_hw *hw);
 769         s32  (*valid_led_default)(struct igc_hw *hw, u16 *data);
 770         s32  (*validate)(struct igc_hw *hw);
 771         s32  (*write)(struct igc_hw *hw, u16 offset, u16 words, u16 *data);
 772 };
 773
 774 struct igc_info {
 775         s32 (*get_invariants)(struct igc_hw *hw);
 776         struct igc_mac_operations *mac_ops;
 777         const struct igc_phy_operations *phy_ops;
 778         struct igc_nvm_operations *nvm_ops;
 779 };
 780
 781 extern const struct igc_info igc_i225_info;
 782
 783 struct igc_mac_info {
 784         struct igc_mac_operations ops;
 785         u8 addr[ETH_ADDR_LEN];
 786         u8 perm_addr[ETH_ADDR_LEN];
 787
 788         enum igc_mac_type type;
 789
 790         u32 collision_delta;
 791         u32 ledctl_default;
 792         u32 ledctl_mode1;
 793         u32 ledctl_mode2;
 794         u32 mc_filter_type;
 795         u32 tx_packet_delta;
 796         u32 txcw;
 797
 798         u16 current_ifs_val;
 799         u16 ifs_max_val;
 800         u16 ifs_min_val;
 801         u16 ifs_ratio;
 802         u16 ifs_step_size;
 803         u16 mta_reg_count;
 804         u16 uta_reg_count;
 805
 806         /* Maximum size of the MTA register table in all supported adapters */
 807 #define MAX_MTA_REG 128
 808         u32 mta_shadow[MAX_MTA_REG];
 809         u16 rar_entry_count;
 810
 811         u8  forced_speed_duplex;
 812
 813         bool adaptive_ifs;
 814         bool has_fwsm;
 815         bool arc_subsystem_valid;
 816         bool asf_firmware_present;
 817         bool autoneg;
 818         bool autoneg_failed;
 819         bool get_link_status;
 820         bool in_ifs_mode;
 821         bool report_tx_early;
 822         enum igc_serdes_link_state serdes_link_state;
 823         bool serdes_has_link;
 824         bool tx_pkt_filtering;
 825 };
 826
 827 struct igc_phy_info {
 828         struct igc_phy_operations ops;
 829         enum igc_phy_type type;
 830
 831         enum igc_1000t_rx_status local_rx;
 832         enum igc_1000t_rx_status remote_rx;
 833         enum igc_ms_type ms_type;
 834         enum igc_ms_type original_ms_type;
 835         enum igc_rev_polarity cable_polarity;
 836         enum igc_smart_speed smart_speed;
 837
 838         u32 addr;
 839         u32 id;
 840         u32 reset_delay_us; /* in usec */
 841         u32 revision;
 842
 843         enum igc_media_type media_type;
 844
 845         u16 autoneg_advertised;
 846         u16 autoneg_mask;
 847         u16 cable_length;
 848         u16 max_cable_length;
 849         u16 min_cable_length;
 850
 851         u8 mdix;
 852
 853         bool disable_polarity_correction;
 854         bool is_mdix;
 855         bool polarity_correction;
 856         bool speed_downgraded;
 857         bool autoneg_wait_to_complete;
 858 };
 859
 860 struct igc_nvm_info {
 861         struct igc_nvm_operations ops;
 862         enum igc_nvm_type type;
 863         enum igc_nvm_override override;
 864
 865         u32 flash_bank_size;
 866         u32 flash_base_addr;
 867
 868         u16 word_size;
 869         u16 delay_usec;
 870         u16 address_bits;
 871         u16 opcode_bits;
 872         u16 page_size;
 873 };
 874
 875 struct igc_bus_info {
 876         enum igc_bus_type type;
 877         enum igc_bus_speed speed;
 878         enum igc_bus_width width;
 879
 880         u16 func;
 881         u16 pci_cmd_word;
 882 };
 883
 884 struct igc_fc_info {
 885         u32 high_water;  /* Flow control high-water mark */
 886         u32 low_water;  /* Flow control low-water mark */
 887         u16 pause_time;  /* Flow control pause timer */
 888         u16 refresh_time;  /* Flow control refresh timer */
 889         bool send_xon;  /* Flow control send XON */
 890         bool strict_ieee;  /* Strict IEEE mode */
 891         enum igc_fc_mode current_mode;  /* FC mode in effect */
 892         enum igc_fc_mode requested_mode;  /* FC mode requested by caller */
 893 };
 894
 895 struct igc_mbx_operations {
 896         s32 (*init_params)(struct igc_hw *hw);
 897 };
 898
 899 struct igc_mbx_stats {
 900         u32 msgs_tx;
 901         u32 msgs_rx;
 902
 903         u32 acks;
 904         u32 reqs;
 905         u32 rsts;
 906 };
 907
 908 struct igc_mbx_info {
 909         struct igc_mbx_operations ops;
 910         struct igc_mbx_stats stats;
 911         u32 timeout;
 912         u32 usec_delay;
 913         u16 size;
 914 };
 915
 916 struct igc_dev_spec_82541 {
 917         enum igc_dsp_config dsp_config;
 918         enum igc_ffe_config ffe_config;
 919         u16 spd_default;
 920         bool phy_init_script;
 921 };
 922
 923 struct igc_dev_spec_82542 {
 924         bool dma_fairness;
 925 };
 926
 927 struct igc_dev_spec_82543 {
 928         u32  tbi_compatibility;
 929         bool dma_fairness;
 930         bool init_phy_disabled;
 931 };
 932
 933 struct igc_dev_spec_82571 {
 934         bool laa_is_present;
 935         u32 smb_counter;
 936         IGC_MUTEX swflag_mutex;
 937 };
 938
 939 struct igc_dev_spec_80003es2lan {
 940         bool  mdic_wa_enable;
 941 };
 942
 943 struct igc_shadow_ram {
 944         u16  value;
 945         bool modified;
 946 };
 947
 948 #define IGC_SHADOW_RAM_WORDS            2048
 949
 950 /* I218 PHY Ultra Low Power (ULP) states */
 951 enum igc_ulp_state {
 952         igc_ulp_state_unknown,
 953         igc_ulp_state_off,
 954         igc_ulp_state_on,
 955 };
 956
 957 struct igc_dev_spec_ich8lan {
 958         bool kmrn_lock_loss_workaround_enabled;
 959         struct igc_shadow_ram shadow_ram[IGC_SHADOW_RAM_WORDS];
 960         IGC_MUTEX nvm_mutex;
 961         IGC_MUTEX swflag_mutex;
 962         bool nvm_k1_enabled;
 963         bool disable_k1_off;
 964         bool eee_disable;
 965         u16 eee_lp_ability;
 966         enum igc_ulp_state ulp_state;
 967         bool ulp_capability_disabled;
 968         bool during_suspend_flow;
 969         bool during_dpg_exit;
 970         u16 lat_enc;
 971         u16 max_ltr_enc;
 972         bool smbus_disable;
 973 };
 974
 975 struct igc_dev_spec_82575 {
 976         bool sgmii_active;
 977         bool global_device_reset;
 978         bool eee_disable;
 979         bool module_plugged;
 980         bool clear_semaphore_once;
 981         u32 mtu;
 982         struct sfp_igc_flags eth_flags;
 983         u8 media_port;
 984         bool media_changed;
 985 };
 986
 987 struct igc_dev_spec_vf {
 988         u32 vf_number;
 989         u32 v2p_mailbox;
 990 };
 991
 992 struct igc_dev_spec_i225 {
 993         bool global_device_reset;
 994         bool eee_disable;
 995         bool clear_semaphore_once;
 996         bool module_plugged;
 997         u8 media_port;
 998         bool mas_capable;
 999         u32 mtu;
1000 };
1001
1002 struct igc_hw {
1003         void *back;
1004
1005         u8 *hw_addr;
1006         u8 *flash_address;
1007         unsigned long io_base;
1008
1009         struct igc_mac_info  mac;
1010         struct igc_fc_info   fc;
1011         struct igc_phy_info  phy;
1012         struct igc_nvm_info  nvm;
1013         struct igc_bus_info  bus;
1014         struct igc_mbx_info mbx;
1015         struct igc_host_mng_dhcp_cookie mng_cookie;
1016
1017         union {
1018                 struct igc_dev_spec_82541 _82541;
1019                 struct igc_dev_spec_82542 _82542;
1020                 struct igc_dev_spec_82543 _82543;
1021                 struct igc_dev_spec_82571 _82571;
1022                 struct igc_dev_spec_80003es2lan _80003es2lan;
1023                 struct igc_dev_spec_ich8lan ich8lan;
1024                 struct igc_dev_spec_82575 _82575;
1025                 struct igc_dev_spec_vf vf;
1026                 struct igc_dev_spec_i225 _i225;
1027         } dev_spec;
1028
1029         u16 device_id;
1030         u16 subsystem_vendor_id;
1031         u16 subsystem_device_id;
1032         u16 vendor_id;
1033
1034         u8  revision_id;
1035 };
1036
1037 #include "igc_82571.h"
1038 #include "igc_ich8lan.h"
1039 #include "igc_82575.h"
1040 #include "igc_i225.h"
1041 #include "igc_base.h"
1042
1043 /* These functions must be implemented by drivers */
1044 void igc_pci_clear_mwi(struct igc_hw *hw);
1045 void igc_pci_set_mwi(struct igc_hw *hw);
1046 s32  igc_read_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
1047 s32  igc_write_pcie_cap_reg(struct igc_hw *hw, u32 reg, u16 *value);
1048 void igc_read_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
1049 void igc_write_pci_cfg(struct igc_hw *hw, u32 reg, u16 *value);
1050
1051 #endif