1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
7 static s32 igc_validate_mdi_setting_generic(struct igc_hw *hw);
8 static void igc_set_lan_id_multi_port_pcie(struct igc_hw *hw);
9 static void igc_config_collision_dist_generic(struct igc_hw *hw);
10 static int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index);
13 * igc_init_mac_ops_generic - Initialize MAC function pointers
14 * @hw: pointer to the HW structure
16 * Setups up the function pointers to no-op functions
18 void igc_init_mac_ops_generic(struct igc_hw *hw)
20 struct igc_mac_info *mac = &hw->mac;
21 DEBUGFUNC("igc_init_mac_ops_generic");
24 mac->ops.init_params = igc_null_ops_generic;
25 mac->ops.init_hw = igc_null_ops_generic;
26 mac->ops.reset_hw = igc_null_ops_generic;
27 mac->ops.setup_physical_interface = igc_null_ops_generic;
28 mac->ops.get_bus_info = igc_null_ops_generic;
29 mac->ops.set_lan_id = igc_set_lan_id_multi_port_pcie;
30 mac->ops.read_mac_addr = igc_read_mac_addr_generic;
31 mac->ops.config_collision_dist = igc_config_collision_dist_generic;
32 mac->ops.clear_hw_cntrs = igc_null_mac_generic;
34 mac->ops.cleanup_led = igc_null_ops_generic;
35 mac->ops.setup_led = igc_null_ops_generic;
36 mac->ops.blink_led = igc_null_ops_generic;
37 mac->ops.led_on = igc_null_ops_generic;
38 mac->ops.led_off = igc_null_ops_generic;
40 mac->ops.setup_link = igc_null_ops_generic;
41 mac->ops.get_link_up_info = igc_null_link_info;
42 mac->ops.check_for_link = igc_null_ops_generic;
44 mac->ops.check_mng_mode = igc_null_mng_mode;
46 mac->ops.update_mc_addr_list = igc_null_update_mc;
47 mac->ops.clear_vfta = igc_null_mac_generic;
48 mac->ops.write_vfta = igc_null_write_vfta;
49 mac->ops.rar_set = igc_rar_set_generic;
50 mac->ops.validate_mdi_setting = igc_validate_mdi_setting_generic;
54 * igc_null_ops_generic - No-op function, returns 0
55 * @hw: pointer to the HW structure
57 s32 igc_null_ops_generic(struct igc_hw IGC_UNUSEDARG * hw)
59 DEBUGFUNC("igc_null_ops_generic");
60 UNREFERENCED_1PARAMETER(hw);
65 * igc_null_mac_generic - No-op function, return void
66 * @hw: pointer to the HW structure
68 void igc_null_mac_generic(struct igc_hw IGC_UNUSEDARG * hw)
70 DEBUGFUNC("igc_null_mac_generic");
71 UNREFERENCED_1PARAMETER(hw);
75 * igc_null_link_info - No-op function, return 0
76 * @hw: pointer to the HW structure
80 s32 igc_null_link_info(struct igc_hw IGC_UNUSEDARG * hw,
81 u16 IGC_UNUSEDARG * s, u16 IGC_UNUSEDARG * d)
83 DEBUGFUNC("igc_null_link_info");
84 UNREFERENCED_3PARAMETER(hw, s, d);
89 * igc_null_mng_mode - No-op function, return false
90 * @hw: pointer to the HW structure
92 bool igc_null_mng_mode(struct igc_hw IGC_UNUSEDARG * hw)
94 DEBUGFUNC("igc_null_mng_mode");
95 UNREFERENCED_1PARAMETER(hw);
100 * igc_null_update_mc - No-op function, return void
101 * @hw: pointer to the HW structure
105 void igc_null_update_mc(struct igc_hw IGC_UNUSEDARG * hw,
106 u8 IGC_UNUSEDARG * h, u32 IGC_UNUSEDARG a)
108 DEBUGFUNC("igc_null_update_mc");
109 UNREFERENCED_3PARAMETER(hw, h, a);
113 * igc_null_write_vfta - No-op function, return void
114 * @hw: pointer to the HW structure
118 void igc_null_write_vfta(struct igc_hw IGC_UNUSEDARG * hw,
119 u32 IGC_UNUSEDARG a, u32 IGC_UNUSEDARG b)
121 DEBUGFUNC("igc_null_write_vfta");
122 UNREFERENCED_3PARAMETER(hw, a, b);
126 * igc_null_rar_set - No-op function, return 0
127 * @hw: pointer to the HW structure
131 int igc_null_rar_set(struct igc_hw IGC_UNUSEDARG * hw,
132 u8 IGC_UNUSEDARG * h, u32 IGC_UNUSEDARG a)
134 DEBUGFUNC("igc_null_rar_set");
135 UNREFERENCED_3PARAMETER(hw, h, a);
140 * igc_get_bus_info_pci_generic - Get PCI(x) bus information
141 * @hw: pointer to the HW structure
143 * Determines and stores the system bus information for a particular
144 * network interface. The following bus information is determined and stored:
145 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
147 s32 igc_get_bus_info_pci_generic(struct igc_hw *hw)
149 struct igc_mac_info *mac = &hw->mac;
150 struct igc_bus_info *bus = &hw->bus;
151 u32 status = IGC_READ_REG(hw, IGC_STATUS);
152 s32 ret_val = IGC_SUCCESS;
154 DEBUGFUNC("igc_get_bus_info_pci_generic");
157 bus->type = (status & IGC_STATUS_PCIX_MODE)
162 if (bus->type == igc_bus_type_pci) {
163 bus->speed = (status & IGC_STATUS_PCI66)
167 switch (status & IGC_STATUS_PCIX_SPEED) {
168 case IGC_STATUS_PCIX_SPEED_66:
169 bus->speed = igc_bus_speed_66;
171 case IGC_STATUS_PCIX_SPEED_100:
172 bus->speed = igc_bus_speed_100;
174 case IGC_STATUS_PCIX_SPEED_133:
175 bus->speed = igc_bus_speed_133;
178 bus->speed = igc_bus_speed_reserved;
184 bus->width = (status & IGC_STATUS_BUS64)
188 /* Which PCI(-X) function? */
189 mac->ops.set_lan_id(hw);
195 * igc_get_bus_info_pcie_generic - Get PCIe bus information
196 * @hw: pointer to the HW structure
198 * Determines and stores the system bus information for a particular
199 * network interface. The following bus information is determined and stored:
200 * bus speed, bus width, type (PCIe), and PCIe function.
202 s32 igc_get_bus_info_pcie_generic(struct igc_hw *hw)
204 struct igc_mac_info *mac = &hw->mac;
205 struct igc_bus_info *bus = &hw->bus;
207 u16 pcie_link_status;
209 DEBUGFUNC("igc_get_bus_info_pcie_generic");
211 bus->type = igc_bus_type_pci_express;
213 ret_val = igc_read_pcie_cap_reg(hw, PCIE_LINK_STATUS,
216 bus->width = igc_bus_width_unknown;
217 bus->speed = igc_bus_speed_unknown;
219 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
220 case PCIE_LINK_SPEED_2500:
221 bus->speed = igc_bus_speed_2500;
223 case PCIE_LINK_SPEED_5000:
224 bus->speed = igc_bus_speed_5000;
227 bus->speed = igc_bus_speed_unknown;
231 bus->width = (enum igc_bus_width)((pcie_link_status &
232 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT);
235 mac->ops.set_lan_id(hw);
241 * igc_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
243 * @hw: pointer to the HW structure
245 * Determines the LAN function id by reading memory-mapped registers
246 * and swaps the port value if requested.
248 static void igc_set_lan_id_multi_port_pcie(struct igc_hw *hw)
250 struct igc_bus_info *bus = &hw->bus;
253 /* The status register reports the correct function number
254 * for the device regardless of function swap state.
256 reg = IGC_READ_REG(hw, IGC_STATUS);
257 bus->func = (reg & IGC_STATUS_FUNC_MASK) >> IGC_STATUS_FUNC_SHIFT;
261 * igc_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
262 * @hw: pointer to the HW structure
264 * Determines the LAN function id by reading PCI config space.
266 void igc_set_lan_id_multi_port_pci(struct igc_hw *hw)
268 struct igc_bus_info *bus = &hw->bus;
272 igc_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
273 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
274 status = IGC_READ_REG(hw, IGC_STATUS);
275 bus->func = (status & IGC_STATUS_FUNC_MASK)
276 >> IGC_STATUS_FUNC_SHIFT;
283 * igc_set_lan_id_single_port - Set LAN id for a single port device
284 * @hw: pointer to the HW structure
286 * Sets the LAN function id to zero for a single port device.
288 void igc_set_lan_id_single_port(struct igc_hw *hw)
290 struct igc_bus_info *bus = &hw->bus;
296 * igc_clear_vfta_generic - Clear VLAN filter table
297 * @hw: pointer to the HW structure
299 * Clears the register array which contains the VLAN filter table by
300 * setting all the values to 0.
302 void igc_clear_vfta_generic(struct igc_hw *hw)
306 DEBUGFUNC("igc_clear_vfta_generic");
308 for (offset = 0; offset < IGC_VLAN_FILTER_TBL_SIZE; offset++) {
309 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, 0);
315 * igc_write_vfta_generic - Write value to VLAN filter table
316 * @hw: pointer to the HW structure
317 * @offset: register offset in VLAN filter table
318 * @value: register value written to VLAN filter table
320 * Writes value at the given offset in the register array which stores
321 * the VLAN filter table.
323 void igc_write_vfta_generic(struct igc_hw *hw, u32 offset, u32 value)
325 DEBUGFUNC("igc_write_vfta_generic");
327 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, offset, value);
332 * igc_init_rx_addrs_generic - Initialize receive address's
333 * @hw: pointer to the HW structure
334 * @rar_count: receive address registers
336 * Setup the receive address registers by setting the base receive address
337 * register to the devices MAC address and clearing all the other receive
338 * address registers to 0.
340 void igc_init_rx_addrs_generic(struct igc_hw *hw, u16 rar_count)
343 u8 mac_addr[ETH_ADDR_LEN] = {0};
345 DEBUGFUNC("igc_init_rx_addrs_generic");
347 /* Setup the receive address */
348 DEBUGOUT("Programming MAC Address into RAR[0]\n");
350 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
352 /* Zero out the other (rar_entry_count - 1) receive addresses */
353 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count - 1);
354 for (i = 1; i < rar_count; i++)
355 hw->mac.ops.rar_set(hw, mac_addr, i);
359 * igc_check_alt_mac_addr_generic - Check for alternate MAC addr
360 * @hw: pointer to the HW structure
362 * Checks the nvm for an alternate MAC address. An alternate MAC address
363 * can be setup by pre-boot software and must be treated like a permanent
364 * address and must override the actual permanent MAC address. If an
365 * alternate MAC address is found it is programmed into RAR0, replacing
366 * the permanent address that was installed into RAR0 by the Si on reset.
367 * This function will return SUCCESS unless it encounters an error while
368 * reading the EEPROM.
370 s32 igc_check_alt_mac_addr_generic(struct igc_hw *hw)
374 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
375 u8 alt_mac_addr[ETH_ADDR_LEN];
377 DEBUGFUNC("igc_check_alt_mac_addr_generic");
379 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
383 /* not supported on older hardware or 82573 */
384 if (hw->mac.type < igc_82571 || hw->mac.type == igc_82573)
387 /* Alternate MAC address is handled by the option ROM for 82580
388 * and newer. SW support not required.
390 if (hw->mac.type >= igc_82580)
393 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
394 &nvm_alt_mac_addr_offset);
396 DEBUGOUT("NVM Read Error\n");
400 if (nvm_alt_mac_addr_offset == 0xFFFF ||
401 nvm_alt_mac_addr_offset == 0x0000)
402 /* There is no Alternate MAC Address */
405 if (hw->bus.func == IGC_FUNC_1)
406 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN1;
407 if (hw->bus.func == IGC_FUNC_2)
408 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN2;
410 if (hw->bus.func == IGC_FUNC_3)
411 nvm_alt_mac_addr_offset += IGC_ALT_MAC_ADDRESS_OFFSET_LAN3;
412 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
413 offset = nvm_alt_mac_addr_offset + (i >> 1);
414 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
416 DEBUGOUT("NVM Read Error\n");
420 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
421 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
424 /* if multicast bit is set, the alternate address will not be used */
425 if (alt_mac_addr[0] & 0x01) {
426 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
430 /* We have a valid alternate MAC address, and we want to treat it the
431 * same as the normal permanent MAC address stored by the HW into the
432 * RAR. Do this by mapping this address into RAR0.
434 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
440 * igc_rar_set_generic - Set receive address register
441 * @hw: pointer to the HW structure
442 * @addr: pointer to the receive address
443 * @index: receive address array register
445 * Sets the receive address array register at index to the address passed
448 static int igc_rar_set_generic(struct igc_hw *hw, u8 *addr, u32 index)
450 u32 rar_low, rar_high;
452 DEBUGFUNC("igc_rar_set_generic");
454 /* HW expects these in little endian so we reverse the byte order
455 * from network order (big endian) to little endian
457 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) |
458 ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
460 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
462 /* If MAC address zero, no need to set the AV bit */
463 if (rar_low || rar_high)
464 rar_high |= IGC_RAH_AV;
466 /* Some bridges will combine consecutive 32-bit writes into
467 * a single burst write, which will malfunction on some parts.
468 * The flushes avoid this.
470 IGC_WRITE_REG(hw, IGC_RAL(index), rar_low);
472 IGC_WRITE_REG(hw, IGC_RAH(index), rar_high);
479 * igc_hash_mc_addr_generic - Generate a multicast hash value
480 * @hw: pointer to the HW structure
481 * @mc_addr: pointer to a multicast address
483 * Generates a multicast address hash value which is used to determine
484 * the multicast filter table array address and new table value.
486 u32 igc_hash_mc_addr_generic(struct igc_hw *hw, u8 *mc_addr)
488 u32 hash_value, hash_mask;
491 DEBUGFUNC("igc_hash_mc_addr_generic");
493 /* Register count multiplied by bits per register */
494 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
496 /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
497 * where 0xFF would still fall within the hash mask.
499 while (hash_mask >> bit_shift != 0xFF)
502 /* The portion of the address that is used for the hash table
503 * is determined by the mc_filter_type setting.
504 * The algorithm is such that there is a total of 8 bits of shifting.
505 * The bit_shift for a mc_filter_type of 0 represents the number of
506 * left-shifts where the MSB of mc_addr[5] would still fall within
507 * the hash_mask. Case 0 does this exactly. Since there are a total
508 * of 8 bits of shifting, then mc_addr[4] will shift right the
509 * remaining number of bits. Thus 8 - bit_shift. The rest of the
510 * cases are a variation of this algorithm...essentially raising the
511 * number of bits to shift mc_addr[5] left, while still keeping the
512 * 8-bit shifting total.
514 * For example, given the following Destination MAC Address and an
515 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
516 * we can see that the bit_shift for case 0 is 4. These are the hash
517 * values resulting from each mc_filter_type...
518 * [0] [1] [2] [3] [4] [5]
522 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
523 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
524 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
525 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
527 switch (hw->mac.mc_filter_type) {
542 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
543 (((u16)mc_addr[5]) << bit_shift)));
549 * igc_update_mc_addr_list_generic - Update Multicast addresses
550 * @hw: pointer to the HW structure
551 * @mc_addr_list: array of multicast addresses to program
552 * @mc_addr_count: number of multicast addresses to program
554 * Updates entire Multicast Table Array.
555 * The caller must have a packed mc_addr_list of multicast addresses.
557 void igc_update_mc_addr_list_generic(struct igc_hw *hw,
558 u8 *mc_addr_list, u32 mc_addr_count)
560 u32 hash_value, hash_bit, hash_reg;
563 DEBUGFUNC("igc_update_mc_addr_list_generic");
565 /* clear mta_shadow */
566 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
568 /* update mta_shadow from mc_addr_list */
569 for (i = 0; (u32)i < mc_addr_count; i++) {
570 hash_value = igc_hash_mc_addr_generic(hw, mc_addr_list);
572 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
573 hash_bit = hash_value & 0x1F;
575 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
576 mc_addr_list += (ETH_ADDR_LEN);
579 /* replace the entire MTA table */
580 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
581 IGC_WRITE_REG_ARRAY(hw, IGC_MTA, i, hw->mac.mta_shadow[i]);
586 * igc_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
587 * @hw: pointer to the HW structure
589 * In certain situations, a system BIOS may report that the PCIx maximum
590 * memory read byte count (MMRBC) value is higher than than the actual
591 * value. We check the PCIx command register with the current PCIx status
594 void igc_pcix_mmrbc_workaround_generic(struct igc_hw *hw)
598 u16 pcix_stat_hi_word;
601 DEBUGFUNC("igc_pcix_mmrbc_workaround_generic");
603 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
604 if (hw->bus.type != igc_bus_type_pcix)
607 igc_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
608 igc_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
609 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
610 PCIX_COMMAND_MMRBC_SHIFT;
611 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
612 PCIX_STATUS_HI_MMRBC_SHIFT;
613 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
614 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
615 if (cmd_mmrbc > stat_mmrbc) {
616 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
617 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
618 igc_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
623 * igc_clear_hw_cntrs_base_generic - Clear base hardware counters
624 * @hw: pointer to the HW structure
626 * Clears the base hardware counters by reading the counter registers.
628 void igc_clear_hw_cntrs_base_generic(struct igc_hw *hw)
630 DEBUGFUNC("igc_clear_hw_cntrs_base_generic");
632 IGC_READ_REG(hw, IGC_CRCERRS);
633 IGC_READ_REG(hw, IGC_SYMERRS);
634 IGC_READ_REG(hw, IGC_MPC);
635 IGC_READ_REG(hw, IGC_SCC);
636 IGC_READ_REG(hw, IGC_ECOL);
637 IGC_READ_REG(hw, IGC_MCC);
638 IGC_READ_REG(hw, IGC_LATECOL);
639 IGC_READ_REG(hw, IGC_COLC);
640 IGC_READ_REG(hw, IGC_DC);
641 IGC_READ_REG(hw, IGC_SEC);
642 IGC_READ_REG(hw, IGC_RLEC);
643 IGC_READ_REG(hw, IGC_XONRXC);
644 IGC_READ_REG(hw, IGC_XONTXC);
645 IGC_READ_REG(hw, IGC_XOFFRXC);
646 IGC_READ_REG(hw, IGC_XOFFTXC);
647 IGC_READ_REG(hw, IGC_FCRUC);
648 IGC_READ_REG(hw, IGC_GPRC);
649 IGC_READ_REG(hw, IGC_BPRC);
650 IGC_READ_REG(hw, IGC_MPRC);
651 IGC_READ_REG(hw, IGC_GPTC);
652 IGC_READ_REG(hw, IGC_GORCL);
653 IGC_READ_REG(hw, IGC_GORCH);
654 IGC_READ_REG(hw, IGC_GOTCL);
655 IGC_READ_REG(hw, IGC_GOTCH);
656 IGC_READ_REG(hw, IGC_RNBC);
657 IGC_READ_REG(hw, IGC_RUC);
658 IGC_READ_REG(hw, IGC_RFC);
659 IGC_READ_REG(hw, IGC_ROC);
660 IGC_READ_REG(hw, IGC_RJC);
661 IGC_READ_REG(hw, IGC_TORL);
662 IGC_READ_REG(hw, IGC_TORH);
663 IGC_READ_REG(hw, IGC_TOTL);
664 IGC_READ_REG(hw, IGC_TOTH);
665 IGC_READ_REG(hw, IGC_TPR);
666 IGC_READ_REG(hw, IGC_TPT);
667 IGC_READ_REG(hw, IGC_MPTC);
668 IGC_READ_REG(hw, IGC_BPTC);
672 * igc_check_for_copper_link_generic - Check for link (Copper)
673 * @hw: pointer to the HW structure
675 * Checks to see of the link status of the hardware has changed. If a
676 * change in link status has been detected, then we read the PHY registers
677 * to get the current speed/duplex if link exists.
679 s32 igc_check_for_copper_link_generic(struct igc_hw *hw)
681 struct igc_mac_info *mac = &hw->mac;
685 DEBUGFUNC("igc_check_for_copper_link");
687 /* We only want to go out to the PHY registers to see if Auto-Neg
688 * has completed and/or if our link status has changed. The
689 * get_link_status flag is set upon receiving a Link Status
690 * Change or Rx Sequence Error interrupt.
692 if (!mac->get_link_status)
695 /* First we want to see if the MII Status Register reports
696 * link. If so, then we want to get the current speed/duplex
699 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
704 return IGC_SUCCESS; /* No link detected */
706 mac->get_link_status = false;
708 /* Check if there was DownShift, must be checked
709 * immediately after link-up
711 igc_check_downshift_generic(hw);
713 /* If we are forcing speed/duplex, then we simply return since
714 * we have already determined whether we have link or not.
717 return -IGC_ERR_CONFIG;
719 /* Auto-Neg is enabled. Auto Speed Detection takes care
720 * of MAC speed/duplex configuration. So we only need to
721 * configure Collision Distance in the MAC.
723 mac->ops.config_collision_dist(hw);
725 /* Configure Flow Control now that Auto-Neg has completed.
726 * First, we need to restore the desired flow control
727 * settings because we may have had to re-autoneg with a
728 * different link partner.
730 ret_val = igc_config_fc_after_link_up_generic(hw);
732 DEBUGOUT("Error configuring flow control\n");
738 * igc_check_for_fiber_link_generic - Check for link (Fiber)
739 * @hw: pointer to the HW structure
741 * Checks for link up on the hardware. If link is not up and we have
742 * a signal, then we need to force link up.
744 s32 igc_check_for_fiber_link_generic(struct igc_hw *hw)
746 struct igc_mac_info *mac = &hw->mac;
752 DEBUGFUNC("igc_check_for_fiber_link_generic");
754 ctrl = IGC_READ_REG(hw, IGC_CTRL);
755 status = IGC_READ_REG(hw, IGC_STATUS);
756 rxcw = IGC_READ_REG(hw, IGC_RXCW);
758 /* If we don't have link (auto-negotiation failed or link partner
759 * cannot auto-negotiate), the cable is plugged in (we have signal),
760 * and our link partner is not trying to auto-negotiate with us (we
761 * are receiving idles or data), we need to force link up. We also
762 * need to give auto-negotiation time to complete, in case the cable
763 * was just plugged in. The autoneg_failed flag does this.
765 /* (ctrl & IGC_CTRL_SWDPIN1) == 1 == have signal */
766 if ((ctrl & IGC_CTRL_SWDPIN1) && !(status & IGC_STATUS_LU) &&
767 !(rxcw & IGC_RXCW_C)) {
768 if (!mac->autoneg_failed) {
769 mac->autoneg_failed = true;
772 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
774 /* Disable auto-negotiation in the TXCW register */
775 IGC_WRITE_REG(hw, IGC_TXCW, (mac->txcw & ~IGC_TXCW_ANE));
777 /* Force link-up and also force full-duplex. */
778 ctrl = IGC_READ_REG(hw, IGC_CTRL);
779 ctrl |= (IGC_CTRL_SLU | IGC_CTRL_FD);
780 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
782 /* Configure Flow Control after forcing link up. */
783 ret_val = igc_config_fc_after_link_up_generic(hw);
785 DEBUGOUT("Error configuring flow control\n");
788 } else if ((ctrl & IGC_CTRL_SLU) && (rxcw & IGC_RXCW_C)) {
789 /* If we are forcing link and we are receiving /C/ ordered
790 * sets, re-enable auto-negotiation in the TXCW register
791 * and disable forced link in the Device Control register
792 * in an attempt to auto-negotiate with our link partner.
794 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
795 IGC_WRITE_REG(hw, IGC_TXCW, mac->txcw);
796 IGC_WRITE_REG(hw, IGC_CTRL, (ctrl & ~IGC_CTRL_SLU));
798 mac->serdes_has_link = true;
805 * igc_check_for_serdes_link_generic - Check for link (Serdes)
806 * @hw: pointer to the HW structure
808 * Checks for link up on the hardware. If link is not up and we have
809 * a signal, then we need to force link up.
811 s32 igc_check_for_serdes_link_generic(struct igc_hw *hw)
813 struct igc_mac_info *mac = &hw->mac;
819 DEBUGFUNC("igc_check_for_serdes_link_generic");
821 ctrl = IGC_READ_REG(hw, IGC_CTRL);
822 status = IGC_READ_REG(hw, IGC_STATUS);
823 rxcw = IGC_READ_REG(hw, IGC_RXCW);
825 /* If we don't have link (auto-negotiation failed or link partner
826 * cannot auto-negotiate), and our link partner is not trying to
827 * auto-negotiate with us (we are receiving idles or data),
828 * we need to force link up. We also need to give auto-negotiation
831 /* (ctrl & IGC_CTRL_SWDPIN1) == 1 == have signal */
832 if (!(status & IGC_STATUS_LU) && !(rxcw & IGC_RXCW_C)) {
833 if (!mac->autoneg_failed) {
834 mac->autoneg_failed = true;
837 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
839 /* Disable auto-negotiation in the TXCW register */
840 IGC_WRITE_REG(hw, IGC_TXCW, (mac->txcw & ~IGC_TXCW_ANE));
842 /* Force link-up and also force full-duplex. */
843 ctrl = IGC_READ_REG(hw, IGC_CTRL);
844 ctrl |= (IGC_CTRL_SLU | IGC_CTRL_FD);
845 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
847 /* Configure Flow Control after forcing link up. */
848 ret_val = igc_config_fc_after_link_up_generic(hw);
850 DEBUGOUT("Error configuring flow control\n");
853 } else if ((ctrl & IGC_CTRL_SLU) && (rxcw & IGC_RXCW_C)) {
854 /* If we are forcing link and we are receiving /C/ ordered
855 * sets, re-enable auto-negotiation in the TXCW register
856 * and disable forced link in the Device Control register
857 * in an attempt to auto-negotiate with our link partner.
859 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
860 IGC_WRITE_REG(hw, IGC_TXCW, mac->txcw);
861 IGC_WRITE_REG(hw, IGC_CTRL, (ctrl & ~IGC_CTRL_SLU));
863 mac->serdes_has_link = true;
864 } else if (!(IGC_TXCW_ANE & IGC_READ_REG(hw, IGC_TXCW))) {
865 /* If we force link for non-auto-negotiation switch, check
866 * link status based on MAC synchronization for internal
869 /* SYNCH bit and IV bit are sticky. */
871 rxcw = IGC_READ_REG(hw, IGC_RXCW);
872 if (rxcw & IGC_RXCW_SYNCH) {
873 if (!(rxcw & IGC_RXCW_IV)) {
874 mac->serdes_has_link = true;
875 DEBUGOUT("SERDES: Link up - forced.\n");
878 mac->serdes_has_link = false;
879 DEBUGOUT("SERDES: Link down - force failed.\n");
883 if (IGC_TXCW_ANE & IGC_READ_REG(hw, IGC_TXCW)) {
884 status = IGC_READ_REG(hw, IGC_STATUS);
885 if (status & IGC_STATUS_LU) {
886 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
888 rxcw = IGC_READ_REG(hw, IGC_RXCW);
889 if (rxcw & IGC_RXCW_SYNCH) {
890 if (!(rxcw & IGC_RXCW_IV)) {
891 mac->serdes_has_link = true;
892 DEBUGOUT("SERDES: Link up - autoneg completed successfully.\n");
894 mac->serdes_has_link = false;
895 DEBUGOUT("SERDES: Link down - invalid codewords detected in autoneg.\n");
898 mac->serdes_has_link = false;
899 DEBUGOUT("SERDES: Link down - no sync.\n");
902 mac->serdes_has_link = false;
903 DEBUGOUT("SERDES: Link down - autoneg failed\n");
911 * igc_set_default_fc_generic - Set flow control default values
912 * @hw: pointer to the HW structure
914 * Read the EEPROM for the default values for flow control and store the
917 s32 igc_set_default_fc_generic(struct igc_hw *hw)
923 DEBUGFUNC("igc_set_default_fc_generic");
925 /* Read and store word 0x0F of the EEPROM. This word contains bits
926 * that determine the hardware's default PAUSE (flow control) mode,
927 * a bit that determines whether the HW defaults to enabling or
928 * disabling auto-negotiation, and the direction of the
929 * SW defined pins. If there is no SW over-ride of the flow
930 * control setting, then the variable hw->fc will
931 * be initialized based on a value in the EEPROM.
933 if (hw->mac.type == igc_i350) {
934 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
935 ret_val = hw->nvm.ops.read(hw,
936 NVM_INIT_CONTROL2_REG +
940 ret_val = hw->nvm.ops.read(hw,
941 NVM_INIT_CONTROL2_REG,
946 DEBUGOUT("NVM Read Error\n");
950 if (!(nvm_data & NVM_WORD0F_PAUSE_MASK))
951 hw->fc.requested_mode = igc_fc_none;
952 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
954 hw->fc.requested_mode = igc_fc_tx_pause;
956 hw->fc.requested_mode = igc_fc_full;
962 * igc_setup_link_generic - Setup flow control and link settings
963 * @hw: pointer to the HW structure
965 * Determines which flow control settings to use, then configures flow
966 * control. Calls the appropriate media-specific link configuration
967 * function. Assuming the adapter has a valid link partner, a valid link
968 * should be established. Assumes the hardware has previously been reset
969 * and the transmitter and receiver are not enabled.
971 s32 igc_setup_link_generic(struct igc_hw *hw)
975 DEBUGFUNC("igc_setup_link_generic");
977 /* In the case of the phy reset being blocked, we already have a link.
978 * We do not need to set it up again.
980 if (hw->phy.ops.check_reset_block && hw->phy.ops.check_reset_block(hw))
983 /* If requested flow control is set to default, set flow control
984 * based on the EEPROM flow control settings.
986 if (hw->fc.requested_mode == igc_fc_default)
987 hw->fc.requested_mode = igc_fc_full;
989 /* Save off the requested flow control mode for use later. Depending
990 * on the link partner's capabilities, we may or may not use this mode.
992 hw->fc.current_mode = hw->fc.requested_mode;
994 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
995 hw->fc.current_mode);
997 /* Call the necessary media_type subroutine to configure the link. */
998 ret_val = hw->mac.ops.setup_physical_interface(hw);
1002 /* Initialize the flow control address, type, and PAUSE timer
1003 * registers to their default values. This is done even if flow
1004 * control is disabled, because it does not hurt anything to
1005 * initialize these registers.
1007 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1008 IGC_WRITE_REG(hw, IGC_FCT, FLOW_CONTROL_TYPE);
1009 IGC_WRITE_REG(hw, IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1010 IGC_WRITE_REG(hw, IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1012 IGC_WRITE_REG(hw, IGC_FCTTV, hw->fc.pause_time);
1014 return igc_set_fc_watermarks_generic(hw);
1018 * igc_commit_fc_settings_generic - Configure flow control
1019 * @hw: pointer to the HW structure
1021 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1022 * base on the flow control settings in igc_mac_info.
1024 s32 igc_commit_fc_settings_generic(struct igc_hw *hw)
1026 struct igc_mac_info *mac = &hw->mac;
1029 DEBUGFUNC("igc_commit_fc_settings_generic");
1031 /* Check for a software override of the flow control settings, and
1032 * setup the device accordingly. If auto-negotiation is enabled, then
1033 * software will have to set the "PAUSE" bits to the correct value in
1034 * the Transmit Config Word Register (TXCW) and re-start auto-
1035 * negotiation. However, if auto-negotiation is disabled, then
1036 * software will have to manually configure the two flow control enable
1037 * bits in the CTRL register.
1039 * The possible values of the "fc" parameter are:
1040 * 0: Flow control is completely disabled
1041 * 1: Rx flow control is enabled (we can receive pause frames,
1042 * but not send pause frames).
1043 * 2: Tx flow control is enabled (we can send pause frames but we
1044 * do not support receiving pause frames).
1045 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1047 switch (hw->fc.current_mode) {
1049 /* Flow control completely disabled by a software over-ride. */
1050 txcw = (IGC_TXCW_ANE | IGC_TXCW_FD);
1052 case igc_fc_rx_pause:
1053 /* Rx Flow control is enabled and Tx Flow control is disabled
1054 * by a software over-ride. Since there really isn't a way to
1055 * advertise that we are capable of Rx Pause ONLY, we will
1056 * advertise that we support both symmetric and asymmetric Rx
1057 * PAUSE. Later, we will disable the adapter's ability to send
1060 txcw = (IGC_TXCW_ANE | IGC_TXCW_FD | IGC_TXCW_PAUSE_MASK);
1062 case igc_fc_tx_pause:
1063 /* Tx Flow control is enabled, and Rx Flow control is disabled,
1064 * by a software over-ride.
1066 txcw = (IGC_TXCW_ANE | IGC_TXCW_FD | IGC_TXCW_ASM_DIR);
1069 /* Flow control (both Rx and Tx) is enabled by a software
1072 txcw = (IGC_TXCW_ANE | IGC_TXCW_FD | IGC_TXCW_PAUSE_MASK);
1075 DEBUGOUT("Flow control param set incorrectly\n");
1076 return -IGC_ERR_CONFIG;
1079 IGC_WRITE_REG(hw, IGC_TXCW, txcw);
1086 * igc_poll_fiber_serdes_link_generic - Poll for link up
1087 * @hw: pointer to the HW structure
1089 * Polls for link up by reading the status register, if link fails to come
1090 * up with auto-negotiation, then the link is forced if a signal is detected.
1092 s32 igc_poll_fiber_serdes_link_generic(struct igc_hw *hw)
1094 struct igc_mac_info *mac = &hw->mac;
1098 DEBUGFUNC("igc_poll_fiber_serdes_link_generic");
1100 /* If we have a signal (the cable is plugged in, or assumed true for
1101 * serdes media) then poll for a "Link-Up" indication in the Device
1102 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1103 * seconds (Auto-negotiation should complete in less than 500
1104 * milliseconds even if the other end is doing it in SW).
1106 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1108 status = IGC_READ_REG(hw, IGC_STATUS);
1109 if (status & IGC_STATUS_LU)
1112 if (i == FIBER_LINK_UP_LIMIT) {
1113 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1114 mac->autoneg_failed = true;
1115 /* AutoNeg failed to achieve a link, so we'll call
1116 * mac->check_for_link. This routine will force the
1117 * link up if we detect a signal. This will allow us to
1118 * communicate with non-autonegotiating link partners.
1120 ret_val = mac->ops.check_for_link(hw);
1122 DEBUGOUT("Error while checking for link\n");
1125 mac->autoneg_failed = false;
1127 mac->autoneg_failed = false;
1128 DEBUGOUT("Valid Link Found\n");
1135 * igc_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1136 * @hw: pointer to the HW structure
1138 * Configures collision distance and flow control for fiber and serdes
1139 * links. Upon successful setup, poll for link.
1141 s32 igc_setup_fiber_serdes_link_generic(struct igc_hw *hw)
1146 DEBUGFUNC("igc_setup_fiber_serdes_link_generic");
1148 ctrl = IGC_READ_REG(hw, IGC_CTRL);
1150 /* Take the link out of reset */
1151 ctrl &= ~IGC_CTRL_LRST;
1153 hw->mac.ops.config_collision_dist(hw);
1155 ret_val = igc_commit_fc_settings_generic(hw);
1159 /* Since auto-negotiation is enabled, take the link out of reset (the
1160 * link will be in reset, because we previously reset the chip). This
1161 * will restart auto-negotiation. If auto-negotiation is successful
1162 * then the link-up status bit will be set and the flow control enable
1163 * bits (RFCE and TFCE) will be set according to their negotiated value.
1165 DEBUGOUT("Auto-negotiation enabled\n");
1167 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
1168 IGC_WRITE_FLUSH(hw);
1171 /* For these adapters, the SW definable pin 1 is set when the optics
1172 * detect a signal. If we have a signal, then poll for a "Link-Up"
1175 if (hw->phy.media_type == igc_media_type_internal_serdes ||
1176 (IGC_READ_REG(hw, IGC_CTRL) & IGC_CTRL_SWDPIN1)) {
1177 ret_val = igc_poll_fiber_serdes_link_generic(hw);
1179 DEBUGOUT("No signal detected\n");
1186 * igc_config_collision_dist_generic - Configure collision distance
1187 * @hw: pointer to the HW structure
1189 * Configures the collision distance to the default value and is used
1190 * during link setup.
1192 static void igc_config_collision_dist_generic(struct igc_hw *hw)
1196 DEBUGFUNC("igc_config_collision_dist_generic");
1198 tctl = IGC_READ_REG(hw, IGC_TCTL);
1200 tctl &= ~IGC_TCTL_COLD;
1201 tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
1203 IGC_WRITE_REG(hw, IGC_TCTL, tctl);
1204 IGC_WRITE_FLUSH(hw);
1208 * igc_set_fc_watermarks_generic - Set flow control high/low watermarks
1209 * @hw: pointer to the HW structure
1211 * Sets the flow control high/low threshold (watermark) registers. If
1212 * flow control XON frame transmission is enabled, then set XON frame
1213 * transmission as well.
1215 s32 igc_set_fc_watermarks_generic(struct igc_hw *hw)
1217 u32 fcrtl = 0, fcrth = 0;
1219 DEBUGFUNC("igc_set_fc_watermarks_generic");
1221 /* Set the flow control receive threshold registers. Normally,
1222 * these registers will be set to a default threshold that may be
1223 * adjusted later by the driver's runtime code. However, if the
1224 * ability to transmit pause frames is not enabled, then these
1225 * registers will be set to 0.
1227 if (hw->fc.current_mode & igc_fc_tx_pause) {
1228 /* We need to set up the Receive Threshold high and low water
1229 * marks as well as (optionally) enabling the transmission of
1232 fcrtl = hw->fc.low_water;
1233 if (hw->fc.send_xon)
1234 fcrtl |= IGC_FCRTL_XONE;
1236 fcrth = hw->fc.high_water;
1238 IGC_WRITE_REG(hw, IGC_FCRTL, fcrtl);
1239 IGC_WRITE_REG(hw, IGC_FCRTH, fcrth);
1245 * igc_force_mac_fc_generic - Force the MAC's flow control settings
1246 * @hw: pointer to the HW structure
1248 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1249 * device control register to reflect the adapter settings. TFCE and RFCE
1250 * need to be explicitly set by software when a copper PHY is used because
1251 * autonegotiation is managed by the PHY rather than the MAC. Software must
1252 * also configure these bits when link is forced on a fiber connection.
1254 s32 igc_force_mac_fc_generic(struct igc_hw *hw)
1258 DEBUGFUNC("igc_force_mac_fc_generic");
1260 ctrl = IGC_READ_REG(hw, IGC_CTRL);
1262 /* Because we didn't get link via the internal auto-negotiation
1263 * mechanism (we either forced link or we got link via PHY
1264 * auto-neg), we have to manually enable/disable transmit an
1265 * receive flow control.
1267 * The "Case" statement below enables/disable flow control
1268 * according to the "hw->fc.current_mode" parameter.
1270 * The possible values of the "fc" parameter are:
1271 * 0: Flow control is completely disabled
1272 * 1: Rx flow control is enabled (we can receive pause
1273 * frames but not send pause frames).
1274 * 2: Tx flow control is enabled (we can send pause frames
1275 * frames but we do not receive pause frames).
1276 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1277 * other: No other values should be possible at this point.
1279 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1281 switch (hw->fc.current_mode) {
1283 ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
1285 case igc_fc_rx_pause:
1286 ctrl &= (~IGC_CTRL_TFCE);
1287 ctrl |= IGC_CTRL_RFCE;
1289 case igc_fc_tx_pause:
1290 ctrl &= (~IGC_CTRL_RFCE);
1291 ctrl |= IGC_CTRL_TFCE;
1294 ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
1297 DEBUGOUT("Flow control param set incorrectly\n");
1298 return -IGC_ERR_CONFIG;
1301 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
1307 * igc_config_fc_after_link_up_generic - Configures flow control after link
1308 * @hw: pointer to the HW structure
1310 * Checks the status of auto-negotiation after link up to ensure that the
1311 * speed and duplex were not forced. If the link needed to be forced, then
1312 * flow control needs to be forced also. If auto-negotiation is enabled
1313 * and did not fail, then we configure flow control based on our link
1316 s32 igc_config_fc_after_link_up_generic(struct igc_hw *hw)
1318 struct igc_mac_info *mac = &hw->mac;
1319 s32 ret_val = IGC_SUCCESS;
1320 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1323 DEBUGFUNC("igc_config_fc_after_link_up_generic");
1325 /* Check for the case where we have fiber media and auto-neg failed
1326 * so we had to force link. In this case, we need to force the
1327 * configuration of the MAC to match the "fc" parameter.
1329 if (mac->autoneg_failed) {
1330 if (hw->phy.media_type == igc_media_type_copper)
1331 ret_val = igc_force_mac_fc_generic(hw);
1335 DEBUGOUT("Error forcing flow control settings\n");
1339 /* Check for the case where we have copper media and auto-neg is
1340 * enabled. In this case, we need to check and see if Auto-Neg
1341 * has completed, and if so, how the PHY and link partner has
1342 * flow control configured.
1344 if (hw->phy.media_type == igc_media_type_copper && mac->autoneg) {
1345 /* Read the MII Status Register and check to see if AutoNeg
1346 * has completed. We read this twice because this reg has
1347 * some "sticky" (latched) bits.
1349 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1352 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1356 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1357 DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
1361 /* The AutoNeg process has completed, so we now need to
1362 * read both the Auto Negotiation Advertisement
1363 * Register (Address 4) and the Auto_Negotiation Base
1364 * Page Ability Register (Address 5) to determine how
1365 * flow control was negotiated.
1367 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1371 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1372 &mii_nway_lp_ability_reg);
1376 /* Two bits in the Auto Negotiation Advertisement Register
1377 * (Address 4) and two bits in the Auto Negotiation Base
1378 * Page Ability Register (Address 5) determine flow control
1379 * for both the PHY and the link partner. The following
1380 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1381 * 1999, describes these PAUSE resolution bits and how flow
1382 * control is determined based upon these settings.
1383 * NOTE: DC = Don't Care
1385 * LOCAL DEVICE | LINK PARTNER
1386 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1387 *-------|---------|-------|---------|--------------------
1388 * 0 | 0 | DC | DC | igc_fc_none
1389 * 0 | 1 | 0 | DC | igc_fc_none
1390 * 0 | 1 | 1 | 0 | igc_fc_none
1391 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
1392 * 1 | 0 | 0 | DC | igc_fc_none
1393 * 1 | DC | 1 | DC | igc_fc_full
1394 * 1 | 1 | 0 | 0 | igc_fc_none
1395 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
1397 * Are both PAUSE bits set to 1? If so, this implies
1398 * Symmetric Flow Control is enabled at both ends. The
1399 * ASM_DIR bits are irrelevant per the spec.
1401 * For Symmetric Flow Control:
1403 * LOCAL DEVICE | LINK PARTNER
1404 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1405 *-------|---------|-------|---------|--------------------
1406 * 1 | DC | 1 | DC | IGC_fc_full
1409 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1410 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1411 /* Now we need to check if the user selected Rx ONLY
1412 * of pause frames. In this case, we had to advertise
1413 * FULL flow control because we could not advertise Rx
1414 * ONLY. Hence, we must now check to see if we need to
1415 * turn OFF the TRANSMISSION of PAUSE frames.
1417 if (hw->fc.requested_mode == igc_fc_full) {
1418 hw->fc.current_mode = igc_fc_full;
1419 DEBUGOUT("Flow Control = FULL.\n");
1421 hw->fc.current_mode = igc_fc_rx_pause;
1422 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1425 /* For receiving PAUSE frames ONLY.
1427 * LOCAL DEVICE | LINK PARTNER
1428 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1429 *-------|---------|-------|---------|--------------------
1430 * 0 | 1 | 1 | 1 | igc_fc_tx_pause
1432 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1433 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1434 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1435 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1436 hw->fc.current_mode = igc_fc_tx_pause;
1437 DEBUGOUT("Flow Control = Tx PAUSE frames only.\n");
1439 /* For transmitting PAUSE frames ONLY.
1441 * LOCAL DEVICE | LINK PARTNER
1442 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1443 *-------|---------|-------|---------|--------------------
1444 * 1 | 1 | 0 | 1 | igc_fc_rx_pause
1446 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1447 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1448 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1449 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1450 hw->fc.current_mode = igc_fc_rx_pause;
1451 DEBUGOUT("Flow Control = Rx PAUSE frames only.\n");
1453 /* Per the IEEE spec, at this point flow control
1454 * should be disabled.
1456 hw->fc.current_mode = igc_fc_none;
1457 DEBUGOUT("Flow Control = NONE.\n");
1460 /* Now we need to do one last check... If we auto-
1461 * negotiated to HALF DUPLEX, flow control should not be
1462 * enabled per IEEE 802.3 spec.
1464 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1466 DEBUGOUT("Error getting link speed and duplex\n");
1470 if (duplex == HALF_DUPLEX)
1471 hw->fc.current_mode = igc_fc_none;
1473 /* Now we call a subroutine to actually force the MAC
1474 * controller to use the correct flow control settings.
1476 ret_val = igc_force_mac_fc_generic(hw);
1478 DEBUGOUT("Error forcing flow control settings\n");
1487 * igc_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1488 * @hw: pointer to the HW structure
1489 * @speed: stores the current speed
1490 * @duplex: stores the current duplex
1492 * Read the status register for the current speed/duplex and store the current
1493 * speed and duplex for copper connections.
1495 s32 igc_get_speed_and_duplex_copper_generic(struct igc_hw *hw, u16 *speed,
1500 DEBUGFUNC("igc_get_speed_and_duplex_copper_generic");
1502 status = IGC_READ_REG(hw, IGC_STATUS);
1503 if (status & IGC_STATUS_SPEED_1000) {
1504 /* For I225, STATUS will indicate 1G speed in both 1 Gbps
1505 * and 2.5 Gbps link modes. An additional bit is used
1506 * to differentiate between 1 Gbps and 2.5 Gbps.
1508 if (hw->mac.type == igc_i225 &&
1509 (status & IGC_STATUS_SPEED_2500)) {
1510 *speed = SPEED_2500;
1511 DEBUGOUT("2500 Mbs, ");
1513 *speed = SPEED_1000;
1514 DEBUGOUT("1000 Mbs, ");
1516 } else if (status & IGC_STATUS_SPEED_100) {
1518 DEBUGOUT("100 Mbs, ");
1521 DEBUGOUT("10 Mbs, ");
1524 if (status & IGC_STATUS_FD) {
1525 *duplex = FULL_DUPLEX;
1526 DEBUGOUT("Full Duplex\n");
1528 *duplex = HALF_DUPLEX;
1529 DEBUGOUT("Half Duplex\n");
1536 * igc_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1537 * @hw: pointer to the HW structure
1538 * @speed: stores the current speed
1539 * @duplex: stores the current duplex
1541 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1542 * for fiber/serdes links.
1545 igc_get_speed_and_duplex_fiber_serdes_generic(struct igc_hw *hw,
1546 u16 *speed, u16 *duplex)
1548 DEBUGFUNC("igc_get_speed_and_duplex_fiber_serdes_generic");
1549 UNREFERENCED_1PARAMETER(hw);
1551 *speed = SPEED_1000;
1552 *duplex = FULL_DUPLEX;
1558 * igc_get_hw_semaphore_generic - Acquire hardware semaphore
1559 * @hw: pointer to the HW structure
1561 * Acquire the HW semaphore to access the PHY or NVM
1563 s32 igc_get_hw_semaphore_generic(struct igc_hw *hw)
1566 s32 timeout = hw->nvm.word_size + 1;
1569 DEBUGFUNC("igc_get_hw_semaphore_generic");
1571 /* Get the SW semaphore */
1572 while (i < timeout) {
1573 swsm = IGC_READ_REG(hw, IGC_SWSM);
1574 if (!(swsm & IGC_SWSM_SMBI))
1582 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1583 return -IGC_ERR_NVM;
1586 /* Get the FW semaphore. */
1587 for (i = 0; i < timeout; i++) {
1588 swsm = IGC_READ_REG(hw, IGC_SWSM);
1589 IGC_WRITE_REG(hw, IGC_SWSM, swsm | IGC_SWSM_SWESMBI);
1591 /* Semaphore acquired if bit latched */
1592 if (IGC_READ_REG(hw, IGC_SWSM) & IGC_SWSM_SWESMBI)
1599 /* Release semaphores */
1600 igc_put_hw_semaphore_generic(hw);
1601 DEBUGOUT("Driver can't access the NVM\n");
1602 return -IGC_ERR_NVM;
1609 * igc_put_hw_semaphore_generic - Release hardware semaphore
1610 * @hw: pointer to the HW structure
1612 * Release hardware semaphore used to access the PHY or NVM
1614 void igc_put_hw_semaphore_generic(struct igc_hw *hw)
1618 DEBUGFUNC("igc_put_hw_semaphore_generic");
1620 swsm = IGC_READ_REG(hw, IGC_SWSM);
1622 swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
1624 IGC_WRITE_REG(hw, IGC_SWSM, swsm);
1628 * igc_get_auto_rd_done_generic - Check for auto read completion
1629 * @hw: pointer to the HW structure
1631 * Check EEPROM for Auto Read done bit.
1633 s32 igc_get_auto_rd_done_generic(struct igc_hw *hw)
1637 DEBUGFUNC("igc_get_auto_rd_done_generic");
1639 while (i < AUTO_READ_DONE_TIMEOUT) {
1640 if (IGC_READ_REG(hw, IGC_EECD) & IGC_EECD_AUTO_RD)
1646 if (i == AUTO_READ_DONE_TIMEOUT) {
1647 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1648 return -IGC_ERR_RESET;
1655 * igc_valid_led_default_generic - Verify a valid default LED config
1656 * @hw: pointer to the HW structure
1657 * @data: pointer to the NVM (EEPROM)
1659 * Read the EEPROM for the current default LED configuration. If the
1660 * LED configuration is not valid, set to a valid LED configuration.
1662 s32 igc_valid_led_default_generic(struct igc_hw *hw, u16 *data)
1666 DEBUGFUNC("igc_valid_led_default_generic");
1668 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1670 DEBUGOUT("NVM Read Error\n");
1674 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1675 *data = ID_LED_DEFAULT;
1681 * igc_id_led_init_generic -
1682 * @hw: pointer to the HW structure
1685 s32 igc_id_led_init_generic(struct igc_hw *hw)
1687 struct igc_mac_info *mac = &hw->mac;
1689 const u32 ledctl_mask = 0x000000FF;
1690 const u32 ledctl_on = IGC_LEDCTL_MODE_LED_ON;
1691 const u32 ledctl_off = IGC_LEDCTL_MODE_LED_OFF;
1693 const u16 led_mask = 0x0F;
1695 DEBUGFUNC("igc_id_led_init_generic");
1697 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1701 mac->ledctl_default = IGC_READ_REG(hw, IGC_LEDCTL);
1702 mac->ledctl_mode1 = mac->ledctl_default;
1703 mac->ledctl_mode2 = mac->ledctl_default;
1705 for (i = 0; i < 4; i++) {
1706 temp = (data >> (i << 2)) & led_mask;
1708 case ID_LED_ON1_DEF2:
1709 case ID_LED_ON1_ON2:
1710 case ID_LED_ON1_OFF2:
1711 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1712 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1714 case ID_LED_OFF1_DEF2:
1715 case ID_LED_OFF1_ON2:
1716 case ID_LED_OFF1_OFF2:
1717 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1718 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1725 case ID_LED_DEF1_ON2:
1726 case ID_LED_ON1_ON2:
1727 case ID_LED_OFF1_ON2:
1728 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1729 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1731 case ID_LED_DEF1_OFF2:
1732 case ID_LED_ON1_OFF2:
1733 case ID_LED_OFF1_OFF2:
1734 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1735 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1747 * igc_setup_led_generic - Configures SW controllable LED
1748 * @hw: pointer to the HW structure
1750 * This prepares the SW controllable LED for use and saves the current state
1751 * of the LED so it can be later restored.
1753 s32 igc_setup_led_generic(struct igc_hw *hw)
1757 DEBUGFUNC("igc_setup_led_generic");
1759 if (hw->mac.ops.setup_led != igc_setup_led_generic)
1760 return -IGC_ERR_CONFIG;
1762 if (hw->phy.media_type == igc_media_type_fiber) {
1763 ledctl = IGC_READ_REG(hw, IGC_LEDCTL);
1764 hw->mac.ledctl_default = ledctl;
1766 ledctl &= ~(IGC_LEDCTL_LED0_IVRT | IGC_LEDCTL_LED0_BLINK |
1767 IGC_LEDCTL_LED0_MODE_MASK);
1768 ledctl |= (IGC_LEDCTL_MODE_LED_OFF <<
1769 IGC_LEDCTL_LED0_MODE_SHIFT);
1770 IGC_WRITE_REG(hw, IGC_LEDCTL, ledctl);
1771 } else if (hw->phy.media_type == igc_media_type_copper) {
1772 IGC_WRITE_REG(hw, IGC_LEDCTL, hw->mac.ledctl_mode1);
1779 * igc_cleanup_led_generic - Set LED config to default operation
1780 * @hw: pointer to the HW structure
1782 * Remove the current LED configuration and set the LED configuration
1783 * to the default value, saved from the EEPROM.
1785 s32 igc_cleanup_led_generic(struct igc_hw *hw)
1787 DEBUGFUNC("igc_cleanup_led_generic");
1789 IGC_WRITE_REG(hw, IGC_LEDCTL, hw->mac.ledctl_default);
1794 * igc_blink_led_generic - Blink LED
1795 * @hw: pointer to the HW structure
1797 * Blink the LEDs which are set to be on.
1799 s32 igc_blink_led_generic(struct igc_hw *hw)
1801 u32 ledctl_blink = 0;
1804 DEBUGFUNC("igc_blink_led_generic");
1806 if (hw->phy.media_type == igc_media_type_fiber) {
1807 /* always blink LED0 for PCI-E fiber */
1808 ledctl_blink = IGC_LEDCTL_LED0_BLINK |
1809 (IGC_LEDCTL_MODE_LED_ON << IGC_LEDCTL_LED0_MODE_SHIFT);
1811 /* Set the blink bit for each LED that's "on" (0x0E)
1812 * (or "off" if inverted) in ledctl_mode2. The blink
1813 * logic in hardware only works when mode is set to "on"
1814 * so it must be changed accordingly when the mode is
1815 * "off" and inverted.
1817 ledctl_blink = hw->mac.ledctl_mode2;
1818 for (i = 0; i < 32; i += 8) {
1819 u32 mode = (hw->mac.ledctl_mode2 >> i) &
1820 IGC_LEDCTL_LED0_MODE_MASK;
1821 u32 led_default = hw->mac.ledctl_default >> i;
1823 if ((!(led_default & IGC_LEDCTL_LED0_IVRT) &&
1824 mode == IGC_LEDCTL_MODE_LED_ON) ||
1825 ((led_default & IGC_LEDCTL_LED0_IVRT) &&
1826 mode == IGC_LEDCTL_MODE_LED_OFF)) {
1828 ~(IGC_LEDCTL_LED0_MODE_MASK << i);
1829 ledctl_blink |= (IGC_LEDCTL_LED0_BLINK |
1830 IGC_LEDCTL_MODE_LED_ON) << i;
1835 IGC_WRITE_REG(hw, IGC_LEDCTL, ledctl_blink);
1841 * igc_led_on_generic - Turn LED on
1842 * @hw: pointer to the HW structure
1846 s32 igc_led_on_generic(struct igc_hw *hw)
1850 DEBUGFUNC("igc_led_on_generic");
1852 switch (hw->phy.media_type) {
1853 case igc_media_type_fiber:
1854 ctrl = IGC_READ_REG(hw, IGC_CTRL);
1855 ctrl &= ~IGC_CTRL_SWDPIN0;
1856 ctrl |= IGC_CTRL_SWDPIO0;
1857 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
1859 case igc_media_type_copper:
1860 IGC_WRITE_REG(hw, IGC_LEDCTL, hw->mac.ledctl_mode2);
1870 * igc_led_off_generic - Turn LED off
1871 * @hw: pointer to the HW structure
1875 s32 igc_led_off_generic(struct igc_hw *hw)
1879 DEBUGFUNC("igc_led_off_generic");
1881 switch (hw->phy.media_type) {
1882 case igc_media_type_fiber:
1883 ctrl = IGC_READ_REG(hw, IGC_CTRL);
1884 ctrl |= IGC_CTRL_SWDPIN0;
1885 ctrl |= IGC_CTRL_SWDPIO0;
1886 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
1888 case igc_media_type_copper:
1889 IGC_WRITE_REG(hw, IGC_LEDCTL, hw->mac.ledctl_mode1);
1899 * igc_set_pcie_no_snoop_generic - Set PCI-express capabilities
1900 * @hw: pointer to the HW structure
1901 * @no_snoop: bitmap of snoop events
1903 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1905 void igc_set_pcie_no_snoop_generic(struct igc_hw *hw, u32 no_snoop)
1909 DEBUGFUNC("igc_set_pcie_no_snoop_generic");
1911 if (hw->bus.type != igc_bus_type_pci_express)
1915 gcr = IGC_READ_REG(hw, IGC_GCR);
1916 gcr &= ~(PCIE_NO_SNOOP_ALL);
1918 IGC_WRITE_REG(hw, IGC_GCR, gcr);
1923 * igc_disable_pcie_master_generic - Disables PCI-express master access
1924 * @hw: pointer to the HW structure
1926 * Returns IGC_SUCCESS if successful, else returns -10
1927 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1928 * the master requests to be disabled.
1930 * Disables PCI-Express master access and verifies there are no pending
1933 s32 igc_disable_pcie_master_generic(struct igc_hw *hw)
1936 s32 timeout = MASTER_DISABLE_TIMEOUT;
1938 DEBUGFUNC("igc_disable_pcie_master_generic");
1940 ctrl = IGC_READ_REG(hw, IGC_CTRL);
1941 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
1942 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
1945 if (!(IGC_READ_REG(hw, IGC_STATUS) &
1946 IGC_STATUS_GIO_MASTER_ENABLE) ||
1947 IGC_REMOVED(hw->hw_addr))
1954 DEBUGOUT("Master requests are pending.\n");
1955 return -IGC_ERR_MASTER_REQUESTS_PENDING;
1962 * igc_reset_adaptive_generic - Reset Adaptive Interframe Spacing
1963 * @hw: pointer to the HW structure
1965 * Reset the Adaptive Interframe Spacing throttle to default values.
1967 void igc_reset_adaptive_generic(struct igc_hw *hw)
1969 struct igc_mac_info *mac = &hw->mac;
1971 DEBUGFUNC("igc_reset_adaptive_generic");
1973 if (!mac->adaptive_ifs) {
1974 DEBUGOUT("Not in Adaptive IFS mode!\n");
1978 mac->current_ifs_val = 0;
1979 mac->ifs_min_val = IFS_MIN;
1980 mac->ifs_max_val = IFS_MAX;
1981 mac->ifs_step_size = IFS_STEP;
1982 mac->ifs_ratio = IFS_RATIO;
1984 mac->in_ifs_mode = false;
1985 IGC_WRITE_REG(hw, IGC_AIT, 0);
1989 * igc_update_adaptive_generic - Update Adaptive Interframe Spacing
1990 * @hw: pointer to the HW structure
1992 * Update the Adaptive Interframe Spacing Throttle value based on the
1993 * time between transmitted packets and time between collisions.
1995 void igc_update_adaptive_generic(struct igc_hw *hw)
1997 struct igc_mac_info *mac = &hw->mac;
1999 DEBUGFUNC("igc_update_adaptive_generic");
2001 if (!mac->adaptive_ifs) {
2002 DEBUGOUT("Not in Adaptive IFS mode!\n");
2006 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2007 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2008 mac->in_ifs_mode = true;
2009 if (mac->current_ifs_val < mac->ifs_max_val) {
2010 if (!mac->current_ifs_val)
2011 mac->current_ifs_val = mac->ifs_min_val;
2013 mac->current_ifs_val +=
2015 IGC_WRITE_REG(hw, IGC_AIT,
2016 mac->current_ifs_val);
2020 if (mac->in_ifs_mode &&
2021 mac->tx_packet_delta <= MIN_NUM_XMITS) {
2022 mac->current_ifs_val = 0;
2023 mac->in_ifs_mode = false;
2024 IGC_WRITE_REG(hw, IGC_AIT, 0);
2030 * igc_validate_mdi_setting_generic - Verify MDI/MDIx settings
2031 * @hw: pointer to the HW structure
2033 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2034 * set, which is forced to MDI mode only.
2036 static s32 igc_validate_mdi_setting_generic(struct igc_hw *hw)
2038 DEBUGFUNC("igc_validate_mdi_setting_generic");
2040 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2041 DEBUGOUT("Invalid MDI setting detected\n");
2043 return -IGC_ERR_CONFIG;
2050 * igc_validate_mdi_setting_crossover_generic - Verify MDI/MDIx settings
2051 * @hw: pointer to the HW structure
2053 * Validate the MDI/MDIx setting, allowing for auto-crossover during forced
2057 igc_validate_mdi_setting_crossover_generic(struct igc_hw IGC_UNUSEDARG * hw)
2059 DEBUGFUNC("igc_validate_mdi_setting_crossover_generic");
2060 UNREFERENCED_1PARAMETER(hw);
2066 * igc_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2067 * @hw: pointer to the HW structure
2068 * @reg: 32bit register offset such as IGC_SCTL
2069 * @offset: register offset to write to
2070 * @data: data to write at register offset
2072 * Writes an address/data control type register. There are several of these
2073 * and they all have the format address << 8 | data and bit 31 is polled for
2076 s32 igc_write_8bit_ctrl_reg_generic(struct igc_hw *hw, u32 reg,
2077 u32 offset, u8 data)
2079 u32 i, regvalue = 0;
2081 DEBUGFUNC("igc_write_8bit_ctrl_reg_generic");
2083 /* Set up the address and data */
2084 regvalue = ((u32)data) | (offset << IGC_GEN_CTL_ADDRESS_SHIFT);
2085 IGC_WRITE_REG(hw, reg, regvalue);
2087 /* Poll the ready bit to see if the MDI read completed */
2088 for (i = 0; i < IGC_GEN_POLL_TIMEOUT; i++) {
2090 regvalue = IGC_READ_REG(hw, reg);
2091 if (regvalue & IGC_GEN_CTL_READY)
2094 if (!(regvalue & IGC_GEN_CTL_READY)) {
2095 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2096 return -IGC_ERR_PHY;