1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
6 #include "igc_manage.h"
9 * igc_calculate_checksum - Calculate checksum for buffer
10 * @buffer: pointer to EEPROM
11 * @length: size of EEPROM to calculate a checksum for
13 * Calculates the checksum for some buffer on a specified length. The
14 * checksum calculated is returned.
16 u8 igc_calculate_checksum(u8 *buffer, u32 length)
21 DEBUGFUNC("igc_calculate_checksum");
26 for (i = 0; i < length; i++)
33 * igc_mng_enable_host_if_generic - Checks host interface is enabled
34 * @hw: pointer to the HW structure
36 * Returns IGC_success upon success, else IGC_ERR_HOST_INTERFACE_COMMAND
38 * This function checks whether the HOST IF is enabled for command operation
39 * and also checks whether the previous command is completed. It busy waits
40 * in case of previous command is not completed.
42 s32 igc_mng_enable_host_if_generic(struct igc_hw *hw)
47 DEBUGFUNC("igc_mng_enable_host_if_generic");
49 if (!hw->mac.arc_subsystem_valid) {
50 DEBUGOUT("ARC subsystem not valid.\n");
51 return -IGC_ERR_HOST_INTERFACE_COMMAND;
54 /* Check that the host interface is enabled. */
55 hicr = IGC_READ_REG(hw, IGC_HICR);
56 if (!(hicr & IGC_HICR_EN)) {
57 DEBUGOUT("IGC_HOST_EN bit disabled.\n");
58 return -IGC_ERR_HOST_INTERFACE_COMMAND;
60 /* check the previous command is completed */
61 for (i = 0; i < IGC_MNG_DHCP_COMMAND_TIMEOUT; i++) {
62 hicr = IGC_READ_REG(hw, IGC_HICR);
63 if (!(hicr & IGC_HICR_C))
68 if (i == IGC_MNG_DHCP_COMMAND_TIMEOUT) {
69 DEBUGOUT("Previous command timeout failed .\n");
70 return -IGC_ERR_HOST_INTERFACE_COMMAND;
77 * igc_check_mng_mode_generic - Generic check management mode
78 * @hw: pointer to the HW structure
80 * Reads the firmware semaphore register and returns true (>0) if
81 * manageability is enabled, else false (0).
83 bool igc_check_mng_mode_generic(struct igc_hw *hw)
85 u32 fwsm = IGC_READ_REG(hw, IGC_FWSM);
87 DEBUGFUNC("igc_check_mng_mode_generic");
90 return (fwsm & IGC_FWSM_MODE_MASK) ==
91 (IGC_MNG_IAMT_MODE << IGC_FWSM_MODE_SHIFT);
95 * igc_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx
96 * @hw: pointer to the HW structure
98 * Enables packet filtering on transmit packets if manageability is enabled
99 * and host interface is enabled.
101 bool igc_enable_tx_pkt_filtering_generic(struct igc_hw *hw)
103 struct igc_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
104 u32 *buffer = (u32 *)&hw->mng_cookie;
106 s32 ret_val, hdr_csum, csum;
109 DEBUGFUNC("igc_enable_tx_pkt_filtering_generic");
111 hw->mac.tx_pkt_filtering = true;
113 /* No manageability, no filtering */
114 if (!hw->mac.ops.check_mng_mode(hw)) {
115 hw->mac.tx_pkt_filtering = false;
116 return hw->mac.tx_pkt_filtering;
119 /* If we can't read from the host interface for whatever
120 * reason, disable filtering.
122 ret_val = igc_mng_enable_host_if_generic(hw);
123 if (ret_val != IGC_SUCCESS) {
124 hw->mac.tx_pkt_filtering = false;
125 return hw->mac.tx_pkt_filtering;
128 /* Read in the header. Length and offset are in dwords. */
129 len = IGC_MNG_DHCP_COOKIE_LENGTH >> 2;
130 offset = IGC_MNG_DHCP_COOKIE_OFFSET >> 2;
131 for (i = 0; i < len; i++)
132 *(buffer + i) = IGC_READ_REG_ARRAY_DWORD(hw, IGC_HOST_IF,
134 hdr_csum = hdr->checksum;
136 csum = igc_calculate_checksum((u8 *)hdr,
137 IGC_MNG_DHCP_COOKIE_LENGTH);
138 /* If either the checksums or signature don't match, then
139 * the cookie area isn't considered valid, in which case we
140 * take the safe route of assuming Tx filtering is enabled.
142 if (hdr_csum != csum || hdr->signature != IGC_IAMT_SIGNATURE) {
143 hw->mac.tx_pkt_filtering = true;
144 return hw->mac.tx_pkt_filtering;
147 /* Cookie area is valid, make the final check for filtering. */
148 if (!(hdr->status & IGC_MNG_DHCP_COOKIE_STATUS_PARSING))
149 hw->mac.tx_pkt_filtering = false;
151 return hw->mac.tx_pkt_filtering;
155 * igc_mng_write_cmd_header_generic - Writes manageability command header
156 * @hw: pointer to the HW structure
157 * @hdr: pointer to the host interface command header
159 * Writes the command header after does the checksum calculation.
161 s32 igc_mng_write_cmd_header_generic(struct igc_hw *hw,
162 struct igc_host_mng_command_header *hdr)
164 u16 i, length = sizeof(struct igc_host_mng_command_header);
166 DEBUGFUNC("igc_mng_write_cmd_header_generic");
168 /* Write the whole command header structure with new checksum. */
170 hdr->checksum = igc_calculate_checksum((u8 *)hdr, length);
173 /* Write the relevant command block into the ram area. */
174 for (i = 0; i < length; i++) {
175 IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, i,
184 * igc_mng_host_if_write_generic - Write to the manageability host interface
185 * @hw: pointer to the HW structure
186 * @buffer: pointer to the host interface buffer
187 * @length: size of the buffer
188 * @offset: location in the buffer to write to
189 * @sum: sum of the data (not checksum)
191 * This function writes the buffer content at the offset given on the host if.
192 * It also does alignment considerations to do the writes in most efficient
193 * way. Also fills up the sum of the buffer in *buffer parameter.
195 s32 igc_mng_host_if_write_generic(struct igc_hw *hw, u8 *buffer,
196 u16 length, u16 offset, u8 *sum)
201 u16 remaining, i, j, prev_bytes;
203 DEBUGFUNC("igc_mng_host_if_write_generic");
205 /* sum = only sum of the data and it is not checksum */
207 if (length == 0 || offset + length > IGC_HI_MAX_MNG_DATA_LENGTH)
208 return -IGC_ERR_PARAM;
211 prev_bytes = offset & 0x3;
215 data = IGC_READ_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset);
216 for (j = prev_bytes; j < sizeof(u32); j++) {
217 *(tmp + j) = *bufptr++;
220 IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset, data);
221 length -= j - prev_bytes;
225 remaining = length & 0x3;
228 /* Calculate length in DWORDs */
231 /* The device driver writes the relevant command block into the
234 for (i = 0; i < length; i++) {
235 for (j = 0; j < sizeof(u32); j++) {
236 *(tmp + j) = *bufptr++;
240 IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset + i,
244 for (j = 0; j < sizeof(u32); j++) {
246 *(tmp + j) = *bufptr++;
252 IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, offset + i,
260 * igc_mng_write_dhcp_info_generic - Writes DHCP info to host interface
261 * @hw: pointer to the HW structure
262 * @buffer: pointer to the host interface
263 * @length: size of the buffer
265 * Writes the DHCP information to the host interface.
267 s32 igc_mng_write_dhcp_info_generic(struct igc_hw *hw, u8 *buffer,
270 struct igc_host_mng_command_header hdr;
274 DEBUGFUNC("igc_mng_write_dhcp_info_generic");
276 hdr.command_id = IGC_MNG_DHCP_TX_PAYLOAD_CMD;
277 hdr.command_length = length;
282 /* Enable the host interface */
283 ret_val = igc_mng_enable_host_if_generic(hw);
287 /* Populate the host interface with the contents of "buffer". */
288 ret_val = igc_mng_host_if_write_generic(hw, buffer, length,
289 sizeof(hdr), &hdr.checksum);
293 /* Write the manageability command header */
294 ret_val = igc_mng_write_cmd_header_generic(hw, &hdr);
298 /* Tell the ARC a new command is pending. */
299 hicr = IGC_READ_REG(hw, IGC_HICR);
300 IGC_WRITE_REG(hw, IGC_HICR, hicr | IGC_HICR_C);
306 * igc_enable_mng_pass_thru - Check if management passthrough is needed
307 * @hw: pointer to the HW structure
309 * Verifies the hardware needs to leave interface enabled so that frames can
310 * be directed to and from the management interface.
312 bool igc_enable_mng_pass_thru(struct igc_hw *hw)
317 DEBUGFUNC("igc_enable_mng_pass_thru");
319 if (!hw->mac.asf_firmware_present)
322 manc = IGC_READ_REG(hw, IGC_MANC);
324 if (!(manc & IGC_MANC_RCV_TCO_EN))
327 if (hw->mac.has_fwsm) {
328 fwsm = IGC_READ_REG(hw, IGC_FWSM);
329 factps = IGC_READ_REG(hw, IGC_FACTPS);
331 if (!(factps & IGC_FACTPS_MNGCG) &&
332 ((fwsm & IGC_FWSM_MODE_MASK) ==
333 (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT)))
335 } else if ((hw->mac.type == igc_82574) ||
336 (hw->mac.type == igc_82583)) {
340 factps = IGC_READ_REG(hw, IGC_FACTPS);
341 ret_val = igc_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
345 if (!(factps & IGC_FACTPS_MNGCG) &&
346 ((data & IGC_NVM_INIT_CTRL2_MNGM) ==
347 (igc_mng_mode_pt << 13)))
349 } else if ((manc & IGC_MANC_SMBUS_EN) &&
350 !(manc & IGC_MANC_ASF_EN)) {
358 * igc_host_interface_command - Writes buffer to host interface
359 * @hw: pointer to the HW structure
360 * @buffer: contains a command to write
361 * @length: the byte length of the buffer, must be multiple of 4 bytes
363 * Writes a buffer to the Host Interface. Upon success, returns IGC_SUCCESS
364 * else returns IGC_ERR_HOST_INTERFACE_COMMAND.
366 s32 igc_host_interface_command(struct igc_hw *hw, u8 *buffer, u32 length)
370 DEBUGFUNC("igc_host_interface_command");
372 if (!(hw->mac.arc_subsystem_valid)) {
373 DEBUGOUT("Hardware doesn't support host interface command.\n");
377 if (!hw->mac.asf_firmware_present) {
378 DEBUGOUT("Firmware is not present.\n");
382 if (length == 0 || length & 0x3 ||
383 length > IGC_HI_MAX_BLOCK_BYTE_LENGTH) {
384 DEBUGOUT("Buffer length failure.\n");
385 return -IGC_ERR_HOST_INTERFACE_COMMAND;
388 /* Check that the host interface is enabled. */
389 hicr = IGC_READ_REG(hw, IGC_HICR);
390 if (!(hicr & IGC_HICR_EN)) {
391 DEBUGOUT("IGC_HOST_EN bit disabled.\n");
392 return -IGC_ERR_HOST_INTERFACE_COMMAND;
395 /* Calculate length in DWORDs */
398 /* The device driver writes the relevant command block
401 for (i = 0; i < length; i++)
402 IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF, i,
403 *((u32 *)buffer + i));
405 /* Setting this bit tells the ARC that a new command is pending. */
406 IGC_WRITE_REG(hw, IGC_HICR, hicr | IGC_HICR_C);
408 for (i = 0; i < IGC_HI_COMMAND_TIMEOUT; i++) {
409 hicr = IGC_READ_REG(hw, IGC_HICR);
410 if (!(hicr & IGC_HICR_C))
415 /* Check command successful completion. */
416 if (i == IGC_HI_COMMAND_TIMEOUT ||
417 (!(IGC_READ_REG(hw, IGC_HICR) & IGC_HICR_SV))) {
418 DEBUGOUT("Command has failed with no status valid.\n");
419 return -IGC_ERR_HOST_INTERFACE_COMMAND;
422 for (i = 0; i < length; i++)
423 *((u32 *)buffer + i) = IGC_READ_REG_ARRAY_DWORD(hw,
431 * igc_load_firmware - Writes proxy FW code buffer to host interface
433 * @hw: pointer to the HW structure
434 * @buffer: contains a firmware to write
435 * @length: the byte length of the buffer, must be multiple of 4 bytes
437 * Upon success returns IGC_SUCCESS, returns IGC_ERR_CONFIG if not enabled
438 * in HW else returns IGC_ERR_HOST_INTERFACE_COMMAND.
440 s32 igc_load_firmware(struct igc_hw *hw, u8 *buffer, u32 length)
442 u32 hicr, hibba, fwsm, icr, i;
444 DEBUGFUNC("igc_load_firmware");
446 if (hw->mac.type < igc_i210) {
447 DEBUGOUT("Hardware doesn't support loading FW by the driver\n");
448 return -IGC_ERR_CONFIG;
451 /* Check that the host interface is enabled. */
452 hicr = IGC_READ_REG(hw, IGC_HICR);
453 if (!(hicr & IGC_HICR_EN)) {
454 DEBUGOUT("IGC_HOST_EN bit disabled.\n");
455 return -IGC_ERR_CONFIG;
457 if (!(hicr & IGC_HICR_MEMORY_BASE_EN)) {
458 DEBUGOUT("IGC_HICR_MEMORY_BASE_EN bit disabled.\n");
459 return -IGC_ERR_CONFIG;
462 if (length == 0 || length & 0x3 || length > IGC_HI_FW_MAX_LENGTH) {
463 DEBUGOUT("Buffer length failure.\n");
464 return -IGC_ERR_INVALID_ARGUMENT;
467 /* Clear notification from ROM-FW by reading ICR register */
468 icr = IGC_READ_REG(hw, IGC_ICR_V2);
471 hicr = IGC_READ_REG(hw, IGC_HICR);
472 hicr |= IGC_HICR_FW_RESET_ENABLE;
473 IGC_WRITE_REG(hw, IGC_HICR, hicr);
474 hicr |= IGC_HICR_FW_RESET;
475 IGC_WRITE_REG(hw, IGC_HICR, hicr);
478 /* Wait till MAC notifies about its readiness after ROM-FW reset */
479 for (i = 0; i < (IGC_HI_COMMAND_TIMEOUT * 2); i++) {
480 icr = IGC_READ_REG(hw, IGC_ICR_V2);
481 if (icr & IGC_ICR_MNG)
486 /* Check for timeout */
487 if (i == IGC_HI_COMMAND_TIMEOUT) {
488 DEBUGOUT("FW reset failed.\n");
489 return -IGC_ERR_HOST_INTERFACE_COMMAND;
492 /* Wait till MAC is ready to accept new FW code */
493 for (i = 0; i < IGC_HI_COMMAND_TIMEOUT; i++) {
494 fwsm = IGC_READ_REG(hw, IGC_FWSM);
495 if ((fwsm & IGC_FWSM_FW_VALID) &&
496 ((fwsm & IGC_FWSM_MODE_MASK) >> IGC_FWSM_MODE_SHIFT ==
497 IGC_FWSM_HI_EN_ONLY_MODE))
502 /* Check for timeout */
503 if (i == IGC_HI_COMMAND_TIMEOUT) {
504 DEBUGOUT("FW reset failed.\n");
505 return -IGC_ERR_HOST_INTERFACE_COMMAND;
508 /* Calculate length in DWORDs */
511 /* The device driver writes the relevant FW code block
512 * into the ram area in DWORDs via 1kB ram addressing window.
514 for (i = 0; i < length; i++) {
515 if (!(i % IGC_HI_FW_BLOCK_DWORD_LENGTH)) {
516 /* Point to correct 1kB ram window */
517 hibba = IGC_HI_FW_BASE_ADDRESS +
518 ((IGC_HI_FW_BLOCK_DWORD_LENGTH << 2) *
519 (i / IGC_HI_FW_BLOCK_DWORD_LENGTH));
521 IGC_WRITE_REG(hw, IGC_HIBBA, hibba);
524 IGC_WRITE_REG_ARRAY_DWORD(hw, IGC_HOST_IF,
525 i % IGC_HI_FW_BLOCK_DWORD_LENGTH,
526 *((u32 *)buffer + i));
529 /* Setting this bit tells the ARC that a new FW is ready to execute. */
530 hicr = IGC_READ_REG(hw, IGC_HICR);
531 IGC_WRITE_REG(hw, IGC_HICR, hicr | IGC_HICR_C);
533 for (i = 0; i < IGC_HI_COMMAND_TIMEOUT; i++) {
534 hicr = IGC_READ_REG(hw, IGC_HICR);
535 if (!(hicr & IGC_HICR_C))
540 /* Check for successful FW start. */
541 if (i == IGC_HI_COMMAND_TIMEOUT) {
542 DEBUGOUT("New FW did not start within timeout period.\n");
543 return -IGC_ERR_HOST_INTERFACE_COMMAND;