1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
7 static void igc_reload_nvm_generic(struct igc_hw *hw);
10 * igc_init_nvm_ops_generic - Initialize NVM function pointers
11 * @hw: pointer to the HW structure
13 * Setups up the function pointers to no-op functions
15 void igc_init_nvm_ops_generic(struct igc_hw *hw)
17 struct igc_nvm_info *nvm = &hw->nvm;
18 DEBUGFUNC("igc_init_nvm_ops_generic");
20 /* Initialize function pointers */
21 nvm->ops.init_params = igc_null_ops_generic;
22 nvm->ops.acquire = igc_null_ops_generic;
23 nvm->ops.read = igc_null_read_nvm;
24 nvm->ops.release = igc_null_nvm_generic;
25 nvm->ops.reload = igc_reload_nvm_generic;
26 nvm->ops.update = igc_null_ops_generic;
27 nvm->ops.valid_led_default = igc_null_led_default;
28 nvm->ops.validate = igc_null_ops_generic;
29 nvm->ops.write = igc_null_write_nvm;
33 * igc_null_nvm_read - No-op function, return 0
34 * @hw: pointer to the HW structure
39 s32 igc_null_read_nvm(struct igc_hw IGC_UNUSEDARG * hw,
40 u16 IGC_UNUSEDARG a, u16 IGC_UNUSEDARG b,
41 u16 IGC_UNUSEDARG * c)
43 DEBUGFUNC("igc_null_read_nvm");
44 UNREFERENCED_4PARAMETER(hw, a, b, c);
49 * igc_null_nvm_generic - No-op function, return void
50 * @hw: pointer to the HW structure
52 void igc_null_nvm_generic(struct igc_hw IGC_UNUSEDARG * hw)
54 DEBUGFUNC("igc_null_nvm_generic");
55 UNREFERENCED_1PARAMETER(hw);
59 * igc_null_led_default - No-op function, return 0
60 * @hw: pointer to the HW structure
61 * @data: dummy variable
63 s32 igc_null_led_default(struct igc_hw IGC_UNUSEDARG * hw,
64 u16 IGC_UNUSEDARG * data)
66 DEBUGFUNC("igc_null_led_default");
67 UNREFERENCED_2PARAMETER(hw, data);
72 * igc_null_write_nvm - No-op function, return 0
73 * @hw: pointer to the HW structure
78 s32 igc_null_write_nvm(struct igc_hw IGC_UNUSEDARG * hw,
79 u16 IGC_UNUSEDARG a, u16 IGC_UNUSEDARG b,
80 u16 IGC_UNUSEDARG * c)
82 DEBUGFUNC("igc_null_write_nvm");
83 UNREFERENCED_4PARAMETER(hw, a, b, c);
88 * igc_raise_eec_clk - Raise EEPROM clock
89 * @hw: pointer to the HW structure
90 * @eecd: pointer to the EEPROM
92 * Enable/Raise the EEPROM clock bit.
94 static void igc_raise_eec_clk(struct igc_hw *hw, u32 *eecd)
96 *eecd = *eecd | IGC_EECD_SK;
97 IGC_WRITE_REG(hw, IGC_EECD, *eecd);
99 usec_delay(hw->nvm.delay_usec);
103 * igc_lower_eec_clk - Lower EEPROM clock
104 * @hw: pointer to the HW structure
105 * @eecd: pointer to the EEPROM
107 * Clear/Lower the EEPROM clock bit.
109 static void igc_lower_eec_clk(struct igc_hw *hw, u32 *eecd)
111 *eecd = *eecd & ~IGC_EECD_SK;
112 IGC_WRITE_REG(hw, IGC_EECD, *eecd);
114 usec_delay(hw->nvm.delay_usec);
118 * igc_shift_out_eec_bits - Shift data bits our to the EEPROM
119 * @hw: pointer to the HW structure
120 * @data: data to send to the EEPROM
121 * @count: number of bits to shift out
123 * We need to shift 'count' bits out to the EEPROM. So, the value in the
124 * "data" parameter will be shifted out to the EEPROM one bit at a time.
125 * In order to do this, "data" must be broken down into bits.
127 static void igc_shift_out_eec_bits(struct igc_hw *hw, u16 data, u16 count)
129 struct igc_nvm_info *nvm = &hw->nvm;
130 u32 eecd = IGC_READ_REG(hw, IGC_EECD);
133 DEBUGFUNC("igc_shift_out_eec_bits");
135 mask = 0x01 << (count - 1);
136 if (nvm->type == igc_nvm_eeprom_microwire)
137 eecd &= ~IGC_EECD_DO;
138 else if (nvm->type == igc_nvm_eeprom_spi)
142 eecd &= ~IGC_EECD_DI;
147 IGC_WRITE_REG(hw, IGC_EECD, eecd);
150 usec_delay(nvm->delay_usec);
152 igc_raise_eec_clk(hw, &eecd);
153 igc_lower_eec_clk(hw, &eecd);
158 eecd &= ~IGC_EECD_DI;
159 IGC_WRITE_REG(hw, IGC_EECD, eecd);
163 * igc_shift_in_eec_bits - Shift data bits in from the EEPROM
164 * @hw: pointer to the HW structure
165 * @count: number of bits to shift in
167 * In order to read a register from the EEPROM, we need to shift 'count' bits
168 * in from the EEPROM. Bits are "shifted in" by raising the clock input to
169 * the EEPROM (setting the SK bit), and then reading the value of the data out
170 * "DO" bit. During this "shifting in" process the data in "DI" bit should
173 static u16 igc_shift_in_eec_bits(struct igc_hw *hw, u16 count)
179 DEBUGFUNC("igc_shift_in_eec_bits");
181 eecd = IGC_READ_REG(hw, IGC_EECD);
183 eecd &= ~(IGC_EECD_DO | IGC_EECD_DI);
186 for (i = 0; i < count; i++) {
188 igc_raise_eec_clk(hw, &eecd);
190 eecd = IGC_READ_REG(hw, IGC_EECD);
192 eecd &= ~IGC_EECD_DI;
193 if (eecd & IGC_EECD_DO)
196 igc_lower_eec_clk(hw, &eecd);
203 * igc_poll_eerd_eewr_done - Poll for EEPROM read/write completion
204 * @hw: pointer to the HW structure
205 * @ee_reg: EEPROM flag for polling
207 * Polls the EEPROM status bit for either read or write completion based
208 * upon the value of 'ee_reg'.
210 s32 igc_poll_eerd_eewr_done(struct igc_hw *hw, int ee_reg)
212 u32 attempts = 100000;
215 DEBUGFUNC("igc_poll_eerd_eewr_done");
217 for (i = 0; i < attempts; i++) {
218 if (ee_reg == IGC_NVM_POLL_READ)
219 reg = IGC_READ_REG(hw, IGC_EERD);
221 reg = IGC_READ_REG(hw, IGC_EEWR);
223 if (reg & IGC_NVM_RW_REG_DONE)
233 * igc_acquire_nvm_generic - Generic request for access to EEPROM
234 * @hw: pointer to the HW structure
236 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
237 * Return successful if access grant bit set, else clear the request for
238 * EEPROM access and return -IGC_ERR_NVM (-1).
240 s32 igc_acquire_nvm_generic(struct igc_hw *hw)
242 u32 eecd = IGC_READ_REG(hw, IGC_EECD);
243 s32 timeout = IGC_NVM_GRANT_ATTEMPTS;
245 DEBUGFUNC("igc_acquire_nvm_generic");
247 IGC_WRITE_REG(hw, IGC_EECD, eecd | IGC_EECD_REQ);
248 eecd = IGC_READ_REG(hw, IGC_EECD);
251 if (eecd & IGC_EECD_GNT)
254 eecd = IGC_READ_REG(hw, IGC_EECD);
259 eecd &= ~IGC_EECD_REQ;
260 IGC_WRITE_REG(hw, IGC_EECD, eecd);
261 DEBUGOUT("Could not acquire NVM grant\n");
269 * igc_standby_nvm - Return EEPROM to standby state
270 * @hw: pointer to the HW structure
272 * Return the EEPROM to a standby state.
274 static void igc_standby_nvm(struct igc_hw *hw)
276 struct igc_nvm_info *nvm = &hw->nvm;
277 u32 eecd = IGC_READ_REG(hw, IGC_EECD);
279 DEBUGFUNC("igc_standby_nvm");
281 if (nvm->type == igc_nvm_eeprom_microwire) {
282 eecd &= ~(IGC_EECD_CS | IGC_EECD_SK);
283 IGC_WRITE_REG(hw, IGC_EECD, eecd);
285 usec_delay(nvm->delay_usec);
287 igc_raise_eec_clk(hw, &eecd);
291 IGC_WRITE_REG(hw, IGC_EECD, eecd);
293 usec_delay(nvm->delay_usec);
295 igc_lower_eec_clk(hw, &eecd);
296 } else if (nvm->type == igc_nvm_eeprom_spi) {
297 /* Toggle CS to flush commands */
299 IGC_WRITE_REG(hw, IGC_EECD, eecd);
301 usec_delay(nvm->delay_usec);
302 eecd &= ~IGC_EECD_CS;
303 IGC_WRITE_REG(hw, IGC_EECD, eecd);
305 usec_delay(nvm->delay_usec);
310 * igc_stop_nvm - Terminate EEPROM command
311 * @hw: pointer to the HW structure
313 * Terminates the current command by inverting the EEPROM's chip select pin.
315 void igc_stop_nvm(struct igc_hw *hw)
319 DEBUGFUNC("igc_stop_nvm");
321 eecd = IGC_READ_REG(hw, IGC_EECD);
322 if (hw->nvm.type == igc_nvm_eeprom_spi) {
325 igc_lower_eec_clk(hw, &eecd);
326 } else if (hw->nvm.type == igc_nvm_eeprom_microwire) {
327 /* CS on Microwire is active-high */
328 eecd &= ~(IGC_EECD_CS | IGC_EECD_DI);
329 IGC_WRITE_REG(hw, IGC_EECD, eecd);
330 igc_raise_eec_clk(hw, &eecd);
331 igc_lower_eec_clk(hw, &eecd);
336 * igc_release_nvm_generic - Release exclusive access to EEPROM
337 * @hw: pointer to the HW structure
339 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
341 void igc_release_nvm_generic(struct igc_hw *hw)
345 DEBUGFUNC("igc_release_nvm_generic");
349 eecd = IGC_READ_REG(hw, IGC_EECD);
350 eecd &= ~IGC_EECD_REQ;
351 IGC_WRITE_REG(hw, IGC_EECD, eecd);
355 * igc_ready_nvm_eeprom - Prepares EEPROM for read/write
356 * @hw: pointer to the HW structure
358 * Setups the EEPROM for reading and writing.
360 static s32 igc_ready_nvm_eeprom(struct igc_hw *hw)
362 struct igc_nvm_info *nvm = &hw->nvm;
363 u32 eecd = IGC_READ_REG(hw, IGC_EECD);
366 DEBUGFUNC("igc_ready_nvm_eeprom");
368 if (nvm->type == igc_nvm_eeprom_microwire) {
369 /* Clear SK and DI */
370 eecd &= ~(IGC_EECD_DI | IGC_EECD_SK);
371 IGC_WRITE_REG(hw, IGC_EECD, eecd);
374 IGC_WRITE_REG(hw, IGC_EECD, eecd);
375 } else if (nvm->type == igc_nvm_eeprom_spi) {
376 u16 timeout = NVM_MAX_RETRY_SPI;
378 /* Clear SK and CS */
379 eecd &= ~(IGC_EECD_CS | IGC_EECD_SK);
380 IGC_WRITE_REG(hw, IGC_EECD, eecd);
384 /* Read "Status Register" repeatedly until the LSB is cleared.
385 * The EEPROM will signal that the command has been completed
386 * by clearing bit 0 of the internal status register. If it's
387 * not cleared within 'timeout', then error out.
390 igc_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
391 hw->nvm.opcode_bits);
392 spi_stat_reg = (u8)igc_shift_in_eec_bits(hw, 8);
393 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
402 DEBUGOUT("SPI NVM Status error\n");
411 * igc_read_nvm_spi - Read EEPROM's using SPI
412 * @hw: pointer to the HW structure
413 * @offset: offset of word in the EEPROM to read
414 * @words: number of words to read
415 * @data: word read from the EEPROM
417 * Reads a 16 bit word from the EEPROM.
419 s32 igc_read_nvm_spi(struct igc_hw *hw, u16 offset, u16 words, u16 *data)
421 struct igc_nvm_info *nvm = &hw->nvm;
425 u8 read_opcode = NVM_READ_OPCODE_SPI;
427 DEBUGFUNC("igc_read_nvm_spi");
429 /* A check for invalid values: offset too large, too many words,
430 * and not enough words.
432 if (offset >= nvm->word_size || words > (nvm->word_size - offset) ||
434 DEBUGOUT("nvm parameter(s) out of bounds\n");
438 ret_val = nvm->ops.acquire(hw);
442 ret_val = igc_ready_nvm_eeprom(hw);
448 if (nvm->address_bits == 8 && offset >= 128)
449 read_opcode |= NVM_A8_OPCODE_SPI;
451 /* Send the READ command (opcode + addr) */
452 igc_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
453 igc_shift_out_eec_bits(hw, (u16)(offset * 2), nvm->address_bits);
455 /* Read the data. SPI NVMs increment the address with each byte
456 * read and will roll over if reading beyond the end. This allows
457 * us to read the whole NVM from any offset
459 for (i = 0; i < words; i++) {
460 word_in = igc_shift_in_eec_bits(hw, 16);
461 data[i] = (word_in >> 8) | (word_in << 8);
465 nvm->ops.release(hw);
471 * igc_read_nvm_microwire - Reads EEPROM's using microwire
472 * @hw: pointer to the HW structure
473 * @offset: offset of word in the EEPROM to read
474 * @words: number of words to read
475 * @data: word read from the EEPROM
477 * Reads a 16 bit word from the EEPROM.
479 s32 igc_read_nvm_microwire(struct igc_hw *hw, u16 offset, u16 words,
482 struct igc_nvm_info *nvm = &hw->nvm;
485 u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
487 DEBUGFUNC("igc_read_nvm_microwire");
489 /* A check for invalid values: offset too large, too many words,
490 * and not enough words.
492 if (offset >= nvm->word_size || words > (nvm->word_size - offset) ||
494 DEBUGOUT("nvm parameter(s) out of bounds\n");
498 ret_val = nvm->ops.acquire(hw);
502 ret_val = igc_ready_nvm_eeprom(hw);
506 for (i = 0; i < words; i++) {
507 /* Send the READ command (opcode + addr) */
508 igc_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
509 igc_shift_out_eec_bits(hw, (u16)(offset + i),
512 /* Read the data. For microwire, each word requires the
513 * overhead of setup and tear-down.
515 data[i] = igc_shift_in_eec_bits(hw, 16);
520 nvm->ops.release(hw);
526 * igc_read_nvm_eerd - Reads EEPROM using EERD register
527 * @hw: pointer to the HW structure
528 * @offset: offset of word in the EEPROM to read
529 * @words: number of words to read
530 * @data: word read from the EEPROM
532 * Reads a 16 bit word from the EEPROM using the EERD register.
534 s32 igc_read_nvm_eerd(struct igc_hw *hw, u16 offset, u16 words, u16 *data)
536 struct igc_nvm_info *nvm = &hw->nvm;
538 s32 ret_val = IGC_SUCCESS;
540 DEBUGFUNC("igc_read_nvm_eerd");
542 /* A check for invalid values: offset too large, too many words,
543 * too many words for the offset, and not enough words.
545 if (offset >= nvm->word_size || words > (nvm->word_size - offset) ||
547 DEBUGOUT("nvm parameter(s) out of bounds\n");
551 for (i = 0; i < words; i++) {
552 eerd = ((offset + i) << IGC_NVM_RW_ADDR_SHIFT) +
553 IGC_NVM_RW_REG_START;
555 IGC_WRITE_REG(hw, IGC_EERD, eerd);
556 ret_val = igc_poll_eerd_eewr_done(hw, IGC_NVM_POLL_READ);
560 data[i] = (IGC_READ_REG(hw, IGC_EERD) >>
561 IGC_NVM_RW_REG_DATA);
565 DEBUGOUT1("NVM read error: %d\n", ret_val);
571 * igc_write_nvm_spi - Write to EEPROM using SPI
572 * @hw: pointer to the HW structure
573 * @offset: offset within the EEPROM to be written to
574 * @words: number of words to write
575 * @data: 16 bit word(s) to be written to the EEPROM
577 * Writes data to EEPROM at offset using SPI interface.
579 * If igc_update_nvm_checksum is not called after this function , the
580 * EEPROM will most likely contain an invalid checksum.
582 s32 igc_write_nvm_spi(struct igc_hw *hw, u16 offset, u16 words, u16 *data)
584 struct igc_nvm_info *nvm = &hw->nvm;
585 s32 ret_val = -IGC_ERR_NVM;
588 DEBUGFUNC("igc_write_nvm_spi");
590 /* A check for invalid values: offset too large, too many words,
591 * and not enough words.
593 if (offset >= nvm->word_size || words > (nvm->word_size - offset) ||
595 DEBUGOUT("nvm parameter(s) out of bounds\n");
599 while (widx < words) {
600 u8 write_opcode = NVM_WRITE_OPCODE_SPI;
602 ret_val = nvm->ops.acquire(hw);
606 ret_val = igc_ready_nvm_eeprom(hw);
608 nvm->ops.release(hw);
614 /* Send the WRITE ENABLE command (8 bit opcode) */
615 igc_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
620 /* Some SPI eeproms use the 8th address bit embedded in the
623 if (nvm->address_bits == 8 && offset >= 128)
624 write_opcode |= NVM_A8_OPCODE_SPI;
626 /* Send the Write command (8-bit opcode + addr) */
627 igc_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
628 igc_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
631 /* Loop to allow for up to whole page write of eeprom */
632 while (widx < words) {
633 u16 word_out = data[widx];
634 word_out = (word_out >> 8) | (word_out << 8);
635 igc_shift_out_eec_bits(hw, word_out, 16);
638 if ((((offset + widx) * 2) % nvm->page_size) == 0) {
644 nvm->ops.release(hw);
651 * igc_write_nvm_microwire - Writes EEPROM using microwire
652 * @hw: pointer to the HW structure
653 * @offset: offset within the EEPROM to be written to
654 * @words: number of words to write
655 * @data: 16 bit word(s) to be written to the EEPROM
657 * Writes data to EEPROM at offset using microwire interface.
659 * If igc_update_nvm_checksum is not called after this function , the
660 * EEPROM will most likely contain an invalid checksum.
662 s32 igc_write_nvm_microwire(struct igc_hw *hw, u16 offset, u16 words,
665 struct igc_nvm_info *nvm = &hw->nvm;
668 u16 words_written = 0;
671 DEBUGFUNC("igc_write_nvm_microwire");
673 /* A check for invalid values: offset too large, too many words,
674 * and not enough words.
676 if (offset >= nvm->word_size || words > (nvm->word_size - offset) ||
678 DEBUGOUT("nvm parameter(s) out of bounds\n");
682 ret_val = nvm->ops.acquire(hw);
686 ret_val = igc_ready_nvm_eeprom(hw);
690 igc_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
691 (u16)(nvm->opcode_bits + 2));
693 igc_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
697 while (words_written < words) {
698 igc_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
701 igc_shift_out_eec_bits(hw, (u16)(offset + words_written),
704 igc_shift_out_eec_bits(hw, data[words_written], 16);
708 for (widx = 0; widx < 200; widx++) {
709 eecd = IGC_READ_REG(hw, IGC_EECD);
710 if (eecd & IGC_EECD_DO)
716 DEBUGOUT("NVM Write did not complete\n");
717 ret_val = -IGC_ERR_NVM;
726 igc_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
727 (u16)(nvm->opcode_bits + 2));
729 igc_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
732 nvm->ops.release(hw);
738 * igc_read_pba_string_generic - Read device part number
739 * @hw: pointer to the HW structure
740 * @pba_num: pointer to device part number
741 * @pba_num_size: size of part number buffer
743 * Reads the product board assembly (PBA) number from the EEPROM and stores
744 * the value in pba_num.
746 s32 igc_read_pba_string_generic(struct igc_hw *hw, u8 *pba_num,
755 DEBUGFUNC("igc_read_pba_string_generic");
757 if (pba_num == NULL) {
758 DEBUGOUT("PBA string buffer was null\n");
759 return -IGC_ERR_INVALID_ARGUMENT;
762 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
764 DEBUGOUT("NVM Read Error\n");
768 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
770 DEBUGOUT("NVM Read Error\n");
774 /* if nvm_data is not ptr guard the PBA must be in legacy format which
775 * means pba_ptr is actually our second data word for the PBA number
776 * and we can decode it into an ascii string
778 if (nvm_data != NVM_PBA_PTR_GUARD) {
779 DEBUGOUT("NVM PBA number is not stored as string\n");
781 /* make sure callers buffer is big enough to store the PBA */
782 if (pba_num_size < IGC_PBANUM_LENGTH) {
783 DEBUGOUT("PBA string buffer too small\n");
784 return IGC_ERR_NO_SPACE;
787 /* extract hex string from data and pba_ptr */
788 pba_num[0] = (nvm_data >> 12) & 0xF;
789 pba_num[1] = (nvm_data >> 8) & 0xF;
790 pba_num[2] = (nvm_data >> 4) & 0xF;
791 pba_num[3] = nvm_data & 0xF;
792 pba_num[4] = (pba_ptr >> 12) & 0xF;
793 pba_num[5] = (pba_ptr >> 8) & 0xF;
796 pba_num[8] = (pba_ptr >> 4) & 0xF;
797 pba_num[9] = pba_ptr & 0xF;
799 /* put a null character on the end of our string */
802 /* switch all the data but the '-' to hex char */
803 for (offset = 0; offset < 10; offset++) {
804 if (pba_num[offset] < 0xA)
805 pba_num[offset] += '0';
806 else if (pba_num[offset] < 0x10)
807 pba_num[offset] += 'A' - 0xA;
813 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
815 DEBUGOUT("NVM Read Error\n");
819 if (length == 0xFFFF || length == 0) {
820 DEBUGOUT("NVM PBA number section invalid length\n");
821 return -IGC_ERR_NVM_PBA_SECTION;
823 /* check if pba_num buffer is big enough */
824 if (pba_num_size < (((u32)length * 2) - 1)) {
825 DEBUGOUT("PBA string buffer too small\n");
826 return -IGC_ERR_NO_SPACE;
829 /* trim pba length from start of string */
833 for (offset = 0; offset < length; offset++) {
834 ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);
836 DEBUGOUT("NVM Read Error\n");
839 pba_num[offset * 2] = (u8)(nvm_data >> 8);
840 pba_num[(offset * 2) + 1] = (u8)(nvm_data & 0xFF);
842 pba_num[offset * 2] = '\0';
848 * igc_read_pba_length_generic - Read device part number length
849 * @hw: pointer to the HW structure
850 * @pba_num_size: size of part number buffer
852 * Reads the product board assembly (PBA) number length from the EEPROM and
853 * stores the value in pba_num_size.
855 s32 igc_read_pba_length_generic(struct igc_hw *hw, u32 *pba_num_size)
862 DEBUGFUNC("igc_read_pba_length_generic");
864 if (pba_num_size == NULL) {
865 DEBUGOUT("PBA buffer size was null\n");
866 return -IGC_ERR_INVALID_ARGUMENT;
869 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
871 DEBUGOUT("NVM Read Error\n");
875 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);
877 DEBUGOUT("NVM Read Error\n");
881 /* if data is not ptr guard the PBA must be in legacy format */
882 if (nvm_data != NVM_PBA_PTR_GUARD) {
883 *pba_num_size = IGC_PBANUM_LENGTH;
887 ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);
889 DEBUGOUT("NVM Read Error\n");
893 if (length == 0xFFFF || length == 0) {
894 DEBUGOUT("NVM PBA number section invalid length\n");
895 return -IGC_ERR_NVM_PBA_SECTION;
898 /* Convert from length in u16 values to u8 chars, add 1 for NULL,
899 * and subtract 2 because length field is included in length.
901 *pba_num_size = ((u32)length * 2) - 1;
907 * igc_read_pba_num_generic - Read device part number
908 * @hw: pointer to the HW structure
909 * @pba_num: pointer to device part number
911 * Reads the product board assembly (PBA) number from the EEPROM and stores
912 * the value in pba_num.
914 s32 igc_read_pba_num_generic(struct igc_hw *hw, u32 *pba_num)
919 DEBUGFUNC("igc_read_pba_num_generic");
921 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
923 DEBUGOUT("NVM Read Error\n");
925 } else if (nvm_data == NVM_PBA_PTR_GUARD) {
926 DEBUGOUT("NVM Not Supported\n");
927 return -IGC_NOT_IMPLEMENTED;
929 *pba_num = (u32)(nvm_data << 16);
931 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
933 DEBUGOUT("NVM Read Error\n");
936 *pba_num |= nvm_data;
944 * @hw: pointer to the HW structure
945 * @eeprom_buf: optional pointer to EEPROM image
946 * @eeprom_buf_size: size of EEPROM image in words
947 * @max_pba_block_size: PBA block size limit
948 * @pba: pointer to output PBA structure
950 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
951 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
954 s32 igc_read_pba_raw(struct igc_hw *hw, u16 *eeprom_buf,
955 u32 eeprom_buf_size, u16 max_pba_block_size,
962 return -IGC_ERR_PARAM;
964 if (eeprom_buf == NULL) {
965 ret_val = igc_read_nvm(hw, NVM_PBA_OFFSET_0, 2,
970 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
971 pba->word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
972 pba->word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
974 return -IGC_ERR_PARAM;
978 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
979 if (pba->pba_block == NULL)
980 return -IGC_ERR_PARAM;
982 ret_val = igc_get_pba_block_size(hw, eeprom_buf,
988 if (pba_block_size > max_pba_block_size)
989 return -IGC_ERR_PARAM;
991 if (eeprom_buf == NULL) {
992 ret_val = igc_read_nvm(hw, pba->word[1],
998 if (eeprom_buf_size > (u32)(pba->word[1] +
1000 memcpy(pba->pba_block,
1001 &eeprom_buf[pba->word[1]],
1002 pba_block_size * sizeof(u16));
1004 return -IGC_ERR_PARAM;
1014 * @hw: pointer to the HW structure
1015 * @eeprom_buf: optional pointer to EEPROM image
1016 * @eeprom_buf_size: size of EEPROM image in words
1017 * @pba: pointer to PBA structure
1019 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
1020 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
1023 s32 igc_write_pba_raw(struct igc_hw *hw, u16 *eeprom_buf,
1024 u32 eeprom_buf_size, struct igc_pba *pba)
1029 return -IGC_ERR_PARAM;
1031 if (eeprom_buf == NULL) {
1032 ret_val = igc_write_nvm(hw, NVM_PBA_OFFSET_0, 2,
1037 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1038 eeprom_buf[NVM_PBA_OFFSET_0] = pba->word[0];
1039 eeprom_buf[NVM_PBA_OFFSET_1] = pba->word[1];
1041 return -IGC_ERR_PARAM;
1045 if (pba->word[0] == NVM_PBA_PTR_GUARD) {
1046 if (pba->pba_block == NULL)
1047 return -IGC_ERR_PARAM;
1049 if (eeprom_buf == NULL) {
1050 ret_val = igc_write_nvm(hw, pba->word[1],
1056 if (eeprom_buf_size > (u32)(pba->word[1] +
1057 pba->pba_block[0])) {
1058 memcpy(&eeprom_buf[pba->word[1]],
1060 pba->pba_block[0] * sizeof(u16));
1062 return -IGC_ERR_PARAM;
1071 * igc_get_pba_block_size
1072 * @hw: pointer to the HW structure
1073 * @eeprom_buf: optional pointer to EEPROM image
1074 * @eeprom_buf_size: size of EEPROM image in words
1075 * @pba_data_size: pointer to output variable
1077 * Returns the size of the PBA block in words. Function operates on EEPROM
1078 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
1082 s32 igc_get_pba_block_size(struct igc_hw *hw, u16 *eeprom_buf,
1083 u32 eeprom_buf_size, u16 *pba_block_size)
1089 DEBUGFUNC("igc_get_pba_block_size");
1091 if (eeprom_buf == NULL) {
1092 ret_val = igc_read_nvm(hw, NVM_PBA_OFFSET_0, 2, &pba_word[0]);
1096 if (eeprom_buf_size > NVM_PBA_OFFSET_1) {
1097 pba_word[0] = eeprom_buf[NVM_PBA_OFFSET_0];
1098 pba_word[1] = eeprom_buf[NVM_PBA_OFFSET_1];
1100 return -IGC_ERR_PARAM;
1104 if (pba_word[0] == NVM_PBA_PTR_GUARD) {
1105 if (eeprom_buf == NULL) {
1106 ret_val = igc_read_nvm(hw, pba_word[1] + 0, 1,
1111 if (eeprom_buf_size > pba_word[1])
1112 length = eeprom_buf[pba_word[1] + 0];
1114 return -IGC_ERR_PARAM;
1117 if (length == 0xFFFF || length == 0)
1118 return -IGC_ERR_NVM_PBA_SECTION;
1120 /* PBA number in legacy format, there is no PBA Block. */
1124 if (pba_block_size != NULL)
1125 *pba_block_size = length;
1131 * igc_read_mac_addr_generic - Read device MAC address
1132 * @hw: pointer to the HW structure
1134 * Reads the device MAC address from the EEPROM and stores the value.
1135 * Since devices with two ports use the same EEPROM, we increment the
1136 * last bit in the MAC address for the second port.
1138 s32 igc_read_mac_addr_generic(struct igc_hw *hw)
1144 rar_high = IGC_READ_REG(hw, IGC_RAH(0));
1145 rar_low = IGC_READ_REG(hw, IGC_RAL(0));
1147 for (i = 0; i < IGC_RAL_MAC_ADDR_LEN; i++)
1148 hw->mac.perm_addr[i] = (u8)(rar_low >> (i * 8));
1150 for (i = 0; i < IGC_RAH_MAC_ADDR_LEN; i++)
1151 hw->mac.perm_addr[i + 4] = (u8)(rar_high >> (i * 8));
1153 for (i = 0; i < ETH_ADDR_LEN; i++)
1154 hw->mac.addr[i] = hw->mac.perm_addr[i];
1160 * igc_validate_nvm_checksum_generic - Validate EEPROM checksum
1161 * @hw: pointer to the HW structure
1163 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
1164 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
1166 s32 igc_validate_nvm_checksum_generic(struct igc_hw *hw)
1172 DEBUGFUNC("igc_validate_nvm_checksum_generic");
1174 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
1175 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1177 DEBUGOUT("NVM Read Error\n");
1180 checksum += nvm_data;
1183 if (checksum != (u16)NVM_SUM) {
1184 DEBUGOUT("NVM Checksum Invalid\n");
1185 return -IGC_ERR_NVM;
1192 * igc_update_nvm_checksum_generic - Update EEPROM checksum
1193 * @hw: pointer to the HW structure
1195 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
1196 * up to the checksum. Then calculates the EEPROM checksum and writes the
1197 * value to the EEPROM.
1199 s32 igc_update_nvm_checksum_generic(struct igc_hw *hw)
1205 DEBUGFUNC("igc_update_nvm_checksum");
1207 for (i = 0; i < NVM_CHECKSUM_REG; i++) {
1208 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
1210 DEBUGOUT("NVM Read Error while updating checksum.\n");
1213 checksum += nvm_data;
1215 checksum = (u16)NVM_SUM - checksum;
1216 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
1218 DEBUGOUT("NVM Write Error while updating checksum.\n");
1224 * igc_reload_nvm_generic - Reloads EEPROM
1225 * @hw: pointer to the HW structure
1227 * Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
1228 * extended control register.
1230 static void igc_reload_nvm_generic(struct igc_hw *hw)
1234 DEBUGFUNC("igc_reload_nvm_generic");
1237 ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
1238 ctrl_ext |= IGC_CTRL_EXT_EE_RST;
1239 IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext);
1240 IGC_WRITE_FLUSH(hw);
1244 * igc_get_fw_version - Get firmware version information
1245 * @hw: pointer to the HW structure
1246 * @fw_vers: pointer to output version structure
1248 * unsupported/not present features return 0 in version structure
1250 void igc_get_fw_version(struct igc_hw *hw, struct igc_fw_version *fw_vers)
1252 u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
1253 u8 q, hval, rem, result;
1254 u16 comb_verh, comb_verl, comb_offset;
1256 memset(fw_vers, 0, sizeof(struct igc_fw_version));
1259 * basic eeprom version numbers, bits used vary by part and by tool
1260 * used to create the nvm images. Check which data format we have.
1262 switch (hw->mac.type) {
1264 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1265 /* find combo image version */
1266 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
1267 if (comb_offset && comb_offset != NVM_VER_INVALID) {
1268 hw->nvm.ops.read(hw, NVM_COMB_VER_OFF + comb_offset + 1,
1270 hw->nvm.ops.read(hw, NVM_COMB_VER_OFF + comb_offset,
1273 /* get Option Rom version if it exists and is valid */
1274 if (comb_verh && comb_verl &&
1275 comb_verh != NVM_VER_INVALID &&
1276 comb_verl != NVM_VER_INVALID) {
1277 fw_vers->or_valid = true;
1278 fw_vers->or_major = comb_verl >>
1280 fw_vers->or_build = (comb_verl <<
1281 NVM_COMB_VER_SHFT) |
1284 fw_vers->or_patch = comb_verh &
1290 hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
1293 hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
1294 fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
1297 /* check for old style version format in newer images*/
1298 if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
1299 eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
1301 eeprom_verl = (fw_version & NVM_MINOR_MASK)
1304 /* Convert minor value to hex before assigning to output struct
1305 * Val to be converted will not be higher than 99, per tool output
1307 q = eeprom_verl / NVM_HEX_CONV;
1308 hval = q * NVM_HEX_TENS;
1309 rem = eeprom_verl % NVM_HEX_CONV;
1310 result = hval + rem;
1311 fw_vers->eep_minor = result;
1313 if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
1314 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
1315 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
1316 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
1318 } else if ((etrack_test & NVM_ETRACK_VALID) == 0) {
1319 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);
1320 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);
1321 fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |