1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2001-2020 Intel Corporation
7 static s32 igc_wait_autoneg(struct igc_hw *hw);
8 static s32 igc_access_phy_wakeup_reg_bm(struct igc_hw *hw, u32 offset,
9 u16 *data, bool read, bool page_set);
10 static u32 igc_get_phy_addr_for_hv_page(u32 page);
11 static s32 igc_access_phy_debug_regs_hv(struct igc_hw *hw, u32 offset,
12 u16 *data, bool read);
14 /* Cable length tables */
15 static const u16 igc_m88_cable_length_table[] = {
16 0, 50, 80, 110, 140, 140, IGC_CABLE_LENGTH_UNDEFINED };
17 #define M88IGC_CABLE_LENGTH_TABLE_SIZE \
18 (sizeof(igc_m88_cable_length_table) / \
19 sizeof(igc_m88_cable_length_table[0]))
21 static const u16 igc_igp_2_cable_length_table[] = {
22 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
23 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
24 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
25 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
26 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
27 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
28 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
30 #define IGP02IGC_CABLE_LENGTH_TABLE_SIZE \
31 (sizeof(igc_igp_2_cable_length_table) / \
32 sizeof(igc_igp_2_cable_length_table[0]))
35 * igc_init_phy_ops_generic - Initialize PHY function pointers
36 * @hw: pointer to the HW structure
38 * Setups up the function pointers to no-op functions
40 void igc_init_phy_ops_generic(struct igc_hw *hw)
42 struct igc_phy_info *phy = &hw->phy;
43 DEBUGFUNC("igc_init_phy_ops_generic");
45 /* Initialize function pointers */
46 phy->ops.init_params = igc_null_ops_generic;
47 phy->ops.acquire = igc_null_ops_generic;
48 phy->ops.check_polarity = igc_null_ops_generic;
49 phy->ops.check_reset_block = igc_null_ops_generic;
50 phy->ops.commit = igc_null_ops_generic;
51 phy->ops.force_speed_duplex = igc_null_ops_generic;
52 phy->ops.get_cfg_done = igc_null_ops_generic;
53 phy->ops.get_cable_length = igc_null_ops_generic;
54 phy->ops.get_info = igc_null_ops_generic;
55 phy->ops.set_page = igc_null_set_page;
56 phy->ops.read_reg = igc_null_read_reg;
57 phy->ops.read_reg_locked = igc_null_read_reg;
58 phy->ops.read_reg_page = igc_null_read_reg;
59 phy->ops.release = igc_null_phy_generic;
60 phy->ops.reset = igc_null_ops_generic;
61 phy->ops.set_d0_lplu_state = igc_null_lplu_state;
62 phy->ops.set_d3_lplu_state = igc_null_lplu_state;
63 phy->ops.write_reg = igc_null_write_reg;
64 phy->ops.write_reg_locked = igc_null_write_reg;
65 phy->ops.write_reg_page = igc_null_write_reg;
66 phy->ops.power_up = igc_null_phy_generic;
67 phy->ops.power_down = igc_null_phy_generic;
68 phy->ops.read_i2c_byte = igc_read_i2c_byte_null;
69 phy->ops.write_i2c_byte = igc_write_i2c_byte_null;
70 phy->ops.cfg_on_link_up = igc_null_ops_generic;
74 * igc_null_set_page - No-op function, return 0
75 * @hw: pointer to the HW structure
76 * @data: dummy variable
78 s32 igc_null_set_page(struct igc_hw IGC_UNUSEDARG * hw,
79 u16 IGC_UNUSEDARG data)
81 DEBUGFUNC("igc_null_set_page");
82 UNREFERENCED_2PARAMETER(hw, data);
87 * igc_null_read_reg - No-op function, return 0
88 * @hw: pointer to the HW structure
89 * @offset: dummy variable
90 * @data: dummy variable
92 s32 igc_null_read_reg(struct igc_hw IGC_UNUSEDARG * hw,
93 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG * data)
95 DEBUGFUNC("igc_null_read_reg");
96 UNREFERENCED_3PARAMETER(hw, offset, data);
101 * igc_null_phy_generic - No-op function, return void
102 * @hw: pointer to the HW structure
104 void igc_null_phy_generic(struct igc_hw IGC_UNUSEDARG * hw)
106 DEBUGFUNC("igc_null_phy_generic");
107 UNREFERENCED_1PARAMETER(hw);
111 * igc_null_lplu_state - No-op function, return 0
112 * @hw: pointer to the HW structure
113 * @active: dummy variable
115 s32 igc_null_lplu_state(struct igc_hw IGC_UNUSEDARG * hw,
116 bool IGC_UNUSEDARG active)
118 DEBUGFUNC("igc_null_lplu_state");
119 UNREFERENCED_2PARAMETER(hw, active);
124 * igc_null_write_reg - No-op function, return 0
125 * @hw: pointer to the HW structure
126 * @offset: dummy variable
127 * @data: dummy variable
129 s32 igc_null_write_reg(struct igc_hw IGC_UNUSEDARG * hw,
130 u32 IGC_UNUSEDARG offset, u16 IGC_UNUSEDARG data)
132 DEBUGFUNC("igc_null_write_reg");
133 UNREFERENCED_3PARAMETER(hw, offset, data);
138 * igc_read_i2c_byte_null - No-op function, return 0
139 * @hw: pointer to hardware structure
140 * @byte_offset: byte offset to write
141 * @dev_addr: device address
142 * @data: data value read
145 s32 igc_read_i2c_byte_null(struct igc_hw IGC_UNUSEDARG * hw,
146 u8 IGC_UNUSEDARG byte_offset,
147 u8 IGC_UNUSEDARG dev_addr,
148 u8 IGC_UNUSEDARG * data)
150 DEBUGFUNC("igc_read_i2c_byte_null");
151 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
156 * igc_write_i2c_byte_null - No-op function, return 0
157 * @hw: pointer to hardware structure
158 * @byte_offset: byte offset to write
159 * @dev_addr: device address
160 * @data: data value to write
163 s32 igc_write_i2c_byte_null(struct igc_hw IGC_UNUSEDARG * hw,
164 u8 IGC_UNUSEDARG byte_offset,
165 u8 IGC_UNUSEDARG dev_addr,
166 u8 IGC_UNUSEDARG data)
168 DEBUGFUNC("igc_write_i2c_byte_null");
169 UNREFERENCED_4PARAMETER(hw, byte_offset, dev_addr, data);
174 * igc_check_reset_block_generic - Check if PHY reset is blocked
175 * @hw: pointer to the HW structure
177 * Read the PHY management control register and check whether a PHY reset
178 * is blocked. If a reset is not blocked return IGC_SUCCESS, otherwise
179 * return IGC_BLK_PHY_RESET (12).
181 s32 igc_check_reset_block_generic(struct igc_hw *hw)
185 DEBUGFUNC("igc_check_reset_block");
187 manc = IGC_READ_REG(hw, IGC_MANC);
189 return (manc & IGC_MANC_BLK_PHY_RST_ON_IDE) ?
190 IGC_BLK_PHY_RESET : IGC_SUCCESS;
194 * igc_get_phy_id - Retrieve the PHY ID and revision
195 * @hw: pointer to the HW structure
197 * Reads the PHY registers and stores the PHY ID and possibly the PHY
198 * revision in the hardware structure.
200 s32 igc_get_phy_id(struct igc_hw *hw)
202 struct igc_phy_info *phy = &hw->phy;
203 s32 ret_val = IGC_SUCCESS;
207 DEBUGFUNC("igc_get_phy_id");
209 if (!phy->ops.read_reg)
212 while (retry_count < 2) {
213 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
217 phy->id = (u32)(phy_id << 16);
219 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
223 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
224 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
226 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
236 * igc_phy_reset_dsp_generic - Reset PHY DSP
237 * @hw: pointer to the HW structure
239 * Reset the digital signal processor.
241 s32 igc_phy_reset_dsp_generic(struct igc_hw *hw)
245 DEBUGFUNC("igc_phy_reset_dsp_generic");
247 if (!hw->phy.ops.write_reg)
250 ret_val = hw->phy.ops.write_reg(hw, M88IGC_PHY_GEN_CONTROL, 0xC1);
254 return hw->phy.ops.write_reg(hw, M88IGC_PHY_GEN_CONTROL, 0);
258 * igc_read_phy_reg_mdic - Read MDI control register
259 * @hw: pointer to the HW structure
260 * @offset: register offset to be read
261 * @data: pointer to the read data
263 * Reads the MDI control register in the PHY at offset and stores the
264 * information read to data.
266 s32 igc_read_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 *data)
268 struct igc_phy_info *phy = &hw->phy;
271 DEBUGFUNC("igc_read_phy_reg_mdic");
273 if (offset > MAX_PHY_REG_ADDRESS) {
274 DEBUGOUT1("PHY Address %d is out of range\n", offset);
275 return -IGC_ERR_PARAM;
278 /* Set up Op-code, Phy Address, and register offset in the MDI
279 * Control register. The MAC will take care of interfacing with the
280 * PHY to retrieve the desired data.
282 mdic = ((offset << IGC_MDIC_REG_SHIFT) |
283 (phy->addr << IGC_MDIC_PHY_SHIFT) |
286 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
288 /* Poll the ready bit to see if the MDI read completed
289 * Increasing the time out as testing showed failures with
292 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
294 mdic = IGC_READ_REG(hw, IGC_MDIC);
295 if (mdic & IGC_MDIC_READY)
298 if (!(mdic & IGC_MDIC_READY)) {
299 DEBUGOUT("MDI Read did not complete\n");
302 if (mdic & IGC_MDIC_ERROR) {
303 DEBUGOUT("MDI Error\n");
306 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
307 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n",
309 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
314 /* Allow some time after each MDIC transaction to avoid
315 * reading duplicate data in the next MDIC transaction.
317 if (hw->mac.type == igc_pch2lan)
324 * igc_write_phy_reg_mdic - Write MDI control register
325 * @hw: pointer to the HW structure
326 * @offset: register offset to write to
327 * @data: data to write to register at offset
329 * Writes data to MDI control register in the PHY at offset.
331 s32 igc_write_phy_reg_mdic(struct igc_hw *hw, u32 offset, u16 data)
333 struct igc_phy_info *phy = &hw->phy;
336 DEBUGFUNC("igc_write_phy_reg_mdic");
338 if (offset > MAX_PHY_REG_ADDRESS) {
339 DEBUGOUT1("PHY Address %d is out of range\n", offset);
340 return -IGC_ERR_PARAM;
343 /* Set up Op-code, Phy Address, and register offset in the MDI
344 * Control register. The MAC will take care of interfacing with the
345 * PHY to retrieve the desired data.
347 mdic = (((u32)data) |
348 (offset << IGC_MDIC_REG_SHIFT) |
349 (phy->addr << IGC_MDIC_PHY_SHIFT) |
350 (IGC_MDIC_OP_WRITE));
352 IGC_WRITE_REG(hw, IGC_MDIC, mdic);
354 /* Poll the ready bit to see if the MDI read completed
355 * Increasing the time out as testing showed failures with
358 for (i = 0; i < (IGC_GEN_POLL_TIMEOUT * 3); i++) {
360 mdic = IGC_READ_REG(hw, IGC_MDIC);
361 if (mdic & IGC_MDIC_READY)
364 if (!(mdic & IGC_MDIC_READY)) {
365 DEBUGOUT("MDI Write did not complete\n");
368 if (mdic & IGC_MDIC_ERROR) {
369 DEBUGOUT("MDI Error\n");
372 if (((mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT) != offset) {
373 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n",
375 (mdic & IGC_MDIC_REG_MASK) >> IGC_MDIC_REG_SHIFT);
379 /* Allow some time after each MDIC transaction to avoid
380 * reading duplicate data in the next MDIC transaction.
382 if (hw->mac.type == igc_pch2lan)
389 * igc_read_phy_reg_i2c - Read PHY register using i2c
390 * @hw: pointer to the HW structure
391 * @offset: register offset to be read
392 * @data: pointer to the read data
394 * Reads the PHY register at offset using the i2c interface and stores the
395 * retrieved information in data.
397 s32 igc_read_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 *data)
399 struct igc_phy_info *phy = &hw->phy;
402 DEBUGFUNC("igc_read_phy_reg_i2c");
404 /* Set up Op-code, Phy Address, and register address in the I2CCMD
405 * register. The MAC will take care of interfacing with the
406 * PHY to retrieve the desired data.
408 i2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |
409 (phy->addr << IGC_I2CCMD_PHY_ADDR_SHIFT) |
410 (IGC_I2CCMD_OPCODE_READ));
412 IGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);
414 /* Poll the ready bit to see if the I2C read completed */
415 for (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {
417 i2ccmd = IGC_READ_REG(hw, IGC_I2CCMD);
418 if (i2ccmd & IGC_I2CCMD_READY)
421 if (!(i2ccmd & IGC_I2CCMD_READY)) {
422 DEBUGOUT("I2CCMD Read did not complete\n");
425 if (i2ccmd & IGC_I2CCMD_ERROR) {
426 DEBUGOUT("I2CCMD Error bit set\n");
430 /* Need to byte-swap the 16-bit value. */
431 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
437 * igc_write_phy_reg_i2c - Write PHY register using i2c
438 * @hw: pointer to the HW structure
439 * @offset: register offset to write to
440 * @data: data to write at register offset
442 * Writes the data to PHY register at the offset using the i2c interface.
444 s32 igc_write_phy_reg_i2c(struct igc_hw *hw, u32 offset, u16 data)
446 struct igc_phy_info *phy = &hw->phy;
448 u16 phy_data_swapped;
450 DEBUGFUNC("igc_write_phy_reg_i2c");
452 /* Prevent overwriting SFP I2C EEPROM which is at A0 address. */
453 if (hw->phy.addr == 0 || hw->phy.addr > 7) {
454 DEBUGOUT1("PHY I2C Address %d is out of range.\n",
456 return -IGC_ERR_CONFIG;
459 /* Swap the data bytes for the I2C interface */
460 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
462 /* Set up Op-code, Phy Address, and register address in the I2CCMD
463 * register. The MAC will take care of interfacing with the
464 * PHY to retrieve the desired data.
466 i2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |
467 (phy->addr << IGC_I2CCMD_PHY_ADDR_SHIFT) |
468 IGC_I2CCMD_OPCODE_WRITE |
471 IGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);
473 /* Poll the ready bit to see if the I2C read completed */
474 for (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {
476 i2ccmd = IGC_READ_REG(hw, IGC_I2CCMD);
477 if (i2ccmd & IGC_I2CCMD_READY)
480 if (!(i2ccmd & IGC_I2CCMD_READY)) {
481 DEBUGOUT("I2CCMD Write did not complete\n");
484 if (i2ccmd & IGC_I2CCMD_ERROR) {
485 DEBUGOUT("I2CCMD Error bit set\n");
493 * igc_read_sfp_data_byte - Reads SFP module data.
494 * @hw: pointer to the HW structure
495 * @offset: byte location offset to be read
496 * @data: read data buffer pointer
498 * Reads one byte from SFP module data stored
499 * in SFP resided EEPROM memory or SFP diagnostic area.
500 * Function should be called with
501 * IGC_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
502 * IGC_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
505 s32 igc_read_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 *data)
511 DEBUGFUNC("igc_read_sfp_data_byte");
513 if (offset > IGC_I2CCMD_SFP_DIAG_ADDR(255)) {
514 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
518 /* Set up Op-code, EEPROM Address,in the I2CCMD
519 * register. The MAC will take care of interfacing with the
520 * EEPROM to retrieve the desired data.
522 i2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |
523 IGC_I2CCMD_OPCODE_READ);
525 IGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);
527 /* Poll the ready bit to see if the I2C read completed */
528 for (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {
530 data_local = IGC_READ_REG(hw, IGC_I2CCMD);
531 if (data_local & IGC_I2CCMD_READY)
534 if (!(data_local & IGC_I2CCMD_READY)) {
535 DEBUGOUT("I2CCMD Read did not complete\n");
538 if (data_local & IGC_I2CCMD_ERROR) {
539 DEBUGOUT("I2CCMD Error bit set\n");
542 *data = (u8)data_local & 0xFF;
548 * igc_write_sfp_data_byte - Writes SFP module data.
549 * @hw: pointer to the HW structure
550 * @offset: byte location offset to write to
551 * @data: data to write
553 * Writes one byte to SFP module data stored
554 * in SFP resided EEPROM memory or SFP diagnostic area.
555 * Function should be called with
556 * IGC_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access
557 * IGC_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters
560 s32 igc_write_sfp_data_byte(struct igc_hw *hw, u16 offset, u8 data)
566 DEBUGFUNC("igc_write_sfp_data_byte");
568 if (offset > IGC_I2CCMD_SFP_DIAG_ADDR(255)) {
569 DEBUGOUT("I2CCMD command address exceeds upper limit\n");
572 /* The programming interface is 16 bits wide
573 * so we need to read the whole word first
574 * then update appropriate byte lane and write
575 * the updated word back.
577 /* Set up Op-code, EEPROM Address,in the I2CCMD
578 * register. The MAC will take care of interfacing
579 * with an EEPROM to write the data given.
581 i2ccmd = ((offset << IGC_I2CCMD_REG_ADDR_SHIFT) |
582 IGC_I2CCMD_OPCODE_READ);
583 /* Set a command to read single word */
584 IGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);
585 for (i = 0; i < IGC_I2CCMD_PHY_TIMEOUT; i++) {
587 /* Poll the ready bit to see if lastly
588 * launched I2C operation completed
590 i2ccmd = IGC_READ_REG(hw, IGC_I2CCMD);
591 if (i2ccmd & IGC_I2CCMD_READY) {
592 /* Check if this is READ or WRITE phase */
593 if ((i2ccmd & IGC_I2CCMD_OPCODE_READ) ==
594 IGC_I2CCMD_OPCODE_READ) {
595 /* Write the selected byte
596 * lane and update whole word
598 data_local = i2ccmd & 0xFF00;
599 data_local |= (u32)data;
601 IGC_I2CCMD_REG_ADDR_SHIFT) |
602 IGC_I2CCMD_OPCODE_WRITE | data_local);
603 IGC_WRITE_REG(hw, IGC_I2CCMD, i2ccmd);
609 if (!(i2ccmd & IGC_I2CCMD_READY)) {
610 DEBUGOUT("I2CCMD Write did not complete\n");
613 if (i2ccmd & IGC_I2CCMD_ERROR) {
614 DEBUGOUT("I2CCMD Error bit set\n");
621 * igc_read_phy_reg_m88 - Read m88 PHY register
622 * @hw: pointer to the HW structure
623 * @offset: register offset to be read
624 * @data: pointer to the read data
626 * Acquires semaphore, if necessary, then reads the PHY register at offset
627 * and storing the retrieved information in data. Release any acquired
628 * semaphores before exiting.
630 s32 igc_read_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 *data)
634 DEBUGFUNC("igc_read_phy_reg_m88");
636 if (!hw->phy.ops.acquire)
639 ret_val = hw->phy.ops.acquire(hw);
643 ret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
646 hw->phy.ops.release(hw);
652 * igc_write_phy_reg_m88 - Write m88 PHY register
653 * @hw: pointer to the HW structure
654 * @offset: register offset to write to
655 * @data: data to write at register offset
657 * Acquires semaphore, if necessary, then writes the data to PHY register
658 * at the offset. Release any acquired semaphores before exiting.
660 s32 igc_write_phy_reg_m88(struct igc_hw *hw, u32 offset, u16 data)
664 DEBUGFUNC("igc_write_phy_reg_m88");
666 if (!hw->phy.ops.acquire)
669 ret_val = hw->phy.ops.acquire(hw);
673 ret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
676 hw->phy.ops.release(hw);
682 * igc_set_page_igp - Set page as on IGP-like PHY(s)
683 * @hw: pointer to the HW structure
684 * @page: page to set (shifted left when necessary)
686 * Sets PHY page required for PHY register access. Assumes semaphore is
687 * already acquired. Note, this function sets phy.addr to 1 so the caller
688 * must set it appropriately (if necessary) after this function returns.
690 s32 igc_set_page_igp(struct igc_hw *hw, u16 page)
692 DEBUGFUNC("igc_set_page_igp");
694 DEBUGOUT1("Setting page 0x%x\n", page);
698 return igc_write_phy_reg_mdic(hw, IGP01IGC_PHY_PAGE_SELECT, page);
702 * __igc_read_phy_reg_igp - Read igp PHY register
703 * @hw: pointer to the HW structure
704 * @offset: register offset to be read
705 * @data: pointer to the read data
706 * @locked: semaphore has already been acquired or not
708 * Acquires semaphore, if necessary, then reads the PHY register at offset
709 * and stores the retrieved information in data. Release any acquired
710 * semaphores before exiting.
712 static s32 __igc_read_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 *data,
715 s32 ret_val = IGC_SUCCESS;
717 DEBUGFUNC("__igc_read_phy_reg_igp");
720 if (!hw->phy.ops.acquire)
723 ret_val = hw->phy.ops.acquire(hw);
728 if (offset > MAX_PHY_MULTI_PAGE_REG)
729 ret_val = igc_write_phy_reg_mdic(hw,
730 IGP01IGC_PHY_PAGE_SELECT,
733 ret_val = igc_read_phy_reg_mdic(hw,
734 MAX_PHY_REG_ADDRESS & offset,
737 hw->phy.ops.release(hw);
743 * igc_read_phy_reg_igp - Read igp PHY register
744 * @hw: pointer to the HW structure
745 * @offset: register offset to be read
746 * @data: pointer to the read data
748 * Acquires semaphore then reads the PHY register at offset and stores the
749 * retrieved information in data.
750 * Release the acquired semaphore before exiting.
752 s32 igc_read_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 *data)
754 return __igc_read_phy_reg_igp(hw, offset, data, false);
758 * igc_read_phy_reg_igp_locked - Read igp PHY register
759 * @hw: pointer to the HW structure
760 * @offset: register offset to be read
761 * @data: pointer to the read data
763 * Reads the PHY register at offset and stores the retrieved information
764 * in data. Assumes semaphore already acquired.
766 s32 igc_read_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 *data)
768 return __igc_read_phy_reg_igp(hw, offset, data, true);
772 * igc_write_phy_reg_igp - Write igp PHY register
773 * @hw: pointer to the HW structure
774 * @offset: register offset to write to
775 * @data: data to write at register offset
776 * @locked: semaphore has already been acquired or not
778 * Acquires semaphore, if necessary, then writes the data to PHY register
779 * at the offset. Release any acquired semaphores before exiting.
781 static s32 __igc_write_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 data,
784 s32 ret_val = IGC_SUCCESS;
786 DEBUGFUNC("igc_write_phy_reg_igp");
789 if (!hw->phy.ops.acquire)
792 ret_val = hw->phy.ops.acquire(hw);
797 if (offset > MAX_PHY_MULTI_PAGE_REG)
798 ret_val = igc_write_phy_reg_mdic(hw,
799 IGP01IGC_PHY_PAGE_SELECT,
802 ret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS &
806 hw->phy.ops.release(hw);
812 * igc_write_phy_reg_igp - Write igp PHY register
813 * @hw: pointer to the HW structure
814 * @offset: register offset to write to
815 * @data: data to write at register offset
817 * Acquires semaphore then writes the data to PHY register
818 * at the offset. Release any acquired semaphores before exiting.
820 s32 igc_write_phy_reg_igp(struct igc_hw *hw, u32 offset, u16 data)
822 return __igc_write_phy_reg_igp(hw, offset, data, false);
826 * igc_write_phy_reg_igp_locked - Write igp PHY register
827 * @hw: pointer to the HW structure
828 * @offset: register offset to write to
829 * @data: data to write at register offset
831 * Writes the data to PHY register at the offset.
832 * Assumes semaphore already acquired.
834 s32 igc_write_phy_reg_igp_locked(struct igc_hw *hw, u32 offset, u16 data)
836 return __igc_write_phy_reg_igp(hw, offset, data, true);
840 * __igc_read_kmrn_reg - Read kumeran register
841 * @hw: pointer to the HW structure
842 * @offset: register offset to be read
843 * @data: pointer to the read data
844 * @locked: semaphore has already been acquired or not
846 * Acquires semaphore, if necessary. Then reads the PHY register at offset
847 * using the kumeran interface. The information retrieved is stored in data.
848 * Release any acquired semaphores before exiting.
850 static s32 __igc_read_kmrn_reg(struct igc_hw *hw, u32 offset, u16 *data,
855 DEBUGFUNC("__igc_read_kmrn_reg");
858 s32 ret_val = IGC_SUCCESS;
860 if (!hw->phy.ops.acquire)
863 ret_val = hw->phy.ops.acquire(hw);
868 kmrnctrlsta = ((offset << IGC_KMRNCTRLSTA_OFFSET_SHIFT) &
869 IGC_KMRNCTRLSTA_OFFSET) | IGC_KMRNCTRLSTA_REN;
870 IGC_WRITE_REG(hw, IGC_KMRNCTRLSTA, kmrnctrlsta);
875 kmrnctrlsta = IGC_READ_REG(hw, IGC_KMRNCTRLSTA);
876 *data = (u16)kmrnctrlsta;
879 hw->phy.ops.release(hw);
885 * igc_read_kmrn_reg_generic - Read kumeran register
886 * @hw: pointer to the HW structure
887 * @offset: register offset to be read
888 * @data: pointer to the read data
890 * Acquires semaphore then reads the PHY register at offset using the
891 * kumeran interface. The information retrieved is stored in data.
892 * Release the acquired semaphore before exiting.
894 s32 igc_read_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 *data)
896 return __igc_read_kmrn_reg(hw, offset, data, false);
900 * igc_read_kmrn_reg_locked - Read kumeran register
901 * @hw: pointer to the HW structure
902 * @offset: register offset to be read
903 * @data: pointer to the read data
905 * Reads the PHY register at offset using the kumeran interface. The
906 * information retrieved is stored in data.
907 * Assumes semaphore already acquired.
909 s32 igc_read_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 *data)
911 return __igc_read_kmrn_reg(hw, offset, data, true);
915 * __igc_write_kmrn_reg - Write kumeran register
916 * @hw: pointer to the HW structure
917 * @offset: register offset to write to
918 * @data: data to write at register offset
919 * @locked: semaphore has already been acquired or not
921 * Acquires semaphore, if necessary. Then write the data to PHY register
922 * at the offset using the kumeran interface. Release any acquired semaphores
925 static s32 __igc_write_kmrn_reg(struct igc_hw *hw, u32 offset, u16 data,
930 DEBUGFUNC("igc_write_kmrn_reg_generic");
933 s32 ret_val = IGC_SUCCESS;
935 if (!hw->phy.ops.acquire)
938 ret_val = hw->phy.ops.acquire(hw);
943 kmrnctrlsta = ((offset << IGC_KMRNCTRLSTA_OFFSET_SHIFT) &
944 IGC_KMRNCTRLSTA_OFFSET) | data;
945 IGC_WRITE_REG(hw, IGC_KMRNCTRLSTA, kmrnctrlsta);
951 hw->phy.ops.release(hw);
957 * igc_write_kmrn_reg_generic - Write kumeran register
958 * @hw: pointer to the HW structure
959 * @offset: register offset to write to
960 * @data: data to write at register offset
962 * Acquires semaphore then writes the data to the PHY register at the offset
963 * using the kumeran interface. Release the acquired semaphore before exiting.
965 s32 igc_write_kmrn_reg_generic(struct igc_hw *hw, u32 offset, u16 data)
967 return __igc_write_kmrn_reg(hw, offset, data, false);
971 * igc_write_kmrn_reg_locked - Write kumeran register
972 * @hw: pointer to the HW structure
973 * @offset: register offset to write to
974 * @data: data to write at register offset
976 * Write the data to PHY register at the offset using the kumeran interface.
977 * Assumes semaphore already acquired.
979 s32 igc_write_kmrn_reg_locked(struct igc_hw *hw, u32 offset, u16 data)
981 return __igc_write_kmrn_reg(hw, offset, data, true);
985 * igc_set_master_slave_mode - Setup PHY for Master/slave mode
986 * @hw: pointer to the HW structure
988 * Sets up Master/slave mode
990 static s32 igc_set_master_slave_mode(struct igc_hw *hw)
995 /* Resolve Master/Slave mode */
996 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
1000 /* load defaults for future use */
1001 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
1002 ((phy_data & CR_1000T_MS_VALUE) ?
1003 igc_ms_force_master :
1004 igc_ms_force_slave) : igc_ms_auto;
1006 switch (hw->phy.ms_type) {
1007 case igc_ms_force_master:
1008 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1010 case igc_ms_force_slave:
1011 phy_data |= CR_1000T_MS_ENABLE;
1012 phy_data &= ~(CR_1000T_MS_VALUE);
1015 phy_data &= ~CR_1000T_MS_ENABLE;
1021 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
1025 * igc_copper_link_setup_82577 - Setup 82577 PHY for copper link
1026 * @hw: pointer to the HW structure
1028 * Sets up Carrier-sense on Transmit and downshift values.
1030 s32 igc_copper_link_setup_82577(struct igc_hw *hw)
1035 DEBUGFUNC("igc_copper_link_setup_82577");
1037 if (hw->phy.type == igc_phy_82580) {
1038 ret_val = hw->phy.ops.reset(hw);
1040 DEBUGOUT("Error resetting the PHY.\n");
1045 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1046 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
1050 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
1052 /* Enable downshift */
1053 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
1055 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
1059 /* Set MDI/MDIX mode */
1060 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data);
1063 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK;
1065 * 0 - Auto (default)
1069 switch (hw->phy.mdix) {
1073 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX;
1077 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX;
1080 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data);
1084 return igc_set_master_slave_mode(hw);
1088 * igc_copper_link_setup_m88 - Setup m88 PHY's for copper link
1089 * @hw: pointer to the HW structure
1091 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
1092 * and downshift values are set also.
1094 s32 igc_copper_link_setup_m88(struct igc_hw *hw)
1096 struct igc_phy_info *phy = &hw->phy;
1100 DEBUGFUNC("igc_copper_link_setup_m88");
1103 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1104 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);
1108 /* For BM PHY this bit is downshift enable */
1109 if (phy->type != igc_phy_bm)
1110 phy_data |= M88IGC_PSCR_ASSERT_CRS_ON_TX;
1113 * MDI/MDI-X = 0 (default)
1114 * 0 - Auto for all speeds
1117 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1119 phy_data &= ~M88IGC_PSCR_AUTO_X_MODE;
1121 switch (phy->mdix) {
1123 phy_data |= M88IGC_PSCR_MDI_MANUAL_MODE;
1126 phy_data |= M88IGC_PSCR_MDIX_MANUAL_MODE;
1129 phy_data |= M88IGC_PSCR_AUTO_X_1000T;
1133 phy_data |= M88IGC_PSCR_AUTO_X_MODE;
1138 * disable_polarity_correction = 0 (default)
1139 * Automatic Correction for Reversed Cable Polarity
1143 phy_data &= ~M88IGC_PSCR_POLARITY_REVERSAL;
1144 if (phy->disable_polarity_correction)
1145 phy_data |= M88IGC_PSCR_POLARITY_REVERSAL;
1147 /* Enable downshift on BM (disabled by default) */
1148 if (phy->type == igc_phy_bm) {
1149 /* For 82574/82583, first disable then enable downshift */
1150 if (phy->id == BMIGC_E_PHY_ID_R2) {
1151 phy_data &= ~BMIGC_PSCR_ENABLE_DOWNSHIFT;
1152 ret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL,
1156 /* Commit the changes. */
1157 ret_val = phy->ops.commit(hw);
1159 DEBUGOUT("Error committing the PHY changes\n");
1164 phy_data |= BMIGC_PSCR_ENABLE_DOWNSHIFT;
1167 ret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);
1171 if (phy->type == igc_phy_m88 && phy->revision < IGC_REVISION_4 &&
1172 phy->id != BMIGC_E_PHY_ID_R2) {
1173 /* Force TX_CLK in the Extended PHY Specific Control Register
1176 ret_val = phy->ops.read_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,
1181 phy_data |= M88IGC_EPSCR_TX_CLK_25;
1183 if (phy->revision == IGC_REVISION_2 &&
1184 phy->id == M88E1111_I_PHY_ID) {
1185 /* 82573L PHY - set the downshift counter to 5x. */
1186 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
1187 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1189 /* Configure Master and Slave downshift values */
1190 phy_data &= ~(M88IGC_EPSCR_MASTER_DOWNSHIFT_MASK |
1191 M88IGC_EPSCR_SLAVE_DOWNSHIFT_MASK);
1192 phy_data |= (M88IGC_EPSCR_MASTER_DOWNSHIFT_1X |
1193 M88IGC_EPSCR_SLAVE_DOWNSHIFT_1X);
1195 ret_val = phy->ops.write_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,
1201 if (phy->type == igc_phy_bm && phy->id == BMIGC_E_PHY_ID_R2) {
1202 /* Set PHY page 0, register 29 to 0x0003 */
1203 ret_val = phy->ops.write_reg(hw, 29, 0x0003);
1207 /* Set PHY page 0, register 30 to 0x0000 */
1208 ret_val = phy->ops.write_reg(hw, 30, 0x0000);
1213 /* Commit the changes. */
1214 ret_val = phy->ops.commit(hw);
1216 DEBUGOUT("Error committing the PHY changes\n");
1220 if (phy->type == igc_phy_82578) {
1221 ret_val = phy->ops.read_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,
1226 /* 82578 PHY - set the downshift count to 1x. */
1227 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
1228 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
1229 ret_val = phy->ops.write_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL,
1239 * igc_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
1240 * @hw: pointer to the HW structure
1242 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
1243 * Also enables and sets the downshift parameters.
1245 s32 igc_copper_link_setup_m88_gen2(struct igc_hw *hw)
1247 struct igc_phy_info *phy = &hw->phy;
1251 DEBUGFUNC("igc_copper_link_setup_m88_gen2");
1254 /* Enable CRS on Tx. This must be set for half-duplex operation. */
1255 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);
1260 * MDI/MDI-X = 0 (default)
1261 * 0 - Auto for all speeds
1264 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1266 phy_data &= ~M88IGC_PSCR_AUTO_X_MODE;
1268 switch (phy->mdix) {
1270 phy_data |= M88IGC_PSCR_MDI_MANUAL_MODE;
1273 phy_data |= M88IGC_PSCR_MDIX_MANUAL_MODE;
1276 /* M88E1112 does not support this mode) */
1277 if (phy->id != M88E1112_E_PHY_ID) {
1278 phy_data |= M88IGC_PSCR_AUTO_X_1000T;
1284 phy_data |= M88IGC_PSCR_AUTO_X_MODE;
1289 * disable_polarity_correction = 0 (default)
1290 * Automatic Correction for Reversed Cable Polarity
1294 phy_data &= ~M88IGC_PSCR_POLARITY_REVERSAL;
1295 if (phy->disable_polarity_correction)
1296 phy_data |= M88IGC_PSCR_POLARITY_REVERSAL;
1298 /* Enable downshift and setting it to X6 */
1299 if (phy->id == M88E1543_E_PHY_ID) {
1300 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE;
1302 phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);
1306 ret_val = phy->ops.commit(hw);
1308 DEBUGOUT("Error committing the PHY changes\n");
1313 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1314 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1315 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1317 ret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);
1321 /* Commit the changes. */
1322 ret_val = phy->ops.commit(hw);
1324 DEBUGOUT("Error committing the PHY changes\n");
1328 ret_val = igc_set_master_slave_mode(hw);
1336 * igc_copper_link_setup_igp - Setup igp PHY's for copper link
1337 * @hw: pointer to the HW structure
1339 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1342 s32 igc_copper_link_setup_igp(struct igc_hw *hw)
1344 struct igc_phy_info *phy = &hw->phy;
1348 DEBUGFUNC("igc_copper_link_setup_igp");
1351 ret_val = hw->phy.ops.reset(hw);
1353 DEBUGOUT("Error resetting the PHY.\n");
1357 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1358 * timeout issues when LFS is enabled.
1362 /* The NVM settings will configure LPLU in D3 for
1365 if (phy->type == igc_phy_igp) {
1366 /* disable lplu d3 during driver init */
1367 ret_val = hw->phy.ops.set_d3_lplu_state(hw, false);
1369 DEBUGOUT("Error Disabling LPLU D3\n");
1374 /* disable lplu d0 during driver init */
1375 if (hw->phy.ops.set_d0_lplu_state) {
1376 ret_val = hw->phy.ops.set_d0_lplu_state(hw, false);
1378 DEBUGOUT("Error Disabling LPLU D0\n");
1382 /* Configure mdi-mdix settings */
1383 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CTRL, &data);
1387 data &= ~IGP01IGC_PSCR_AUTO_MDIX;
1389 switch (phy->mdix) {
1391 data &= ~IGP01IGC_PSCR_FORCE_MDI_MDIX;
1394 data |= IGP01IGC_PSCR_FORCE_MDI_MDIX;
1398 data |= IGP01IGC_PSCR_AUTO_MDIX;
1401 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CTRL, data);
1405 /* set auto-master slave resolution settings */
1406 if (hw->mac.autoneg) {
1407 /* when autonegotiation advertisement is only 1000Mbps then we
1408 * should disable SmartSpeed and enable Auto MasterSlave
1409 * resolution as hardware default.
1411 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1412 /* Disable SmartSpeed */
1413 ret_val = phy->ops.read_reg(hw,
1414 IGP01IGC_PHY_PORT_CONFIG,
1419 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
1420 ret_val = phy->ops.write_reg(hw,
1421 IGP01IGC_PHY_PORT_CONFIG,
1426 /* Set auto Master/Slave resolution process */
1427 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1431 data &= ~CR_1000T_MS_ENABLE;
1432 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1437 ret_val = igc_set_master_slave_mode(hw);
1444 * igc_phy_setup_autoneg - Configure PHY for auto-negotiation
1445 * @hw: pointer to the HW structure
1447 * Reads the MII auto-neg advertisement register and/or the 1000T control
1448 * register and if the PHY is already setup for auto-negotiation, then
1449 * return successful. Otherwise, setup advertisement and flow control to
1450 * the appropriate values for the wanted auto-negotiation.
1452 s32 igc_phy_setup_autoneg(struct igc_hw *hw)
1454 struct igc_phy_info *phy = &hw->phy;
1456 u16 mii_autoneg_adv_reg;
1457 u16 mii_1000t_ctrl_reg = 0;
1458 u16 aneg_multigbt_an_ctrl = 0;
1460 DEBUGFUNC("igc_phy_setup_autoneg");
1462 phy->autoneg_advertised &= phy->autoneg_mask;
1464 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1465 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1469 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1470 /* Read the MII 1000Base-T Control Register (Address 9). */
1471 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1472 &mii_1000t_ctrl_reg);
1477 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&
1478 hw->phy.id == I225_I_PHY_ID) {
1479 /* Read the MULTI GBT AN Control Register - reg 7.32 */
1480 ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK <<
1481 MMD_DEVADDR_SHIFT) |
1482 ANEG_MULTIGBT_AN_CTRL,
1483 &aneg_multigbt_an_ctrl);
1489 /* Need to parse both autoneg_advertised and fc and set up
1490 * the appropriate PHY registers. First we will parse for
1491 * autoneg_advertised software override. Since we can advertise
1492 * a plethora of combinations, we need to check each bit
1496 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1497 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1498 * the 1000Base-T Control Register (Address 9).
1500 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1501 NWAY_AR_100TX_HD_CAPS |
1502 NWAY_AR_10T_FD_CAPS |
1503 NWAY_AR_10T_HD_CAPS);
1504 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1506 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1508 /* Do we want to advertise 10 Mb Half Duplex? */
1509 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1510 DEBUGOUT("Advertise 10mb Half duplex\n");
1511 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1514 /* Do we want to advertise 10 Mb Full Duplex? */
1515 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1516 DEBUGOUT("Advertise 10mb Full duplex\n");
1517 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1520 /* Do we want to advertise 100 Mb Half Duplex? */
1521 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1522 DEBUGOUT("Advertise 100mb Half duplex\n");
1523 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1526 /* Do we want to advertise 100 Mb Full Duplex? */
1527 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1528 DEBUGOUT("Advertise 100mb Full duplex\n");
1529 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1532 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1533 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1534 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1536 /* Do we want to advertise 1000 Mb Full Duplex? */
1537 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1538 DEBUGOUT("Advertise 1000mb Full duplex\n");
1539 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1542 /* We do not allow the Phy to advertise 2500 Mb Half Duplex */
1543 if (phy->autoneg_advertised & ADVERTISE_2500_HALF)
1544 DEBUGOUT("Advertise 2500mb Half duplex request denied!\n");
1546 /* Do we want to advertise 2500 Mb Full Duplex? */
1547 if (phy->autoneg_advertised & ADVERTISE_2500_FULL) {
1548 DEBUGOUT("Advertise 2500mb Full duplex\n");
1549 aneg_multigbt_an_ctrl |= CR_2500T_FD_CAPS;
1551 aneg_multigbt_an_ctrl &= ~CR_2500T_FD_CAPS;
1554 /* Check for a software override of the flow control settings, and
1555 * setup the PHY advertisement registers accordingly. If
1556 * auto-negotiation is enabled, then software will have to set the
1557 * "PAUSE" bits to the correct value in the Auto-Negotiation
1558 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1561 * The possible values of the "fc" parameter are:
1562 * 0: Flow control is completely disabled
1563 * 1: Rx flow control is enabled (we can receive pause frames
1564 * but not send pause frames).
1565 * 2: Tx flow control is enabled (we can send pause frames
1566 * but we do not support receiving pause frames).
1567 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1568 * other: No software override. The flow control configuration
1569 * in the EEPROM is used.
1571 switch (hw->fc.current_mode) {
1573 /* Flow control (Rx & Tx) is completely disabled by a
1574 * software over-ride.
1576 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1578 case igc_fc_rx_pause:
1579 /* Rx Flow control is enabled, and Tx Flow control is
1580 * disabled, by a software over-ride.
1582 * Since there really isn't a way to advertise that we are
1583 * capable of Rx Pause ONLY, we will advertise that we
1584 * support both symmetric and asymmetric Rx PAUSE. Later
1585 * (in igc_config_fc_after_link_up) we will disable the
1586 * hw's ability to send PAUSE frames.
1588 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1590 case igc_fc_tx_pause:
1591 /* Tx Flow control is enabled, and Rx Flow control is
1592 * disabled, by a software over-ride.
1594 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1595 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1598 /* Flow control (both Rx and Tx) is enabled by a software
1601 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1604 DEBUGOUT("Flow control param set incorrectly\n");
1605 return -IGC_ERR_CONFIG;
1608 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1612 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1614 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1615 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL,
1616 mii_1000t_ctrl_reg);
1618 if ((phy->autoneg_mask & ADVERTISE_2500_FULL) &&
1619 hw->phy.id == I225_I_PHY_ID)
1620 ret_val = phy->ops.write_reg(hw,
1621 (STANDARD_AN_REG_MASK <<
1622 MMD_DEVADDR_SHIFT) |
1623 ANEG_MULTIGBT_AN_CTRL,
1624 aneg_multigbt_an_ctrl);
1630 * igc_copper_link_autoneg - Setup/Enable autoneg for copper link
1631 * @hw: pointer to the HW structure
1633 * Performs initial bounds checking on autoneg advertisement parameter, then
1634 * configure to advertise the full capability. Setup the PHY to autoneg
1635 * and restart the negotiation process between the link partner. If
1636 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1638 s32 igc_copper_link_autoneg(struct igc_hw *hw)
1640 struct igc_phy_info *phy = &hw->phy;
1644 DEBUGFUNC("igc_copper_link_autoneg");
1646 /* Perform some bounds checking on the autoneg advertisement
1649 phy->autoneg_advertised &= phy->autoneg_mask;
1651 /* If autoneg_advertised is zero, we assume it was not defaulted
1652 * by the calling code so we set to advertise full capability.
1654 if (!phy->autoneg_advertised)
1655 phy->autoneg_advertised = phy->autoneg_mask;
1657 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1658 ret_val = igc_phy_setup_autoneg(hw);
1660 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1663 DEBUGOUT("Restarting Auto-Neg\n");
1665 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1666 * the Auto Neg Restart bit in the PHY control register.
1668 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1672 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1673 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1677 /* Does the user want to wait for Auto-Neg to complete here, or
1678 * check at a later time (for example, callback routine).
1680 if (phy->autoneg_wait_to_complete) {
1681 ret_val = igc_wait_autoneg(hw);
1683 DEBUGOUT("Error while waiting for autoneg to complete\n");
1688 hw->mac.get_link_status = true;
1694 * igc_setup_copper_link_generic - Configure copper link settings
1695 * @hw: pointer to the HW structure
1697 * Calls the appropriate function to configure the link for auto-neg or forced
1698 * speed and duplex. Then we check for link, once link is established calls
1699 * to configure collision distance and flow control are called. If link is
1700 * not established, we return -IGC_ERR_PHY (-2).
1702 s32 igc_setup_copper_link_generic(struct igc_hw *hw)
1707 DEBUGFUNC("igc_setup_copper_link_generic");
1709 if (hw->mac.autoneg) {
1710 /* Setup autoneg and flow control advertisement and perform
1713 ret_val = igc_copper_link_autoneg(hw);
1717 /* PHY will be set to 10H, 10F, 100H or 100F
1718 * depending on user settings.
1720 DEBUGOUT("Forcing Speed and Duplex\n");
1721 ret_val = hw->phy.ops.force_speed_duplex(hw);
1723 DEBUGOUT("Error Forcing Speed and Duplex\n");
1728 /* Check link status. Wait up to 100 microseconds for link to become
1731 ret_val = igc_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10,
1737 DEBUGOUT("Valid link established!!!\n");
1738 hw->mac.ops.config_collision_dist(hw);
1739 ret_val = igc_config_fc_after_link_up_generic(hw);
1741 DEBUGOUT("Unable to establish link!!!\n");
1748 * igc_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1749 * @hw: pointer to the HW structure
1751 * Calls the PHY setup function to force speed and duplex. Clears the
1752 * auto-crossover to force MDI manually. Waits for link and returns
1753 * successful if link up is successful, else -IGC_ERR_PHY (-2).
1755 s32 igc_phy_force_speed_duplex_igp(struct igc_hw *hw)
1757 struct igc_phy_info *phy = &hw->phy;
1762 DEBUGFUNC("igc_phy_force_speed_duplex_igp");
1764 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1768 igc_phy_force_speed_duplex_setup(hw, &phy_data);
1770 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1774 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
1775 * forced whenever speed and duplex are forced.
1777 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CTRL, &phy_data);
1781 phy_data &= ~IGP01IGC_PSCR_AUTO_MDIX;
1782 phy_data &= ~IGP01IGC_PSCR_FORCE_MDI_MDIX;
1784 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CTRL, phy_data);
1788 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1792 if (phy->autoneg_wait_to_complete) {
1793 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1795 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1801 DEBUGOUT("Link taking longer than expected.\n");
1804 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1812 * igc_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1813 * @hw: pointer to the HW structure
1815 * Calls the PHY setup function to force speed and duplex. Clears the
1816 * auto-crossover to force MDI manually. Resets the PHY to commit the
1817 * changes. If time expires while waiting for link up, we reset the DSP.
1818 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1819 * successful completion, else return corresponding error code.
1821 s32 igc_phy_force_speed_duplex_m88(struct igc_hw *hw)
1823 struct igc_phy_info *phy = &hw->phy;
1828 DEBUGFUNC("igc_phy_force_speed_duplex_m88");
1830 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1831 if (phy->type != igc_phy_i210) {
1832 /* Clear Auto-Crossover to force MDI manually. M88E1000
1833 * requires MDI forced whenever speed and duplex are forced.
1835 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL,
1840 phy_data &= ~M88IGC_PSCR_AUTO_X_MODE;
1841 ret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL,
1846 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1849 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1853 igc_phy_force_speed_duplex_setup(hw, &phy_data);
1855 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1859 /* Reset the phy to commit changes. */
1860 ret_val = hw->phy.ops.commit(hw);
1864 if (phy->autoneg_wait_to_complete) {
1865 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1867 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1873 bool reset_dsp = true;
1875 switch (hw->phy.id) {
1876 case I347AT4_E_PHY_ID:
1877 case M88E1340M_E_PHY_ID:
1878 case M88E1112_E_PHY_ID:
1879 case M88E1543_E_PHY_ID:
1880 case M88E1512_E_PHY_ID:
1888 if (hw->phy.type != igc_phy_m88)
1894 DEBUGOUT("Link taking longer than expected.\n");
1896 /* We didn't get link.
1897 * Reset the DSP and cross our fingers.
1899 ret_val = phy->ops.write_reg(hw,
1900 M88IGC_PHY_PAGE_SELECT,
1904 ret_val = igc_phy_reset_dsp_generic(hw);
1911 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1917 if (hw->phy.type != igc_phy_m88)
1920 if (hw->phy.id == I347AT4_E_PHY_ID ||
1921 hw->phy.id == M88E1340M_E_PHY_ID ||
1922 hw->phy.id == M88E1112_E_PHY_ID)
1924 if (hw->phy.id == I210_I_PHY_ID)
1926 if (hw->phy.id == I225_I_PHY_ID)
1928 if (hw->phy.id == M88E1543_E_PHY_ID || hw->phy.id == M88E1512_E_PHY_ID)
1930 ret_val = phy->ops.read_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL, &phy_data);
1934 /* Resetting the phy means we need to re-force TX_CLK in the
1935 * Extended PHY Specific Control Register to 25MHz clock from
1936 * the reset value of 2.5MHz.
1938 phy_data |= M88IGC_EPSCR_TX_CLK_25;
1939 ret_val = phy->ops.write_reg(hw, M88IGC_EXT_PHY_SPEC_CTRL, phy_data);
1943 /* In addition, we must re-enable CRS on Tx for both half and full
1946 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);
1950 phy_data |= M88IGC_PSCR_ASSERT_CRS_ON_TX;
1951 ret_val = phy->ops.write_reg(hw, M88IGC_PHY_SPEC_CTRL, phy_data);
1957 * igc_phy_force_speed_duplex_ife - Force PHY speed & duplex
1958 * @hw: pointer to the HW structure
1960 * Forces the speed and duplex settings of the PHY.
1961 * This is a function pointer entry point only called by
1962 * PHY setup routines.
1964 s32 igc_phy_force_speed_duplex_ife(struct igc_hw *hw)
1966 struct igc_phy_info *phy = &hw->phy;
1971 DEBUGFUNC("igc_phy_force_speed_duplex_ife");
1973 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1977 igc_phy_force_speed_duplex_setup(hw, &data);
1979 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1983 /* Disable MDI-X support for 10/100 */
1984 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1988 data &= ~IFE_PMC_AUTO_MDIX;
1989 data &= ~IFE_PMC_FORCE_MDIX;
1991 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1995 DEBUGOUT1("IFE PMC: %X\n", data);
1999 if (phy->autoneg_wait_to_complete) {
2000 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
2002 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2008 DEBUGOUT("Link taking longer than expected.\n");
2011 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
2021 * igc_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
2022 * @hw: pointer to the HW structure
2023 * @phy_ctrl: pointer to current value of PHY_CONTROL
2025 * Forces speed and duplex on the PHY by doing the following: disable flow
2026 * control, force speed/duplex on the MAC, disable auto speed detection,
2027 * disable auto-negotiation, configure duplex, configure speed, configure
2028 * the collision distance, write configuration to CTRL register. The
2029 * caller must write to the PHY_CONTROL register for these settings to
2032 void igc_phy_force_speed_duplex_setup(struct igc_hw *hw, u16 *phy_ctrl)
2034 struct igc_mac_info *mac = &hw->mac;
2037 DEBUGFUNC("igc_phy_force_speed_duplex_setup");
2039 /* Turn off flow control when forcing speed/duplex */
2040 hw->fc.current_mode = igc_fc_none;
2042 /* Force speed/duplex on the mac */
2043 ctrl = IGC_READ_REG(hw, IGC_CTRL);
2044 ctrl |= (IGC_CTRL_FRCSPD | IGC_CTRL_FRCDPX);
2045 ctrl &= ~IGC_CTRL_SPD_SEL;
2047 /* Disable Auto Speed Detection */
2048 ctrl &= ~IGC_CTRL_ASDE;
2050 /* Disable autoneg on the phy */
2051 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
2053 /* Forcing Full or Half Duplex? */
2054 if (mac->forced_speed_duplex & IGC_ALL_HALF_DUPLEX) {
2055 ctrl &= ~IGC_CTRL_FD;
2056 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
2057 DEBUGOUT("Half Duplex\n");
2059 ctrl |= IGC_CTRL_FD;
2060 *phy_ctrl |= MII_CR_FULL_DUPLEX;
2061 DEBUGOUT("Full Duplex\n");
2064 /* Forcing 10mb or 100mb? */
2065 if (mac->forced_speed_duplex & IGC_ALL_100_SPEED) {
2066 ctrl |= IGC_CTRL_SPD_100;
2067 *phy_ctrl |= MII_CR_SPEED_100;
2068 *phy_ctrl &= ~MII_CR_SPEED_1000;
2069 DEBUGOUT("Forcing 100mb\n");
2071 ctrl &= ~(IGC_CTRL_SPD_1000 | IGC_CTRL_SPD_100);
2072 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
2073 DEBUGOUT("Forcing 10mb\n");
2076 hw->mac.ops.config_collision_dist(hw);
2078 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
2082 * igc_set_d3_lplu_state_generic - Sets low power link up state for D3
2083 * @hw: pointer to the HW structure
2084 * @active: boolean used to enable/disable lplu
2086 * Success returns 0, Failure returns 1
2088 * The low power link up (lplu) state is set to the power management level D3
2089 * and SmartSpeed is disabled when active is true, else clear lplu for D3
2090 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2091 * is used during Dx states where the power conservation is most important.
2092 * During driver activity, SmartSpeed should be enabled so performance is
2095 s32 igc_set_d3_lplu_state_generic(struct igc_hw *hw, bool active)
2097 struct igc_phy_info *phy = &hw->phy;
2101 DEBUGFUNC("igc_set_d3_lplu_state_generic");
2103 if (!hw->phy.ops.read_reg)
2106 ret_val = phy->ops.read_reg(hw, IGP02IGC_PHY_POWER_MGMT, &data);
2111 data &= ~IGP02IGC_PM_D3_LPLU;
2112 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
2116 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
2117 * during Dx states where the power conservation is most
2118 * important. During driver activity we should enable
2119 * SmartSpeed, so performance is maintained.
2121 if (phy->smart_speed == igc_smart_speed_on) {
2122 ret_val = phy->ops.read_reg(hw,
2123 IGP01IGC_PHY_PORT_CONFIG,
2128 data |= IGP01IGC_PSCFR_SMART_SPEED;
2129 ret_val = phy->ops.write_reg(hw,
2130 IGP01IGC_PHY_PORT_CONFIG,
2134 } else if (phy->smart_speed == igc_smart_speed_off) {
2135 ret_val = phy->ops.read_reg(hw,
2136 IGP01IGC_PHY_PORT_CONFIG,
2141 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
2142 ret_val = phy->ops.write_reg(hw,
2143 IGP01IGC_PHY_PORT_CONFIG,
2148 } else if ((phy->autoneg_advertised == IGC_ALL_SPEED_DUPLEX) ||
2149 (phy->autoneg_advertised == IGC_ALL_NOT_GIG) ||
2150 (phy->autoneg_advertised == IGC_ALL_10_SPEED)) {
2151 data |= IGP02IGC_PM_D3_LPLU;
2152 ret_val = phy->ops.write_reg(hw, IGP02IGC_PHY_POWER_MGMT,
2157 /* When LPLU is enabled, we should disable SmartSpeed */
2158 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
2163 data &= ~IGP01IGC_PSCFR_SMART_SPEED;
2164 ret_val = phy->ops.write_reg(hw, IGP01IGC_PHY_PORT_CONFIG,
2172 * igc_check_downshift_generic - Checks whether a downshift in speed occurred
2173 * @hw: pointer to the HW structure
2175 * Success returns 0, Failure returns 1
2177 * A downshift is detected by querying the PHY link health.
2179 s32 igc_check_downshift_generic(struct igc_hw *hw)
2181 struct igc_phy_info *phy = &hw->phy;
2183 u16 phy_data, offset, mask;
2185 DEBUGFUNC("igc_check_downshift_generic");
2187 switch (phy->type) {
2190 case igc_phy_gg82563:
2193 offset = M88IGC_PHY_SPEC_STATUS;
2194 mask = M88IGC_PSSR_DOWNSHIFT;
2199 offset = IGP01IGC_PHY_LINK_HEALTH;
2200 mask = IGP01IGC_PLHR_SS_DOWNGRADE;
2203 /* speed downshift not supported */
2204 phy->speed_downgraded = false;
2208 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2211 phy->speed_downgraded = !!(phy_data & mask);
2217 * igc_check_polarity_m88 - Checks the polarity.
2218 * @hw: pointer to the HW structure
2220 * Success returns 0, Failure returns -IGC_ERR_PHY (-2)
2222 * Polarity is determined based on the PHY specific status register.
2224 s32 igc_check_polarity_m88(struct igc_hw *hw)
2226 struct igc_phy_info *phy = &hw->phy;
2230 DEBUGFUNC("igc_check_polarity_m88");
2232 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_STATUS, &data);
2235 phy->cable_polarity = ((data & M88IGC_PSSR_REV_POLARITY)
2236 ? igc_rev_polarity_reversed
2237 : igc_rev_polarity_normal);
2243 * igc_check_polarity_igp - Checks the polarity.
2244 * @hw: pointer to the HW structure
2246 * Success returns 0, Failure returns -IGC_ERR_PHY (-2)
2248 * Polarity is determined based on the PHY port status register, and the
2249 * current speed (since there is no polarity at 100Mbps).
2251 s32 igc_check_polarity_igp(struct igc_hw *hw)
2253 struct igc_phy_info *phy = &hw->phy;
2255 u16 data, offset, mask;
2257 DEBUGFUNC("igc_check_polarity_igp");
2259 /* Polarity is determined based on the speed of
2262 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_STATUS, &data);
2266 if ((data & IGP01IGC_PSSR_SPEED_MASK) ==
2267 IGP01IGC_PSSR_SPEED_1000MBPS) {
2268 offset = IGP01IGC_PHY_PCS_INIT_REG;
2269 mask = IGP01IGC_PHY_POLARITY_MASK;
2271 /* This really only applies to 10Mbps since
2272 * there is no polarity for 100Mbps (always 0).
2274 offset = IGP01IGC_PHY_PORT_STATUS;
2275 mask = IGP01IGC_PSSR_POLARITY_REVERSED;
2278 ret_val = phy->ops.read_reg(hw, offset, &data);
2281 phy->cable_polarity = ((data & mask)
2282 ? igc_rev_polarity_reversed
2283 : igc_rev_polarity_normal);
2289 * igc_check_polarity_ife - Check cable polarity for IFE PHY
2290 * @hw: pointer to the HW structure
2292 * Polarity is determined on the polarity reversal feature being enabled.
2294 s32 igc_check_polarity_ife(struct igc_hw *hw)
2296 struct igc_phy_info *phy = &hw->phy;
2298 u16 phy_data, offset, mask;
2300 DEBUGFUNC("igc_check_polarity_ife");
2302 /* Polarity is determined based on the reversal feature being enabled.
2304 if (phy->polarity_correction) {
2305 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
2306 mask = IFE_PESC_POLARITY_REVERSED;
2308 offset = IFE_PHY_SPECIAL_CONTROL;
2309 mask = IFE_PSC_FORCE_POLARITY;
2312 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2315 phy->cable_polarity = ((phy_data & mask)
2316 ? igc_rev_polarity_reversed
2317 : igc_rev_polarity_normal);
2323 * igc_wait_autoneg - Wait for auto-neg completion
2324 * @hw: pointer to the HW structure
2326 * Waits for auto-negotiation to complete or for the auto-negotiation time
2327 * limit to expire, which ever happens first.
2329 static s32 igc_wait_autoneg(struct igc_hw *hw)
2331 s32 ret_val = IGC_SUCCESS;
2334 DEBUGFUNC("igc_wait_autoneg");
2336 if (!hw->phy.ops.read_reg)
2339 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2340 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2341 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2344 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2347 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2352 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2359 * igc_phy_has_link_generic - Polls PHY for link
2360 * @hw: pointer to the HW structure
2361 * @iterations: number of times to poll for link
2362 * @usec_interval: delay between polling attempts
2363 * @success: pointer to whether polling was successful or not
2365 * Polls the PHY status register for link, 'iterations' number of times.
2367 s32 igc_phy_has_link_generic(struct igc_hw *hw, u32 iterations,
2368 u32 usec_interval, bool *success)
2370 s32 ret_val = IGC_SUCCESS;
2373 DEBUGFUNC("igc_phy_has_link_generic");
2375 if (!hw->phy.ops.read_reg)
2378 for (i = 0; i < iterations; i++) {
2379 /* Some PHYs require the PHY_STATUS register to be read
2380 * twice due to the link bit being sticky. No harm doing
2381 * it across the board.
2383 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2385 /* If the first read fails, another entity may have
2386 * ownership of the resources, wait and try again to
2387 * see if they have relinquished the resources yet.
2389 if (usec_interval >= 1000)
2390 msec_delay(usec_interval / 1000);
2392 usec_delay(usec_interval);
2394 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2397 if (phy_status & MII_SR_LINK_STATUS)
2399 if (usec_interval >= 1000)
2400 msec_delay(usec_interval / 1000);
2402 usec_delay(usec_interval);
2405 *success = (i < iterations);
2411 * igc_get_cable_length_m88 - Determine cable length for m88 PHY
2412 * @hw: pointer to the HW structure
2414 * Reads the PHY specific status register to retrieve the cable length
2415 * information. The cable length is determined by averaging the minimum and
2416 * maximum values to get the "average" cable length. The m88 PHY has four
2417 * possible cable length values, which are:
2418 * Register Value Cable Length
2422 * 3 110 - 140 meters
2425 s32 igc_get_cable_length_m88(struct igc_hw *hw)
2427 struct igc_phy_info *phy = &hw->phy;
2429 u16 phy_data, index;
2431 DEBUGFUNC("igc_get_cable_length_m88");
2433 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_STATUS, &phy_data);
2437 index = ((phy_data & M88IGC_PSSR_CABLE_LENGTH) >>
2438 M88IGC_PSSR_CABLE_LENGTH_SHIFT);
2440 if (index >= M88IGC_CABLE_LENGTH_TABLE_SIZE - 1)
2441 return -IGC_ERR_PHY;
2443 phy->min_cable_length = igc_m88_cable_length_table[index];
2444 phy->max_cable_length = igc_m88_cable_length_table[index + 1];
2446 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2451 s32 igc_get_cable_length_m88_gen2(struct igc_hw *hw)
2453 struct igc_phy_info *phy = &hw->phy;
2455 u16 phy_data, phy_data2, is_cm;
2456 u16 index, default_page;
2458 DEBUGFUNC("igc_get_cable_length_m88_gen2");
2460 switch (hw->phy.id) {
2462 /* Get cable length from PHY Cable Diagnostics Control Reg */
2463 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2464 (I347AT4_PCDL + phy->addr),
2469 /* Check if the unit of cable length is meters or cm */
2470 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
2471 I347AT4_PCDC, &phy_data2);
2475 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2477 /* Populate the phy structure with cable length in meters */
2478 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2479 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2480 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2485 /* TODO - complete with Foxville data */
2487 case M88E1543_E_PHY_ID:
2488 case M88E1512_E_PHY_ID:
2489 case M88E1340M_E_PHY_ID:
2490 case I347AT4_E_PHY_ID:
2491 /* Remember the original page select and set it to 7 */
2492 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2497 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2501 /* Get cable length from PHY Cable Diagnostics Control Reg */
2502 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2507 /* Check if the unit of cable length is meters or cm */
2508 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2512 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2514 /* Populate the phy structure with cable length in meters */
2515 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2516 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2517 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2519 /* Reset the page select to its original value */
2520 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2526 case M88E1112_E_PHY_ID:
2527 /* Remember the original page select and set it to 5 */
2528 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2533 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2537 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2542 index = (phy_data & M88IGC_PSSR_CABLE_LENGTH) >>
2543 M88IGC_PSSR_CABLE_LENGTH_SHIFT;
2545 if (index >= M88IGC_CABLE_LENGTH_TABLE_SIZE - 1)
2546 return -IGC_ERR_PHY;
2548 phy->min_cable_length = igc_m88_cable_length_table[index];
2549 phy->max_cable_length = igc_m88_cable_length_table[index + 1];
2551 phy->cable_length = (phy->min_cable_length +
2552 phy->max_cable_length) / 2;
2554 /* Reset the page select to its original value */
2555 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2562 return -IGC_ERR_PHY;
2569 * igc_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2570 * @hw: pointer to the HW structure
2572 * The automatic gain control (agc) normalizes the amplitude of the
2573 * received signal, adjusting for the attenuation produced by the
2574 * cable. By reading the AGC registers, which represent the
2575 * combination of coarse and fine gain value, the value can be put
2576 * into a lookup table to obtain the approximate cable length
2579 s32 igc_get_cable_length_igp_2(struct igc_hw *hw)
2581 struct igc_phy_info *phy = &hw->phy;
2583 u16 phy_data, i, agc_value = 0;
2584 u16 cur_agc_index, max_agc_index = 0;
2585 u16 min_agc_index = IGP02IGC_CABLE_LENGTH_TABLE_SIZE - 1;
2586 static const u16 agc_reg_array[IGP02IGC_PHY_CHANNEL_NUM] = {
2593 DEBUGFUNC("igc_get_cable_length_igp_2");
2595 /* Read the AGC registers for all channels */
2596 for (i = 0; i < IGP02IGC_PHY_CHANNEL_NUM; i++) {
2597 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2601 /* Getting bits 15:9, which represent the combination of
2602 * coarse and fine gain values. The result is a number
2603 * that can be put into the lookup table to obtain the
2604 * approximate cable length.
2606 cur_agc_index = ((phy_data >> IGP02IGC_AGC_LENGTH_SHIFT) &
2607 IGP02IGC_AGC_LENGTH_MASK);
2609 /* Array index bound check. */
2610 if (cur_agc_index >= IGP02IGC_CABLE_LENGTH_TABLE_SIZE ||
2612 return -IGC_ERR_PHY;
2614 /* Remove min & max AGC values from calculation. */
2615 if (igc_igp_2_cable_length_table[min_agc_index] >
2616 igc_igp_2_cable_length_table[cur_agc_index])
2617 min_agc_index = cur_agc_index;
2618 if (igc_igp_2_cable_length_table[max_agc_index] <
2619 igc_igp_2_cable_length_table[cur_agc_index])
2620 max_agc_index = cur_agc_index;
2622 agc_value += igc_igp_2_cable_length_table[cur_agc_index];
2625 agc_value -= (igc_igp_2_cable_length_table[min_agc_index] +
2626 igc_igp_2_cable_length_table[max_agc_index]);
2627 agc_value /= (IGP02IGC_PHY_CHANNEL_NUM - 2);
2629 /* Calculate cable length with the error range of +/- 10 meters. */
2630 phy->min_cable_length = (((agc_value - IGP02IGC_AGC_RANGE) > 0) ?
2631 (agc_value - IGP02IGC_AGC_RANGE) : 0);
2632 phy->max_cable_length = agc_value + IGP02IGC_AGC_RANGE;
2634 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2640 * igc_get_phy_info_m88 - Retrieve PHY information
2641 * @hw: pointer to the HW structure
2643 * Valid for only copper links. Read the PHY status register (sticky read)
2644 * to verify that link is up. Read the PHY special control register to
2645 * determine the polarity and 10base-T extended distance. Read the PHY
2646 * special status register to determine MDI/MDIx and current speed. If
2647 * speed is 1000, then determine cable length, local and remote receiver.
2649 s32 igc_get_phy_info_m88(struct igc_hw *hw)
2651 struct igc_phy_info *phy = &hw->phy;
2656 DEBUGFUNC("igc_get_phy_info_m88");
2658 if (phy->media_type != igc_media_type_copper) {
2659 DEBUGOUT("Phy info is only valid for copper media\n");
2660 return -IGC_ERR_CONFIG;
2663 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
2668 DEBUGOUT("Phy info is only valid if link is up\n");
2669 return -IGC_ERR_CONFIG;
2672 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_CTRL, &phy_data);
2676 phy->polarity_correction = !!(phy_data &
2677 M88IGC_PSCR_POLARITY_REVERSAL);
2679 ret_val = igc_check_polarity_m88(hw);
2683 ret_val = phy->ops.read_reg(hw, M88IGC_PHY_SPEC_STATUS, &phy_data);
2687 phy->is_mdix = !!(phy_data & M88IGC_PSSR_MDIX);
2689 if ((phy_data & M88IGC_PSSR_SPEED) == M88IGC_PSSR_1000MBS) {
2690 ret_val = hw->phy.ops.get_cable_length(hw);
2694 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2698 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2699 ? igc_1000t_rx_status_ok
2700 : igc_1000t_rx_status_not_ok;
2702 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2703 ? igc_1000t_rx_status_ok
2704 : igc_1000t_rx_status_not_ok;
2706 /* Set values to "undefined" */
2707 phy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;
2708 phy->local_rx = igc_1000t_rx_status_undefined;
2709 phy->remote_rx = igc_1000t_rx_status_undefined;
2716 * igc_get_phy_info_igp - Retrieve igp PHY information
2717 * @hw: pointer to the HW structure
2719 * Read PHY status to determine if link is up. If link is up, then
2720 * set/determine 10base-T extended distance and polarity correction. Read
2721 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2722 * determine on the cable length, local and remote receiver.
2724 s32 igc_get_phy_info_igp(struct igc_hw *hw)
2726 struct igc_phy_info *phy = &hw->phy;
2731 DEBUGFUNC("igc_get_phy_info_igp");
2733 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
2738 DEBUGOUT("Phy info is only valid if link is up\n");
2739 return -IGC_ERR_CONFIG;
2742 phy->polarity_correction = true;
2744 ret_val = igc_check_polarity_igp(hw);
2748 ret_val = phy->ops.read_reg(hw, IGP01IGC_PHY_PORT_STATUS, &data);
2752 phy->is_mdix = !!(data & IGP01IGC_PSSR_MDIX);
2754 if ((data & IGP01IGC_PSSR_SPEED_MASK) ==
2755 IGP01IGC_PSSR_SPEED_1000MBPS) {
2756 ret_val = phy->ops.get_cable_length(hw);
2760 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2764 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2765 ? igc_1000t_rx_status_ok
2766 : igc_1000t_rx_status_not_ok;
2768 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2769 ? igc_1000t_rx_status_ok
2770 : igc_1000t_rx_status_not_ok;
2772 phy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;
2773 phy->local_rx = igc_1000t_rx_status_undefined;
2774 phy->remote_rx = igc_1000t_rx_status_undefined;
2781 * igc_get_phy_info_ife - Retrieves various IFE PHY states
2782 * @hw: pointer to the HW structure
2784 * Populates "phy" structure with various feature states.
2786 s32 igc_get_phy_info_ife(struct igc_hw *hw)
2788 struct igc_phy_info *phy = &hw->phy;
2793 DEBUGFUNC("igc_get_phy_info_ife");
2795 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
2800 DEBUGOUT("Phy info is only valid if link is up\n");
2801 return -IGC_ERR_CONFIG;
2804 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2807 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE);
2809 if (phy->polarity_correction) {
2810 ret_val = igc_check_polarity_ife(hw);
2814 /* Polarity is forced */
2815 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY)
2816 ? igc_rev_polarity_reversed
2817 : igc_rev_polarity_normal);
2820 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2824 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS);
2826 /* The following parameters are undefined for 10/100 operation. */
2827 phy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;
2828 phy->local_rx = igc_1000t_rx_status_undefined;
2829 phy->remote_rx = igc_1000t_rx_status_undefined;
2835 * igc_phy_sw_reset_generic - PHY software reset
2836 * @hw: pointer to the HW structure
2838 * Does a software reset of the PHY by reading the PHY control register and
2839 * setting/write the control register reset bit to the PHY.
2841 s32 igc_phy_sw_reset_generic(struct igc_hw *hw)
2846 DEBUGFUNC("igc_phy_sw_reset_generic");
2848 if (!hw->phy.ops.read_reg)
2851 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2855 phy_ctrl |= MII_CR_RESET;
2856 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2866 * igc_phy_hw_reset_generic - PHY hardware reset
2867 * @hw: pointer to the HW structure
2869 * Verify the reset block is not blocking us from resetting. Acquire
2870 * semaphore (if necessary) and read/set/write the device control reset
2871 * bit in the PHY. Wait the appropriate delay time for the device to
2872 * reset and release the semaphore (if necessary).
2874 s32 igc_phy_hw_reset_generic(struct igc_hw *hw)
2876 struct igc_phy_info *phy = &hw->phy;
2880 DEBUGFUNC("igc_phy_hw_reset_generic");
2882 if (phy->ops.check_reset_block) {
2883 ret_val = phy->ops.check_reset_block(hw);
2888 ret_val = phy->ops.acquire(hw);
2892 ctrl = IGC_READ_REG(hw, IGC_CTRL);
2893 IGC_WRITE_REG(hw, IGC_CTRL, ctrl | IGC_CTRL_PHY_RST);
2894 IGC_WRITE_FLUSH(hw);
2896 usec_delay(phy->reset_delay_us);
2898 IGC_WRITE_REG(hw, IGC_CTRL, ctrl);
2899 IGC_WRITE_FLUSH(hw);
2903 phy->ops.release(hw);
2909 * igc_get_cfg_done_generic - Generic configuration done
2910 * @hw: pointer to the HW structure
2912 * Generic function to wait 10 milli-seconds for configuration to complete
2913 * and return success.
2915 s32 igc_get_cfg_done_generic(struct igc_hw IGC_UNUSEDARG * hw)
2917 DEBUGFUNC("igc_get_cfg_done_generic");
2918 UNREFERENCED_1PARAMETER(hw);
2926 * igc_phy_init_script_igp3 - Inits the IGP3 PHY
2927 * @hw: pointer to the HW structure
2929 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2931 s32 igc_phy_init_script_igp3(struct igc_hw *hw)
2933 DEBUGOUT("Running IGP 3 PHY init script\n");
2935 /* PHY init IGP 3 */
2936 /* Enable rise/fall, 10-mode work in class-A */
2937 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2938 /* Remove all caps from Replica path filter */
2939 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2940 /* Bias trimming for ADC, AFE and Driver (Default) */
2941 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2942 /* Increase Hybrid poly bias */
2943 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2944 /* Add 4% to Tx amplitude in Gig mode */
2945 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2946 /* Disable trimming (TTT) */
2947 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2948 /* Poly DC correction to 94.6% + 2% for all channels */
2949 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2950 /* ABS DC correction to 95.9% */
2951 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2952 /* BG temp curve trim */
2953 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2954 /* Increasing ADC OPAMP stage 1 currents to max */
2955 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2956 /* Force 1000 ( required for enabling PHY regs configuration) */
2957 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2958 /* Set upd_freq to 6 */
2959 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2961 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2962 /* Disable adaptive fixed FFE (Default) */
2963 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2964 /* Enable FFE hysteresis */
2965 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2966 /* Fixed FFE for short cable lengths */
2967 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2968 /* Fixed FFE for medium cable lengths */
2969 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2970 /* Fixed FFE for long cable lengths */
2971 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2972 /* Enable Adaptive Clip Threshold */
2973 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2974 /* AHT reset limit to 1 */
2975 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2976 /* Set AHT master delay to 127 msec */
2977 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2978 /* Set scan bits for AHT */
2979 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2980 /* Set AHT Preset bits */
2981 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2982 /* Change integ_factor of channel A to 3 */
2983 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2984 /* Change prop_factor of channels BCD to 8 */
2985 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2986 /* Change cg_icount + enable integbp for channels BCD */
2987 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2988 /* Change cg_icount + enable integbp + change prop_factor_master
2989 * to 8 for channel A
2991 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2992 /* Disable AHT in Slave mode on channel A */
2993 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2994 /* Enable LPLU and disable AN to 1000 in non-D0a states,
2997 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2998 /* Enable restart AN on an1000_dis change */
2999 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
3000 /* Enable wh_fifo read clock in 10/100 modes */
3001 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
3002 /* Restart AN, Speed selection is 1000 */
3003 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
3009 * igc_get_phy_type_from_id - Get PHY type from id
3010 * @phy_id: phy_id read from the phy
3012 * Returns the phy type from the id.
3014 enum igc_phy_type igc_get_phy_type_from_id(u32 phy_id)
3016 enum igc_phy_type phy_type = igc_phy_unknown;
3019 case M88IGC_I_PHY_ID:
3020 case M88IGC_E_PHY_ID:
3021 case M88E1111_I_PHY_ID:
3022 case M88E1011_I_PHY_ID:
3023 case M88E1543_E_PHY_ID:
3024 case M88E1512_E_PHY_ID:
3025 case I347AT4_E_PHY_ID:
3026 case M88E1112_E_PHY_ID:
3027 case M88E1340M_E_PHY_ID:
3028 phy_type = igc_phy_m88;
3030 case IGP01IGC_I_PHY_ID: /* IGP 1 & 2 share this */
3031 phy_type = igc_phy_igp_2;
3033 case GG82563_E_PHY_ID:
3034 phy_type = igc_phy_gg82563;
3036 case IGP03IGC_E_PHY_ID:
3037 phy_type = igc_phy_igp_3;
3040 case IFE_PLUS_E_PHY_ID:
3041 case IFE_C_E_PHY_ID:
3042 phy_type = igc_phy_ife;
3044 case BMIGC_E_PHY_ID:
3045 case BMIGC_E_PHY_ID_R2:
3046 phy_type = igc_phy_bm;
3048 case I82578_E_PHY_ID:
3049 phy_type = igc_phy_82578;
3051 case I82577_E_PHY_ID:
3052 phy_type = igc_phy_82577;
3054 case I82579_E_PHY_ID:
3055 phy_type = igc_phy_82579;
3058 phy_type = igc_phy_i217;
3060 case I82580_I_PHY_ID:
3061 phy_type = igc_phy_82580;
3064 phy_type = igc_phy_i210;
3067 phy_type = igc_phy_i225;
3070 phy_type = igc_phy_unknown;
3077 * igc_determine_phy_address - Determines PHY address.
3078 * @hw: pointer to the HW structure
3080 * This uses a trial and error method to loop through possible PHY
3081 * addresses. It tests each by reading the PHY ID registers and
3082 * checking for a match.
3084 s32 igc_determine_phy_address(struct igc_hw *hw)
3088 enum igc_phy_type phy_type = igc_phy_unknown;
3090 hw->phy.id = phy_type;
3092 for (phy_addr = 0; phy_addr < IGC_MAX_PHY_ADDR; phy_addr++) {
3093 hw->phy.addr = phy_addr;
3098 phy_type = igc_get_phy_type_from_id(hw->phy.id);
3100 /* If phy_type is valid, break - we found our
3103 if (phy_type != igc_phy_unknown)
3111 return -IGC_ERR_PHY_TYPE;
3115 * igc_get_phy_addr_for_bm_page - Retrieve PHY page address
3116 * @page: page to access
3117 * @reg: register to access
3119 * Returns the phy address for the page requested.
3121 static u32 igc_get_phy_addr_for_bm_page(u32 page, u32 reg)
3125 if (page >= 768 || (page == 0 && reg == 25) || reg == 31)
3132 * igc_write_phy_reg_bm - Write BM PHY register
3133 * @hw: pointer to the HW structure
3134 * @offset: register offset to write to
3135 * @data: data to write at register offset
3137 * Acquires semaphore, if necessary, then writes the data to PHY register
3138 * at the offset. Release any acquired semaphores before exiting.
3140 s32 igc_write_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 data)
3143 u32 page = offset >> IGP_PAGE_SHIFT;
3145 DEBUGFUNC("igc_write_phy_reg_bm");
3147 ret_val = hw->phy.ops.acquire(hw);
3151 /* Page 800 works differently than the rest so it has its own func */
3152 if (page == BM_WUC_PAGE) {
3153 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, &data,
3158 hw->phy.addr = igc_get_phy_addr_for_bm_page(page, offset);
3160 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3161 u32 page_shift, page_select;
3163 /* Page select is register 31 for phy address 1 and 22 for
3164 * phy address 2 and 3. Page select is shifted only for
3167 if (hw->phy.addr == 1) {
3168 page_shift = IGP_PAGE_SHIFT;
3169 page_select = IGP01IGC_PHY_PAGE_SELECT;
3172 page_select = BM_PHY_PAGE_SELECT;
3175 /* Page is shifted left, PHY expects (page x 32) */
3176 ret_val = igc_write_phy_reg_mdic(hw, page_select,
3177 (page << page_shift));
3182 ret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3186 hw->phy.ops.release(hw);
3191 * igc_read_phy_reg_bm - Read BM PHY register
3192 * @hw: pointer to the HW structure
3193 * @offset: register offset to be read
3194 * @data: pointer to the read data
3196 * Acquires semaphore, if necessary, then reads the PHY register at offset
3197 * and storing the retrieved information in data. Release any acquired
3198 * semaphores before exiting.
3200 s32 igc_read_phy_reg_bm(struct igc_hw *hw, u32 offset, u16 *data)
3203 u32 page = offset >> IGP_PAGE_SHIFT;
3205 DEBUGFUNC("igc_read_phy_reg_bm");
3207 ret_val = hw->phy.ops.acquire(hw);
3211 /* Page 800 works differently than the rest so it has its own func */
3212 if (page == BM_WUC_PAGE) {
3213 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, data,
3218 hw->phy.addr = igc_get_phy_addr_for_bm_page(page, offset);
3220 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3221 u32 page_shift, page_select;
3223 /* Page select is register 31 for phy address 1 and 22 for
3224 * phy address 2 and 3. Page select is shifted only for
3227 if (hw->phy.addr == 1) {
3228 page_shift = IGP_PAGE_SHIFT;
3229 page_select = IGP01IGC_PHY_PAGE_SELECT;
3232 page_select = BM_PHY_PAGE_SELECT;
3235 /* Page is shifted left, PHY expects (page x 32) */
3236 ret_val = igc_write_phy_reg_mdic(hw, page_select,
3237 (page << page_shift));
3242 ret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3245 hw->phy.ops.release(hw);
3250 * igc_read_phy_reg_bm2 - Read BM PHY register
3251 * @hw: pointer to the HW structure
3252 * @offset: register offset to be read
3253 * @data: pointer to the read data
3255 * Acquires semaphore, if necessary, then reads the PHY register at offset
3256 * and storing the retrieved information in data. Release any acquired
3257 * semaphores before exiting.
3259 s32 igc_read_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 *data)
3262 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3264 DEBUGFUNC("igc_read_phy_reg_bm2");
3266 ret_val = hw->phy.ops.acquire(hw);
3270 /* Page 800 works differently than the rest so it has its own func */
3271 if (page == BM_WUC_PAGE) {
3272 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, data,
3279 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3280 /* Page is shifted left, PHY expects (page x 32) */
3281 ret_val = igc_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3288 ret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3291 hw->phy.ops.release(hw);
3296 * igc_write_phy_reg_bm2 - Write BM PHY register
3297 * @hw: pointer to the HW structure
3298 * @offset: register offset to write to
3299 * @data: data to write at register offset
3301 * Acquires semaphore, if necessary, then writes the data to PHY register
3302 * at the offset. Release any acquired semaphores before exiting.
3304 s32 igc_write_phy_reg_bm2(struct igc_hw *hw, u32 offset, u16 data)
3307 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
3309 DEBUGFUNC("igc_write_phy_reg_bm2");
3311 ret_val = hw->phy.ops.acquire(hw);
3315 /* Page 800 works differently than the rest so it has its own func */
3316 if (page == BM_WUC_PAGE) {
3317 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, &data,
3324 if (offset > MAX_PHY_MULTI_PAGE_REG) {
3325 /* Page is shifted left, PHY expects (page x 32) */
3326 ret_val = igc_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
3333 ret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
3337 hw->phy.ops.release(hw);
3342 * igc_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
3343 * @hw: pointer to the HW structure
3344 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
3346 * Assumes semaphore already acquired and phy_reg points to a valid memory
3347 * address to store contents of the BM_WUC_ENABLE_REG register.
3349 s32 igc_enable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg)
3354 DEBUGFUNC("igc_enable_phy_wakeup_reg_access_bm");
3357 return -IGC_ERR_PARAM;
3359 /* All page select, port ctrl and wakeup registers use phy address 1 */
3362 /* Select Port Control Registers page */
3363 ret_val = igc_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3365 DEBUGOUT("Could not set Port Control page\n");
3369 ret_val = igc_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
3371 DEBUGOUT2("Could not read PHY register %d.%d\n",
3372 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3376 /* Enable both PHY wakeup mode and Wakeup register page writes.
3377 * Prevent a power state change by disabling ME and Host PHY wakeup.
3380 temp |= BM_WUC_ENABLE_BIT;
3381 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
3383 ret_val = igc_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
3385 DEBUGOUT2("Could not write PHY register %d.%d\n",
3386 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3390 /* Select Host Wakeup Registers page - caller now able to write
3391 * registers on the Wakeup registers page
3393 return igc_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
3397 * igc_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
3398 * @hw: pointer to the HW structure
3399 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
3401 * Restore BM_WUC_ENABLE_REG to its original value.
3403 * Assumes semaphore already acquired and *phy_reg is the contents of the
3404 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
3407 s32 igc_disable_phy_wakeup_reg_access_bm(struct igc_hw *hw, u16 *phy_reg)
3411 DEBUGFUNC("igc_disable_phy_wakeup_reg_access_bm");
3414 return -IGC_ERR_PARAM;
3416 /* Select Port Control Registers page */
3417 ret_val = igc_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
3419 DEBUGOUT("Could not set Port Control page\n");
3423 /* Restore 769.17 to its original value */
3424 ret_val = igc_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
3426 DEBUGOUT2("Could not restore PHY register %d.%d\n",
3427 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
3433 * igc_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
3434 * @hw: pointer to the HW structure
3435 * @offset: register offset to be read or written
3436 * @data: pointer to the data to read or write
3437 * @read: determines if operation is read or write
3438 * @page_set: BM_WUC_PAGE already set and access enabled
3440 * Read the PHY register at offset and store the retrieved information in
3441 * data, or write data to PHY register at offset. Note the procedure to
3442 * access the PHY wakeup registers is different than reading the other PHY
3443 * registers. It works as such:
3444 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
3445 * 2) Set page to 800 for host (801 if we were manageability)
3446 * 3) Write the address using the address opcode (0x11)
3447 * 4) Read or write the data using the data opcode (0x12)
3448 * 5) Restore 769.17.2 to its original value
3450 * Steps 1 and 2 are done by igc_enable_phy_wakeup_reg_access_bm() and
3451 * step 5 is done by igc_disable_phy_wakeup_reg_access_bm().
3453 * Assumes semaphore is already acquired. When page_set==true, assumes
3454 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
3455 * is responsible for calls to igc_[enable|disable]_phy_wakeup_reg_bm()).
3457 static s32 igc_access_phy_wakeup_reg_bm(struct igc_hw *hw, u32 offset,
3458 u16 *data, bool read, bool page_set)
3461 u16 reg = BM_PHY_REG_NUM(offset);
3462 u16 page = BM_PHY_REG_PAGE(offset);
3465 DEBUGFUNC("igc_access_phy_wakeup_reg_bm");
3467 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
3468 if (hw->mac.type == igc_pchlan &&
3469 !(IGC_READ_REG(hw, IGC_PHY_CTRL) & IGC_PHY_CTRL_GBE_DISABLE))
3470 DEBUGOUT1("Attempting to access page %d while gig enabled.\n",
3474 /* Enable access to PHY wakeup registers */
3475 ret_val = igc_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3477 DEBUGOUT("Could not enable PHY wakeup reg access\n");
3482 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg);
3484 /* Write the Wakeup register page offset value using opcode 0x11 */
3485 ret_val = igc_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
3487 DEBUGOUT1("Could not write address opcode to page %d\n", page);
3492 /* Read the Wakeup register page value using opcode 0x12 */
3493 ret_val = igc_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3496 /* Write the Wakeup register page value using opcode 0x12 */
3497 ret_val = igc_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
3502 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg);
3507 ret_val = igc_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
3513 * igc_power_up_phy_copper - Restore copper link in case of PHY power down
3514 * @hw: pointer to the HW structure
3516 * In the case of a PHY power down to save power, or to turn off link during a
3517 * driver unload, or wake on lan is not enabled, restore the link to previous
3520 void igc_power_up_phy_copper(struct igc_hw *hw)
3524 /* The PHY will retain its settings across a power down/up cycle */
3525 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3526 mii_reg &= ~MII_CR_POWER_DOWN;
3527 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3531 * igc_power_down_phy_copper - Restore copper link in case of PHY power down
3532 * @hw: pointer to the HW structure
3534 * In the case of a PHY power down to save power, or to turn off link during a
3535 * driver unload, or wake on lan is not enabled, restore the link to previous
3538 void igc_power_down_phy_copper(struct igc_hw *hw)
3542 /* The PHY will retain its settings across a power down/up cycle */
3543 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
3544 mii_reg |= MII_CR_POWER_DOWN;
3545 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
3550 * __igc_read_phy_reg_hv - Read HV PHY register
3551 * @hw: pointer to the HW structure
3552 * @offset: register offset to be read
3553 * @data: pointer to the read data
3554 * @locked: semaphore has already been acquired or not
3555 * @page_set: BM_WUC_PAGE already set and access enabled
3557 * Acquires semaphore, if necessary, then reads the PHY register at offset
3558 * and stores the retrieved information in data. Release any acquired
3559 * semaphore before exiting.
3561 static s32 __igc_read_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 *data,
3562 bool locked, bool page_set)
3565 u16 page = BM_PHY_REG_PAGE(offset);
3566 u16 reg = BM_PHY_REG_NUM(offset);
3567 u32 phy_addr = hw->phy.addr = igc_get_phy_addr_for_hv_page(page);
3569 DEBUGFUNC("__igc_read_phy_reg_hv");
3572 ret_val = hw->phy.ops.acquire(hw);
3576 /* Page 800 works differently than the rest so it has its own func */
3577 if (page == BM_WUC_PAGE) {
3578 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, data,
3583 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3584 ret_val = igc_access_phy_debug_regs_hv(hw, offset,
3590 if (page == HV_INTC_FC_PAGE_START)
3593 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3594 /* Page is shifted left, PHY expects (page x 32) */
3595 ret_val = igc_set_page_igp(hw,
3596 (page << IGP_PAGE_SHIFT));
3598 hw->phy.addr = phy_addr;
3605 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3606 page << IGP_PAGE_SHIFT, reg);
3608 ret_val = igc_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3612 hw->phy.ops.release(hw);
3618 * igc_read_phy_reg_hv - Read HV PHY register
3619 * @hw: pointer to the HW structure
3620 * @offset: register offset to be read
3621 * @data: pointer to the read data
3623 * Acquires semaphore then reads the PHY register at offset and stores
3624 * the retrieved information in data. Release the acquired semaphore
3627 s32 igc_read_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 *data)
3629 return __igc_read_phy_reg_hv(hw, offset, data, false, false);
3633 * igc_read_phy_reg_hv_locked - Read HV PHY register
3634 * @hw: pointer to the HW structure
3635 * @offset: register offset to be read
3636 * @data: pointer to the read data
3638 * Reads the PHY register at offset and stores the retrieved information
3639 * in data. Assumes semaphore already acquired.
3641 s32 igc_read_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 *data)
3643 return __igc_read_phy_reg_hv(hw, offset, data, true, false);
3647 * igc_read_phy_reg_page_hv - Read HV PHY register
3648 * @hw: pointer to the HW structure
3649 * @offset: register offset to write to
3650 * @data: data to write at register offset
3652 * Reads the PHY register at offset and stores the retrieved information
3653 * in data. Assumes semaphore already acquired and page already set.
3655 s32 igc_read_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 *data)
3657 return __igc_read_phy_reg_hv(hw, offset, data, true, true);
3661 * __igc_write_phy_reg_hv - Write HV PHY register
3662 * @hw: pointer to the HW structure
3663 * @offset: register offset to write to
3664 * @data: data to write at register offset
3665 * @locked: semaphore has already been acquired or not
3666 * @page_set: BM_WUC_PAGE already set and access enabled
3668 * Acquires semaphore, if necessary, then writes the data to PHY register
3669 * at the offset. Release any acquired semaphores before exiting.
3671 static s32 __igc_write_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 data,
3672 bool locked, bool page_set)
3675 u16 page = BM_PHY_REG_PAGE(offset);
3676 u16 reg = BM_PHY_REG_NUM(offset);
3677 u32 phy_addr = hw->phy.addr = igc_get_phy_addr_for_hv_page(page);
3679 DEBUGFUNC("__igc_write_phy_reg_hv");
3682 ret_val = hw->phy.ops.acquire(hw);
3686 /* Page 800 works differently than the rest so it has its own func */
3687 if (page == BM_WUC_PAGE) {
3688 ret_val = igc_access_phy_wakeup_reg_bm(hw, offset, &data,
3693 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3694 ret_val = igc_access_phy_debug_regs_hv(hw, offset,
3700 if (page == HV_INTC_FC_PAGE_START)
3704 * Workaround MDIO accesses being disabled after entering IEEE
3705 * Power Down (when bit 11 of the PHY Control register is set)
3707 if (hw->phy.type == igc_phy_82578 &&
3708 hw->phy.revision >= 1 &&
3709 hw->phy.addr == 2 &&
3710 !(MAX_PHY_REG_ADDRESS & reg) &&
3711 (data & (1 << 11))) {
3713 ret_val = igc_access_phy_debug_regs_hv(hw,
3720 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3721 /* Page is shifted left, PHY expects (page x 32) */
3722 ret_val = igc_set_page_igp(hw,
3723 (page << IGP_PAGE_SHIFT));
3725 hw->phy.addr = phy_addr;
3732 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3733 page << IGP_PAGE_SHIFT, reg);
3735 ret_val = igc_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3740 hw->phy.ops.release(hw);
3746 * igc_write_phy_reg_hv - Write HV PHY register
3747 * @hw: pointer to the HW structure
3748 * @offset: register offset to write to
3749 * @data: data to write at register offset
3751 * Acquires semaphore then writes the data to PHY register at the offset.
3752 * Release the acquired semaphores before exiting.
3754 s32 igc_write_phy_reg_hv(struct igc_hw *hw, u32 offset, u16 data)
3756 return __igc_write_phy_reg_hv(hw, offset, data, false, false);
3760 * igc_write_phy_reg_hv_locked - Write HV PHY register
3761 * @hw: pointer to the HW structure
3762 * @offset: register offset to write to
3763 * @data: data to write at register offset
3765 * Writes the data to PHY register at the offset. Assumes semaphore
3768 s32 igc_write_phy_reg_hv_locked(struct igc_hw *hw, u32 offset, u16 data)
3770 return __igc_write_phy_reg_hv(hw, offset, data, true, false);
3774 * igc_write_phy_reg_page_hv - Write HV PHY register
3775 * @hw: pointer to the HW structure
3776 * @offset: register offset to write to
3777 * @data: data to write at register offset
3779 * Writes the data to PHY register at the offset. Assumes semaphore
3780 * already acquired and page already set.
3782 s32 igc_write_phy_reg_page_hv(struct igc_hw *hw, u32 offset, u16 data)
3784 return __igc_write_phy_reg_hv(hw, offset, data, true, true);
3788 * igc_get_phy_addr_for_hv_page - Get PHY address based on page
3789 * @page: page to be accessed
3791 static u32 igc_get_phy_addr_for_hv_page(u32 page)
3795 if (page >= HV_INTC_FC_PAGE_START)
3802 * igc_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3803 * @hw: pointer to the HW structure
3804 * @offset: register offset to be read or written
3805 * @data: pointer to the data to be read or written
3806 * @read: determines if operation is read or write
3808 * Reads the PHY register at offset and stores the retrieved information
3809 * in data. Assumes semaphore already acquired. Note that the procedure
3810 * to access these regs uses the address port and data port to read/write.
3811 * These accesses done with PHY address 2 and without using pages.
3813 static s32 igc_access_phy_debug_regs_hv(struct igc_hw *hw, u32 offset,
3814 u16 *data, bool read)
3820 DEBUGFUNC("igc_access_phy_debug_regs_hv");
3822 /* This takes care of the difference with desktop vs mobile phy */
3823 addr_reg = ((hw->phy.type == igc_phy_82578) ?
3824 I82578_ADDR_REG : I82577_ADDR_REG);
3825 data_reg = addr_reg + 1;
3827 /* All operations in this function are phy address 2 */
3830 /* masking with 0x3F to remove the page from offset */
3831 ret_val = igc_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3833 DEBUGOUT("Could not write the Address Offset port register\n");
3837 /* Read or write the data value next */
3839 ret_val = igc_read_phy_reg_mdic(hw, data_reg, data);
3841 ret_val = igc_write_phy_reg_mdic(hw, data_reg, *data);
3844 DEBUGOUT("Could not access the Data port register\n");
3850 * igc_link_stall_workaround_hv - Si workaround
3851 * @hw: pointer to the HW structure
3853 * This function works around a Si bug where the link partner can get
3854 * a link up indication before the PHY does. If small packets are sent
3855 * by the link partner they can be placed in the packet buffer without
3856 * being properly accounted for by the PHY and will stall preventing
3857 * further packets from being received. The workaround is to clear the
3858 * packet buffer after the PHY detects link up.
3860 s32 igc_link_stall_workaround_hv(struct igc_hw *hw)
3862 s32 ret_val = IGC_SUCCESS;
3865 DEBUGFUNC("igc_link_stall_workaround_hv");
3867 if (hw->phy.type != igc_phy_82578)
3870 /* Do not apply workaround if in PHY loopback bit 14 set */
3871 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data);
3872 if (data & PHY_CONTROL_LB)
3875 /* check if link is up and at 1Gbps */
3876 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data);
3880 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3881 BM_CS_STATUS_SPEED_MASK);
3883 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED |
3884 BM_CS_STATUS_SPEED_1000))
3889 /* flush the packets in the fifo buffer */
3890 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3891 (HV_MUX_DATA_CTRL_GEN_TO_MAC |
3892 HV_MUX_DATA_CTRL_FORCE_SPEED));
3896 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL,
3897 HV_MUX_DATA_CTRL_GEN_TO_MAC);
3901 * igc_check_polarity_82577 - Checks the polarity.
3902 * @hw: pointer to the HW structure
3904 * Success returns 0, Failure returns -IGC_ERR_PHY (-2)
3906 * Polarity is determined based on the PHY specific status register.
3908 s32 igc_check_polarity_82577(struct igc_hw *hw)
3910 struct igc_phy_info *phy = &hw->phy;
3914 DEBUGFUNC("igc_check_polarity_82577");
3916 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
3919 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY)
3920 ? igc_rev_polarity_reversed
3921 : igc_rev_polarity_normal);
3927 * igc_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3928 * @hw: pointer to the HW structure
3930 * Calls the PHY setup function to force speed and duplex.
3932 s32 igc_phy_force_speed_duplex_82577(struct igc_hw *hw)
3934 struct igc_phy_info *phy = &hw->phy;
3939 DEBUGFUNC("igc_phy_force_speed_duplex_82577");
3941 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
3945 igc_phy_force_speed_duplex_setup(hw, &phy_data);
3947 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
3953 if (phy->autoneg_wait_to_complete) {
3954 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
3956 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3962 DEBUGOUT("Link taking longer than expected.\n");
3965 ret_val = igc_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
3973 * igc_get_phy_info_82577 - Retrieve I82577 PHY information
3974 * @hw: pointer to the HW structure
3976 * Read PHY status to determine if link is up. If link is up, then
3977 * set/determine 10base-T extended distance and polarity correction. Read
3978 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3979 * determine on the cable length, local and remote receiver.
3981 s32 igc_get_phy_info_82577(struct igc_hw *hw)
3983 struct igc_phy_info *phy = &hw->phy;
3988 DEBUGFUNC("igc_get_phy_info_82577");
3990 ret_val = igc_phy_has_link_generic(hw, 1, 0, &link);
3995 DEBUGOUT("Phy info is only valid if link is up\n");
3996 return -IGC_ERR_CONFIG;
3999 phy->polarity_correction = true;
4001 ret_val = igc_check_polarity_82577(hw);
4005 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
4009 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX);
4011 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
4012 I82577_PHY_STATUS2_SPEED_1000MBPS) {
4013 ret_val = hw->phy.ops.get_cable_length(hw);
4017 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
4021 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
4022 ? igc_1000t_rx_status_ok
4023 : igc_1000t_rx_status_not_ok;
4025 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
4026 ? igc_1000t_rx_status_ok
4027 : igc_1000t_rx_status_not_ok;
4029 phy->cable_length = IGC_CABLE_LENGTH_UNDEFINED;
4030 phy->local_rx = igc_1000t_rx_status_undefined;
4031 phy->remote_rx = igc_1000t_rx_status_undefined;
4038 * igc_get_cable_length_82577 - Determine cable length for 82577 PHY
4039 * @hw: pointer to the HW structure
4041 * Reads the diagnostic status register and verifies result is valid before
4042 * placing it in the phy_cable_length field.
4044 s32 igc_get_cable_length_82577(struct igc_hw *hw)
4046 struct igc_phy_info *phy = &hw->phy;
4048 u16 phy_data, length;
4050 DEBUGFUNC("igc_get_cable_length_82577");
4052 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
4056 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
4057 I82577_DSTATUS_CABLE_LENGTH_SHIFT);
4059 if (length == IGC_CABLE_LENGTH_UNDEFINED)
4060 return -IGC_ERR_PHY;
4062 phy->cable_length = length;
4068 * igc_write_phy_reg_gs40g - Write GS40G PHY register
4069 * @hw: pointer to the HW structure
4070 * @offset: register offset to write to
4071 * @data: data to write at register offset
4073 * Acquires semaphore, if necessary, then writes the data to PHY register
4074 * at the offset. Release any acquired semaphores before exiting.
4076 s32 igc_write_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 data)
4079 u16 page = offset >> GS40G_PAGE_SHIFT;
4081 DEBUGFUNC("igc_write_phy_reg_gs40g");
4083 offset = offset & GS40G_OFFSET_MASK;
4084 ret_val = hw->phy.ops.acquire(hw);
4088 ret_val = igc_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4091 ret_val = igc_write_phy_reg_mdic(hw, offset, data);
4094 hw->phy.ops.release(hw);
4099 * igc_read_phy_reg_gs40g - Read GS40G PHY register
4100 * @hw: pointer to the HW structure
4101 * @offset: lower half is register offset to read to
4102 * upper half is page to use.
4103 * @data: data to read at register offset
4105 * Acquires semaphore, if necessary, then reads the data in the PHY register
4106 * at the offset. Release any acquired semaphores before exiting.
4108 s32 igc_read_phy_reg_gs40g(struct igc_hw *hw, u32 offset, u16 *data)
4111 u16 page = offset >> GS40G_PAGE_SHIFT;
4113 DEBUGFUNC("igc_read_phy_reg_gs40g");
4115 offset = offset & GS40G_OFFSET_MASK;
4116 ret_val = hw->phy.ops.acquire(hw);
4120 ret_val = igc_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
4123 ret_val = igc_read_phy_reg_mdic(hw, offset, data);
4126 hw->phy.ops.release(hw);
4131 * igc_write_phy_reg_gpy - Write GPY PHY register
4132 * @hw: pointer to the HW structure
4133 * @offset: register offset to write to
4134 * @data: data to write at register offset
4136 * Acquires semaphore, if necessary, then writes the data to PHY register
4137 * at the offset. Release any acquired semaphores before exiting.
4139 s32 igc_write_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 data)
4142 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
4144 DEBUGFUNC("igc_write_phy_reg_gpy");
4146 offset = offset & GPY_REG_MASK;
4149 ret_val = hw->phy.ops.acquire(hw);
4152 ret_val = igc_write_phy_reg_mdic(hw, offset, data);
4155 hw->phy.ops.release(hw);
4157 ret_val = igc_write_xmdio_reg(hw, (u16)offset, dev_addr,
4164 * igc_read_phy_reg_gpy - Read GPY PHY register
4165 * @hw: pointer to the HW structure
4166 * @offset: lower half is register offset to read to
4167 * upper half is MMD to use.
4168 * @data: data to read at register offset
4170 * Acquires semaphore, if necessary, then reads the data in the PHY register
4171 * at the offset. Release any acquired semaphores before exiting.
4173 s32 igc_read_phy_reg_gpy(struct igc_hw *hw, u32 offset, u16 *data)
4176 u8 dev_addr = (offset & GPY_MMD_MASK) >> GPY_MMD_SHIFT;
4178 DEBUGFUNC("igc_read_phy_reg_gpy");
4180 offset = offset & GPY_REG_MASK;
4183 ret_val = hw->phy.ops.acquire(hw);
4186 ret_val = igc_read_phy_reg_mdic(hw, offset, data);
4189 hw->phy.ops.release(hw);
4191 ret_val = igc_read_xmdio_reg(hw, (u16)offset, dev_addr,
4198 * igc_read_phy_reg_mphy - Read mPHY control register
4199 * @hw: pointer to the HW structure
4200 * @address: address to be read
4201 * @data: pointer to the read data
4203 * Reads the mPHY control register in the PHY at offset and stores the
4204 * information read to data.
4206 s32 igc_read_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 *data)
4209 bool locked = false;
4212 DEBUGFUNC("igc_read_phy_reg_mphy");
4214 /* Check if mPHY is ready to read/write operations */
4215 ready = igc_is_mphy_ready(hw);
4217 return -IGC_ERR_PHY;
4219 /* Check if mPHY access is disabled and enable it if so */
4220 mphy_ctrl = IGC_READ_REG(hw, IGC_MPHY_ADDR_CTRL);
4221 if (mphy_ctrl & IGC_MPHY_DIS_ACCESS) {
4223 ready = igc_is_mphy_ready(hw);
4225 return -IGC_ERR_PHY;
4226 mphy_ctrl |= IGC_MPHY_ENA_ACCESS;
4227 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);
4230 /* Set the address that we want to read */
4231 ready = igc_is_mphy_ready(hw);
4233 return -IGC_ERR_PHY;
4235 /* We mask address, because we want to use only current lane */
4236 mphy_ctrl = (mphy_ctrl & ~IGC_MPHY_ADDRESS_MASK &
4237 ~IGC_MPHY_ADDRESS_FNC_OVERRIDE) |
4238 (address & IGC_MPHY_ADDRESS_MASK);
4239 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);
4241 /* Read data from the address */
4242 ready = igc_is_mphy_ready(hw);
4244 return -IGC_ERR_PHY;
4245 *data = IGC_READ_REG(hw, IGC_MPHY_DATA);
4247 /* Disable access to mPHY if it was originally disabled */
4249 ready = igc_is_mphy_ready(hw);
4251 return -IGC_ERR_PHY;
4252 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL,
4253 IGC_MPHY_DIS_ACCESS);
4259 * igc_write_phy_reg_mphy - Write mPHY control register
4260 * @hw: pointer to the HW structure
4261 * @address: address to write to
4262 * @data: data to write to register at offset
4263 * @line_override: used when we want to use different line than default one
4265 * Writes data to mPHY control register.
4267 s32 igc_write_phy_reg_mphy(struct igc_hw *hw, u32 address, u32 data,
4271 bool locked = false;
4274 DEBUGFUNC("igc_write_phy_reg_mphy");
4276 /* Check if mPHY is ready to read/write operations */
4277 ready = igc_is_mphy_ready(hw);
4279 return -IGC_ERR_PHY;
4281 /* Check if mPHY access is disabled and enable it if so */
4282 mphy_ctrl = IGC_READ_REG(hw, IGC_MPHY_ADDR_CTRL);
4283 if (mphy_ctrl & IGC_MPHY_DIS_ACCESS) {
4285 ready = igc_is_mphy_ready(hw);
4287 return -IGC_ERR_PHY;
4288 mphy_ctrl |= IGC_MPHY_ENA_ACCESS;
4289 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);
4292 /* Set the address that we want to read */
4293 ready = igc_is_mphy_ready(hw);
4295 return -IGC_ERR_PHY;
4297 /* We mask address, because we want to use only current lane */
4299 mphy_ctrl |= IGC_MPHY_ADDRESS_FNC_OVERRIDE;
4301 mphy_ctrl &= ~IGC_MPHY_ADDRESS_FNC_OVERRIDE;
4302 mphy_ctrl = (mphy_ctrl & ~IGC_MPHY_ADDRESS_MASK) |
4303 (address & IGC_MPHY_ADDRESS_MASK);
4304 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL, mphy_ctrl);
4306 /* Read data from the address */
4307 ready = igc_is_mphy_ready(hw);
4309 return -IGC_ERR_PHY;
4310 IGC_WRITE_REG(hw, IGC_MPHY_DATA, data);
4312 /* Disable access to mPHY if it was originally disabled */
4314 ready = igc_is_mphy_ready(hw);
4316 return -IGC_ERR_PHY;
4317 IGC_WRITE_REG(hw, IGC_MPHY_ADDR_CTRL,
4318 IGC_MPHY_DIS_ACCESS);
4324 * igc_is_mphy_ready - Check if mPHY control register is not busy
4325 * @hw: pointer to the HW structure
4327 * Returns mPHY control register status.
4329 bool igc_is_mphy_ready(struct igc_hw *hw)
4331 u16 retry_count = 0;
4335 while (retry_count < 2) {
4336 mphy_ctrl = IGC_READ_REG(hw, IGC_MPHY_ADDR_CTRL);
4337 if (mphy_ctrl & IGC_MPHY_BUSY) {
4347 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n");
4353 * __igc_access_xmdio_reg - Read/write XMDIO register
4354 * @hw: pointer to the HW structure
4355 * @address: XMDIO address to program
4356 * @dev_addr: device address to program
4357 * @data: pointer to value to read/write from/to the XMDIO address
4358 * @read: boolean flag to indicate read or write
4360 static s32 __igc_access_xmdio_reg(struct igc_hw *hw, u16 address,
4361 u8 dev_addr, u16 *data, bool read)
4365 DEBUGFUNC("__igc_access_xmdio_reg");
4367 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, dev_addr);
4371 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, address);
4375 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, IGC_MMDAC_FUNC_DATA |
4381 ret_val = hw->phy.ops.read_reg(hw, IGC_MMDAAD, data);
4383 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAAD, *data);
4387 /* Recalibrate the device back to 0 */
4388 ret_val = hw->phy.ops.write_reg(hw, IGC_MMDAC, 0);
4396 * igc_read_xmdio_reg - Read XMDIO register
4397 * @hw: pointer to the HW structure
4398 * @addr: XMDIO address to program
4399 * @dev_addr: device address to program
4400 * @data: value to be read from the EMI address
4402 s32 igc_read_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 *data)
4404 DEBUGFUNC("igc_read_xmdio_reg");
4406 return __igc_access_xmdio_reg(hw, addr, dev_addr, data, true);
4410 * igc_write_xmdio_reg - Write XMDIO register
4411 * @hw: pointer to the HW structure
4412 * @addr: XMDIO address to program
4413 * @dev_addr: device address to program
4414 * @data: value to be written to the XMDIO address
4416 s32 igc_write_xmdio_reg(struct igc_hw *hw, u16 addr, u8 dev_addr, u16 data)
4418 DEBUGFUNC("igc_write_xmdio_reg");
4420 return __igc_access_xmdio_reg(hw, addr, dev_addr, &data,