drivers/net/igc/igc_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019-2020 Intel Corporation
   3  */
   4
   5 #include <stdint.h>
   6 #include <string.h>
   7
   8 #include <rte_string_fns.h>
   9 #include <rte_pci.h>
  10 #include <rte_bus_pci.h>
  11 #include <ethdev_driver.h>
  12 #include <ethdev_pci.h>
  13 #include <rte_malloc.h>
  14 #include <rte_alarm.h>
  15
  16 #include "igc_logs.h"
  17 #include "igc_txrx.h"
  18 #include "igc_filter.h"
  19 #include "igc_flow.h"
  20
  21 #define IGC_INTEL_VENDOR_ID             0x8086
  22
  23 /*
  24  * The overhead from MTU to max frame size.
  25  * Considering VLAN so tag needs to be counted.
  26  */
  27 #define IGC_ETH_OVERHEAD                (RTE_ETHER_HDR_LEN + \
  28                                         RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE)
  29
  30 #define IGC_FC_PAUSE_TIME               0x0680
  31 #define IGC_LINK_UPDATE_CHECK_TIMEOUT   90  /* 9s */
  32 #define IGC_LINK_UPDATE_CHECK_INTERVAL  100 /* ms */
  33
  34 #define IGC_MISC_VEC_ID                 RTE_INTR_VEC_ZERO_OFFSET
  35 #define IGC_RX_VEC_START                RTE_INTR_VEC_RXTX_OFFSET
  36 #define IGC_MSIX_OTHER_INTR_VEC         0   /* MSI-X other interrupt vector */
  37 #define IGC_FLAG_NEED_LINK_UPDATE       (1u << 0)       /* need update link */
  38
  39 #define IGC_DEFAULT_RX_FREE_THRESH      32
  40
  41 #define IGC_DEFAULT_RX_PTHRESH          8
  42 #define IGC_DEFAULT_RX_HTHRESH          8
  43 #define IGC_DEFAULT_RX_WTHRESH          4
  44
  45 #define IGC_DEFAULT_TX_PTHRESH          8
  46 #define IGC_DEFAULT_TX_HTHRESH          1
  47 #define IGC_DEFAULT_TX_WTHRESH          16
  48
  49 /* MSI-X other interrupt vector */
  50 #define IGC_MSIX_OTHER_INTR_VEC         0
  51
  52 /* External VLAN Enable bit mask */
  53 #define IGC_CTRL_EXT_EXT_VLAN           (1u << 26)
  54
  55 /* Speed select */
  56 #define IGC_CTRL_SPEED_MASK             (7u << 8)
  57 #define IGC_CTRL_SPEED_2500             (6u << 8)
  58
  59 /* External VLAN Ether Type bit mask and shift */
  60 #define IGC_VET_EXT                     0xFFFF0000
  61 #define IGC_VET_EXT_SHIFT               16
  62
  63 /* Force EEE Auto-negotiation */
  64 #define IGC_EEER_EEE_FRC_AN             (1u << 28)
  65
  66 /* Per Queue Good Packets Received Count */
  67 #define IGC_PQGPRC(idx)         (0x10010 + 0x100 * (idx))
  68 /* Per Queue Good Octets Received Count */
  69 #define IGC_PQGORC(idx)         (0x10018 + 0x100 * (idx))
  70 /* Per Queue Good Octets Transmitted Count */
  71 #define IGC_PQGOTC(idx)         (0x10034 + 0x100 * (idx))
  72 /* Per Queue Multicast Packets Received Count */
  73 #define IGC_PQMPRC(idx)         (0x10038 + 0x100 * (idx))
  74 /* Transmit Queue Drop Packet Count */
  75 #define IGC_TQDPC(idx)          (0xe030 + 0x40 * (idx))
  76
  77 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
  78 #define U32_0_IN_U64            0       /* lower bytes of u64 */
  79 #define U32_1_IN_U64            1       /* higher bytes of u64 */
  80 #else
  81 #define U32_0_IN_U64            1
  82 #define U32_1_IN_U64            0
  83 #endif
  84
  85 #define IGC_ALARM_INTERVAL      8000000u
  86 /* us, about 13.6s some per-queue registers will wrap around back to 0. */
  87
  88 static const struct rte_eth_desc_lim rx_desc_lim = {
  89         .nb_max = IGC_MAX_RXD,
  90         .nb_min = IGC_MIN_RXD,
  91         .nb_align = IGC_RXD_ALIGN,
  92 };
  93
  94 static const struct rte_eth_desc_lim tx_desc_lim = {
  95         .nb_max = IGC_MAX_TXD,
  96         .nb_min = IGC_MIN_TXD,
  97         .nb_align = IGC_TXD_ALIGN,
  98         .nb_seg_max = IGC_TX_MAX_SEG,
  99         .nb_mtu_seg_max = IGC_TX_MAX_MTU_SEG,
 100 };
 101
 102 static const struct rte_pci_id pci_id_igc_map[] = {
 103         { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_LM) },
 104         { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_V)  },
 105         { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_I)  },
 106         { RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_K)  },
 107         { .vendor_id = 0, /* sentinel */ },
 108 };
 109
 110 /* store statistics names and its offset in stats structure */
 111 struct rte_igc_xstats_name_off {
 112         char name[RTE_ETH_XSTATS_NAME_SIZE];
 113         unsigned int offset;
 114 };
 115
 116 static const struct rte_igc_xstats_name_off rte_igc_stats_strings[] = {
 117         {"rx_crc_errors", offsetof(struct igc_hw_stats, crcerrs)},
 118         {"rx_align_errors", offsetof(struct igc_hw_stats, algnerrc)},
 119         {"rx_errors", offsetof(struct igc_hw_stats, rxerrc)},
 120         {"rx_missed_packets", offsetof(struct igc_hw_stats, mpc)},
 121         {"tx_single_collision_packets", offsetof(struct igc_hw_stats, scc)},
 122         {"tx_multiple_collision_packets", offsetof(struct igc_hw_stats, mcc)},
 123         {"tx_excessive_collision_packets", offsetof(struct igc_hw_stats,
 124                 ecol)},
 125         {"tx_late_collisions", offsetof(struct igc_hw_stats, latecol)},
 126         {"tx_total_collisions", offsetof(struct igc_hw_stats, colc)},
 127         {"tx_deferred_packets", offsetof(struct igc_hw_stats, dc)},
 128         {"tx_no_carrier_sense_packets", offsetof(struct igc_hw_stats, tncrs)},
 129         {"tx_discarded_packets", offsetof(struct igc_hw_stats, htdpmc)},
 130         {"rx_length_errors", offsetof(struct igc_hw_stats, rlec)},
 131         {"rx_xon_packets", offsetof(struct igc_hw_stats, xonrxc)},
 132         {"tx_xon_packets", offsetof(struct igc_hw_stats, xontxc)},
 133         {"rx_xoff_packets", offsetof(struct igc_hw_stats, xoffrxc)},
 134         {"tx_xoff_packets", offsetof(struct igc_hw_stats, xofftxc)},
 135         {"rx_flow_control_unsupported_packets", offsetof(struct igc_hw_stats,
 136                 fcruc)},
 137         {"rx_size_64_packets", offsetof(struct igc_hw_stats, prc64)},
 138         {"rx_size_65_to_127_packets", offsetof(struct igc_hw_stats, prc127)},
 139         {"rx_size_128_to_255_packets", offsetof(struct igc_hw_stats, prc255)},
 140         {"rx_size_256_to_511_packets", offsetof(struct igc_hw_stats, prc511)},
 141         {"rx_size_512_to_1023_packets", offsetof(struct igc_hw_stats,
 142                 prc1023)},
 143         {"rx_size_1024_to_max_packets", offsetof(struct igc_hw_stats,
 144                 prc1522)},
 145         {"rx_broadcast_packets", offsetof(struct igc_hw_stats, bprc)},
 146         {"rx_multicast_packets", offsetof(struct igc_hw_stats, mprc)},
 147         {"rx_undersize_errors", offsetof(struct igc_hw_stats, ruc)},
 148         {"rx_fragment_errors", offsetof(struct igc_hw_stats, rfc)},
 149         {"rx_oversize_errors", offsetof(struct igc_hw_stats, roc)},
 150         {"rx_jabber_errors", offsetof(struct igc_hw_stats, rjc)},
 151         {"rx_no_buffers", offsetof(struct igc_hw_stats, rnbc)},
 152         {"rx_management_packets", offsetof(struct igc_hw_stats, mgprc)},
 153         {"rx_management_dropped", offsetof(struct igc_hw_stats, mgpdc)},
 154         {"tx_management_packets", offsetof(struct igc_hw_stats, mgptc)},
 155         {"rx_total_packets", offsetof(struct igc_hw_stats, tpr)},
 156         {"tx_total_packets", offsetof(struct igc_hw_stats, tpt)},
 157         {"rx_total_bytes", offsetof(struct igc_hw_stats, tor)},
 158         {"tx_total_bytes", offsetof(struct igc_hw_stats, tot)},
 159         {"tx_size_64_packets", offsetof(struct igc_hw_stats, ptc64)},
 160         {"tx_size_65_to_127_packets", offsetof(struct igc_hw_stats, ptc127)},
 161         {"tx_size_128_to_255_packets", offsetof(struct igc_hw_stats, ptc255)},
 162         {"tx_size_256_to_511_packets", offsetof(struct igc_hw_stats, ptc511)},
 163         {"tx_size_512_to_1023_packets", offsetof(struct igc_hw_stats,
 164                 ptc1023)},
 165         {"tx_size_1023_to_max_packets", offsetof(struct igc_hw_stats,
 166                 ptc1522)},
 167         {"tx_multicast_packets", offsetof(struct igc_hw_stats, mptc)},
 168         {"tx_broadcast_packets", offsetof(struct igc_hw_stats, bptc)},
 169         {"tx_tso_packets", offsetof(struct igc_hw_stats, tsctc)},
 170         {"rx_sent_to_host_packets", offsetof(struct igc_hw_stats, rpthc)},
 171         {"tx_sent_by_host_packets", offsetof(struct igc_hw_stats, hgptc)},
 172         {"interrupt_assert_count", offsetof(struct igc_hw_stats, iac)},
 173         {"rx_descriptor_lower_threshold",
 174                 offsetof(struct igc_hw_stats, icrxdmtc)},
 175 };
 176
 177 #define IGC_NB_XSTATS (sizeof(rte_igc_stats_strings) / \
 178                 sizeof(rte_igc_stats_strings[0]))
 179
 180 static int eth_igc_configure(struct rte_eth_dev *dev);
 181 static int eth_igc_link_update(struct rte_eth_dev *dev, int wait_to_complete);
 182 static int eth_igc_stop(struct rte_eth_dev *dev);
 183 static int eth_igc_start(struct rte_eth_dev *dev);
 184 static int eth_igc_set_link_up(struct rte_eth_dev *dev);
 185 static int eth_igc_set_link_down(struct rte_eth_dev *dev);
 186 static int eth_igc_close(struct rte_eth_dev *dev);
 187 static int eth_igc_reset(struct rte_eth_dev *dev);
 188 static int eth_igc_promiscuous_enable(struct rte_eth_dev *dev);
 189 static int eth_igc_promiscuous_disable(struct rte_eth_dev *dev);
 190 static int eth_igc_fw_version_get(struct rte_eth_dev *dev,
 191                                 char *fw_version, size_t fw_size);
 192 static int eth_igc_infos_get(struct rte_eth_dev *dev,
 193                         struct rte_eth_dev_info *dev_info);
 194 static int eth_igc_led_on(struct rte_eth_dev *dev);
 195 static int eth_igc_led_off(struct rte_eth_dev *dev);
 196 static const uint32_t *eth_igc_supported_ptypes_get(struct rte_eth_dev *dev);
 197 static int eth_igc_rar_set(struct rte_eth_dev *dev,
 198                 struct rte_ether_addr *mac_addr, uint32_t index, uint32_t pool);
 199 static void eth_igc_rar_clear(struct rte_eth_dev *dev, uint32_t index);
 200 static int eth_igc_default_mac_addr_set(struct rte_eth_dev *dev,
 201                         struct rte_ether_addr *addr);
 202 static int eth_igc_set_mc_addr_list(struct rte_eth_dev *dev,
 203                          struct rte_ether_addr *mc_addr_set,
 204                          uint32_t nb_mc_addr);
 205 static int eth_igc_allmulticast_enable(struct rte_eth_dev *dev);
 206 static int eth_igc_allmulticast_disable(struct rte_eth_dev *dev);
 207 static int eth_igc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 208 static int eth_igc_stats_get(struct rte_eth_dev *dev,
 209                         struct rte_eth_stats *rte_stats);
 210 static int eth_igc_xstats_get(struct rte_eth_dev *dev,
 211                         struct rte_eth_xstat *xstats, unsigned int n);
 212 static int eth_igc_xstats_get_by_id(struct rte_eth_dev *dev,
 213                                 const uint64_t *ids,
 214                                 uint64_t *values, unsigned int n);
 215 static int eth_igc_xstats_get_names(struct rte_eth_dev *dev,
 216                                 struct rte_eth_xstat_name *xstats_names,
 217                                 unsigned int size);
 218 static int eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,
 219                 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names,
 220                 unsigned int limit);
 221 static int eth_igc_xstats_reset(struct rte_eth_dev *dev);
 222 static int
 223 eth_igc_queue_stats_mapping_set(struct rte_eth_dev *dev,
 224         uint16_t queue_id, uint8_t stat_idx, uint8_t is_rx);
 225 static int
 226 eth_igc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 227 static int
 228 eth_igc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 229 static int
 230 eth_igc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
 231 static int
 232 eth_igc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf);
 233 static int eth_igc_rss_reta_update(struct rte_eth_dev *dev,
 234                         struct rte_eth_rss_reta_entry64 *reta_conf,
 235                         uint16_t reta_size);
 236 static int eth_igc_rss_reta_query(struct rte_eth_dev *dev,
 237                        struct rte_eth_rss_reta_entry64 *reta_conf,
 238                        uint16_t reta_size);
 239 static int eth_igc_rss_hash_update(struct rte_eth_dev *dev,
 240                         struct rte_eth_rss_conf *rss_conf);
 241 static int eth_igc_rss_hash_conf_get(struct rte_eth_dev *dev,
 242                         struct rte_eth_rss_conf *rss_conf);
 243 static int
 244 eth_igc_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on);
 245 static int eth_igc_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 246 static int eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
 247                       enum rte_vlan_type vlan_type, uint16_t tpid);
 248
 249 static const struct eth_dev_ops eth_igc_ops = {
 250         .dev_configure          = eth_igc_configure,
 251         .link_update            = eth_igc_link_update,
 252         .dev_stop               = eth_igc_stop,
 253         .dev_start              = eth_igc_start,
 254         .dev_close              = eth_igc_close,
 255         .dev_reset              = eth_igc_reset,
 256         .dev_set_link_up        = eth_igc_set_link_up,
 257         .dev_set_link_down      = eth_igc_set_link_down,
 258         .promiscuous_enable     = eth_igc_promiscuous_enable,
 259         .promiscuous_disable    = eth_igc_promiscuous_disable,
 260         .allmulticast_enable    = eth_igc_allmulticast_enable,
 261         .allmulticast_disable   = eth_igc_allmulticast_disable,
 262         .fw_version_get         = eth_igc_fw_version_get,
 263         .dev_infos_get          = eth_igc_infos_get,
 264         .dev_led_on             = eth_igc_led_on,
 265         .dev_led_off            = eth_igc_led_off,
 266         .dev_supported_ptypes_get = eth_igc_supported_ptypes_get,
 267         .mtu_set                = eth_igc_mtu_set,
 268         .mac_addr_add           = eth_igc_rar_set,
 269         .mac_addr_remove        = eth_igc_rar_clear,
 270         .mac_addr_set           = eth_igc_default_mac_addr_set,
 271         .set_mc_addr_list       = eth_igc_set_mc_addr_list,
 272
 273         .rx_queue_setup         = eth_igc_rx_queue_setup,
 274         .rx_queue_release       = eth_igc_rx_queue_release,
 275         .tx_queue_setup         = eth_igc_tx_queue_setup,
 276         .tx_queue_release       = eth_igc_tx_queue_release,
 277         .tx_done_cleanup        = eth_igc_tx_done_cleanup,
 278         .rxq_info_get           = eth_igc_rxq_info_get,
 279         .txq_info_get           = eth_igc_txq_info_get,
 280         .stats_get              = eth_igc_stats_get,
 281         .xstats_get             = eth_igc_xstats_get,
 282         .xstats_get_by_id       = eth_igc_xstats_get_by_id,
 283         .xstats_get_names_by_id = eth_igc_xstats_get_names_by_id,
 284         .xstats_get_names       = eth_igc_xstats_get_names,
 285         .stats_reset            = eth_igc_xstats_reset,
 286         .xstats_reset           = eth_igc_xstats_reset,
 287         .queue_stats_mapping_set = eth_igc_queue_stats_mapping_set,
 288         .rx_queue_intr_enable   = eth_igc_rx_queue_intr_enable,
 289         .rx_queue_intr_disable  = eth_igc_rx_queue_intr_disable,
 290         .flow_ctrl_get          = eth_igc_flow_ctrl_get,
 291         .flow_ctrl_set          = eth_igc_flow_ctrl_set,
 292         .reta_update            = eth_igc_rss_reta_update,
 293         .reta_query             = eth_igc_rss_reta_query,
 294         .rss_hash_update        = eth_igc_rss_hash_update,
 295         .rss_hash_conf_get      = eth_igc_rss_hash_conf_get,
 296         .vlan_filter_set        = eth_igc_vlan_filter_set,
 297         .vlan_offload_set       = eth_igc_vlan_offload_set,
 298         .vlan_tpid_set          = eth_igc_vlan_tpid_set,
 299         .vlan_strip_queue_set   = eth_igc_vlan_strip_queue_set,
 300         .flow_ops_get           = eth_igc_flow_ops_get,
 301 };
 302
 303 /*
 304  * multiple queue mode checking
 305  */
 306 static int
 307 igc_check_mq_mode(struct rte_eth_dev *dev)
 308 {
 309         enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 310         enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
 311
 312         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
 313                 PMD_INIT_LOG(ERR, "SRIOV is not supported.");
 314                 return -EINVAL;
 315         }
 316
 317         if (rx_mq_mode != ETH_MQ_RX_NONE &&
 318                 rx_mq_mode != ETH_MQ_RX_RSS) {
 319                 /* RSS together with VMDq not supported*/
 320                 PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
 321                                 rx_mq_mode);
 322                 return -EINVAL;
 323         }
 324
 325         /* To no break software that set invalid mode, only display
 326          * warning if invalid mode is used.
 327          */
 328         if (tx_mq_mode != ETH_MQ_TX_NONE)
 329                 PMD_INIT_LOG(WARNING,
 330                         "TX mode %d is not supported. Due to meaningless in this driver, just ignore",
 331                         tx_mq_mode);
 332
 333         return 0;
 334 }
 335
 336 static int
 337 eth_igc_configure(struct rte_eth_dev *dev)
 338 {
 339         struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
 340         int ret;
 341
 342         PMD_INIT_FUNC_TRACE();
 343
 344         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
 345                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
 346
 347         ret  = igc_check_mq_mode(dev);
 348         if (ret != 0)
 349                 return ret;
 350
 351         intr->flags |= IGC_FLAG_NEED_LINK_UPDATE;
 352         return 0;
 353 }
 354
 355 static int
 356 eth_igc_set_link_up(struct rte_eth_dev *dev)
 357 {
 358         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 359
 360         if (hw->phy.media_type == igc_media_type_copper)
 361                 igc_power_up_phy(hw);
 362         else
 363                 igc_power_up_fiber_serdes_link(hw);
 364         return 0;
 365 }
 366
 367 static int
 368 eth_igc_set_link_down(struct rte_eth_dev *dev)
 369 {
 370         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 371
 372         if (hw->phy.media_type == igc_media_type_copper)
 373                 igc_power_down_phy(hw);
 374         else
 375                 igc_shutdown_fiber_serdes_link(hw);
 376         return 0;
 377 }
 378
 379 /*
 380  * disable other interrupt
 381  */
 382 static void
 383 igc_intr_other_disable(struct rte_eth_dev *dev)
 384 {
 385         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 386         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 387         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 388
 389         if (rte_intr_allow_others(intr_handle) &&
 390                 dev->data->dev_conf.intr_conf.lsc) {
 391                 IGC_WRITE_REG(hw, IGC_EIMC, 1u << IGC_MSIX_OTHER_INTR_VEC);
 392         }
 393
 394         IGC_WRITE_REG(hw, IGC_IMC, ~0);
 395         IGC_WRITE_FLUSH(hw);
 396 }
 397
 398 /*
 399  * enable other interrupt
 400  */
 401 static inline void
 402 igc_intr_other_enable(struct rte_eth_dev *dev)
 403 {
 404         struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
 405         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 406         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 407         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 408
 409         if (rte_intr_allow_others(intr_handle) &&
 410                 dev->data->dev_conf.intr_conf.lsc) {
 411                 IGC_WRITE_REG(hw, IGC_EIMS, 1u << IGC_MSIX_OTHER_INTR_VEC);
 412         }
 413
 414         IGC_WRITE_REG(hw, IGC_IMS, intr->mask);
 415         IGC_WRITE_FLUSH(hw);
 416 }
 417
 418 /*
 419  * It reads ICR and gets interrupt causes, check it and set a bit flag
 420  * to update link status.
 421  */
 422 static void
 423 eth_igc_interrupt_get_status(struct rte_eth_dev *dev)
 424 {
 425         uint32_t icr;
 426         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 427         struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
 428
 429         /* read-on-clear nic registers here */
 430         icr = IGC_READ_REG(hw, IGC_ICR);
 431
 432         intr->flags = 0;
 433         if (icr & IGC_ICR_LSC)
 434                 intr->flags |= IGC_FLAG_NEED_LINK_UPDATE;
 435 }
 436
 437 /* return 0 means link status changed, -1 means not changed */
 438 static int
 439 eth_igc_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 440 {
 441         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 442         struct rte_eth_link link;
 443         int link_check, count;
 444
 445         link_check = 0;
 446         hw->mac.get_link_status = 1;
 447
 448         /* possible wait-to-complete in up to 9 seconds */
 449         for (count = 0; count < IGC_LINK_UPDATE_CHECK_TIMEOUT; count++) {
 450                 /* Read the real link status */
 451                 switch (hw->phy.media_type) {
 452                 case igc_media_type_copper:
 453                         /* Do the work to read phy */
 454                         igc_check_for_link(hw);
 455                         link_check = !hw->mac.get_link_status;
 456                         break;
 457
 458                 case igc_media_type_fiber:
 459                         igc_check_for_link(hw);
 460                         link_check = (IGC_READ_REG(hw, IGC_STATUS) &
 461                                       IGC_STATUS_LU);
 462                         break;
 463
 464                 case igc_media_type_internal_serdes:
 465                         igc_check_for_link(hw);
 466                         link_check = hw->mac.serdes_has_link;
 467                         break;
 468
 469                 default:
 470                         break;
 471                 }
 472                 if (link_check || wait_to_complete == 0)
 473                         break;
 474                 rte_delay_ms(IGC_LINK_UPDATE_CHECK_INTERVAL);
 475         }
 476         memset(&link, 0, sizeof(link));
 477
 478         /* Now we check if a transition has happened */
 479         if (link_check) {
 480                 uint16_t duplex, speed;
 481                 hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
 482                 link.link_duplex = (duplex == FULL_DUPLEX) ?
 483                                 ETH_LINK_FULL_DUPLEX :
 484                                 ETH_LINK_HALF_DUPLEX;
 485                 link.link_speed = speed;
 486                 link.link_status = ETH_LINK_UP;
 487                 link.link_autoneg = !(dev->data->dev_conf.link_speeds &
 488                                 ETH_LINK_SPEED_FIXED);
 489
 490                 if (speed == SPEED_2500) {
 491                         uint32_t tipg = IGC_READ_REG(hw, IGC_TIPG);
 492                         if ((tipg & IGC_TIPG_IPGT_MASK) != 0x0b) {
 493                                 tipg &= ~IGC_TIPG_IPGT_MASK;
 494                                 tipg |= 0x0b;
 495                                 IGC_WRITE_REG(hw, IGC_TIPG, tipg);
 496                         }
 497                 }
 498         } else {
 499                 link.link_speed = 0;
 500                 link.link_duplex = ETH_LINK_HALF_DUPLEX;
 501                 link.link_status = ETH_LINK_DOWN;
 502                 link.link_autoneg = ETH_LINK_FIXED;
 503         }
 504
 505         return rte_eth_linkstatus_set(dev, &link);
 506 }
 507
 508 /*
 509  * It executes link_update after knowing an interrupt is present.
 510  */
 511 static void
 512 eth_igc_interrupt_action(struct rte_eth_dev *dev)
 513 {
 514         struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
 515         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 516         struct rte_eth_link link;
 517         int ret;
 518
 519         if (intr->flags & IGC_FLAG_NEED_LINK_UPDATE) {
 520                 intr->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
 521
 522                 /* set get_link_status to check register later */
 523                 ret = eth_igc_link_update(dev, 0);
 524
 525                 /* check if link has changed */
 526                 if (ret < 0)
 527                         return;
 528
 529                 rte_eth_linkstatus_get(dev, &link);
 530                 if (link.link_status)
 531                         PMD_DRV_LOG(INFO,
 532                                 " Port %d: Link Up - speed %u Mbps - %s",
 533                                 dev->data->port_id,
 534                                 (unsigned int)link.link_speed,
 535                                 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
 536                                 "full-duplex" : "half-duplex");
 537                 else
 538                         PMD_DRV_LOG(INFO, " Port %d: Link Down",
 539                                 dev->data->port_id);
 540
 541                 PMD_DRV_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
 542                                 pci_dev->addr.domain,
 543                                 pci_dev->addr.bus,
 544                                 pci_dev->addr.devid,
 545                                 pci_dev->addr.function);
 546                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
 547         }
 548 }
 549
 550 /*
 551  * Interrupt handler which shall be registered at first.
 552  *
 553  * @handle
 554  *  Pointer to interrupt handle.
 555  * @param
 556  *  The address of parameter (struct rte_eth_dev *) registered before.
 557  */
 558 static void
 559 eth_igc_interrupt_handler(void *param)
 560 {
 561         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
 562
 563         eth_igc_interrupt_get_status(dev);
 564         eth_igc_interrupt_action(dev);
 565 }
 566
 567 static void igc_read_queue_stats_register(struct rte_eth_dev *dev);
 568
 569 /*
 570  * Update the queue status every IGC_ALARM_INTERVAL time.
 571  * @param
 572  *  The address of parameter (struct rte_eth_dev *) registered before.
 573  */
 574 static void
 575 igc_update_queue_stats_handler(void *param)
 576 {
 577         struct rte_eth_dev *dev = param;
 578         igc_read_queue_stats_register(dev);
 579         rte_eal_alarm_set(IGC_ALARM_INTERVAL,
 580                         igc_update_queue_stats_handler, dev);
 581 }
 582
 583 /*
 584  * rx,tx enable/disable
 585  */
 586 static void
 587 eth_igc_rxtx_control(struct rte_eth_dev *dev, bool enable)
 588 {
 589         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 590         uint32_t tctl, rctl;
 591
 592         tctl = IGC_READ_REG(hw, IGC_TCTL);
 593         rctl = IGC_READ_REG(hw, IGC_RCTL);
 594
 595         if (enable) {
 596                 /* enable Tx/Rx */
 597                 tctl |= IGC_TCTL_EN;
 598                 rctl |= IGC_RCTL_EN;
 599         } else {
 600                 /* disable Tx/Rx */
 601                 tctl &= ~IGC_TCTL_EN;
 602                 rctl &= ~IGC_RCTL_EN;
 603         }
 604         IGC_WRITE_REG(hw, IGC_TCTL, tctl);
 605         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
 606         IGC_WRITE_FLUSH(hw);
 607 }
 608
 609 /*
 610  *  This routine disables all traffic on the adapter by issuing a
 611  *  global reset on the MAC.
 612  */
 613 static int
 614 eth_igc_stop(struct rte_eth_dev *dev)
 615 {
 616         struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
 617         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 618         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 619         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 620         struct rte_eth_link link;
 621
 622         dev->data->dev_started = 0;
 623         adapter->stopped = 1;
 624
 625         /* disable receive and transmit */
 626         eth_igc_rxtx_control(dev, false);
 627
 628         /* disable all MSI-X interrupts */
 629         IGC_WRITE_REG(hw, IGC_EIMC, 0x1f);
 630         IGC_WRITE_FLUSH(hw);
 631
 632         /* clear all MSI-X interrupts */
 633         IGC_WRITE_REG(hw, IGC_EICR, 0x1f);
 634
 635         igc_intr_other_disable(dev);
 636
 637         rte_eal_alarm_cancel(igc_update_queue_stats_handler, dev);
 638
 639         /* disable intr eventfd mapping */
 640         rte_intr_disable(intr_handle);
 641
 642         igc_reset_hw(hw);
 643
 644         /* disable all wake up */
 645         IGC_WRITE_REG(hw, IGC_WUC, 0);
 646
 647         /* disable checking EEE operation in MAC loopback mode */
 648         igc_read_reg_check_clear_bits(hw, IGC_EEER, IGC_EEER_EEE_FRC_AN);
 649
 650         /* Set bit for Go Link disconnect */
 651         igc_read_reg_check_set_bits(hw, IGC_82580_PHY_POWER_MGMT,
 652                         IGC_82580_PM_GO_LINKD);
 653
 654         /* Power down the phy. Needed to make the link go Down */
 655         eth_igc_set_link_down(dev);
 656
 657         igc_dev_clear_queues(dev);
 658
 659         /* clear the recorded link status */
 660         memset(&link, 0, sizeof(link));
 661         rte_eth_linkstatus_set(dev, &link);
 662
 663         if (!rte_intr_allow_others(intr_handle))
 664                 /* resume to the default handler */
 665                 rte_intr_callback_register(intr_handle,
 666                                            eth_igc_interrupt_handler,
 667                                            (void *)dev);
 668
 669         /* Clean datapath event and queue/vec mapping */
 670         rte_intr_efd_disable(intr_handle);
 671         if (intr_handle->intr_vec != NULL) {
 672                 rte_free(intr_handle->intr_vec);
 673                 intr_handle->intr_vec = NULL;
 674         }
 675
 676         return 0;
 677 }
 678
 679 /*
 680  * write interrupt vector allocation register
 681  * @hw
 682  *  board private structure
 683  * @queue_index
 684  *  queue index, valid 0,1,2,3
 685  * @tx
 686  *  tx:1, rx:0
 687  * @msix_vector
 688  *  msix-vector, valid 0,1,2,3,4
 689  */
 690 static void
 691 igc_write_ivar(struct igc_hw *hw, uint8_t queue_index,
 692                 bool tx, uint8_t msix_vector)
 693 {
 694         uint8_t offset = 0;
 695         uint8_t reg_index = queue_index >> 1;
 696         uint32_t val;
 697
 698         /*
 699          * IVAR(0)
 700          * bit31...24   bit23...16      bit15...8       bit7...0
 701          * TX1          RX1             TX0             RX0
 702          *
 703          * IVAR(1)
 704          * bit31...24   bit23...16      bit15...8       bit7...0
 705          * TX3          RX3             TX2             RX2
 706          */
 707
 708         if (tx)
 709                 offset = 8;
 710
 711         if (queue_index & 1)
 712                 offset += 16;
 713
 714         val = IGC_READ_REG_ARRAY(hw, IGC_IVAR0, reg_index);
 715
 716         /* clear bits */
 717         val &= ~((uint32_t)0xFF << offset);
 718
 719         /* write vector and valid bit */
 720         val |= (uint32_t)(msix_vector | IGC_IVAR_VALID) << offset;
 721
 722         IGC_WRITE_REG_ARRAY(hw, IGC_IVAR0, reg_index, val);
 723 }
 724
 725 /* Sets up the hardware to generate MSI-X interrupts properly
 726  * @hw
 727  *  board private structure
 728  */
 729 static void
 730 igc_configure_msix_intr(struct rte_eth_dev *dev)
 731 {
 732         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 733         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 734         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 735
 736         uint32_t intr_mask;
 737         uint32_t vec = IGC_MISC_VEC_ID;
 738         uint32_t base = IGC_MISC_VEC_ID;
 739         uint32_t misc_shift = 0;
 740         int i;
 741
 742         /* won't configure msix register if no mapping is done
 743          * between intr vector and event fd
 744          */
 745         if (!rte_intr_dp_is_en(intr_handle))
 746                 return;
 747
 748         if (rte_intr_allow_others(intr_handle)) {
 749                 base = IGC_RX_VEC_START;
 750                 vec = base;
 751                 misc_shift = 1;
 752         }
 753
 754         /* turn on MSI-X capability first */
 755         IGC_WRITE_REG(hw, IGC_GPIE, IGC_GPIE_MSIX_MODE |
 756                                 IGC_GPIE_PBA | IGC_GPIE_EIAME |
 757                                 IGC_GPIE_NSICR);
 758         intr_mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) <<
 759                 misc_shift;
 760
 761         if (dev->data->dev_conf.intr_conf.lsc)
 762                 intr_mask |= (1u << IGC_MSIX_OTHER_INTR_VEC);
 763
 764         /* enable msix auto-clear */
 765         igc_read_reg_check_set_bits(hw, IGC_EIAC, intr_mask);
 766
 767         /* set other cause interrupt vector */
 768         igc_read_reg_check_set_bits(hw, IGC_IVAR_MISC,
 769                 (uint32_t)(IGC_MSIX_OTHER_INTR_VEC | IGC_IVAR_VALID) << 8);
 770
 771         /* enable auto-mask */
 772         igc_read_reg_check_set_bits(hw, IGC_EIAM, intr_mask);
 773
 774         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 775                 igc_write_ivar(hw, i, 0, vec);
 776                 intr_handle->intr_vec[i] = vec;
 777                 if (vec < base + intr_handle->nb_efd - 1)
 778                         vec++;
 779         }
 780
 781         IGC_WRITE_FLUSH(hw);
 782 }
 783
 784 /**
 785  * It enables the interrupt mask and then enable the interrupt.
 786  *
 787  * @dev
 788  *  Pointer to struct rte_eth_dev.
 789  * @on
 790  *  Enable or Disable
 791  */
 792 static void
 793 igc_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
 794 {
 795         struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
 796
 797         if (on)
 798                 intr->mask |= IGC_ICR_LSC;
 799         else
 800                 intr->mask &= ~IGC_ICR_LSC;
 801 }
 802
 803 /*
 804  * It enables the interrupt.
 805  * It will be called once only during nic initialized.
 806  */
 807 static void
 808 igc_rxq_interrupt_setup(struct rte_eth_dev *dev)
 809 {
 810         uint32_t mask;
 811         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 812         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 813         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 814         int misc_shift = rte_intr_allow_others(intr_handle) ? 1 : 0;
 815
 816         /* won't configure msix register if no mapping is done
 817          * between intr vector and event fd
 818          */
 819         if (!rte_intr_dp_is_en(intr_handle))
 820                 return;
 821
 822         mask = RTE_LEN2MASK(intr_handle->nb_efd, uint32_t) << misc_shift;
 823         IGC_WRITE_REG(hw, IGC_EIMS, mask);
 824 }
 825
 826 /*
 827  *  Get hardware rx-buffer size.
 828  */
 829 static inline int
 830 igc_get_rx_buffer_size(struct igc_hw *hw)
 831 {
 832         return (IGC_READ_REG(hw, IGC_RXPBS) & 0x3f) << 10;
 833 }
 834
 835 /*
 836  * igc_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
 837  * For ASF and Pass Through versions of f/w this means
 838  * that the driver is loaded.
 839  */
 840 static void
 841 igc_hw_control_acquire(struct igc_hw *hw)
 842 {
 843         uint32_t ctrl_ext;
 844
 845         /* Let firmware know the driver has taken over */
 846         ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
 847         IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
 848 }
 849
 850 /*
 851  * igc_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
 852  * For ASF and Pass Through versions of f/w this means that the
 853  * driver is no longer loaded.
 854  */
 855 static void
 856 igc_hw_control_release(struct igc_hw *hw)
 857 {
 858         uint32_t ctrl_ext;
 859
 860         /* Let firmware taken over control of h/w */
 861         ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
 862         IGC_WRITE_REG(hw, IGC_CTRL_EXT,
 863                         ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
 864 }
 865
 866 static int
 867 igc_hardware_init(struct igc_hw *hw)
 868 {
 869         uint32_t rx_buf_size;
 870         int diag;
 871
 872         /* Let the firmware know the OS is in control */
 873         igc_hw_control_acquire(hw);
 874
 875         /* Issue a global reset */
 876         igc_reset_hw(hw);
 877
 878         /* disable all wake up */
 879         IGC_WRITE_REG(hw, IGC_WUC, 0);
 880
 881         /*
 882          * Hardware flow control
 883          * - High water mark should allow for at least two standard size (1518)
 884          *   frames to be received after sending an XOFF.
 885          * - Low water mark works best when it is very near the high water mark.
 886          *   This allows the receiver to restart by sending XON when it has
 887          *   drained a bit. Here we use an arbitrary value of 1500 which will
 888          *   restart after one full frame is pulled from the buffer. There
 889          *   could be several smaller frames in the buffer and if so they will
 890          *   not trigger the XON until their total number reduces the buffer
 891          *   by 1500.
 892          */
 893         rx_buf_size = igc_get_rx_buffer_size(hw);
 894         hw->fc.high_water = rx_buf_size - (RTE_ETHER_MAX_LEN * 2);
 895         hw->fc.low_water = hw->fc.high_water - 1500;
 896         hw->fc.pause_time = IGC_FC_PAUSE_TIME;
 897         hw->fc.send_xon = 1;
 898         hw->fc.requested_mode = igc_fc_full;
 899
 900         diag = igc_init_hw(hw);
 901         if (diag < 0)
 902                 return diag;
 903
 904         igc_get_phy_info(hw);
 905         igc_check_for_link(hw);
 906
 907         return 0;
 908 }
 909
 910 static int
 911 eth_igc_start(struct rte_eth_dev *dev)
 912 {
 913         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
 914         struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
 915         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 916         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 917         uint32_t *speeds;
 918         int ret;
 919
 920         PMD_INIT_FUNC_TRACE();
 921
 922         /* disable all MSI-X interrupts */
 923         IGC_WRITE_REG(hw, IGC_EIMC, 0x1f);
 924         IGC_WRITE_FLUSH(hw);
 925
 926         /* clear all MSI-X interrupts */
 927         IGC_WRITE_REG(hw, IGC_EICR, 0x1f);
 928
 929         /* disable uio/vfio intr/eventfd mapping */
 930         if (!adapter->stopped)
 931                 rte_intr_disable(intr_handle);
 932
 933         /* Power up the phy. Needed to make the link go Up */
 934         eth_igc_set_link_up(dev);
 935
 936         /* Put the address into the Receive Address Array */
 937         igc_rar_set(hw, hw->mac.addr, 0);
 938
 939         /* Initialize the hardware */
 940         if (igc_hardware_init(hw)) {
 941                 PMD_DRV_LOG(ERR, "Unable to initialize the hardware");
 942                 return -EIO;
 943         }
 944         adapter->stopped = 0;
 945
 946         /* check and configure queue intr-vector mapping */
 947         if (rte_intr_cap_multiple(intr_handle) &&
 948                 dev->data->dev_conf.intr_conf.rxq) {
 949                 uint32_t intr_vector = dev->data->nb_rx_queues;
 950                 if (rte_intr_efd_enable(intr_handle, intr_vector))
 951                         return -1;
 952         }
 953
 954         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
 955                 intr_handle->intr_vec = rte_zmalloc("intr_vec",
 956                         dev->data->nb_rx_queues * sizeof(int), 0);
 957                 if (intr_handle->intr_vec == NULL) {
 958                         PMD_DRV_LOG(ERR,
 959                                 "Failed to allocate %d rx_queues intr_vec",
 960                                 dev->data->nb_rx_queues);
 961                         return -ENOMEM;
 962                 }
 963         }
 964
 965         /* configure msix for rx interrupt */
 966         igc_configure_msix_intr(dev);
 967
 968         igc_tx_init(dev);
 969
 970         /* This can fail when allocating mbufs for descriptor rings */
 971         ret = igc_rx_init(dev);
 972         if (ret) {
 973                 PMD_DRV_LOG(ERR, "Unable to initialize RX hardware");
 974                 igc_dev_clear_queues(dev);
 975                 return ret;
 976         }
 977
 978         igc_clear_hw_cntrs_base_generic(hw);
 979
 980         /* VLAN Offload Settings */
 981         eth_igc_vlan_offload_set(dev,
 982                 ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
 983                 ETH_VLAN_EXTEND_MASK);
 984
 985         /* Setup link speed and duplex */
 986         speeds = &dev->data->dev_conf.link_speeds;
 987         if (*speeds == ETH_LINK_SPEED_AUTONEG) {
 988                 hw->phy.autoneg_advertised = IGC_ALL_SPEED_DUPLEX_2500;
 989                 hw->mac.autoneg = 1;
 990         } else {
 991                 int num_speeds = 0;
 992
 993                 if (*speeds & ETH_LINK_SPEED_FIXED) {
 994                         PMD_DRV_LOG(ERR,
 995                                     "Force speed mode currently not supported");
 996                         igc_dev_clear_queues(dev);
 997                         return -EINVAL;
 998                 }
 999
1000                 hw->phy.autoneg_advertised = 0;
1001                 hw->mac.autoneg = 1;
1002
1003                 if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1004                                 ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1005                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G)) {
1006                         num_speeds = -1;
1007                         goto error_invalid_config;
1008                 }
1009                 if (*speeds & ETH_LINK_SPEED_10M_HD) {
1010                         hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
1011                         num_speeds++;
1012                 }
1013                 if (*speeds & ETH_LINK_SPEED_10M) {
1014                         hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
1015                         num_speeds++;
1016                 }
1017                 if (*speeds & ETH_LINK_SPEED_100M_HD) {
1018                         hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
1019                         num_speeds++;
1020                 }
1021                 if (*speeds & ETH_LINK_SPEED_100M) {
1022                         hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
1023                         num_speeds++;
1024                 }
1025                 if (*speeds & ETH_LINK_SPEED_1G) {
1026                         hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
1027                         num_speeds++;
1028                 }
1029                 if (*speeds & ETH_LINK_SPEED_2_5G) {
1030                         hw->phy.autoneg_advertised |= ADVERTISE_2500_FULL;
1031                         num_speeds++;
1032                 }
1033                 if (num_speeds == 0)
1034                         goto error_invalid_config;
1035         }
1036
1037         igc_setup_link(hw);
1038
1039         if (rte_intr_allow_others(intr_handle)) {
1040                 /* check if lsc interrupt is enabled */
1041                 if (dev->data->dev_conf.intr_conf.lsc)
1042                         igc_lsc_interrupt_setup(dev, 1);
1043                 else
1044                         igc_lsc_interrupt_setup(dev, 0);
1045         } else {
1046                 rte_intr_callback_unregister(intr_handle,
1047                                              eth_igc_interrupt_handler,
1048                                              (void *)dev);
1049                 if (dev->data->dev_conf.intr_conf.lsc)
1050                         PMD_DRV_LOG(INFO,
1051                                 "LSC won't enable because of no intr multiplex");
1052         }
1053
1054         /* enable uio/vfio intr/eventfd mapping */
1055         rte_intr_enable(intr_handle);
1056
1057         rte_eal_alarm_set(IGC_ALARM_INTERVAL,
1058                         igc_update_queue_stats_handler, dev);
1059
1060         /* check if rxq interrupt is enabled */
1061         if (dev->data->dev_conf.intr_conf.rxq &&
1062                         rte_intr_dp_is_en(intr_handle))
1063                 igc_rxq_interrupt_setup(dev);
1064
1065         /* resume enabled intr since hw reset */
1066         igc_intr_other_enable(dev);
1067
1068         eth_igc_rxtx_control(dev, true);
1069         eth_igc_link_update(dev, 0);
1070
1071         /* configure MAC-loopback mode */
1072         if (dev->data->dev_conf.lpbk_mode == 1) {
1073                 uint32_t reg_val;
1074
1075                 reg_val = IGC_READ_REG(hw, IGC_CTRL);
1076                 reg_val &= ~IGC_CTRL_SPEED_MASK;
1077                 reg_val |= IGC_CTRL_SLU | IGC_CTRL_FRCSPD |
1078                         IGC_CTRL_FRCDPX | IGC_CTRL_FD | IGC_CTRL_SPEED_2500;
1079                 IGC_WRITE_REG(hw, IGC_CTRL, reg_val);
1080
1081                 igc_read_reg_check_set_bits(hw, IGC_EEER, IGC_EEER_EEE_FRC_AN);
1082         }
1083
1084         return 0;
1085
1086 error_invalid_config:
1087         PMD_DRV_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
1088                      dev->data->dev_conf.link_speeds, dev->data->port_id);
1089         igc_dev_clear_queues(dev);
1090         return -EINVAL;
1091 }
1092
1093 static int
1094 igc_reset_swfw_lock(struct igc_hw *hw)
1095 {
1096         int ret_val;
1097
1098         /*
1099          * Do mac ops initialization manually here, since we will need
1100          * some function pointers set by this call.
1101          */
1102         ret_val = igc_init_mac_params(hw);
1103         if (ret_val)
1104                 return ret_val;
1105
1106         /*
1107          * SMBI lock should not fail in this early stage. If this is the case,
1108          * it is due to an improper exit of the application.
1109          * So force the release of the faulty lock.
1110          */
1111         if (igc_get_hw_semaphore_generic(hw) < 0)
1112                 PMD_DRV_LOG(DEBUG, "SMBI lock released");
1113
1114         igc_put_hw_semaphore_generic(hw);
1115
1116         if (hw->mac.ops.acquire_swfw_sync != NULL) {
1117                 uint16_t mask;
1118
1119                 /*
1120                  * Phy lock should not fail in this early stage.
1121                  * If this is the case, it is due to an improper exit of the
1122                  * application. So force the release of the faulty lock.
1123                  */
1124                 mask = IGC_SWFW_PHY0_SM;
1125                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0) {
1126                         PMD_DRV_LOG(DEBUG, "SWFW phy%d lock released",
1127                                     hw->bus.func);
1128                 }
1129                 hw->mac.ops.release_swfw_sync(hw, mask);
1130
1131                 /*
1132                  * This one is more tricky since it is common to all ports; but
1133                  * swfw_sync retries last long enough (1s) to be almost sure
1134                  * that if lock can not be taken it is due to an improper lock
1135                  * of the semaphore.
1136                  */
1137                 mask = IGC_SWFW_EEP_SM;
1138                 if (hw->mac.ops.acquire_swfw_sync(hw, mask) < 0)
1139                         PMD_DRV_LOG(DEBUG, "SWFW common locks released");
1140
1141                 hw->mac.ops.release_swfw_sync(hw, mask);
1142         }
1143
1144         return IGC_SUCCESS;
1145 }
1146
1147 /*
1148  * free all rx/tx queues.
1149  */
1150 static void
1151 igc_dev_free_queues(struct rte_eth_dev *dev)
1152 {
1153         uint16_t i;
1154
1155         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1156                 eth_igc_rx_queue_release(dev, i);
1157                 dev->data->rx_queues[i] = NULL;
1158         }
1159         dev->data->nb_rx_queues = 0;
1160
1161         for (i = 0; i < dev->data->nb_tx_queues; i++) {
1162                 eth_igc_tx_queue_release(dev, i);
1163                 dev->data->tx_queues[i] = NULL;
1164         }
1165         dev->data->nb_tx_queues = 0;
1166 }
1167
1168 static int
1169 eth_igc_close(struct rte_eth_dev *dev)
1170 {
1171         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1172         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1173         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1174         struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
1175         int retry = 0;
1176         int ret = 0;
1177
1178         PMD_INIT_FUNC_TRACE();
1179         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1180                 return 0;
1181
1182         if (!adapter->stopped)
1183                 ret = eth_igc_stop(dev);
1184
1185         igc_flow_flush(dev, NULL);
1186         igc_clear_all_filter(dev);
1187
1188         igc_intr_other_disable(dev);
1189         do {
1190                 int ret = rte_intr_callback_unregister(intr_handle,
1191                                 eth_igc_interrupt_handler, dev);
1192                 if (ret >= 0 || ret == -ENOENT || ret == -EINVAL)
1193                         break;
1194
1195                 PMD_DRV_LOG(ERR, "intr callback unregister failed: %d", ret);
1196                 DELAY(200 * 1000); /* delay 200ms */
1197         } while (retry++ < 5);
1198
1199         igc_phy_hw_reset(hw);
1200         igc_hw_control_release(hw);
1201         igc_dev_free_queues(dev);
1202
1203         /* Reset any pending lock */
1204         igc_reset_swfw_lock(hw);
1205
1206         return ret;
1207 }
1208
1209 static void
1210 igc_identify_hardware(struct rte_eth_dev *dev, struct rte_pci_device *pci_dev)
1211 {
1212         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1213
1214         hw->vendor_id = pci_dev->id.vendor_id;
1215         hw->device_id = pci_dev->id.device_id;
1216         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1217         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1218 }
1219
1220 static int
1221 eth_igc_dev_init(struct rte_eth_dev *dev)
1222 {
1223         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1224         struct igc_adapter *igc = IGC_DEV_PRIVATE(dev);
1225         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1226         int i, error = 0;
1227
1228         PMD_INIT_FUNC_TRACE();
1229         dev->dev_ops = &eth_igc_ops;
1230         dev->rx_queue_count = eth_igc_rx_queue_count;
1231         dev->rx_descriptor_status = eth_igc_rx_descriptor_status;
1232         dev->tx_descriptor_status = eth_igc_tx_descriptor_status;
1233
1234         /*
1235          * for secondary processes, we don't initialize any further as primary
1236          * has already done this work. Only check we don't need a different
1237          * RX function.
1238          */
1239         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1240                 return 0;
1241
1242         rte_eth_copy_pci_info(dev, pci_dev);
1243         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
1244
1245         hw->back = pci_dev;
1246         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1247
1248         igc_identify_hardware(dev, pci_dev);
1249         if (igc_setup_init_funcs(hw, false) != IGC_SUCCESS) {
1250                 error = -EIO;
1251                 goto err_late;
1252         }
1253
1254         igc_get_bus_info(hw);
1255
1256         /* Reset any pending lock */
1257         if (igc_reset_swfw_lock(hw) != IGC_SUCCESS) {
1258                 error = -EIO;
1259                 goto err_late;
1260         }
1261
1262         /* Finish initialization */
1263         if (igc_setup_init_funcs(hw, true) != IGC_SUCCESS) {
1264                 error = -EIO;
1265                 goto err_late;
1266         }
1267
1268         hw->mac.autoneg = 1;
1269         hw->phy.autoneg_wait_to_complete = 0;
1270         hw->phy.autoneg_advertised = IGC_ALL_SPEED_DUPLEX_2500;
1271
1272         /* Copper options */
1273         if (hw->phy.media_type == igc_media_type_copper) {
1274                 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
1275                 hw->phy.disable_polarity_correction = 0;
1276                 hw->phy.ms_type = igc_ms_hw_default;
1277         }
1278
1279         /*
1280          * Start from a known state, this is important in reading the nvm
1281          * and mac from that.
1282          */
1283         igc_reset_hw(hw);
1284
1285         /* Make sure we have a good EEPROM before we read from it */
1286         if (igc_validate_nvm_checksum(hw) < 0) {
1287                 /*
1288                  * Some PCI-E parts fail the first check due to
1289                  * the link being in sleep state, call it again,
1290                  * if it fails a second time its a real issue.
1291                  */
1292                 if (igc_validate_nvm_checksum(hw) < 0) {
1293                         PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
1294                         error = -EIO;
1295                         goto err_late;
1296                 }
1297         }
1298
1299         /* Read the permanent MAC address out of the EEPROM */
1300         if (igc_read_mac_addr(hw) != 0) {
1301                 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
1302                 error = -EIO;
1303                 goto err_late;
1304         }
1305
1306         /* Allocate memory for storing MAC addresses */
1307         dev->data->mac_addrs = rte_zmalloc("igc",
1308                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
1309         if (dev->data->mac_addrs == NULL) {
1310                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes for storing MAC",
1311                                 RTE_ETHER_ADDR_LEN * hw->mac.rar_entry_count);
1312                 error = -ENOMEM;
1313                 goto err_late;
1314         }
1315
1316         /* Copy the permanent MAC address */
1317         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1318                         &dev->data->mac_addrs[0]);
1319
1320         /* Now initialize the hardware */
1321         if (igc_hardware_init(hw) != 0) {
1322                 PMD_INIT_LOG(ERR, "Hardware initialization failed");
1323                 rte_free(dev->data->mac_addrs);
1324                 dev->data->mac_addrs = NULL;
1325                 error = -ENODEV;
1326                 goto err_late;
1327         }
1328
1329         hw->mac.get_link_status = 1;
1330         igc->stopped = 0;
1331
1332         /* Indicate SOL/IDER usage */
1333         if (igc_check_reset_block(hw) < 0)
1334                 PMD_INIT_LOG(ERR,
1335                         "PHY reset is blocked due to SOL/IDER session.");
1336
1337         PMD_INIT_LOG(DEBUG, "port_id %d vendorID=0x%x deviceID=0x%x",
1338                         dev->data->port_id, pci_dev->id.vendor_id,
1339                         pci_dev->id.device_id);
1340
1341         rte_intr_callback_register(&pci_dev->intr_handle,
1342                         eth_igc_interrupt_handler, (void *)dev);
1343
1344         /* enable uio/vfio intr/eventfd mapping */
1345         rte_intr_enable(&pci_dev->intr_handle);
1346
1347         /* enable support intr */
1348         igc_intr_other_enable(dev);
1349
1350         /* initiate queue status */
1351         for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) {
1352                 igc->txq_stats_map[i] = -1;
1353                 igc->rxq_stats_map[i] = -1;
1354         }
1355
1356         igc_flow_init(dev);
1357         igc_clear_all_filter(dev);
1358         return 0;
1359
1360 err_late:
1361         igc_hw_control_release(hw);
1362         return error;
1363 }
1364
1365 static int
1366 eth_igc_dev_uninit(__rte_unused struct rte_eth_dev *eth_dev)
1367 {
1368         PMD_INIT_FUNC_TRACE();
1369         eth_igc_close(eth_dev);
1370         return 0;
1371 }
1372
1373 static int
1374 eth_igc_reset(struct rte_eth_dev *dev)
1375 {
1376         int ret;
1377
1378         PMD_INIT_FUNC_TRACE();
1379
1380         ret = eth_igc_dev_uninit(dev);
1381         if (ret)
1382                 return ret;
1383
1384         return eth_igc_dev_init(dev);
1385 }
1386
1387 static int
1388 eth_igc_promiscuous_enable(struct rte_eth_dev *dev)
1389 {
1390         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1391         uint32_t rctl;
1392
1393         rctl = IGC_READ_REG(hw, IGC_RCTL);
1394         rctl |= (IGC_RCTL_UPE | IGC_RCTL_MPE);
1395         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
1396         return 0;
1397 }
1398
1399 static int
1400 eth_igc_promiscuous_disable(struct rte_eth_dev *dev)
1401 {
1402         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1403         uint32_t rctl;
1404
1405         rctl = IGC_READ_REG(hw, IGC_RCTL);
1406         rctl &= (~IGC_RCTL_UPE);
1407         if (dev->data->all_multicast == 1)
1408                 rctl |= IGC_RCTL_MPE;
1409         else
1410                 rctl &= (~IGC_RCTL_MPE);
1411         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
1412         return 0;
1413 }
1414
1415 static int
1416 eth_igc_allmulticast_enable(struct rte_eth_dev *dev)
1417 {
1418         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1419         uint32_t rctl;
1420
1421         rctl = IGC_READ_REG(hw, IGC_RCTL);
1422         rctl |= IGC_RCTL_MPE;
1423         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
1424         return 0;
1425 }
1426
1427 static int
1428 eth_igc_allmulticast_disable(struct rte_eth_dev *dev)
1429 {
1430         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1431         uint32_t rctl;
1432
1433         if (dev->data->promiscuous == 1)
1434                 return 0;       /* must remain in all_multicast mode */
1435
1436         rctl = IGC_READ_REG(hw, IGC_RCTL);
1437         rctl &= (~IGC_RCTL_MPE);
1438         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
1439         return 0;
1440 }
1441
1442 static int
1443 eth_igc_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
1444                        size_t fw_size)
1445 {
1446         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1447         struct igc_fw_version fw;
1448         int ret;
1449
1450         igc_get_fw_version(hw, &fw);
1451
1452         /* if option rom is valid, display its version too */
1453         if (fw.or_valid) {
1454                 ret = snprintf(fw_version, fw_size,
1455                          "%d.%d, 0x%08x, %d.%d.%d",
1456                          fw.eep_major, fw.eep_minor, fw.etrack_id,
1457                          fw.or_major, fw.or_build, fw.or_patch);
1458         /* no option rom */
1459         } else {
1460                 if (fw.etrack_id != 0X0000) {
1461                         ret = snprintf(fw_version, fw_size,
1462                                  "%d.%d, 0x%08x",
1463                                  fw.eep_major, fw.eep_minor,
1464                                  fw.etrack_id);
1465                 } else {
1466                         ret = snprintf(fw_version, fw_size,
1467                                  "%d.%d.%d",
1468                                  fw.eep_major, fw.eep_minor,
1469                                  fw.eep_build);
1470                 }
1471         }
1472         if (ret < 0)
1473                 return -EINVAL;
1474
1475         ret += 1; /* add the size of '\0' */
1476         if (fw_size < (size_t)ret)
1477                 return ret;
1478         else
1479                 return 0;
1480 }
1481
1482 static int
1483 eth_igc_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1484 {
1485         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1486
1487         dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
1488         dev_info->max_rx_pktlen = MAX_RX_JUMBO_FRAME_SIZE;
1489         dev_info->max_mac_addrs = hw->mac.rar_entry_count;
1490         dev_info->rx_offload_capa = IGC_RX_OFFLOAD_ALL;
1491         dev_info->tx_offload_capa = IGC_TX_OFFLOAD_ALL;
1492         dev_info->rx_queue_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1493
1494         dev_info->max_rx_queues = IGC_QUEUE_PAIRS_NUM;
1495         dev_info->max_tx_queues = IGC_QUEUE_PAIRS_NUM;
1496         dev_info->max_vmdq_pools = 0;
1497
1498         dev_info->hash_key_size = IGC_HKEY_MAX_INDEX * sizeof(uint32_t);
1499         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
1500         dev_info->flow_type_rss_offloads = IGC_RSS_OFFLOAD_ALL;
1501
1502         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1503                 .rx_thresh = {
1504                         .pthresh = IGC_DEFAULT_RX_PTHRESH,
1505                         .hthresh = IGC_DEFAULT_RX_HTHRESH,
1506                         .wthresh = IGC_DEFAULT_RX_WTHRESH,
1507                 },
1508                 .rx_free_thresh = IGC_DEFAULT_RX_FREE_THRESH,
1509                 .rx_drop_en = 0,
1510                 .offloads = 0,
1511         };
1512
1513         dev_info->default_txconf = (struct rte_eth_txconf) {
1514                 .tx_thresh = {
1515                         .pthresh = IGC_DEFAULT_TX_PTHRESH,
1516                         .hthresh = IGC_DEFAULT_TX_HTHRESH,
1517                         .wthresh = IGC_DEFAULT_TX_WTHRESH,
1518                 },
1519                 .offloads = 0,
1520         };
1521
1522         dev_info->rx_desc_lim = rx_desc_lim;
1523         dev_info->tx_desc_lim = tx_desc_lim;
1524
1525         dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
1526                         ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
1527                         ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G;
1528
1529         dev_info->max_mtu = dev_info->max_rx_pktlen - IGC_ETH_OVERHEAD;
1530         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
1531         return 0;
1532 }
1533
1534 static int
1535 eth_igc_led_on(struct rte_eth_dev *dev)
1536 {
1537         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1538
1539         return igc_led_on(hw) == IGC_SUCCESS ? 0 : -ENOTSUP;
1540 }
1541
1542 static int
1543 eth_igc_led_off(struct rte_eth_dev *dev)
1544 {
1545         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1546
1547         return igc_led_off(hw) == IGC_SUCCESS ? 0 : -ENOTSUP;
1548 }
1549
1550 static const uint32_t *
1551 eth_igc_supported_ptypes_get(__rte_unused struct rte_eth_dev *dev)
1552 {
1553         static const uint32_t ptypes[] = {
1554                 /* refers to rx_desc_pkt_info_to_pkt_type() */
1555                 RTE_PTYPE_L2_ETHER,
1556                 RTE_PTYPE_L3_IPV4,
1557                 RTE_PTYPE_L3_IPV4_EXT,
1558                 RTE_PTYPE_L3_IPV6,
1559                 RTE_PTYPE_L3_IPV6_EXT,
1560                 RTE_PTYPE_L4_TCP,
1561                 RTE_PTYPE_L4_UDP,
1562                 RTE_PTYPE_L4_SCTP,
1563                 RTE_PTYPE_TUNNEL_IP,
1564                 RTE_PTYPE_INNER_L3_IPV6,
1565                 RTE_PTYPE_INNER_L3_IPV6_EXT,
1566                 RTE_PTYPE_INNER_L4_TCP,
1567                 RTE_PTYPE_INNER_L4_UDP,
1568                 RTE_PTYPE_UNKNOWN
1569         };
1570
1571         return ptypes;
1572 }
1573
1574 static int
1575 eth_igc_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
1576 {
1577         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1578         uint32_t frame_size = mtu + IGC_ETH_OVERHEAD;
1579         uint32_t rctl;
1580
1581         /* if extend vlan has been enabled */
1582         if (IGC_READ_REG(hw, IGC_CTRL_EXT) & IGC_CTRL_EXT_EXT_VLAN)
1583                 frame_size += VLAN_TAG_SIZE;
1584
1585         /* check that mtu is within the allowed range */
1586         if (mtu < RTE_ETHER_MIN_MTU ||
1587                 frame_size > MAX_RX_JUMBO_FRAME_SIZE)
1588                 return -EINVAL;
1589
1590         /*
1591          * If device is started, refuse mtu that requires the support of
1592          * scattered packets when this feature has not been enabled before.
1593          */
1594         if (dev->data->dev_started && !dev->data->scattered_rx &&
1595             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
1596                 PMD_INIT_LOG(ERR, "Stop port first.");
1597                 return -EINVAL;
1598         }
1599
1600         rctl = IGC_READ_REG(hw, IGC_RCTL);
1601
1602         /* switch to jumbo mode if needed */
1603         if (mtu > RTE_ETHER_MTU) {
1604                 dev->data->dev_conf.rxmode.offloads |=
1605                         DEV_RX_OFFLOAD_JUMBO_FRAME;
1606                 rctl |= IGC_RCTL_LPE;
1607         } else {
1608                 dev->data->dev_conf.rxmode.offloads &=
1609                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
1610                 rctl &= ~IGC_RCTL_LPE;
1611         }
1612         IGC_WRITE_REG(hw, IGC_RCTL, rctl);
1613
1614         /* update max frame size */
1615         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1616
1617         IGC_WRITE_REG(hw, IGC_RLPML,
1618                         dev->data->dev_conf.rxmode.max_rx_pkt_len);
1619
1620         return 0;
1621 }
1622
1623 static int
1624 eth_igc_rar_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
1625                 uint32_t index, uint32_t pool)
1626 {
1627         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1628
1629         igc_rar_set(hw, mac_addr->addr_bytes, index);
1630         RTE_SET_USED(pool);
1631         return 0;
1632 }
1633
1634 static void
1635 eth_igc_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1636 {
1637         uint8_t addr[RTE_ETHER_ADDR_LEN];
1638         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1639
1640         memset(addr, 0, sizeof(addr));
1641         igc_rar_set(hw, addr, index);
1642 }
1643
1644 static int
1645 eth_igc_default_mac_addr_set(struct rte_eth_dev *dev,
1646                         struct rte_ether_addr *addr)
1647 {
1648         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1649         igc_rar_set(hw, addr->addr_bytes, 0);
1650         return 0;
1651 }
1652
1653 static int
1654 eth_igc_set_mc_addr_list(struct rte_eth_dev *dev,
1655                          struct rte_ether_addr *mc_addr_set,
1656                          uint32_t nb_mc_addr)
1657 {
1658         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1659         igc_update_mc_addr_list(hw, (u8 *)mc_addr_set, nb_mc_addr);
1660         return 0;
1661 }
1662
1663 /*
1664  * Read hardware registers
1665  */
1666 static void
1667 igc_read_stats_registers(struct igc_hw *hw, struct igc_hw_stats *stats)
1668 {
1669         int pause_frames;
1670
1671         uint64_t old_gprc  = stats->gprc;
1672         uint64_t old_gptc  = stats->gptc;
1673         uint64_t old_tpr   = stats->tpr;
1674         uint64_t old_tpt   = stats->tpt;
1675         uint64_t old_rpthc = stats->rpthc;
1676         uint64_t old_hgptc = stats->hgptc;
1677
1678         stats->crcerrs += IGC_READ_REG(hw, IGC_CRCERRS);
1679         stats->algnerrc += IGC_READ_REG(hw, IGC_ALGNERRC);
1680         stats->rxerrc += IGC_READ_REG(hw, IGC_RXERRC);
1681         stats->mpc += IGC_READ_REG(hw, IGC_MPC);
1682         stats->scc += IGC_READ_REG(hw, IGC_SCC);
1683         stats->ecol += IGC_READ_REG(hw, IGC_ECOL);
1684
1685         stats->mcc += IGC_READ_REG(hw, IGC_MCC);
1686         stats->latecol += IGC_READ_REG(hw, IGC_LATECOL);
1687         stats->colc += IGC_READ_REG(hw, IGC_COLC);
1688
1689         stats->dc += IGC_READ_REG(hw, IGC_DC);
1690         stats->tncrs += IGC_READ_REG(hw, IGC_TNCRS);
1691         stats->htdpmc += IGC_READ_REG(hw, IGC_HTDPMC);
1692         stats->rlec += IGC_READ_REG(hw, IGC_RLEC);
1693         stats->xonrxc += IGC_READ_REG(hw, IGC_XONRXC);
1694         stats->xontxc += IGC_READ_REG(hw, IGC_XONTXC);
1695
1696         /*
1697          * For watchdog management we need to know if we have been
1698          * paused during the last interval, so capture that here.
1699          */
1700         pause_frames = IGC_READ_REG(hw, IGC_XOFFRXC);
1701         stats->xoffrxc += pause_frames;
1702         stats->xofftxc += IGC_READ_REG(hw, IGC_XOFFTXC);
1703         stats->fcruc += IGC_READ_REG(hw, IGC_FCRUC);
1704         stats->prc64 += IGC_READ_REG(hw, IGC_PRC64);
1705         stats->prc127 += IGC_READ_REG(hw, IGC_PRC127);
1706         stats->prc255 += IGC_READ_REG(hw, IGC_PRC255);
1707         stats->prc511 += IGC_READ_REG(hw, IGC_PRC511);
1708         stats->prc1023 += IGC_READ_REG(hw, IGC_PRC1023);
1709         stats->prc1522 += IGC_READ_REG(hw, IGC_PRC1522);
1710         stats->gprc += IGC_READ_REG(hw, IGC_GPRC);
1711         stats->bprc += IGC_READ_REG(hw, IGC_BPRC);
1712         stats->mprc += IGC_READ_REG(hw, IGC_MPRC);
1713         stats->gptc += IGC_READ_REG(hw, IGC_GPTC);
1714
1715         /* For the 64-bit byte counters the low dword must be read first. */
1716         /* Both registers clear on the read of the high dword */
1717
1718         /* Workaround CRC bytes included in size, take away 4 bytes/packet */
1719         stats->gorc += IGC_READ_REG(hw, IGC_GORCL);
1720         stats->gorc += ((uint64_t)IGC_READ_REG(hw, IGC_GORCH) << 32);
1721         stats->gorc -= (stats->gprc - old_gprc) * RTE_ETHER_CRC_LEN;
1722         stats->gotc += IGC_READ_REG(hw, IGC_GOTCL);
1723         stats->gotc += ((uint64_t)IGC_READ_REG(hw, IGC_GOTCH) << 32);
1724         stats->gotc -= (stats->gptc - old_gptc) * RTE_ETHER_CRC_LEN;
1725
1726         stats->rnbc += IGC_READ_REG(hw, IGC_RNBC);
1727         stats->ruc += IGC_READ_REG(hw, IGC_RUC);
1728         stats->rfc += IGC_READ_REG(hw, IGC_RFC);
1729         stats->roc += IGC_READ_REG(hw, IGC_ROC);
1730         stats->rjc += IGC_READ_REG(hw, IGC_RJC);
1731
1732         stats->mgprc += IGC_READ_REG(hw, IGC_MGTPRC);
1733         stats->mgpdc += IGC_READ_REG(hw, IGC_MGTPDC);
1734         stats->mgptc += IGC_READ_REG(hw, IGC_MGTPTC);
1735         stats->b2ospc += IGC_READ_REG(hw, IGC_B2OSPC);
1736         stats->b2ogprc += IGC_READ_REG(hw, IGC_B2OGPRC);
1737         stats->o2bgptc += IGC_READ_REG(hw, IGC_O2BGPTC);
1738         stats->o2bspc += IGC_READ_REG(hw, IGC_O2BSPC);
1739
1740         stats->tpr += IGC_READ_REG(hw, IGC_TPR);
1741         stats->tpt += IGC_READ_REG(hw, IGC_TPT);
1742
1743         stats->tor += IGC_READ_REG(hw, IGC_TORL);
1744         stats->tor += ((uint64_t)IGC_READ_REG(hw, IGC_TORH) << 32);
1745         stats->tor -= (stats->tpr - old_tpr) * RTE_ETHER_CRC_LEN;
1746         stats->tot += IGC_READ_REG(hw, IGC_TOTL);
1747         stats->tot += ((uint64_t)IGC_READ_REG(hw, IGC_TOTH) << 32);
1748         stats->tot -= (stats->tpt - old_tpt) * RTE_ETHER_CRC_LEN;
1749
1750         stats->ptc64 += IGC_READ_REG(hw, IGC_PTC64);
1751         stats->ptc127 += IGC_READ_REG(hw, IGC_PTC127);
1752         stats->ptc255 += IGC_READ_REG(hw, IGC_PTC255);
1753         stats->ptc511 += IGC_READ_REG(hw, IGC_PTC511);
1754         stats->ptc1023 += IGC_READ_REG(hw, IGC_PTC1023);
1755         stats->ptc1522 += IGC_READ_REG(hw, IGC_PTC1522);
1756         stats->mptc += IGC_READ_REG(hw, IGC_MPTC);
1757         stats->bptc += IGC_READ_REG(hw, IGC_BPTC);
1758         stats->tsctc += IGC_READ_REG(hw, IGC_TSCTC);
1759
1760         stats->iac += IGC_READ_REG(hw, IGC_IAC);
1761         stats->rpthc += IGC_READ_REG(hw, IGC_RPTHC);
1762         stats->hgptc += IGC_READ_REG(hw, IGC_HGPTC);
1763         stats->icrxdmtc += IGC_READ_REG(hw, IGC_ICRXDMTC);
1764
1765         /* Host to Card Statistics */
1766         stats->hgorc += IGC_READ_REG(hw, IGC_HGORCL);
1767         stats->hgorc += ((uint64_t)IGC_READ_REG(hw, IGC_HGORCH) << 32);
1768         stats->hgorc -= (stats->rpthc - old_rpthc) * RTE_ETHER_CRC_LEN;
1769         stats->hgotc += IGC_READ_REG(hw, IGC_HGOTCL);
1770         stats->hgotc += ((uint64_t)IGC_READ_REG(hw, IGC_HGOTCH) << 32);
1771         stats->hgotc -= (stats->hgptc - old_hgptc) * RTE_ETHER_CRC_LEN;
1772         stats->lenerrs += IGC_READ_REG(hw, IGC_LENERRS);
1773 }
1774
1775 /*
1776  * Write 0 to all queue status registers
1777  */
1778 static void
1779 igc_reset_queue_stats_register(struct igc_hw *hw)
1780 {
1781         int i;
1782
1783         for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) {
1784                 IGC_WRITE_REG(hw, IGC_PQGPRC(i), 0);
1785                 IGC_WRITE_REG(hw, IGC_PQGPTC(i), 0);
1786                 IGC_WRITE_REG(hw, IGC_PQGORC(i), 0);
1787                 IGC_WRITE_REG(hw, IGC_PQGOTC(i), 0);
1788                 IGC_WRITE_REG(hw, IGC_PQMPRC(i), 0);
1789                 IGC_WRITE_REG(hw, IGC_RQDPC(i), 0);
1790                 IGC_WRITE_REG(hw, IGC_TQDPC(i), 0);
1791         }
1792 }
1793
1794 /*
1795  * Read all hardware queue status registers
1796  */
1797 static void
1798 igc_read_queue_stats_register(struct rte_eth_dev *dev)
1799 {
1800         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1801         struct igc_hw_queue_stats *queue_stats =
1802                                 IGC_DEV_PRIVATE_QUEUE_STATS(dev);
1803         int i;
1804
1805         /*
1806          * This register is not cleared on read. Furthermore, the register wraps
1807          * around back to 0x00000000 on the next increment when reaching a value
1808          * of 0xFFFFFFFF and then continues normal count operation.
1809          */
1810         for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) {
1811                 union {
1812                         u64 ddword;
1813                         u32 dword[2];
1814                 } value;
1815                 u32 tmp;
1816
1817                 /*
1818                  * Read the register first, if the value is smaller than that
1819                  * previous read, that mean the register has been overflowed,
1820                  * then we add the high 4 bytes by 1 and replace the low 4
1821                  * bytes by the new value.
1822                  */
1823                 tmp = IGC_READ_REG(hw, IGC_PQGPRC(i));
1824                 value.ddword = queue_stats->pqgprc[i];
1825                 if (value.dword[U32_0_IN_U64] > tmp)
1826                         value.dword[U32_1_IN_U64]++;
1827                 value.dword[U32_0_IN_U64] = tmp;
1828                 queue_stats->pqgprc[i] = value.ddword;
1829
1830                 tmp = IGC_READ_REG(hw, IGC_PQGPTC(i));
1831                 value.ddword = queue_stats->pqgptc[i];
1832                 if (value.dword[U32_0_IN_U64] > tmp)
1833                         value.dword[U32_1_IN_U64]++;
1834                 value.dword[U32_0_IN_U64] = tmp;
1835                 queue_stats->pqgptc[i] = value.ddword;
1836
1837                 tmp = IGC_READ_REG(hw, IGC_PQGORC(i));
1838                 value.ddword = queue_stats->pqgorc[i];
1839                 if (value.dword[U32_0_IN_U64] > tmp)
1840                         value.dword[U32_1_IN_U64]++;
1841                 value.dword[U32_0_IN_U64] = tmp;
1842                 queue_stats->pqgorc[i] = value.ddword;
1843
1844                 tmp = IGC_READ_REG(hw, IGC_PQGOTC(i));
1845                 value.ddword = queue_stats->pqgotc[i];
1846                 if (value.dword[U32_0_IN_U64] > tmp)
1847                         value.dword[U32_1_IN_U64]++;
1848                 value.dword[U32_0_IN_U64] = tmp;
1849                 queue_stats->pqgotc[i] = value.ddword;
1850
1851                 tmp = IGC_READ_REG(hw, IGC_PQMPRC(i));
1852                 value.ddword = queue_stats->pqmprc[i];
1853                 if (value.dword[U32_0_IN_U64] > tmp)
1854                         value.dword[U32_1_IN_U64]++;
1855                 value.dword[U32_0_IN_U64] = tmp;
1856                 queue_stats->pqmprc[i] = value.ddword;
1857
1858                 tmp = IGC_READ_REG(hw, IGC_RQDPC(i));
1859                 value.ddword = queue_stats->rqdpc[i];
1860                 if (value.dword[U32_0_IN_U64] > tmp)
1861                         value.dword[U32_1_IN_U64]++;
1862                 value.dword[U32_0_IN_U64] = tmp;
1863                 queue_stats->rqdpc[i] = value.ddword;
1864
1865                 tmp = IGC_READ_REG(hw, IGC_TQDPC(i));
1866                 value.ddword = queue_stats->tqdpc[i];
1867                 if (value.dword[U32_0_IN_U64] > tmp)
1868                         value.dword[U32_1_IN_U64]++;
1869                 value.dword[U32_0_IN_U64] = tmp;
1870                 queue_stats->tqdpc[i] = value.ddword;
1871         }
1872 }
1873
1874 static int
1875 eth_igc_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
1876 {
1877         struct igc_adapter *igc = IGC_DEV_PRIVATE(dev);
1878         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1879         struct igc_hw_stats *stats = IGC_DEV_PRIVATE_STATS(dev);
1880         struct igc_hw_queue_stats *queue_stats =
1881                         IGC_DEV_PRIVATE_QUEUE_STATS(dev);
1882         int i;
1883
1884         /*
1885          * Cancel status handler since it will read the queue status registers
1886          */
1887         rte_eal_alarm_cancel(igc_update_queue_stats_handler, dev);
1888
1889         /* Read status register */
1890         igc_read_queue_stats_register(dev);
1891         igc_read_stats_registers(hw, stats);
1892
1893         if (rte_stats == NULL) {
1894                 /* Restart queue status handler */
1895                 rte_eal_alarm_set(IGC_ALARM_INTERVAL,
1896                                 igc_update_queue_stats_handler, dev);
1897                 return -EINVAL;
1898         }
1899
1900         /* Rx Errors */
1901         rte_stats->imissed = stats->mpc;
1902         rte_stats->ierrors = stats->crcerrs + stats->rlec +
1903                         stats->rxerrc + stats->algnerrc;
1904
1905         /* Tx Errors */
1906         rte_stats->oerrors = stats->ecol + stats->latecol;
1907
1908         rte_stats->ipackets = stats->gprc;
1909         rte_stats->opackets = stats->gptc;
1910         rte_stats->ibytes   = stats->gorc;
1911         rte_stats->obytes   = stats->gotc;
1912
1913         /* Get per-queue statuses */
1914         for (i = 0; i < IGC_QUEUE_PAIRS_NUM; i++) {
1915                 /* GET TX queue statuses */
1916                 int map_id = igc->txq_stats_map[i];
1917                 if (map_id >= 0) {
1918                         rte_stats->q_opackets[map_id] += queue_stats->pqgptc[i];
1919                         rte_stats->q_obytes[map_id] += queue_stats->pqgotc[i];
1920                 }
1921                 /* Get RX queue statuses */
1922                 map_id = igc->rxq_stats_map[i];
1923                 if (map_id >= 0) {
1924                         rte_stats->q_ipackets[map_id] += queue_stats->pqgprc[i];
1925                         rte_stats->q_ibytes[map_id] += queue_stats->pqgorc[i];
1926                         rte_stats->q_errors[map_id] += queue_stats->rqdpc[i];
1927                 }
1928         }
1929
1930         /* Restart queue status handler */
1931         rte_eal_alarm_set(IGC_ALARM_INTERVAL,
1932                         igc_update_queue_stats_handler, dev);
1933         return 0;
1934 }
1935
1936 static int
1937 eth_igc_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1938                    unsigned int n)
1939 {
1940         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1941         struct igc_hw_stats *hw_stats =
1942                         IGC_DEV_PRIVATE_STATS(dev);
1943         unsigned int i;
1944
1945         igc_read_stats_registers(hw, hw_stats);
1946
1947         if (n < IGC_NB_XSTATS)
1948                 return IGC_NB_XSTATS;
1949
1950         /* If this is a reset xstats is NULL, and we have cleared the
1951          * registers by reading them.
1952          */
1953         if (!xstats)
1954                 return 0;
1955
1956         /* Extended stats */
1957         for (i = 0; i < IGC_NB_XSTATS; i++) {
1958                 xstats[i].id = i;
1959                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) +
1960                         rte_igc_stats_strings[i].offset);
1961         }
1962
1963         return IGC_NB_XSTATS;
1964 }
1965
1966 static int
1967 eth_igc_xstats_reset(struct rte_eth_dev *dev)
1968 {
1969         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
1970         struct igc_hw_stats *hw_stats = IGC_DEV_PRIVATE_STATS(dev);
1971         struct igc_hw_queue_stats *queue_stats =
1972                         IGC_DEV_PRIVATE_QUEUE_STATS(dev);
1973
1974         /* Cancel queue status handler for avoid conflict */
1975         rte_eal_alarm_cancel(igc_update_queue_stats_handler, dev);
1976
1977         /* HW registers are cleared on read */
1978         igc_reset_queue_stats_register(hw);
1979         igc_read_stats_registers(hw, hw_stats);
1980
1981         /* Reset software totals */
1982         memset(hw_stats, 0, sizeof(*hw_stats));
1983         memset(queue_stats, 0, sizeof(*queue_stats));
1984
1985         /* Restart the queue status handler */
1986         rte_eal_alarm_set(IGC_ALARM_INTERVAL, igc_update_queue_stats_handler,
1987                         dev);
1988
1989         return 0;
1990 }
1991
1992 static int
1993 eth_igc_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1994         struct rte_eth_xstat_name *xstats_names, unsigned int size)
1995 {
1996         unsigned int i;
1997
1998         if (xstats_names == NULL)
1999                 return IGC_NB_XSTATS;
2000
2001         if (size < IGC_NB_XSTATS) {
2002                 PMD_DRV_LOG(ERR, "not enough buffers!");
2003                 return IGC_NB_XSTATS;
2004         }
2005
2006         for (i = 0; i < IGC_NB_XSTATS; i++)
2007                 strlcpy(xstats_names[i].name, rte_igc_stats_strings[i].name,
2008                         sizeof(xstats_names[i].name));
2009
2010         return IGC_NB_XSTATS;
2011 }
2012
2013 static int
2014 eth_igc_xstats_get_names_by_id(struct rte_eth_dev *dev,
2015                 const uint64_t *ids, struct rte_eth_xstat_name *xstats_names,
2016                 unsigned int limit)
2017 {
2018         unsigned int i;
2019
2020         if (!ids)
2021                 return eth_igc_xstats_get_names(dev, xstats_names, limit);
2022
2023         for (i = 0; i < limit; i++) {
2024                 if (ids[i] >= IGC_NB_XSTATS) {
2025                         PMD_DRV_LOG(ERR, "id value isn't valid");
2026                         return -EINVAL;
2027                 }
2028                 strlcpy(xstats_names[i].name,
2029                         rte_igc_stats_strings[ids[i]].name,
2030                         sizeof(xstats_names[i].name));
2031         }
2032         return limit;
2033 }
2034
2035 static int
2036 eth_igc_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2037                 uint64_t *values, unsigned int n)
2038 {
2039         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2040         struct igc_hw_stats *hw_stats = IGC_DEV_PRIVATE_STATS(dev);
2041         unsigned int i;
2042
2043         igc_read_stats_registers(hw, hw_stats);
2044
2045         if (!ids) {
2046                 if (n < IGC_NB_XSTATS)
2047                         return IGC_NB_XSTATS;
2048
2049                 /* If this is a reset xstats is NULL, and we have cleared the
2050                  * registers by reading them.
2051                  */
2052                 if (!values)
2053                         return 0;
2054
2055                 /* Extended stats */
2056                 for (i = 0; i < IGC_NB_XSTATS; i++)
2057                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2058                                         rte_igc_stats_strings[i].offset);
2059
2060                 return IGC_NB_XSTATS;
2061
2062         } else {
2063                 for (i = 0; i < n; i++) {
2064                         if (ids[i] >= IGC_NB_XSTATS) {
2065                                 PMD_DRV_LOG(ERR, "id value isn't valid");
2066                                 return -EINVAL;
2067                         }
2068                         values[i] = *(uint64_t *)(((char *)hw_stats) +
2069                                         rte_igc_stats_strings[ids[i]].offset);
2070                 }
2071                 return n;
2072         }
2073 }
2074
2075 static int
2076 eth_igc_queue_stats_mapping_set(struct rte_eth_dev *dev,
2077                 uint16_t queue_id, uint8_t stat_idx, uint8_t is_rx)
2078 {
2079         struct igc_adapter *igc = IGC_DEV_PRIVATE(dev);
2080
2081         /* check queue id is valid */
2082         if (queue_id >= IGC_QUEUE_PAIRS_NUM) {
2083                 PMD_DRV_LOG(ERR, "queue id(%u) error, max is %u",
2084                         queue_id, IGC_QUEUE_PAIRS_NUM - 1);
2085                 return -EINVAL;
2086         }
2087
2088         /* store the mapping status id */
2089         if (is_rx)
2090                 igc->rxq_stats_map[queue_id] = stat_idx;
2091         else
2092                 igc->txq_stats_map[queue_id] = stat_idx;
2093
2094         return 0;
2095 }
2096
2097 static int
2098 eth_igc_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
2099 {
2100         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2101         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2102         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2103         uint32_t vec = IGC_MISC_VEC_ID;
2104
2105         if (rte_intr_allow_others(intr_handle))
2106                 vec = IGC_RX_VEC_START;
2107
2108         uint32_t mask = 1u << (queue_id + vec);
2109
2110         IGC_WRITE_REG(hw, IGC_EIMC, mask);
2111         IGC_WRITE_FLUSH(hw);
2112
2113         return 0;
2114 }
2115
2116 static int
2117 eth_igc_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
2118 {
2119         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2120         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2121         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2122         uint32_t vec = IGC_MISC_VEC_ID;
2123
2124         if (rte_intr_allow_others(intr_handle))
2125                 vec = IGC_RX_VEC_START;
2126
2127         uint32_t mask = 1u << (queue_id + vec);
2128
2129         IGC_WRITE_REG(hw, IGC_EIMS, mask);
2130         IGC_WRITE_FLUSH(hw);
2131
2132         rte_intr_enable(intr_handle);
2133
2134         return 0;
2135 }
2136
2137 static int
2138 eth_igc_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2139 {
2140         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2141         uint32_t ctrl;
2142         int tx_pause;
2143         int rx_pause;
2144
2145         fc_conf->pause_time = hw->fc.pause_time;
2146         fc_conf->high_water = hw->fc.high_water;
2147         fc_conf->low_water = hw->fc.low_water;
2148         fc_conf->send_xon = hw->fc.send_xon;
2149         fc_conf->autoneg = hw->mac.autoneg;
2150
2151         /*
2152          * Return rx_pause and tx_pause status according to actual setting of
2153          * the TFCE and RFCE bits in the CTRL register.
2154          */
2155         ctrl = IGC_READ_REG(hw, IGC_CTRL);
2156         if (ctrl & IGC_CTRL_TFCE)
2157                 tx_pause = 1;
2158         else
2159                 tx_pause = 0;
2160
2161         if (ctrl & IGC_CTRL_RFCE)
2162                 rx_pause = 1;
2163         else
2164                 rx_pause = 0;
2165
2166         if (rx_pause && tx_pause)
2167                 fc_conf->mode = RTE_FC_FULL;
2168         else if (rx_pause)
2169                 fc_conf->mode = RTE_FC_RX_PAUSE;
2170         else if (tx_pause)
2171                 fc_conf->mode = RTE_FC_TX_PAUSE;
2172         else
2173                 fc_conf->mode = RTE_FC_NONE;
2174
2175         return 0;
2176 }
2177
2178 static int
2179 eth_igc_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
2180 {
2181         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2182         uint32_t rx_buf_size;
2183         uint32_t max_high_water;
2184         uint32_t rctl;
2185         int err;
2186
2187         if (fc_conf->autoneg != hw->mac.autoneg)
2188                 return -ENOTSUP;
2189
2190         rx_buf_size = igc_get_rx_buffer_size(hw);
2191         PMD_DRV_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
2192
2193         /* At least reserve one Ethernet frame for watermark */
2194         max_high_water = rx_buf_size - RTE_ETHER_MAX_LEN;
2195         if (fc_conf->high_water > max_high_water ||
2196                 fc_conf->high_water < fc_conf->low_water) {
2197                 PMD_DRV_LOG(ERR,
2198                         "Incorrect high(%u)/low(%u) water value, max is %u",
2199                         fc_conf->high_water, fc_conf->low_water,
2200                         max_high_water);
2201                 return -EINVAL;
2202         }
2203
2204         switch (fc_conf->mode) {
2205         case RTE_FC_NONE:
2206                 hw->fc.requested_mode = igc_fc_none;
2207                 break;
2208         case RTE_FC_RX_PAUSE:
2209                 hw->fc.requested_mode = igc_fc_rx_pause;
2210                 break;
2211         case RTE_FC_TX_PAUSE:
2212                 hw->fc.requested_mode = igc_fc_tx_pause;
2213                 break;
2214         case RTE_FC_FULL:
2215                 hw->fc.requested_mode = igc_fc_full;
2216                 break;
2217         default:
2218                 PMD_DRV_LOG(ERR, "unsupported fc mode: %u", fc_conf->mode);
2219                 return -EINVAL;
2220         }
2221
2222         hw->fc.pause_time     = fc_conf->pause_time;
2223         hw->fc.high_water     = fc_conf->high_water;
2224         hw->fc.low_water      = fc_conf->low_water;
2225         hw->fc.send_xon       = fc_conf->send_xon;
2226
2227         err = igc_setup_link_generic(hw);
2228         if (err == IGC_SUCCESS) {
2229                 /**
2230                  * check if we want to forward MAC frames - driver doesn't have
2231                  * native capability to do that, so we'll write the registers
2232                  * ourselves
2233                  **/
2234                 rctl = IGC_READ_REG(hw, IGC_RCTL);
2235
2236                 /* set or clear MFLCN.PMCF bit depending on configuration */
2237                 if (fc_conf->mac_ctrl_frame_fwd != 0)
2238                         rctl |= IGC_RCTL_PMCF;
2239                 else
2240                         rctl &= ~IGC_RCTL_PMCF;
2241
2242                 IGC_WRITE_REG(hw, IGC_RCTL, rctl);
2243                 IGC_WRITE_FLUSH(hw);
2244
2245                 return 0;
2246         }
2247
2248         PMD_DRV_LOG(ERR, "igc_setup_link_generic = 0x%x", err);
2249         return -EIO;
2250 }
2251
2252 static int
2253 eth_igc_rss_reta_update(struct rte_eth_dev *dev,
2254                         struct rte_eth_rss_reta_entry64 *reta_conf,
2255                         uint16_t reta_size)
2256 {
2257         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2258         uint16_t i;
2259
2260         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2261                 PMD_DRV_LOG(ERR,
2262                         "The size of RSS redirection table configured(%d) doesn't match the number hardware can supported(%d)",
2263                         reta_size, ETH_RSS_RETA_SIZE_128);
2264                 return -EINVAL;
2265         }
2266
2267         RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE);
2268
2269         /* set redirection table */
2270         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {
2271                 union igc_rss_reta_reg reta, reg;
2272                 uint16_t idx, shift;
2273                 uint8_t j, mask;
2274
2275                 idx = i / RTE_RETA_GROUP_SIZE;
2276                 shift = i % RTE_RETA_GROUP_SIZE;
2277                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2278                                 IGC_RSS_RDT_REG_SIZE_MASK);
2279
2280                 /* if no need to update the register */
2281                 if (!mask ||
2282                     shift > (RTE_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE))
2283                         continue;
2284
2285                 /* check mask whether need to read the register value first */
2286                 if (mask == IGC_RSS_RDT_REG_SIZE_MASK)
2287                         reg.dword = 0;
2288                 else
2289                         reg.dword = IGC_READ_REG_LE_VALUE(hw,
2290                                         IGC_RETA(i / IGC_RSS_RDT_REG_SIZE));
2291
2292                 /* update the register */
2293                 RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE);
2294                 for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
2295                         if (mask & (1u << j))
2296                                 reta.bytes[j] =
2297                                         (uint8_t)reta_conf[idx].reta[shift + j];
2298                         else
2299                                 reta.bytes[j] = reg.bytes[j];
2300                 }
2301                 IGC_WRITE_REG_LE_VALUE(hw,
2302                         IGC_RETA(i / IGC_RSS_RDT_REG_SIZE), reta.dword);
2303         }
2304
2305         return 0;
2306 }
2307
2308 static int
2309 eth_igc_rss_reta_query(struct rte_eth_dev *dev,
2310                        struct rte_eth_rss_reta_entry64 *reta_conf,
2311                        uint16_t reta_size)
2312 {
2313         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2314         uint16_t i;
2315
2316         if (reta_size != ETH_RSS_RETA_SIZE_128) {
2317                 PMD_DRV_LOG(ERR,
2318                         "The size of RSS redirection table configured(%d) doesn't match the number hardware can supported(%d)",
2319                         reta_size, ETH_RSS_RETA_SIZE_128);
2320                 return -EINVAL;
2321         }
2322
2323         RTE_BUILD_BUG_ON(ETH_RSS_RETA_SIZE_128 % IGC_RSS_RDT_REG_SIZE);
2324
2325         /* read redirection table */
2326         for (i = 0; i < ETH_RSS_RETA_SIZE_128; i += IGC_RSS_RDT_REG_SIZE) {
2327                 union igc_rss_reta_reg reta;
2328                 uint16_t idx, shift;
2329                 uint8_t j, mask;
2330
2331                 idx = i / RTE_RETA_GROUP_SIZE;
2332                 shift = i % RTE_RETA_GROUP_SIZE;
2333                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2334                                 IGC_RSS_RDT_REG_SIZE_MASK);
2335
2336                 /* if no need to read register */
2337                 if (!mask ||
2338                     shift > (RTE_RETA_GROUP_SIZE - IGC_RSS_RDT_REG_SIZE))
2339                         continue;
2340
2341                 /* read register and get the queue index */
2342                 RTE_BUILD_BUG_ON(sizeof(reta.bytes) != IGC_RSS_RDT_REG_SIZE);
2343                 reta.dword = IGC_READ_REG_LE_VALUE(hw,
2344                                 IGC_RETA(i / IGC_RSS_RDT_REG_SIZE));
2345                 for (j = 0; j < IGC_RSS_RDT_REG_SIZE; j++) {
2346                         if (mask & (1u << j))
2347                                 reta_conf[idx].reta[shift + j] = reta.bytes[j];
2348                 }
2349         }
2350
2351         return 0;
2352 }
2353
2354 static int
2355 eth_igc_rss_hash_update(struct rte_eth_dev *dev,
2356                         struct rte_eth_rss_conf *rss_conf)
2357 {
2358         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2359         igc_hw_rss_hash_set(hw, rss_conf);
2360         return 0;
2361 }
2362
2363 static int
2364 eth_igc_rss_hash_conf_get(struct rte_eth_dev *dev,
2365                         struct rte_eth_rss_conf *rss_conf)
2366 {
2367         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2368         uint32_t *hash_key = (uint32_t *)rss_conf->rss_key;
2369         uint32_t mrqc;
2370         uint64_t rss_hf;
2371
2372         if (hash_key != NULL) {
2373                 int i;
2374
2375                 /* if not enough space for store hash key */
2376                 if (rss_conf->rss_key_len != IGC_HKEY_SIZE) {
2377                         PMD_DRV_LOG(ERR,
2378                                 "RSS hash key size %u in parameter doesn't match the hardware hash key size %u",
2379                                 rss_conf->rss_key_len, IGC_HKEY_SIZE);
2380                         return -EINVAL;
2381                 }
2382
2383                 /* read RSS key from register */
2384                 for (i = 0; i < IGC_HKEY_MAX_INDEX; i++)
2385                         hash_key[i] = IGC_READ_REG_LE_VALUE(hw, IGC_RSSRK(i));
2386         }
2387
2388         /* get RSS functions configured in MRQC register */
2389         mrqc = IGC_READ_REG(hw, IGC_MRQC);
2390         if ((mrqc & IGC_MRQC_ENABLE_RSS_4Q) == 0)
2391                 return 0;
2392
2393         rss_hf = 0;
2394         if (mrqc & IGC_MRQC_RSS_FIELD_IPV4)
2395                 rss_hf |= ETH_RSS_IPV4;
2396         if (mrqc & IGC_MRQC_RSS_FIELD_IPV4_TCP)
2397                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
2398         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6)
2399                 rss_hf |= ETH_RSS_IPV6;
2400         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_EX)
2401                 rss_hf |= ETH_RSS_IPV6_EX;
2402         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_TCP)
2403                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
2404         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_TCP_EX)
2405                 rss_hf |= ETH_RSS_IPV6_TCP_EX;
2406         if (mrqc & IGC_MRQC_RSS_FIELD_IPV4_UDP)
2407                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
2408         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_UDP)
2409                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
2410         if (mrqc & IGC_MRQC_RSS_FIELD_IPV6_UDP_EX)
2411                 rss_hf |= ETH_RSS_IPV6_UDP_EX;
2412
2413         rss_conf->rss_hf |= rss_hf;
2414         return 0;
2415 }
2416
2417 static int
2418 eth_igc_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2419 {
2420         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2421         struct igc_vfta *shadow_vfta = IGC_DEV_PRIVATE_VFTA(dev);
2422         uint32_t vfta;
2423         uint32_t vid_idx;
2424         uint32_t vid_bit;
2425
2426         vid_idx = (vlan_id >> IGC_VFTA_ENTRY_SHIFT) & IGC_VFTA_ENTRY_MASK;
2427         vid_bit = 1u << (vlan_id & IGC_VFTA_ENTRY_BIT_SHIFT_MASK);
2428         vfta = shadow_vfta->vfta[vid_idx];
2429         if (on)
2430                 vfta |= vid_bit;
2431         else
2432                 vfta &= ~vid_bit;
2433         IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, vid_idx, vfta);
2434
2435         /* update local VFTA copy */
2436         shadow_vfta->vfta[vid_idx] = vfta;
2437
2438         return 0;
2439 }
2440
2441 static void
2442 igc_vlan_hw_filter_disable(struct rte_eth_dev *dev)
2443 {
2444         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2445         igc_read_reg_check_clear_bits(hw, IGC_RCTL,
2446                         IGC_RCTL_CFIEN | IGC_RCTL_VFE);
2447 }
2448
2449 static void
2450 igc_vlan_hw_filter_enable(struct rte_eth_dev *dev)
2451 {
2452         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2453         struct igc_vfta *shadow_vfta = IGC_DEV_PRIVATE_VFTA(dev);
2454         uint32_t reg_val;
2455         int i;
2456
2457         /* Filter Table Enable, CFI not used for packet acceptance */
2458         reg_val = IGC_READ_REG(hw, IGC_RCTL);
2459         reg_val &= ~IGC_RCTL_CFIEN;
2460         reg_val |= IGC_RCTL_VFE;
2461         IGC_WRITE_REG(hw, IGC_RCTL, reg_val);
2462
2463         /* restore VFTA table */
2464         for (i = 0; i < IGC_VFTA_SIZE; i++)
2465                 IGC_WRITE_REG_ARRAY(hw, IGC_VFTA, i, shadow_vfta->vfta[i]);
2466 }
2467
2468 static void
2469 igc_vlan_hw_strip_disable(struct rte_eth_dev *dev)
2470 {
2471         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2472
2473         igc_read_reg_check_clear_bits(hw, IGC_CTRL, IGC_CTRL_VME);
2474 }
2475
2476 static void
2477 igc_vlan_hw_strip_enable(struct rte_eth_dev *dev)
2478 {
2479         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2480
2481         igc_read_reg_check_set_bits(hw, IGC_CTRL, IGC_CTRL_VME);
2482 }
2483
2484 static int
2485 igc_vlan_hw_extend_disable(struct rte_eth_dev *dev)
2486 {
2487         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2488         uint32_t ctrl_ext;
2489
2490         ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
2491
2492         /* if extend vlan hasn't been enabled */
2493         if ((ctrl_ext & IGC_CTRL_EXT_EXT_VLAN) == 0)
2494                 return 0;
2495
2496         if ((dev->data->dev_conf.rxmode.offloads &
2497                         DEV_RX_OFFLOAD_JUMBO_FRAME) == 0)
2498                 goto write_ext_vlan;
2499
2500         /* Update maximum packet length */
2501         if (dev->data->dev_conf.rxmode.max_rx_pkt_len <
2502                 RTE_ETHER_MIN_MTU + VLAN_TAG_SIZE) {
2503                 PMD_DRV_LOG(ERR, "Maximum packet length %u error, min is %u",
2504                         dev->data->dev_conf.rxmode.max_rx_pkt_len,
2505                         VLAN_TAG_SIZE + RTE_ETHER_MIN_MTU);
2506                 return -EINVAL;
2507         }
2508         dev->data->dev_conf.rxmode.max_rx_pkt_len -= VLAN_TAG_SIZE;
2509         IGC_WRITE_REG(hw, IGC_RLPML,
2510                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
2511
2512 write_ext_vlan:
2513         IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext & ~IGC_CTRL_EXT_EXT_VLAN);
2514         return 0;
2515 }
2516
2517 static int
2518 igc_vlan_hw_extend_enable(struct rte_eth_dev *dev)
2519 {
2520         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2521         uint32_t ctrl_ext;
2522
2523         ctrl_ext = IGC_READ_REG(hw, IGC_CTRL_EXT);
2524
2525         /* if extend vlan has been enabled */
2526         if (ctrl_ext & IGC_CTRL_EXT_EXT_VLAN)
2527                 return 0;
2528
2529         if ((dev->data->dev_conf.rxmode.offloads &
2530                         DEV_RX_OFFLOAD_JUMBO_FRAME) == 0)
2531                 goto write_ext_vlan;
2532
2533         /* Update maximum packet length */
2534         if (dev->data->dev_conf.rxmode.max_rx_pkt_len >
2535                 MAX_RX_JUMBO_FRAME_SIZE - VLAN_TAG_SIZE) {
2536                 PMD_DRV_LOG(ERR, "Maximum packet length %u error, max is %u",
2537                         dev->data->dev_conf.rxmode.max_rx_pkt_len +
2538                         VLAN_TAG_SIZE, MAX_RX_JUMBO_FRAME_SIZE);
2539                 return -EINVAL;
2540         }
2541         dev->data->dev_conf.rxmode.max_rx_pkt_len += VLAN_TAG_SIZE;
2542         IGC_WRITE_REG(hw, IGC_RLPML,
2543                 dev->data->dev_conf.rxmode.max_rx_pkt_len);
2544
2545 write_ext_vlan:
2546         IGC_WRITE_REG(hw, IGC_CTRL_EXT, ctrl_ext | IGC_CTRL_EXT_EXT_VLAN);
2547         return 0;
2548 }
2549
2550 static int
2551 eth_igc_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2552 {
2553         struct rte_eth_rxmode *rxmode;
2554
2555         rxmode = &dev->data->dev_conf.rxmode;
2556         if (mask & ETH_VLAN_STRIP_MASK) {
2557                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2558                         igc_vlan_hw_strip_enable(dev);
2559                 else
2560                         igc_vlan_hw_strip_disable(dev);
2561         }
2562
2563         if (mask & ETH_VLAN_FILTER_MASK) {
2564                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2565                         igc_vlan_hw_filter_enable(dev);
2566                 else
2567                         igc_vlan_hw_filter_disable(dev);
2568         }
2569
2570         if (mask & ETH_VLAN_EXTEND_MASK) {
2571                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2572                         return igc_vlan_hw_extend_enable(dev);
2573                 else
2574                         return igc_vlan_hw_extend_disable(dev);
2575         }
2576
2577         return 0;
2578 }
2579
2580 static int
2581 eth_igc_vlan_tpid_set(struct rte_eth_dev *dev,
2582                       enum rte_vlan_type vlan_type,
2583                       uint16_t tpid)
2584 {
2585         struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
2586         uint32_t reg_val;
2587
2588         /* only outer TPID of double VLAN can be configured*/
2589         if (vlan_type == ETH_VLAN_TYPE_OUTER) {
2590                 reg_val = IGC_READ_REG(hw, IGC_VET);
2591                 reg_val = (reg_val & (~IGC_VET_EXT)) |
2592                         ((uint32_t)tpid << IGC_VET_EXT_SHIFT);
2593                 IGC_WRITE_REG(hw, IGC_VET, reg_val);
2594
2595                 return 0;
2596         }
2597
2598         /* all other TPID values are read-only*/
2599         PMD_DRV_LOG(ERR, "Not supported");
2600         return -ENOTSUP;
2601 }
2602
2603 static int
2604 eth_igc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2605         struct rte_pci_device *pci_dev)
2606 {
2607         PMD_INIT_FUNC_TRACE();
2608         return rte_eth_dev_pci_generic_probe(pci_dev,
2609                 sizeof(struct igc_adapter), eth_igc_dev_init);
2610 }
2611
2612 static int
2613 eth_igc_pci_remove(struct rte_pci_device *pci_dev)
2614 {
2615         PMD_INIT_FUNC_TRACE();
2616         return rte_eth_dev_pci_generic_remove(pci_dev, eth_igc_dev_uninit);
2617 }
2618
2619 static struct rte_pci_driver rte_igc_pmd = {
2620         .id_table = pci_id_igc_map,
2621         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2622         .probe = eth_igc_pci_probe,
2623         .remove = eth_igc_pci_remove,
2624 };
2625
2626 RTE_PMD_REGISTER_PCI(net_igc, rte_igc_pmd);
2627 RTE_PMD_REGISTER_PCI_TABLE(net_igc, pci_id_igc_map);
2628 RTE_PMD_REGISTER_KMOD_DEP(net_igc, "* igb_uio | uio_pci_generic | vfio-pci");