1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2020 Intel Corporation
8 #include <rte_ethdev.h>
10 #include "base/igc_osdep.h"
11 #include "base/igc_hw.h"
12 #include "base/igc_i225.h"
13 #include "base/igc_api.h"
19 #define IGC_RSS_RDT_SIZD 128
21 /* VLAN filter table size */
22 #define IGC_VFTA_SIZE 128
24 #define IGC_QUEUE_PAIRS_NUM 4
26 #define IGC_HKEY_MAX_INDEX 10
27 #define IGC_RSS_RDT_SIZD 128
29 #define IGC_DEFAULT_REG_SIZE 4
30 #define IGC_DEFAULT_REG_SIZE_MASK 0xf
32 #define IGC_RSS_RDT_REG_SIZE IGC_DEFAULT_REG_SIZE
33 #define IGC_RSS_RDT_REG_SIZE_MASK IGC_DEFAULT_REG_SIZE_MASK
34 #define IGC_HKEY_REG_SIZE IGC_DEFAULT_REG_SIZE
35 #define IGC_HKEY_SIZE (IGC_HKEY_REG_SIZE * IGC_HKEY_MAX_INDEX)
38 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
39 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
40 * This will also optimize cache line size effect.
41 * H/W supports up to cache line size 128.
45 #define IGC_TX_DESCRIPTOR_MULTIPLE 8
46 #define IGC_RX_DESCRIPTOR_MULTIPLE 8
48 #define IGC_RXD_ALIGN ((uint16_t)(IGC_ALIGN / \
49 sizeof(union igc_adv_rx_desc)))
50 #define IGC_TXD_ALIGN ((uint16_t)(IGC_ALIGN / \
51 sizeof(union igc_adv_tx_desc)))
52 #define IGC_MIN_TXD IGC_TX_DESCRIPTOR_MULTIPLE
53 #define IGC_MAX_TXD ((uint16_t)(0x80000 / sizeof(union igc_adv_tx_desc)))
54 #define IGC_MIN_RXD IGC_RX_DESCRIPTOR_MULTIPLE
55 #define IGC_MAX_RXD ((uint16_t)(0x80000 / sizeof(union igc_adv_rx_desc)))
57 #define IGC_TX_MAX_SEG UINT8_MAX
58 #define IGC_TX_MAX_MTU_SEG UINT8_MAX
60 #define IGC_RX_OFFLOAD_ALL ( \
61 DEV_RX_OFFLOAD_VLAN_STRIP | \
62 DEV_RX_OFFLOAD_VLAN_FILTER | \
63 DEV_RX_OFFLOAD_VLAN_EXTEND | \
64 DEV_RX_OFFLOAD_IPV4_CKSUM | \
65 DEV_RX_OFFLOAD_UDP_CKSUM | \
66 DEV_RX_OFFLOAD_TCP_CKSUM | \
67 DEV_RX_OFFLOAD_SCTP_CKSUM | \
68 DEV_RX_OFFLOAD_JUMBO_FRAME | \
69 DEV_RX_OFFLOAD_KEEP_CRC | \
70 DEV_RX_OFFLOAD_SCATTER)
72 #define IGC_TX_OFFLOAD_ALL ( \
73 DEV_TX_OFFLOAD_VLAN_INSERT | \
74 DEV_TX_OFFLOAD_IPV4_CKSUM | \
75 DEV_TX_OFFLOAD_UDP_CKSUM | \
76 DEV_TX_OFFLOAD_TCP_CKSUM | \
77 DEV_TX_OFFLOAD_SCTP_CKSUM | \
78 DEV_TX_OFFLOAD_TCP_TSO | \
79 DEV_TX_OFFLOAD_UDP_TSO | \
80 DEV_TX_OFFLOAD_MULTI_SEGS)
82 #define IGC_RSS_OFFLOAD_ALL ( \
84 ETH_RSS_NONFRAG_IPV4_TCP | \
85 ETH_RSS_NONFRAG_IPV4_UDP | \
87 ETH_RSS_NONFRAG_IPV6_TCP | \
88 ETH_RSS_NONFRAG_IPV6_UDP | \
90 ETH_RSS_IPV6_TCP_EX | \
93 /* structure for interrupt relative data */
94 struct igc_interrupt {
99 /* Union of RSS redirect table register */
100 union igc_rss_reta_reg {
105 /* Structure to per-queue statics */
106 struct igc_hw_queue_stats {
107 u64 pqgprc[IGC_QUEUE_PAIRS_NUM];
108 /* per queue good packets received count */
109 u64 pqgptc[IGC_QUEUE_PAIRS_NUM];
110 /* per queue good packets transmitted count */
111 u64 pqgorc[IGC_QUEUE_PAIRS_NUM];
112 /* per queue good octets received count */
113 u64 pqgotc[IGC_QUEUE_PAIRS_NUM];
114 /* per queue good octets transmitted count */
115 u64 pqmprc[IGC_QUEUE_PAIRS_NUM];
116 /* per queue multicast packets received count */
117 u64 rqdpc[IGC_QUEUE_PAIRS_NUM];
118 /* per receive queue drop packet count */
119 u64 tqdpc[IGC_QUEUE_PAIRS_NUM];
120 /* per transmit queue drop packet count */
123 /* local vfta copy */
125 uint32_t vfta[IGC_VFTA_SIZE];
129 * Structure to store private data for each driver instance (for each port).
133 struct igc_hw_stats stats;
134 struct igc_hw_queue_stats queue_stats;
135 int16_t txq_stats_map[IGC_QUEUE_PAIRS_NUM];
136 int16_t rxq_stats_map[IGC_QUEUE_PAIRS_NUM];
138 struct igc_interrupt intr;
139 struct igc_vfta shadow_vfta;
143 #define IGC_DEV_PRIVATE(_dev) ((_dev)->data->dev_private)
145 #define IGC_DEV_PRIVATE_HW(_dev) \
146 (&((struct igc_adapter *)(_dev)->data->dev_private)->hw)
148 #define IGC_DEV_PRIVATE_STATS(_dev) \
149 (&((struct igc_adapter *)(_dev)->data->dev_private)->stats)
151 #define IGC_DEV_PRIVATE_QUEUE_STATS(_dev) \
152 (&((struct igc_adapter *)(_dev)->data->dev_private)->queue_stats)
154 #define IGC_DEV_PRIVATE_INTR(_dev) \
155 (&((struct igc_adapter *)(_dev)->data->dev_private)->intr)
157 #define IGC_DEV_PRIVATE_VFTA(_dev) \
158 (&((struct igc_adapter *)(_dev)->data->dev_private)->shadow_vfta)
161 igc_read_reg_check_set_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
163 uint32_t reg_val = IGC_READ_REG(hw, reg);
167 return; /* no need to write back */
169 IGC_WRITE_REG(hw, reg, bits);
173 igc_read_reg_check_clear_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
175 uint32_t reg_val = IGC_READ_REG(hw, reg);
177 bits = reg_val & ~bits;
179 return; /* no need to write back */
181 IGC_WRITE_REG(hw, reg, bits);
188 #endif /* _IGC_ETHDEV_H_ */