1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2020 Intel Corporation
8 #include <rte_ethdev.h>
10 #include "base/igc_osdep.h"
11 #include "base/igc_hw.h"
12 #include "base/igc_i225.h"
13 #include "base/igc_api.h"
19 #define IGC_RSS_RDT_SIZD 128
21 /* VLAN filter table size */
22 #define IGC_VFTA_SIZE 128
24 #define IGC_QUEUE_PAIRS_NUM 4
26 #define IGC_HKEY_MAX_INDEX 10
27 #define IGC_RSS_RDT_SIZD 128
29 #define IGC_DEFAULT_REG_SIZE 4
30 #define IGC_DEFAULT_REG_SIZE_MASK 0xf
32 #define IGC_RSS_RDT_REG_SIZE IGC_DEFAULT_REG_SIZE
33 #define IGC_RSS_RDT_REG_SIZE_MASK IGC_DEFAULT_REG_SIZE_MASK
34 #define IGC_HKEY_REG_SIZE IGC_DEFAULT_REG_SIZE
35 #define IGC_HKEY_SIZE (IGC_HKEY_REG_SIZE * IGC_HKEY_MAX_INDEX)
38 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
39 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
40 * This will also optimize cache line size effect.
41 * H/W supports up to cache line size 128.
45 #define IGC_TX_DESCRIPTOR_MULTIPLE 8
46 #define IGC_RX_DESCRIPTOR_MULTIPLE 8
48 #define IGC_RXD_ALIGN ((uint16_t)(IGC_ALIGN / \
49 sizeof(union igc_adv_rx_desc)))
50 #define IGC_TXD_ALIGN ((uint16_t)(IGC_ALIGN / \
51 sizeof(union igc_adv_tx_desc)))
52 #define IGC_MIN_TXD IGC_TX_DESCRIPTOR_MULTIPLE
53 #define IGC_MAX_TXD ((uint16_t)(0x80000 / sizeof(union igc_adv_tx_desc)))
54 #define IGC_MIN_RXD IGC_RX_DESCRIPTOR_MULTIPLE
55 #define IGC_MAX_RXD ((uint16_t)(0x80000 / sizeof(union igc_adv_rx_desc)))
57 #define IGC_TX_MAX_SEG UINT8_MAX
58 #define IGC_TX_MAX_MTU_SEG UINT8_MAX
60 #define IGC_RX_OFFLOAD_ALL ( \
61 DEV_RX_OFFLOAD_VLAN_STRIP | \
62 DEV_RX_OFFLOAD_VLAN_FILTER | \
63 DEV_RX_OFFLOAD_VLAN_EXTEND | \
64 DEV_RX_OFFLOAD_IPV4_CKSUM | \
65 DEV_RX_OFFLOAD_UDP_CKSUM | \
66 DEV_RX_OFFLOAD_TCP_CKSUM | \
67 DEV_RX_OFFLOAD_SCTP_CKSUM | \
68 DEV_RX_OFFLOAD_JUMBO_FRAME | \
69 DEV_RX_OFFLOAD_KEEP_CRC | \
70 DEV_RX_OFFLOAD_SCATTER | \
71 DEV_RX_OFFLOAD_RSS_HASH)
73 #define IGC_TX_OFFLOAD_ALL ( \
74 DEV_TX_OFFLOAD_VLAN_INSERT | \
75 DEV_TX_OFFLOAD_IPV4_CKSUM | \
76 DEV_TX_OFFLOAD_UDP_CKSUM | \
77 DEV_TX_OFFLOAD_TCP_CKSUM | \
78 DEV_TX_OFFLOAD_SCTP_CKSUM | \
79 DEV_TX_OFFLOAD_TCP_TSO | \
80 DEV_TX_OFFLOAD_UDP_TSO | \
81 DEV_TX_OFFLOAD_MULTI_SEGS)
83 #define IGC_RSS_OFFLOAD_ALL ( \
85 ETH_RSS_NONFRAG_IPV4_TCP | \
86 ETH_RSS_NONFRAG_IPV4_UDP | \
88 ETH_RSS_NONFRAG_IPV6_TCP | \
89 ETH_RSS_NONFRAG_IPV6_UDP | \
91 ETH_RSS_IPV6_TCP_EX | \
94 #define IGC_MAX_ETQF_FILTERS 3 /* etqf(3) is used for 1588 */
95 #define IGC_ETQF_FILTER_1588 3
96 #define IGC_ETQF_QUEUE_SHIFT 16
97 #define IGC_ETQF_QUEUE_MASK (7u << IGC_ETQF_QUEUE_SHIFT)
99 #define IGC_MAX_NTUPLE_FILTERS 8
100 #define IGC_NTUPLE_MAX_PRI 7
102 #define IGC_SYN_FILTER_ENABLE 0x01 /* syn filter enable field */
103 #define IGC_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field */
104 #define IGC_SYN_FILTER_QUEUE 0x0000000E /* syn filter queue field */
105 #define IGC_RFCTL_SYNQFP 0x00080000 /* SYNQFP in RFCTL register */
107 /* structure for interrupt relative data */
108 struct igc_interrupt {
113 /* Union of RSS redirect table register */
114 union igc_rss_reta_reg {
119 /* Structure to per-queue statics */
120 struct igc_hw_queue_stats {
121 u64 pqgprc[IGC_QUEUE_PAIRS_NUM];
122 /* per queue good packets received count */
123 u64 pqgptc[IGC_QUEUE_PAIRS_NUM];
124 /* per queue good packets transmitted count */
125 u64 pqgorc[IGC_QUEUE_PAIRS_NUM];
126 /* per queue good octets received count */
127 u64 pqgotc[IGC_QUEUE_PAIRS_NUM];
128 /* per queue good octets transmitted count */
129 u64 pqmprc[IGC_QUEUE_PAIRS_NUM];
130 /* per queue multicast packets received count */
131 u64 rqdpc[IGC_QUEUE_PAIRS_NUM];
132 /* per receive queue drop packet count */
133 u64 tqdpc[IGC_QUEUE_PAIRS_NUM];
134 /* per transmit queue drop packet count */
137 /* local vfta copy */
139 uint32_t vfta[IGC_VFTA_SIZE];
142 /* ethertype filter structure */
143 struct igc_ethertype_filter {
148 /* Structure of ntuple filter info. */
149 struct igc_ntuple_info {
151 uint8_t proto; /* l4 protocol. */
154 * the packet matched above 2tuple and contain any set bit will hit
160 * seven levels (001b-111b), 111b is highest, used when more than one
164 uint8_t dst_port_mask:1, /* if mask is 1b, do compare dst port. */
165 proto_mask:1; /* if mask is 1b, do compare protocol. */
168 /* Structure of n-tuple filter */
169 struct igc_ntuple_filter {
173 struct igc_ntuple_info tuple_info;
179 /* Structure of TCP SYN filter */
180 struct igc_syn_filter {
183 uint8_t hig_pri:1, /* 1 - higher priority than other filters, */
184 /* 0 - lower priority. */
185 enable:1; /* 1-enable; 0-disable */
188 /* Structure to store RTE flow RSS configure. */
189 struct igc_rss_filter {
190 struct rte_flow_action_rss conf; /* RSS parameters. */
191 uint8_t key[IGC_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
192 uint16_t queue[IGC_RSS_RDT_SIZD];/* Queues indices to use. */
193 uint8_t enable; /* 1-enabled, 0-disabled */
196 /* Feature filter types */
197 enum igc_filter_type {
198 IGC_FILTER_TYPE_ETHERTYPE,
199 IGC_FILTER_TYPE_NTUPLE,
204 /* Structure to store flow */
206 TAILQ_ENTRY(rte_flow) node;
207 enum igc_filter_type filter_type;
209 char filter[0]; /* filter data */
212 /* Flow list header */
213 TAILQ_HEAD(igc_flow_list, rte_flow);
216 * Structure to store private data for each driver instance (for each port).
220 struct igc_hw_stats stats;
221 struct igc_hw_queue_stats queue_stats;
222 int16_t txq_stats_map[IGC_QUEUE_PAIRS_NUM];
223 int16_t rxq_stats_map[IGC_QUEUE_PAIRS_NUM];
225 struct igc_interrupt intr;
226 struct igc_vfta shadow_vfta;
229 struct igc_ethertype_filter ethertype_filters[IGC_MAX_ETQF_FILTERS];
230 struct igc_ntuple_filter ntuple_filters[IGC_MAX_NTUPLE_FILTERS];
231 struct igc_syn_filter syn_filter;
232 struct igc_rss_filter rss_filter;
233 struct igc_flow_list flow_list;
236 #define IGC_DEV_PRIVATE(_dev) ((_dev)->data->dev_private)
238 #define IGC_DEV_PRIVATE_HW(_dev) \
239 (&((struct igc_adapter *)(_dev)->data->dev_private)->hw)
241 #define IGC_DEV_PRIVATE_STATS(_dev) \
242 (&((struct igc_adapter *)(_dev)->data->dev_private)->stats)
244 #define IGC_DEV_PRIVATE_QUEUE_STATS(_dev) \
245 (&((struct igc_adapter *)(_dev)->data->dev_private)->queue_stats)
247 #define IGC_DEV_PRIVATE_INTR(_dev) \
248 (&((struct igc_adapter *)(_dev)->data->dev_private)->intr)
250 #define IGC_DEV_PRIVATE_VFTA(_dev) \
251 (&((struct igc_adapter *)(_dev)->data->dev_private)->shadow_vfta)
253 #define IGC_DEV_PRIVATE_RSS_FILTER(_dev) \
254 (&((struct igc_adapter *)(_dev)->data->dev_private)->rss_filter)
256 #define IGC_DEV_PRIVATE_FLOW_LIST(_dev) \
257 (&((struct igc_adapter *)(_dev)->data->dev_private)->flow_list)
260 igc_read_reg_check_set_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
262 uint32_t reg_val = IGC_READ_REG(hw, reg);
266 return; /* no need to write back */
268 IGC_WRITE_REG(hw, reg, bits);
272 igc_read_reg_check_clear_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
274 uint32_t reg_val = IGC_READ_REG(hw, reg);
276 bits = reg_val & ~bits;
278 return; /* no need to write back */
280 IGC_WRITE_REG(hw, reg, bits);
287 #endif /* _IGC_ETHDEV_H_ */