1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2020 Intel Corporation
8 #include <rte_ethdev.h>
11 #include "base/igc_osdep.h"
12 #include "base/igc_hw.h"
13 #include "base/igc_i225.h"
14 #include "base/igc_api.h"
20 #define IGC_RSS_RDT_SIZD 128
22 /* VLAN filter table size */
23 #define IGC_VFTA_SIZE 128
25 #define IGC_QUEUE_PAIRS_NUM 4
27 #define IGC_HKEY_MAX_INDEX 10
28 #define IGC_RSS_RDT_SIZD 128
30 #define IGC_DEFAULT_REG_SIZE 4
31 #define IGC_DEFAULT_REG_SIZE_MASK 0xf
33 #define IGC_RSS_RDT_REG_SIZE IGC_DEFAULT_REG_SIZE
34 #define IGC_RSS_RDT_REG_SIZE_MASK IGC_DEFAULT_REG_SIZE_MASK
35 #define IGC_HKEY_REG_SIZE IGC_DEFAULT_REG_SIZE
36 #define IGC_HKEY_SIZE (IGC_HKEY_REG_SIZE * IGC_HKEY_MAX_INDEX)
39 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
40 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
41 * This will also optimize cache line size effect.
42 * H/W supports up to cache line size 128.
46 #define IGC_TX_DESCRIPTOR_MULTIPLE 8
47 #define IGC_RX_DESCRIPTOR_MULTIPLE 8
49 #define IGC_RXD_ALIGN ((uint16_t)(IGC_ALIGN / \
50 sizeof(union igc_adv_rx_desc)))
51 #define IGC_TXD_ALIGN ((uint16_t)(IGC_ALIGN / \
52 sizeof(union igc_adv_tx_desc)))
53 #define IGC_MIN_TXD IGC_TX_DESCRIPTOR_MULTIPLE
54 #define IGC_MAX_TXD ((uint16_t)(0x80000 / sizeof(union igc_adv_tx_desc)))
55 #define IGC_MIN_RXD IGC_RX_DESCRIPTOR_MULTIPLE
56 #define IGC_MAX_RXD ((uint16_t)(0x80000 / sizeof(union igc_adv_rx_desc)))
58 #define IGC_TX_MAX_SEG UINT8_MAX
59 #define IGC_TX_MAX_MTU_SEG UINT8_MAX
61 #define IGC_RX_OFFLOAD_ALL ( \
62 DEV_RX_OFFLOAD_VLAN_STRIP | \
63 DEV_RX_OFFLOAD_VLAN_FILTER | \
64 DEV_RX_OFFLOAD_VLAN_EXTEND | \
65 DEV_RX_OFFLOAD_IPV4_CKSUM | \
66 DEV_RX_OFFLOAD_UDP_CKSUM | \
67 DEV_RX_OFFLOAD_TCP_CKSUM | \
68 DEV_RX_OFFLOAD_SCTP_CKSUM | \
69 DEV_RX_OFFLOAD_JUMBO_FRAME | \
70 DEV_RX_OFFLOAD_KEEP_CRC | \
71 DEV_RX_OFFLOAD_SCATTER | \
72 DEV_RX_OFFLOAD_RSS_HASH)
74 #define IGC_TX_OFFLOAD_ALL ( \
75 DEV_TX_OFFLOAD_VLAN_INSERT | \
76 DEV_TX_OFFLOAD_IPV4_CKSUM | \
77 DEV_TX_OFFLOAD_UDP_CKSUM | \
78 DEV_TX_OFFLOAD_TCP_CKSUM | \
79 DEV_TX_OFFLOAD_SCTP_CKSUM | \
80 DEV_TX_OFFLOAD_TCP_TSO | \
81 DEV_TX_OFFLOAD_UDP_TSO | \
82 DEV_TX_OFFLOAD_MULTI_SEGS)
84 #define IGC_RSS_OFFLOAD_ALL ( \
86 ETH_RSS_NONFRAG_IPV4_TCP | \
87 ETH_RSS_NONFRAG_IPV4_UDP | \
89 ETH_RSS_NONFRAG_IPV6_TCP | \
90 ETH_RSS_NONFRAG_IPV6_UDP | \
92 ETH_RSS_IPV6_TCP_EX | \
95 #define IGC_MAX_ETQF_FILTERS 3 /* etqf(3) is used for 1588 */
96 #define IGC_ETQF_FILTER_1588 3
97 #define IGC_ETQF_QUEUE_SHIFT 16
98 #define IGC_ETQF_QUEUE_MASK (7u << IGC_ETQF_QUEUE_SHIFT)
100 #define IGC_MAX_NTUPLE_FILTERS 8
101 #define IGC_NTUPLE_MAX_PRI 7
103 #define IGC_SYN_FILTER_ENABLE 0x01 /* syn filter enable field */
104 #define IGC_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field */
105 #define IGC_SYN_FILTER_QUEUE 0x0000000E /* syn filter queue field */
106 #define IGC_RFCTL_SYNQFP 0x00080000 /* SYNQFP in RFCTL register */
108 /* structure for interrupt relative data */
109 struct igc_interrupt {
114 /* Union of RSS redirect table register */
115 union igc_rss_reta_reg {
120 /* Structure to per-queue statics */
121 struct igc_hw_queue_stats {
122 u64 pqgprc[IGC_QUEUE_PAIRS_NUM];
123 /* per queue good packets received count */
124 u64 pqgptc[IGC_QUEUE_PAIRS_NUM];
125 /* per queue good packets transmitted count */
126 u64 pqgorc[IGC_QUEUE_PAIRS_NUM];
127 /* per queue good octets received count */
128 u64 pqgotc[IGC_QUEUE_PAIRS_NUM];
129 /* per queue good octets transmitted count */
130 u64 pqmprc[IGC_QUEUE_PAIRS_NUM];
131 /* per queue multicast packets received count */
132 u64 rqdpc[IGC_QUEUE_PAIRS_NUM];
133 /* per receive queue drop packet count */
134 u64 tqdpc[IGC_QUEUE_PAIRS_NUM];
135 /* per transmit queue drop packet count */
138 /* local vfta copy */
140 uint32_t vfta[IGC_VFTA_SIZE];
143 /* ethertype filter structure */
144 struct igc_ethertype_filter {
149 /* Structure of ntuple filter info. */
150 struct igc_ntuple_info {
152 uint8_t proto; /* l4 protocol. */
155 * the packet matched above 2tuple and contain any set bit will hit
161 * seven levels (001b-111b), 111b is highest, used when more than one
165 uint8_t dst_port_mask:1, /* if mask is 1b, do compare dst port. */
166 proto_mask:1; /* if mask is 1b, do compare protocol. */
169 /* Structure of n-tuple filter */
170 struct igc_ntuple_filter {
174 struct igc_ntuple_info tuple_info;
180 /* Structure of TCP SYN filter */
181 struct igc_syn_filter {
184 uint8_t hig_pri:1, /* 1 - higher priority than other filters, */
185 /* 0 - lower priority. */
186 enable:1; /* 1-enable; 0-disable */
189 /* Structure to store RTE flow RSS configure. */
190 struct igc_rss_filter {
191 struct rte_flow_action_rss conf; /* RSS parameters. */
192 uint8_t key[IGC_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
193 uint16_t queue[IGC_RSS_RDT_SIZD];/* Queues indices to use. */
194 uint8_t enable; /* 1-enabled, 0-disabled */
197 /* Feature filter types */
198 enum igc_filter_type {
199 IGC_FILTER_TYPE_ETHERTYPE,
200 IGC_FILTER_TYPE_NTUPLE,
205 /* Structure to store flow */
207 TAILQ_ENTRY(rte_flow) node;
208 enum igc_filter_type filter_type;
210 char filter[0]; /* filter data */
213 /* Flow list header */
214 TAILQ_HEAD(igc_flow_list, rte_flow);
217 * Structure to store private data for each driver instance (for each port).
221 struct igc_hw_stats stats;
222 struct igc_hw_queue_stats queue_stats;
223 int16_t txq_stats_map[IGC_QUEUE_PAIRS_NUM];
224 int16_t rxq_stats_map[IGC_QUEUE_PAIRS_NUM];
226 struct igc_interrupt intr;
227 struct igc_vfta shadow_vfta;
230 struct igc_ethertype_filter ethertype_filters[IGC_MAX_ETQF_FILTERS];
231 struct igc_ntuple_filter ntuple_filters[IGC_MAX_NTUPLE_FILTERS];
232 struct igc_syn_filter syn_filter;
233 struct igc_rss_filter rss_filter;
234 struct igc_flow_list flow_list;
237 #define IGC_DEV_PRIVATE(_dev) ((_dev)->data->dev_private)
239 #define IGC_DEV_PRIVATE_HW(_dev) \
240 (&((struct igc_adapter *)(_dev)->data->dev_private)->hw)
242 #define IGC_DEV_PRIVATE_STATS(_dev) \
243 (&((struct igc_adapter *)(_dev)->data->dev_private)->stats)
245 #define IGC_DEV_PRIVATE_QUEUE_STATS(_dev) \
246 (&((struct igc_adapter *)(_dev)->data->dev_private)->queue_stats)
248 #define IGC_DEV_PRIVATE_INTR(_dev) \
249 (&((struct igc_adapter *)(_dev)->data->dev_private)->intr)
251 #define IGC_DEV_PRIVATE_VFTA(_dev) \
252 (&((struct igc_adapter *)(_dev)->data->dev_private)->shadow_vfta)
254 #define IGC_DEV_PRIVATE_RSS_FILTER(_dev) \
255 (&((struct igc_adapter *)(_dev)->data->dev_private)->rss_filter)
257 #define IGC_DEV_PRIVATE_FLOW_LIST(_dev) \
258 (&((struct igc_adapter *)(_dev)->data->dev_private)->flow_list)
261 igc_read_reg_check_set_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
263 uint32_t reg_val = IGC_READ_REG(hw, reg);
267 return; /* no need to write back */
269 IGC_WRITE_REG(hw, reg, bits);
273 igc_read_reg_check_clear_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
275 uint32_t reg_val = IGC_READ_REG(hw, reg);
277 bits = reg_val & ~bits;
279 return; /* no need to write back */
281 IGC_WRITE_REG(hw, reg, bits);
288 #endif /* _IGC_ETHDEV_H_ */