1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2020 Intel Corporation
8 #include <rte_ethdev.h>
11 #include "base/igc_osdep.h"
12 #include "base/igc_hw.h"
13 #include "base/igc_i225.h"
14 #include "base/igc_api.h"
20 #define IGC_RSS_RDT_SIZD 128
22 /* VLAN filter table size */
23 #define IGC_VFTA_SIZE 128
25 #define IGC_QUEUE_PAIRS_NUM 4
27 #define IGC_HKEY_MAX_INDEX 10
28 #define IGC_RSS_RDT_SIZD 128
30 #define IGC_DEFAULT_REG_SIZE 4
31 #define IGC_DEFAULT_REG_SIZE_MASK 0xf
33 #define IGC_RSS_RDT_REG_SIZE IGC_DEFAULT_REG_SIZE
34 #define IGC_RSS_RDT_REG_SIZE_MASK IGC_DEFAULT_REG_SIZE_MASK
35 #define IGC_HKEY_REG_SIZE IGC_DEFAULT_REG_SIZE
36 #define IGC_HKEY_SIZE (IGC_HKEY_REG_SIZE * IGC_HKEY_MAX_INDEX)
39 * The overhead from MTU to max frame size.
40 * Considering VLAN so tag needs to be counted.
42 #define IGC_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + \
43 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2)
46 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
47 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
48 * This will also optimize cache line size effect.
49 * H/W supports up to cache line size 128.
53 #define IGC_TX_DESCRIPTOR_MULTIPLE 8
54 #define IGC_RX_DESCRIPTOR_MULTIPLE 8
56 #define IGC_RXD_ALIGN ((uint16_t)(IGC_ALIGN / \
57 sizeof(union igc_adv_rx_desc)))
58 #define IGC_TXD_ALIGN ((uint16_t)(IGC_ALIGN / \
59 sizeof(union igc_adv_tx_desc)))
60 #define IGC_MIN_TXD IGC_TX_DESCRIPTOR_MULTIPLE
61 #define IGC_MAX_TXD ((uint16_t)(0x80000 / sizeof(union igc_adv_tx_desc)))
62 #define IGC_MIN_RXD IGC_RX_DESCRIPTOR_MULTIPLE
63 #define IGC_MAX_RXD ((uint16_t)(0x80000 / sizeof(union igc_adv_rx_desc)))
65 #define IGC_TX_MAX_SEG UINT8_MAX
66 #define IGC_TX_MAX_MTU_SEG UINT8_MAX
68 #define IGC_RX_OFFLOAD_ALL ( \
69 DEV_RX_OFFLOAD_VLAN_STRIP | \
70 DEV_RX_OFFLOAD_VLAN_FILTER | \
71 DEV_RX_OFFLOAD_VLAN_EXTEND | \
72 DEV_RX_OFFLOAD_IPV4_CKSUM | \
73 DEV_RX_OFFLOAD_UDP_CKSUM | \
74 DEV_RX_OFFLOAD_TCP_CKSUM | \
75 DEV_RX_OFFLOAD_SCTP_CKSUM | \
76 DEV_RX_OFFLOAD_JUMBO_FRAME | \
77 DEV_RX_OFFLOAD_KEEP_CRC | \
78 DEV_RX_OFFLOAD_SCATTER | \
79 DEV_RX_OFFLOAD_RSS_HASH)
81 #define IGC_TX_OFFLOAD_ALL ( \
82 DEV_TX_OFFLOAD_VLAN_INSERT | \
83 DEV_TX_OFFLOAD_IPV4_CKSUM | \
84 DEV_TX_OFFLOAD_UDP_CKSUM | \
85 DEV_TX_OFFLOAD_TCP_CKSUM | \
86 DEV_TX_OFFLOAD_SCTP_CKSUM | \
87 DEV_TX_OFFLOAD_TCP_TSO | \
88 DEV_TX_OFFLOAD_UDP_TSO | \
89 DEV_TX_OFFLOAD_MULTI_SEGS)
91 #define IGC_RSS_OFFLOAD_ALL ( \
93 ETH_RSS_NONFRAG_IPV4_TCP | \
94 ETH_RSS_NONFRAG_IPV4_UDP | \
96 ETH_RSS_NONFRAG_IPV6_TCP | \
97 ETH_RSS_NONFRAG_IPV6_UDP | \
99 ETH_RSS_IPV6_TCP_EX | \
102 #define IGC_MAX_ETQF_FILTERS 3 /* etqf(3) is used for 1588 */
103 #define IGC_ETQF_FILTER_1588 3
104 #define IGC_ETQF_QUEUE_SHIFT 16
105 #define IGC_ETQF_QUEUE_MASK (7u << IGC_ETQF_QUEUE_SHIFT)
107 #define IGC_MAX_NTUPLE_FILTERS 8
108 #define IGC_NTUPLE_MAX_PRI 7
110 #define IGC_SYN_FILTER_ENABLE 0x01 /* syn filter enable field */
111 #define IGC_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field */
112 #define IGC_SYN_FILTER_QUEUE 0x0000000E /* syn filter queue field */
113 #define IGC_RFCTL_SYNQFP 0x00080000 /* SYNQFP in RFCTL register */
115 /* structure for interrupt relative data */
116 struct igc_interrupt {
121 /* Union of RSS redirect table register */
122 union igc_rss_reta_reg {
127 /* Structure to per-queue statics */
128 struct igc_hw_queue_stats {
129 u64 pqgprc[IGC_QUEUE_PAIRS_NUM];
130 /* per queue good packets received count */
131 u64 pqgptc[IGC_QUEUE_PAIRS_NUM];
132 /* per queue good packets transmitted count */
133 u64 pqgorc[IGC_QUEUE_PAIRS_NUM];
134 /* per queue good octets received count */
135 u64 pqgotc[IGC_QUEUE_PAIRS_NUM];
136 /* per queue good octets transmitted count */
137 u64 pqmprc[IGC_QUEUE_PAIRS_NUM];
138 /* per queue multicast packets received count */
139 u64 rqdpc[IGC_QUEUE_PAIRS_NUM];
140 /* per receive queue drop packet count */
141 u64 tqdpc[IGC_QUEUE_PAIRS_NUM];
142 /* per transmit queue drop packet count */
145 /* local vfta copy */
147 uint32_t vfta[IGC_VFTA_SIZE];
150 /* ethertype filter structure */
151 struct igc_ethertype_filter {
156 /* Structure of ntuple filter info. */
157 struct igc_ntuple_info {
159 uint8_t proto; /* l4 protocol. */
162 * the packet matched above 2tuple and contain any set bit will hit
168 * seven levels (001b-111b), 111b is highest, used when more than one
172 uint8_t dst_port_mask:1, /* if mask is 1b, do compare dst port. */
173 proto_mask:1; /* if mask is 1b, do compare protocol. */
176 /* Structure of n-tuple filter */
177 struct igc_ntuple_filter {
181 struct igc_ntuple_info tuple_info;
187 /* Structure of TCP SYN filter */
188 struct igc_syn_filter {
191 uint8_t hig_pri:1, /* 1 - higher priority than other filters, */
192 /* 0 - lower priority. */
193 enable:1; /* 1-enable; 0-disable */
196 /* Structure to store RTE flow RSS configure. */
197 struct igc_rss_filter {
198 struct rte_flow_action_rss conf; /* RSS parameters. */
199 uint8_t key[IGC_HKEY_MAX_INDEX * sizeof(uint32_t)]; /* Hash key. */
200 uint16_t queue[IGC_RSS_RDT_SIZD];/* Queues indices to use. */
201 uint8_t enable; /* 1-enabled, 0-disabled */
204 /* Feature filter types */
205 enum igc_filter_type {
206 IGC_FILTER_TYPE_ETHERTYPE,
207 IGC_FILTER_TYPE_NTUPLE,
212 /* Structure to store flow */
214 TAILQ_ENTRY(rte_flow) node;
215 enum igc_filter_type filter_type;
217 char filter[0]; /* filter data */
220 /* Flow list header */
221 TAILQ_HEAD(igc_flow_list, rte_flow);
224 * Structure to store private data for each driver instance (for each port).
228 struct igc_hw_stats stats;
229 struct igc_hw_queue_stats queue_stats;
230 int16_t txq_stats_map[IGC_QUEUE_PAIRS_NUM];
231 int16_t rxq_stats_map[IGC_QUEUE_PAIRS_NUM];
233 struct igc_interrupt intr;
234 struct igc_vfta shadow_vfta;
237 struct igc_ethertype_filter ethertype_filters[IGC_MAX_ETQF_FILTERS];
238 struct igc_ntuple_filter ntuple_filters[IGC_MAX_NTUPLE_FILTERS];
239 struct igc_syn_filter syn_filter;
240 struct igc_rss_filter rss_filter;
241 struct igc_flow_list flow_list;
244 #define IGC_DEV_PRIVATE(_dev) ((_dev)->data->dev_private)
246 #define IGC_DEV_PRIVATE_HW(_dev) \
247 (&((struct igc_adapter *)(_dev)->data->dev_private)->hw)
249 #define IGC_DEV_PRIVATE_STATS(_dev) \
250 (&((struct igc_adapter *)(_dev)->data->dev_private)->stats)
252 #define IGC_DEV_PRIVATE_QUEUE_STATS(_dev) \
253 (&((struct igc_adapter *)(_dev)->data->dev_private)->queue_stats)
255 #define IGC_DEV_PRIVATE_INTR(_dev) \
256 (&((struct igc_adapter *)(_dev)->data->dev_private)->intr)
258 #define IGC_DEV_PRIVATE_VFTA(_dev) \
259 (&((struct igc_adapter *)(_dev)->data->dev_private)->shadow_vfta)
261 #define IGC_DEV_PRIVATE_RSS_FILTER(_dev) \
262 (&((struct igc_adapter *)(_dev)->data->dev_private)->rss_filter)
264 #define IGC_DEV_PRIVATE_FLOW_LIST(_dev) \
265 (&((struct igc_adapter *)(_dev)->data->dev_private)->flow_list)
268 igc_read_reg_check_set_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
270 uint32_t reg_val = IGC_READ_REG(hw, reg);
274 return; /* no need to write back */
276 IGC_WRITE_REG(hw, reg, bits);
280 igc_read_reg_check_clear_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
282 uint32_t reg_val = IGC_READ_REG(hw, reg);
284 bits = reg_val & ~bits;
286 return; /* no need to write back */
288 IGC_WRITE_REG(hw, reg, bits);
295 #endif /* _IGC_ETHDEV_H_ */