1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2019-2020 Intel Corporation
8 #include <rte_ethdev.h>
10 #include "base/igc_osdep.h"
11 #include "base/igc_hw.h"
12 #include "base/igc_i225.h"
13 #include "base/igc_api.h"
19 #define IGC_RSS_RDT_SIZD 128
20 #define IGC_QUEUE_PAIRS_NUM 4
22 #define IGC_HKEY_MAX_INDEX 10
23 #define IGC_RSS_RDT_SIZD 128
25 #define IGC_DEFAULT_REG_SIZE 4
26 #define IGC_DEFAULT_REG_SIZE_MASK 0xf
28 #define IGC_RSS_RDT_REG_SIZE IGC_DEFAULT_REG_SIZE
29 #define IGC_RSS_RDT_REG_SIZE_MASK IGC_DEFAULT_REG_SIZE_MASK
30 #define IGC_HKEY_REG_SIZE IGC_DEFAULT_REG_SIZE
31 #define IGC_HKEY_SIZE (IGC_HKEY_REG_SIZE * IGC_HKEY_MAX_INDEX)
34 * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
35 * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary.
36 * This will also optimize cache line size effect.
37 * H/W supports up to cache line size 128.
41 #define IGC_TX_DESCRIPTOR_MULTIPLE 8
42 #define IGC_RX_DESCRIPTOR_MULTIPLE 8
44 #define IGC_RXD_ALIGN ((uint16_t)(IGC_ALIGN / \
45 sizeof(union igc_adv_rx_desc)))
46 #define IGC_TXD_ALIGN ((uint16_t)(IGC_ALIGN / \
47 sizeof(union igc_adv_tx_desc)))
48 #define IGC_MIN_TXD IGC_TX_DESCRIPTOR_MULTIPLE
49 #define IGC_MAX_TXD ((uint16_t)(0x80000 / sizeof(union igc_adv_tx_desc)))
50 #define IGC_MIN_RXD IGC_RX_DESCRIPTOR_MULTIPLE
51 #define IGC_MAX_RXD ((uint16_t)(0x80000 / sizeof(union igc_adv_rx_desc)))
53 #define IGC_TX_MAX_SEG UINT8_MAX
54 #define IGC_TX_MAX_MTU_SEG UINT8_MAX
56 #define IGC_RX_OFFLOAD_ALL ( \
57 DEV_RX_OFFLOAD_IPV4_CKSUM | \
58 DEV_RX_OFFLOAD_UDP_CKSUM | \
59 DEV_RX_OFFLOAD_TCP_CKSUM | \
60 DEV_RX_OFFLOAD_SCTP_CKSUM | \
61 DEV_RX_OFFLOAD_JUMBO_FRAME | \
62 DEV_RX_OFFLOAD_KEEP_CRC | \
63 DEV_RX_OFFLOAD_SCATTER)
65 #define IGC_TX_OFFLOAD_ALL ( \
66 DEV_TX_OFFLOAD_VLAN_INSERT | \
67 DEV_TX_OFFLOAD_IPV4_CKSUM | \
68 DEV_TX_OFFLOAD_UDP_CKSUM | \
69 DEV_TX_OFFLOAD_TCP_CKSUM | \
70 DEV_TX_OFFLOAD_SCTP_CKSUM | \
71 DEV_TX_OFFLOAD_TCP_TSO | \
72 DEV_TX_OFFLOAD_UDP_TSO | \
73 DEV_TX_OFFLOAD_MULTI_SEGS)
75 #define IGC_RSS_OFFLOAD_ALL ( \
77 ETH_RSS_NONFRAG_IPV4_TCP | \
78 ETH_RSS_NONFRAG_IPV4_UDP | \
80 ETH_RSS_NONFRAG_IPV6_TCP | \
81 ETH_RSS_NONFRAG_IPV6_UDP | \
83 ETH_RSS_IPV6_TCP_EX | \
86 /* structure for interrupt relative data */
87 struct igc_interrupt {
92 /* Union of RSS redirect table register */
93 union igc_rss_reta_reg {
98 /* Structure to per-queue statics */
99 struct igc_hw_queue_stats {
100 u64 pqgprc[IGC_QUEUE_PAIRS_NUM];
101 /* per queue good packets received count */
102 u64 pqgptc[IGC_QUEUE_PAIRS_NUM];
103 /* per queue good packets transmitted count */
104 u64 pqgorc[IGC_QUEUE_PAIRS_NUM];
105 /* per queue good octets received count */
106 u64 pqgotc[IGC_QUEUE_PAIRS_NUM];
107 /* per queue good octets transmitted count */
108 u64 pqmprc[IGC_QUEUE_PAIRS_NUM];
109 /* per queue multicast packets received count */
110 u64 rqdpc[IGC_QUEUE_PAIRS_NUM];
111 /* per receive queue drop packet count */
112 u64 tqdpc[IGC_QUEUE_PAIRS_NUM];
113 /* per transmit queue drop packet count */
117 * Structure to store private data for each driver instance (for each port).
121 struct igc_hw_stats stats;
122 struct igc_hw_queue_stats queue_stats;
123 int16_t txq_stats_map[IGC_QUEUE_PAIRS_NUM];
124 int16_t rxq_stats_map[IGC_QUEUE_PAIRS_NUM];
126 struct igc_interrupt intr;
130 #define IGC_DEV_PRIVATE(_dev) ((_dev)->data->dev_private)
132 #define IGC_DEV_PRIVATE_HW(_dev) \
133 (&((struct igc_adapter *)(_dev)->data->dev_private)->hw)
135 #define IGC_DEV_PRIVATE_STATS(_dev) \
136 (&((struct igc_adapter *)(_dev)->data->dev_private)->stats)
138 #define IGC_DEV_PRIVATE_QUEUE_STATS(_dev) \
139 (&((struct igc_adapter *)(_dev)->data->dev_private)->queue_stats)
141 #define IGC_DEV_PRIVATE_INTR(_dev) \
142 (&((struct igc_adapter *)(_dev)->data->dev_private)->intr)
145 igc_read_reg_check_set_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
147 uint32_t reg_val = IGC_READ_REG(hw, reg);
151 return; /* no need to write back */
153 IGC_WRITE_REG(hw, reg, bits);
157 igc_read_reg_check_clear_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
159 uint32_t reg_val = IGC_READ_REG(hw, reg);
161 bits = reg_val & ~bits;
163 return; /* no need to write back */
165 IGC_WRITE_REG(hw, reg, bits);
172 #endif /* _IGC_ETHDEV_H_ */