1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
7 #include <rte_malloc.h>
10 #include "ionic_lif.h"
14 ionic_dev_setup(struct ionic_adapter *adapter)
16 struct ionic_dev_bar *bar = adapter->bars;
17 unsigned int num_bars = adapter->num_bars;
18 struct ionic_dev *idev = &adapter->idev;
23 /* BAR0: dev_cmd and interrupts */
25 IONIC_PRINT(ERR, "No bars found, aborting");
29 if (bar->len < IONIC_BAR0_SIZE) {
31 "Resource bar size %lu too small, aborting",
36 bar0_base = bar->vaddr;
37 idev->dev_info = (union ionic_dev_info_regs *)
38 &bar0_base[IONIC_BAR0_DEV_INFO_REGS_OFFSET];
39 idev->dev_cmd = (union ionic_dev_cmd_regs *)
40 &bar0_base[IONIC_BAR0_DEV_CMD_REGS_OFFSET];
41 idev->intr_status = (struct ionic_intr_status *)
42 &bar0_base[IONIC_BAR0_INTR_STATUS_OFFSET];
43 idev->intr_ctrl = (struct ionic_intr *)
44 &bar0_base[IONIC_BAR0_INTR_CTRL_OFFSET];
46 sig = ioread32(&idev->dev_info->signature);
47 if (sig != IONIC_DEV_INFO_SIGNATURE) {
48 IONIC_PRINT(ERR, "Incompatible firmware signature %" PRIx32 "",
53 for (i = 0; i < IONIC_DEVINFO_FWVERS_BUFLEN; i++)
54 adapter->fw_version[i] =
55 ioread8(&idev->dev_info->fw_version[i]);
56 adapter->fw_version[IONIC_DEVINFO_FWVERS_BUFLEN - 1] = '\0';
58 IONIC_PRINT(DEBUG, "Firmware version: %s", adapter->fw_version);
63 IONIC_PRINT(ERR, "Doorbell bar missing, aborting");
67 idev->db_pages = bar->vaddr;
72 /* Devcmd Interface */
75 ionic_dev_cmd_status(struct ionic_dev *idev)
77 return ioread8(&idev->dev_cmd->comp.comp.status);
81 ionic_dev_cmd_done(struct ionic_dev *idev)
83 return ioread32(&idev->dev_cmd->done) & IONIC_DEV_CMD_DONE;
87 ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem)
89 union ionic_dev_cmd_comp *comp = mem;
91 uint32_t comp_size = sizeof(comp->words) /
92 sizeof(comp->words[0]);
94 for (i = 0; i < comp_size; i++)
95 comp->words[i] = ioread32(&idev->dev_cmd->comp.words[i]);
99 ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
102 uint32_t cmd_size = sizeof(cmd->words) /
103 sizeof(cmd->words[0]);
105 IONIC_PRINT(DEBUG, "Sending %s (%d) via dev_cmd",
106 ionic_opcode_to_str(cmd->cmd.opcode), cmd->cmd.opcode);
108 for (i = 0; i < cmd_size; i++)
109 iowrite32(cmd->words[i], &idev->dev_cmd->cmd.words[i]);
111 iowrite32(0, &idev->dev_cmd->done);
112 iowrite32(1, &idev->dev_cmd->doorbell);
115 /* Device commands */
118 ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver)
120 union ionic_dev_cmd cmd = {
121 .identify.opcode = IONIC_CMD_IDENTIFY,
125 ionic_dev_cmd_go(idev, &cmd);
129 ionic_dev_cmd_init(struct ionic_dev *idev)
131 union ionic_dev_cmd cmd = {
132 .init.opcode = IONIC_CMD_INIT,
136 ionic_dev_cmd_go(idev, &cmd);
140 ionic_dev_cmd_reset(struct ionic_dev *idev)
142 union ionic_dev_cmd cmd = {
143 .reset.opcode = IONIC_CMD_RESET,
146 ionic_dev_cmd_go(idev, &cmd);
152 ionic_dev_cmd_port_identify(struct ionic_dev *idev)
154 union ionic_dev_cmd cmd = {
155 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY,
156 .port_init.index = 0,
159 ionic_dev_cmd_go(idev, &cmd);
163 ionic_dev_cmd_port_init(struct ionic_dev *idev)
165 union ionic_dev_cmd cmd = {
166 .port_init.opcode = IONIC_CMD_PORT_INIT,
167 .port_init.index = 0,
168 .port_init.info_pa = rte_cpu_to_le_64(idev->port_info_pa),
171 ionic_dev_cmd_go(idev, &cmd);
175 ionic_dev_cmd_port_reset(struct ionic_dev *idev)
177 union ionic_dev_cmd cmd = {
178 .port_reset.opcode = IONIC_CMD_PORT_RESET,
179 .port_reset.index = 0,
182 ionic_dev_cmd_go(idev, &cmd);
186 ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state)
188 union ionic_dev_cmd cmd = {
189 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
190 .port_setattr.index = 0,
191 .port_setattr.attr = IONIC_PORT_ATTR_STATE,
192 .port_setattr.state = state,
195 ionic_dev_cmd_go(idev, &cmd);
199 ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed)
201 union ionic_dev_cmd cmd = {
202 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
203 .port_setattr.index = 0,
204 .port_setattr.attr = IONIC_PORT_ATTR_SPEED,
205 .port_setattr.speed = rte_cpu_to_le_32(speed),
208 ionic_dev_cmd_go(idev, &cmd);
212 ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu)
214 union ionic_dev_cmd cmd = {
215 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
216 .port_setattr.index = 0,
217 .port_setattr.attr = IONIC_PORT_ATTR_MTU,
218 .port_setattr.mtu = rte_cpu_to_le_32(mtu),
221 ionic_dev_cmd_go(idev, &cmd);
225 ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable)
227 union ionic_dev_cmd cmd = {
228 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
229 .port_setattr.index = 0,
230 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
231 .port_setattr.an_enable = an_enable,
234 ionic_dev_cmd_go(idev, &cmd);
238 ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type)
240 union ionic_dev_cmd cmd = {
241 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
242 .port_setattr.index = 0,
243 .port_setattr.attr = IONIC_PORT_ATTR_FEC,
244 .port_setattr.fec_type = fec_type,
247 ionic_dev_cmd_go(idev, &cmd);
251 ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type)
253 union ionic_dev_cmd cmd = {
254 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
255 .port_setattr.index = 0,
256 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
257 .port_setattr.pause_type = pause_type,
260 ionic_dev_cmd_go(idev, &cmd);
264 ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode)
266 union ionic_dev_cmd cmd = {
267 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
268 .port_setattr.index = 0,
269 .port_setattr.attr = IONIC_PORT_ATTR_LOOPBACK,
270 .port_setattr.loopback_mode = loopback_mode,
273 ionic_dev_cmd_go(idev, &cmd);
279 ionic_dev_cmd_queue_identify(struct ionic_dev *idev,
280 uint16_t lif_type, uint8_t qtype, uint8_t qver)
282 union ionic_dev_cmd cmd = {
283 .q_identify.opcode = IONIC_CMD_Q_IDENTIFY,
284 .q_identify.lif_type = rte_cpu_to_le_16(lif_type),
285 .q_identify.type = qtype,
286 .q_identify.ver = qver,
289 ionic_dev_cmd_go(idev, &cmd);
293 ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver)
295 union ionic_dev_cmd cmd = {
296 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY,
297 .lif_identify.type = type,
298 .lif_identify.ver = ver,
301 ionic_dev_cmd_go(idev, &cmd);
305 ionic_dev_cmd_lif_init(struct ionic_dev *idev, rte_iova_t info_pa)
307 union ionic_dev_cmd cmd = {
308 .lif_init.opcode = IONIC_CMD_LIF_INIT,
309 .lif_init.info_pa = rte_cpu_to_le_64(info_pa),
312 ionic_dev_cmd_go(idev, &cmd);
316 ionic_dev_cmd_lif_reset(struct ionic_dev *idev)
318 union ionic_dev_cmd cmd = {
319 .lif_init.opcode = IONIC_CMD_LIF_RESET,
322 ionic_dev_cmd_go(idev, &cmd);
325 struct ionic_doorbell *
326 ionic_db_map(struct ionic_lif *lif, struct ionic_queue *q)
328 return lif->kern_dbpage + q->hw_type;
332 ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,
335 ionic_intr_clean(idev->intr_ctrl, index);
340 ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq)
342 struct ionic_queue *q = &qcq->q;
343 struct ionic_cq *cq = &qcq->cq;
345 union ionic_dev_cmd cmd = {
346 .q_init.opcode = IONIC_CMD_Q_INIT,
347 .q_init.type = q->type,
348 .q_init.ver = qcq->lif->qtype_info[q->type].version,
349 .q_init.index = rte_cpu_to_le_32(q->index),
350 .q_init.flags = rte_cpu_to_le_16(IONIC_QINIT_F_ENA),
351 .q_init.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),
352 .q_init.ring_size = rte_log2_u32(q->num_descs),
353 .q_init.ring_base = rte_cpu_to_le_64(q->base_pa),
354 .q_init.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),
357 IONIC_PRINT(DEBUG, "adminq.q_init.ver %u", cmd.q_init.ver);
359 ionic_dev_cmd_go(idev, &cmd);
363 ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
364 uint32_t num_descs, size_t desc_size)
366 if (desc_size == 0) {
367 IONIC_PRINT(ERR, "Descriptor size is %zu", desc_size);
371 if (!rte_is_power_of_2(num_descs) ||
372 num_descs < IONIC_MIN_RING_DESC ||
373 num_descs > IONIC_MAX_RING_DESC) {
374 IONIC_PRINT(ERR, "%u descriptors (min: %u max: %u)",
375 num_descs, IONIC_MIN_RING_DESC, IONIC_MAX_RING_DESC);
380 cq->num_descs = num_descs;
381 cq->desc_size = desc_size;
389 ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa)
392 cq->base_pa = base_pa;
396 ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q)
403 ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,
404 ionic_cq_cb cb, void *cb_arg)
406 uint32_t work_done = 0;
411 while (cb(cq, cq->tail_idx, cb_arg)) {
412 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
413 if (cq->tail_idx == 0)
414 cq->done_color = !cq->done_color;
416 if (++work_done == work_to_do)
424 ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
425 struct ionic_queue *q, uint32_t index, uint32_t num_descs,
426 size_t desc_size, size_t sg_desc_size)
430 if (desc_size == 0 || !rte_is_power_of_2(num_descs))
433 ring_size = rte_log2_u32(num_descs);
435 if (ring_size < 2 || ring_size > 16)
441 q->num_descs = num_descs;
442 q->desc_size = desc_size;
443 q->sg_desc_size = sg_desc_size;
451 ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
454 q->base_pa = base_pa;
458 ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
461 q->sg_base_pa = base_pa;
465 ionic_q_flush(struct ionic_queue *q)
467 writeq(IONIC_DBELL_QID(q->hw_index) | q->head_idx, q->db);
471 ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb,
474 struct ionic_desc_info *head = &q->info[q->head_idx];
477 head->cb_arg = cb_arg;
479 q->head_idx = (q->head_idx + 1) & (q->num_descs - 1);
486 ionic_q_space_avail(struct ionic_queue *q)
488 uint32_t avail = q->tail_idx;
490 if (q->head_idx >= avail)
491 avail += q->num_descs - q->head_idx - 1;
493 avail -= q->head_idx + 1;
499 ionic_q_has_space(struct ionic_queue *q, uint32_t want)
501 return ionic_q_space_avail(q) >= want;
505 ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index,
506 uint32_t stop_index, void *service_cb_arg)
508 struct ionic_desc_info *desc_info;
509 uint32_t curr_q_tail_idx;
512 desc_info = &q->info[q->tail_idx];
515 desc_info->cb(q, q->tail_idx, cq_desc_index,
516 desc_info->cb_arg, service_cb_arg);
518 desc_info->cb = NULL;
519 desc_info->cb_arg = NULL;
521 curr_q_tail_idx = q->tail_idx;
522 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
524 } while (curr_q_tail_idx != stop_index);
528 ionic_adminq_cb(struct ionic_queue *q,
529 uint32_t q_desc_index, uint32_t cq_desc_index,
530 void *cb_arg, void *service_cb_arg __rte_unused)
532 struct ionic_admin_ctx *ctx = cb_arg;
533 struct ionic_admin_comp *cq_desc_base = q->bound_cq->base;
534 struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
540 comp_index = rte_le_to_cpu_16(cq_desc->comp_index);
541 if (unlikely(comp_index != q_desc_index)) {
542 IONIC_WARN_ON(comp_index != q_desc_index);
546 memcpy(&ctx->comp, cq_desc, sizeof(*cq_desc));
548 ctx->pending_work = false; /* done */
551 /** ionic_adminq_post - Post an admin command.
552 * @lif: Handle to lif.
553 * @cmd_ctx: Api admin command context.
555 * Post the command to an admin queue in the ethernet driver. If this command
556 * succeeds, then the command has been posted, but that does not indicate a
557 * completion. If this command returns success, then the completion callback
558 * will eventually be called.
560 * Return: zero or negative error status.
563 ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)
565 struct ionic_queue *adminq = &lif->adminqcq->q;
566 struct ionic_admin_cmd *q_desc_base = adminq->base;
567 struct ionic_admin_cmd *q_desc;
570 rte_spinlock_lock(&lif->adminq_lock);
572 if (!ionic_q_has_space(adminq, 1)) {
577 q_desc = &q_desc_base[adminq->head_idx];
579 memcpy(q_desc, &ctx->cmd, sizeof(ctx->cmd));
581 ionic_q_post(adminq, true, ionic_adminq_cb, ctx);
584 rte_spinlock_unlock(&lif->adminq_lock);