drivers/net/ionic/ionic_dev.c

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
   3  */
   4
   5 #include <stdbool.h>
   6
   7 #include <rte_malloc.h>
   8
   9 #include "ionic_dev.h"
  10 #include "ionic_lif.h"
  11 #include "ionic.h"
  12
  13 int
  14 ionic_dev_setup(struct ionic_adapter *adapter)
  15 {
  16         struct ionic_dev_bar *bar = adapter->bars;
  17         unsigned int num_bars = adapter->num_bars;
  18         struct ionic_dev *idev = &adapter->idev;
  19         uint32_t sig;
  20         u_char *bar0_base;
  21         unsigned int i;
  22
  23         /* BAR0: dev_cmd and interrupts */
  24         if (num_bars < 1) {
  25                 IONIC_PRINT(ERR, "No bars found, aborting");
  26                 return -EFAULT;
  27         }
  28
  29         if (bar->len < IONIC_BAR0_SIZE) {
  30                 IONIC_PRINT(ERR,
  31                         "Resource bar size %lu too small, aborting",
  32                         bar->len);
  33                 return -EFAULT;
  34         }
  35
  36         bar0_base = bar->vaddr;
  37         idev->dev_info = (union ionic_dev_info_regs *)
  38                 &bar0_base[IONIC_BAR0_DEV_INFO_REGS_OFFSET];
  39         idev->dev_cmd = (union ionic_dev_cmd_regs *)
  40                 &bar0_base[IONIC_BAR0_DEV_CMD_REGS_OFFSET];
  41         idev->intr_status = (struct ionic_intr_status *)
  42                 &bar0_base[IONIC_BAR0_INTR_STATUS_OFFSET];
  43         idev->intr_ctrl = (struct ionic_intr *)
  44                 &bar0_base[IONIC_BAR0_INTR_CTRL_OFFSET];
  45
  46         sig = ioread32(&idev->dev_info->signature);
  47         if (sig != IONIC_DEV_INFO_SIGNATURE) {
  48                 IONIC_PRINT(ERR, "Incompatible firmware signature %" PRIx32 "",
  49                         sig);
  50                 return -EFAULT;
  51         }
  52
  53         for (i = 0; i < IONIC_DEVINFO_FWVERS_BUFLEN; i++)
  54                 adapter->fw_version[i] =
  55                         ioread8(&idev->dev_info->fw_version[i]);
  56         adapter->fw_version[IONIC_DEVINFO_FWVERS_BUFLEN - 1] = '\0';
  57
  58         IONIC_PRINT(DEBUG, "Firmware version: %s", adapter->fw_version);
  59
  60         /* BAR1: doorbells */
  61         bar++;
  62         if (num_bars < 2) {
  63                 IONIC_PRINT(ERR, "Doorbell bar missing, aborting");
  64                 return -EFAULT;
  65         }
  66
  67         idev->db_pages = bar->vaddr;
  68         idev->phy_db_pages = bar->bus_addr;
  69
  70         return 0;
  71 }
  72
  73 /* Devcmd Interface */
  74
  75 uint8_t
  76 ionic_dev_cmd_status(struct ionic_dev *idev)
  77 {
  78         return ioread8(&idev->dev_cmd->comp.comp.status);
  79 }
  80
  81 bool
  82 ionic_dev_cmd_done(struct ionic_dev *idev)
  83 {
  84         return ioread32(&idev->dev_cmd->done) & IONIC_DEV_CMD_DONE;
  85 }
  86
  87 void
  88 ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem)
  89 {
  90         union ionic_dev_cmd_comp *comp = mem;
  91         unsigned int i;
  92         uint32_t comp_size = sizeof(comp->words) /
  93                 sizeof(comp->words[0]);
  94
  95         for (i = 0; i < comp_size; i++)
  96                 comp->words[i] = ioread32(&idev->dev_cmd->comp.words[i]);
  97 }
  98
  99 void
 100 ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
 101 {
 102         unsigned int i;
 103         uint32_t cmd_size = sizeof(cmd->words) /
 104                 sizeof(cmd->words[0]);
 105
 106         for (i = 0; i < cmd_size; i++)
 107                 iowrite32(cmd->words[i], &idev->dev_cmd->cmd.words[i]);
 108
 109         iowrite32(0, &idev->dev_cmd->done);
 110         iowrite32(1, &idev->dev_cmd->doorbell);
 111 }
 112
 113 /* Device commands */
 114
 115 void
 116 ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver)
 117 {
 118         union ionic_dev_cmd cmd = {
 119                 .identify.opcode = IONIC_CMD_IDENTIFY,
 120                 .identify.ver = ver,
 121         };
 122
 123         ionic_dev_cmd_go(idev, &cmd);
 124 }
 125
 126 void
 127 ionic_dev_cmd_init(struct ionic_dev *idev)
 128 {
 129         union ionic_dev_cmd cmd = {
 130                 .init.opcode = IONIC_CMD_INIT,
 131                 .init.type = 0,
 132         };
 133
 134         ionic_dev_cmd_go(idev, &cmd);
 135 }
 136
 137 void
 138 ionic_dev_cmd_reset(struct ionic_dev *idev)
 139 {
 140         union ionic_dev_cmd cmd = {
 141                 .reset.opcode = IONIC_CMD_RESET,
 142         };
 143
 144         ionic_dev_cmd_go(idev, &cmd);
 145 }
 146
 147 /* Port commands */
 148
 149 void
 150 ionic_dev_cmd_port_identify(struct ionic_dev *idev)
 151 {
 152         union ionic_dev_cmd cmd = {
 153                 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY,
 154                 .port_init.index = 0,
 155         };
 156
 157         ionic_dev_cmd_go(idev, &cmd);
 158 }
 159
 160 void
 161 ionic_dev_cmd_port_init(struct ionic_dev *idev)
 162 {
 163         union ionic_dev_cmd cmd = {
 164                 .port_init.opcode = IONIC_CMD_PORT_INIT,
 165                 .port_init.index = 0,
 166                 .port_init.info_pa = idev->port_info_pa,
 167         };
 168
 169         ionic_dev_cmd_go(idev, &cmd);
 170 }
 171
 172 void
 173 ionic_dev_cmd_port_reset(struct ionic_dev *idev)
 174 {
 175         union ionic_dev_cmd cmd = {
 176                 .port_reset.opcode = IONIC_CMD_PORT_RESET,
 177                 .port_reset.index = 0,
 178         };
 179
 180         ionic_dev_cmd_go(idev, &cmd);
 181 }
 182
 183 void
 184 ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state)
 185 {
 186         union ionic_dev_cmd cmd = {
 187                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 188                 .port_setattr.index = 0,
 189                 .port_setattr.attr = IONIC_PORT_ATTR_STATE,
 190                 .port_setattr.state = state,
 191         };
 192
 193         ionic_dev_cmd_go(idev, &cmd);
 194 }
 195
 196 void
 197 ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed)
 198 {
 199         union ionic_dev_cmd cmd = {
 200                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 201                 .port_setattr.index = 0,
 202                 .port_setattr.attr = IONIC_PORT_ATTR_SPEED,
 203                 .port_setattr.speed = speed,
 204         };
 205
 206         ionic_dev_cmd_go(idev, &cmd);
 207 }
 208
 209 void
 210 ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu)
 211 {
 212         union ionic_dev_cmd cmd = {
 213                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 214                 .port_setattr.index = 0,
 215                 .port_setattr.attr = IONIC_PORT_ATTR_MTU,
 216                 .port_setattr.mtu = mtu,
 217         };
 218
 219         ionic_dev_cmd_go(idev, &cmd);
 220 }
 221
 222 void
 223 ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable)
 224 {
 225         union ionic_dev_cmd cmd = {
 226                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 227                 .port_setattr.index = 0,
 228                 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
 229                 .port_setattr.an_enable = an_enable,
 230         };
 231
 232         ionic_dev_cmd_go(idev, &cmd);
 233 }
 234
 235 void
 236 ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type)
 237 {
 238         union ionic_dev_cmd cmd = {
 239                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 240                 .port_setattr.index = 0,
 241                 .port_setattr.attr = IONIC_PORT_ATTR_FEC,
 242                 .port_setattr.fec_type = fec_type,
 243         };
 244
 245         ionic_dev_cmd_go(idev, &cmd);
 246 }
 247
 248 void
 249 ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type)
 250 {
 251         union ionic_dev_cmd cmd = {
 252                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 253                 .port_setattr.index = 0,
 254                 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
 255                 .port_setattr.pause_type = pause_type,
 256         };
 257
 258         ionic_dev_cmd_go(idev, &cmd);
 259 }
 260
 261 void
 262 ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode)
 263 {
 264         union ionic_dev_cmd cmd = {
 265                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 266                 .port_setattr.index = 0,
 267                 .port_setattr.attr = IONIC_PORT_ATTR_LOOPBACK,
 268                 .port_setattr.loopback_mode = loopback_mode,
 269         };
 270
 271         ionic_dev_cmd_go(idev, &cmd);
 272 }
 273
 274 /* LIF commands */
 275
 276 void
 277 ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver)
 278 {
 279         union ionic_dev_cmd cmd = {
 280                 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY,
 281                 .lif_identify.type = type,
 282                 .lif_identify.ver = ver,
 283         };
 284
 285         ionic_dev_cmd_go(idev, &cmd);
 286 }
 287
 288 void
 289 ionic_dev_cmd_lif_init(struct ionic_dev *idev, uint16_t lif_index,
 290                        rte_iova_t info_pa)
 291 {
 292         union ionic_dev_cmd cmd = {
 293                 .lif_init.opcode = IONIC_CMD_LIF_INIT,
 294                 .lif_init.index = lif_index,
 295                 .lif_init.info_pa = info_pa,
 296         };
 297
 298         ionic_dev_cmd_go(idev, &cmd);
 299 }
 300
 301 void
 302 ionic_dev_cmd_lif_reset(struct ionic_dev *idev, uint16_t lif_index)
 303 {
 304         union ionic_dev_cmd cmd = {
 305                 .lif_init.opcode = IONIC_CMD_LIF_RESET,
 306                 .lif_init.index = lif_index,
 307         };
 308
 309         ionic_dev_cmd_go(idev, &cmd);
 310 }
 311
 312 struct ionic_doorbell *
 313 ionic_db_map(struct ionic_lif *lif, struct ionic_queue *q)
 314 {
 315         return lif->kern_dbpage + q->hw_type;
 316 }
 317
 318 int
 319 ionic_db_page_num(struct ionic_lif *lif, int pid)
 320 {
 321         return (lif->index * 0) + pid;
 322 }
 323
 324 void
 325 ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,
 326                 unsigned long index)
 327 {
 328         ionic_intr_clean(idev->intr_ctrl, index);
 329         intr->index = index;
 330 }
 331
 332 void
 333 ionic_dev_cmd_adminq_init(struct ionic_dev *idev,
 334                 struct ionic_qcq *qcq,
 335                 uint16_t lif_index, uint16_t intr_index)
 336 {
 337         struct ionic_queue *q = &qcq->q;
 338         struct ionic_cq *cq = &qcq->cq;
 339
 340         union ionic_dev_cmd cmd = {
 341                 .q_init.opcode = IONIC_CMD_Q_INIT,
 342                 .q_init.lif_index = lif_index,
 343                 .q_init.type = q->type,
 344                 .q_init.index = q->index,
 345                 .q_init.flags = IONIC_QINIT_F_ENA,
 346                 .q_init.pid = q->pid,
 347                 .q_init.intr_index = intr_index,
 348                 .q_init.ring_size = rte_log2_u32(q->num_descs),
 349                 .q_init.ring_base = q->base_pa,
 350                 .q_init.cq_ring_base = cq->base_pa,
 351         };
 352
 353         ionic_dev_cmd_go(idev, &cmd);
 354 }
 355
 356 int
 357 ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
 358                 struct ionic_intr_info *intr,
 359                 uint32_t num_descs, size_t desc_size)
 360 {
 361         if (desc_size == 0) {
 362                 IONIC_PRINT(ERR, "Descriptor size is %zu", desc_size);
 363                 return -EINVAL;
 364         }
 365
 366         if (!rte_is_power_of_2(num_descs) ||
 367             num_descs < IONIC_MIN_RING_DESC ||
 368             num_descs > IONIC_MAX_RING_DESC) {
 369                 IONIC_PRINT(ERR, "%u descriptors (min: %u max: %u)",
 370                         num_descs, IONIC_MIN_RING_DESC, IONIC_MAX_RING_DESC);
 371                 return -EINVAL;
 372         }
 373
 374         cq->lif = lif;
 375         cq->bound_intr = intr;
 376         cq->num_descs = num_descs;
 377         cq->desc_size = desc_size;
 378         cq->tail_idx = 0;
 379         cq->done_color = 1;
 380
 381         return 0;
 382 }
 383
 384 void
 385 ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa)
 386 {
 387         cq->base = base;
 388         cq->base_pa = base_pa;
 389 }
 390
 391 void
 392 ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q)
 393 {
 394         cq->bound_q = q;
 395         q->bound_cq = cq;
 396 }
 397
 398 uint32_t
 399 ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,
 400                  ionic_cq_cb cb, void *cb_arg)
 401 {
 402         uint32_t work_done = 0;
 403
 404         if (work_to_do == 0)
 405                 return 0;
 406
 407         while (cb(cq, cq->tail_idx, cb_arg)) {
 408                 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
 409                 if (cq->tail_idx == 0)
 410                         cq->done_color = !cq->done_color;
 411
 412                 if (++work_done == work_to_do)
 413                         break;
 414         }
 415
 416         return work_done;
 417 }
 418
 419 int
 420 ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
 421              struct ionic_queue *q, uint32_t index, uint32_t num_descs,
 422              size_t desc_size, size_t sg_desc_size, uint32_t pid)
 423 {
 424         uint32_t ring_size;
 425
 426         if (desc_size == 0 || !rte_is_power_of_2(num_descs))
 427                 return -EINVAL;
 428
 429         ring_size = rte_log2_u32(num_descs);
 430
 431         if (ring_size < 2 || ring_size > 16)
 432                 return -EINVAL;
 433
 434         q->lif = lif;
 435         q->idev = idev;
 436         q->index = index;
 437         q->num_descs = num_descs;
 438         q->desc_size = desc_size;
 439         q->sg_desc_size = sg_desc_size;
 440         q->head_idx = 0;
 441         q->tail_idx = 0;
 442         q->pid = pid;
 443
 444         return 0;
 445 }
 446
 447 void
 448 ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
 449 {
 450         q->base = base;
 451         q->base_pa = base_pa;
 452 }
 453
 454 void
 455 ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
 456 {
 457         q->sg_base = base;
 458         q->sg_base_pa = base_pa;
 459 }
 460
 461 void
 462 ionic_q_flush(struct ionic_queue *q)
 463 {
 464         writeq(IONIC_DBELL_QID(q->hw_index) | q->head_idx, q->db);
 465 }
 466
 467 void
 468 ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb,
 469              void *cb_arg)
 470 {
 471         struct ionic_desc_info *head = &q->info[q->head_idx];
 472
 473         head->cb = cb;
 474         head->cb_arg = cb_arg;
 475
 476         q->head_idx = (q->head_idx + 1) & (q->num_descs - 1);
 477
 478         if (ring_doorbell)
 479                 ionic_q_flush(q);
 480 }
 481
 482 uint32_t
 483 ionic_q_space_avail(struct ionic_queue *q)
 484 {
 485         uint32_t avail = q->tail_idx;
 486
 487         if (q->head_idx >= avail)
 488                 avail += q->num_descs - q->head_idx - 1;
 489         else
 490                 avail -= q->head_idx + 1;
 491
 492         return avail;
 493 }
 494
 495 bool
 496 ionic_q_has_space(struct ionic_queue *q, uint32_t want)
 497 {
 498         return ionic_q_space_avail(q) >= want;
 499 }
 500
 501 void
 502 ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index,
 503                 uint32_t stop_index, void *service_cb_arg)
 504 {
 505         struct ionic_desc_info *desc_info;
 506         uint32_t curr_q_tail_idx;
 507
 508         do {
 509                 desc_info = &q->info[q->tail_idx];
 510
 511                 if (desc_info->cb)
 512                         desc_info->cb(q, q->tail_idx, cq_desc_index,
 513                                 desc_info->cb_arg, service_cb_arg);
 514
 515                 desc_info->cb = NULL;
 516                 desc_info->cb_arg = NULL;
 517
 518                 curr_q_tail_idx = q->tail_idx;
 519                 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
 520
 521         } while (curr_q_tail_idx != stop_index);
 522 }
 523
 524 static void
 525 ionic_adminq_cb(struct ionic_queue *q,
 526                 uint32_t q_desc_index, uint32_t cq_desc_index,
 527                 void *cb_arg, void *service_cb_arg __rte_unused)
 528 {
 529         struct ionic_admin_ctx *ctx = cb_arg;
 530         struct ionic_admin_comp *cq_desc_base = q->bound_cq->base;
 531         struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
 532
 533         if (unlikely(cq_desc->comp_index != q_desc_index)) {
 534                 IONIC_WARN_ON(cq_desc->comp_index != q_desc_index);
 535                 return;
 536         }
 537
 538         memcpy(&ctx->comp, cq_desc, sizeof(*cq_desc));
 539
 540         ctx->pending_work = false; /* done */
 541 }
 542
 543 /** ionic_adminq_post - Post an admin command.
 544  * @lif:                Handle to lif.
 545  * @cmd_ctx:            Api admin command context.
 546  *
 547  * Post the command to an admin queue in the ethernet driver.  If this command
 548  * succeeds, then the command has been posted, but that does not indicate a
 549  * completion.  If this command returns success, then the completion callback
 550  * will eventually be called.
 551  *
 552  * Return: zero or negative error status.
 553  */
 554 int
 555 ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)
 556 {
 557         struct ionic_queue *adminq = &lif->adminqcq->q;
 558         struct ionic_admin_cmd *q_desc_base = adminq->base;
 559         struct ionic_admin_cmd *q_desc;
 560         int err = 0;
 561
 562         rte_spinlock_lock(&lif->adminq_lock);
 563
 564         if (!ionic_q_has_space(adminq, 1)) {
 565                 err = -ENOSPC;
 566                 goto err_out;
 567         }
 568
 569         q_desc = &q_desc_base[adminq->head_idx];
 570
 571         memcpy(q_desc, &ctx->cmd, sizeof(ctx->cmd));
 572
 573         ionic_q_post(adminq, true, ionic_adminq_cb, ctx);
 574
 575 err_out:
 576         rte_spinlock_unlock(&lif->adminq_lock);
 577
 578         return err;
 579 }