drivers/net/ionic/ionic_dev.c

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
   3  */
   4
   5 #include <stdbool.h>
   6
   7 #include <rte_malloc.h>
   8
   9 #include "ionic_dev.h"
  10 #include "ionic_lif.h"
  11 #include "ionic.h"
  12
  13 int
  14 ionic_dev_setup(struct ionic_adapter *adapter)
  15 {
  16         struct ionic_dev_bar *bar = adapter->bars;
  17         unsigned int num_bars = adapter->num_bars;
  18         struct ionic_dev *idev = &adapter->idev;
  19         uint32_t sig;
  20         u_char *bar0_base;
  21         unsigned int i;
  22
  23         /* BAR0: dev_cmd and interrupts */
  24         if (num_bars < 1) {
  25                 IONIC_PRINT(ERR, "No bars found, aborting");
  26                 return -EFAULT;
  27         }
  28
  29         if (bar->len < IONIC_BAR0_SIZE) {
  30                 IONIC_PRINT(ERR,
  31                         "Resource bar size %lu too small, aborting",
  32                         bar->len);
  33                 return -EFAULT;
  34         }
  35
  36         bar0_base = bar->vaddr;
  37         idev->dev_info = (union ionic_dev_info_regs *)
  38                 &bar0_base[IONIC_BAR0_DEV_INFO_REGS_OFFSET];
  39         idev->dev_cmd = (union ionic_dev_cmd_regs *)
  40                 &bar0_base[IONIC_BAR0_DEV_CMD_REGS_OFFSET];
  41         idev->intr_status = (struct ionic_intr_status *)
  42                 &bar0_base[IONIC_BAR0_INTR_STATUS_OFFSET];
  43         idev->intr_ctrl = (struct ionic_intr *)
  44                 &bar0_base[IONIC_BAR0_INTR_CTRL_OFFSET];
  45
  46         sig = ioread32(&idev->dev_info->signature);
  47         if (sig != IONIC_DEV_INFO_SIGNATURE) {
  48                 IONIC_PRINT(ERR, "Incompatible firmware signature %" PRIx32 "",
  49                         sig);
  50                 return -EFAULT;
  51         }
  52
  53         for (i = 0; i < IONIC_DEVINFO_FWVERS_BUFLEN; i++)
  54                 adapter->fw_version[i] =
  55                         ioread8(&idev->dev_info->fw_version[i]);
  56         adapter->fw_version[IONIC_DEVINFO_FWVERS_BUFLEN - 1] = '\0';
  57
  58         IONIC_PRINT(DEBUG, "Firmware version: %s", adapter->fw_version);
  59
  60         /* BAR1: doorbells */
  61         bar++;
  62         if (num_bars < 2) {
  63                 IONIC_PRINT(ERR, "Doorbell bar missing, aborting");
  64                 return -EFAULT;
  65         }
  66
  67         idev->db_pages = bar->vaddr;
  68
  69         return 0;
  70 }
  71
  72 /* Devcmd Interface */
  73
  74 uint8_t
  75 ionic_dev_cmd_status(struct ionic_dev *idev)
  76 {
  77         return ioread8(&idev->dev_cmd->comp.comp.status);
  78 }
  79
  80 bool
  81 ionic_dev_cmd_done(struct ionic_dev *idev)
  82 {
  83         return ioread32(&idev->dev_cmd->done) & IONIC_DEV_CMD_DONE;
  84 }
  85
  86 void
  87 ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem)
  88 {
  89         union ionic_dev_cmd_comp *comp = mem;
  90         unsigned int i;
  91         uint32_t comp_size = sizeof(comp->words) /
  92                 sizeof(comp->words[0]);
  93
  94         for (i = 0; i < comp_size; i++)
  95                 comp->words[i] = ioread32(&idev->dev_cmd->comp.words[i]);
  96 }
  97
  98 void
  99 ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
 100 {
 101         unsigned int i;
 102         uint32_t cmd_size = sizeof(cmd->words) /
 103                 sizeof(cmd->words[0]);
 104
 105         for (i = 0; i < cmd_size; i++)
 106                 iowrite32(cmd->words[i], &idev->dev_cmd->cmd.words[i]);
 107
 108         iowrite32(0, &idev->dev_cmd->done);
 109         iowrite32(1, &idev->dev_cmd->doorbell);
 110 }
 111
 112 /* Device commands */
 113
 114 void
 115 ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver)
 116 {
 117         union ionic_dev_cmd cmd = {
 118                 .identify.opcode = IONIC_CMD_IDENTIFY,
 119                 .identify.ver = ver,
 120         };
 121
 122         ionic_dev_cmd_go(idev, &cmd);
 123 }
 124
 125 void
 126 ionic_dev_cmd_init(struct ionic_dev *idev)
 127 {
 128         union ionic_dev_cmd cmd = {
 129                 .init.opcode = IONIC_CMD_INIT,
 130                 .init.type = 0,
 131         };
 132
 133         ionic_dev_cmd_go(idev, &cmd);
 134 }
 135
 136 void
 137 ionic_dev_cmd_reset(struct ionic_dev *idev)
 138 {
 139         union ionic_dev_cmd cmd = {
 140                 .reset.opcode = IONIC_CMD_RESET,
 141         };
 142
 143         ionic_dev_cmd_go(idev, &cmd);
 144 }
 145
 146 /* Port commands */
 147
 148 void
 149 ionic_dev_cmd_port_identify(struct ionic_dev *idev)
 150 {
 151         union ionic_dev_cmd cmd = {
 152                 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY,
 153                 .port_init.index = 0,
 154         };
 155
 156         ionic_dev_cmd_go(idev, &cmd);
 157 }
 158
 159 void
 160 ionic_dev_cmd_port_init(struct ionic_dev *idev)
 161 {
 162         union ionic_dev_cmd cmd = {
 163                 .port_init.opcode = IONIC_CMD_PORT_INIT,
 164                 .port_init.index = 0,
 165                 .port_init.info_pa = idev->port_info_pa,
 166         };
 167
 168         ionic_dev_cmd_go(idev, &cmd);
 169 }
 170
 171 void
 172 ionic_dev_cmd_port_reset(struct ionic_dev *idev)
 173 {
 174         union ionic_dev_cmd cmd = {
 175                 .port_reset.opcode = IONIC_CMD_PORT_RESET,
 176                 .port_reset.index = 0,
 177         };
 178
 179         ionic_dev_cmd_go(idev, &cmd);
 180 }
 181
 182 void
 183 ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state)
 184 {
 185         union ionic_dev_cmd cmd = {
 186                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 187                 .port_setattr.index = 0,
 188                 .port_setattr.attr = IONIC_PORT_ATTR_STATE,
 189                 .port_setattr.state = state,
 190         };
 191
 192         ionic_dev_cmd_go(idev, &cmd);
 193 }
 194
 195 void
 196 ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed)
 197 {
 198         union ionic_dev_cmd cmd = {
 199                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 200                 .port_setattr.index = 0,
 201                 .port_setattr.attr = IONIC_PORT_ATTR_SPEED,
 202                 .port_setattr.speed = speed,
 203         };
 204
 205         ionic_dev_cmd_go(idev, &cmd);
 206 }
 207
 208 void
 209 ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu)
 210 {
 211         union ionic_dev_cmd cmd = {
 212                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 213                 .port_setattr.index = 0,
 214                 .port_setattr.attr = IONIC_PORT_ATTR_MTU,
 215                 .port_setattr.mtu = mtu,
 216         };
 217
 218         ionic_dev_cmd_go(idev, &cmd);
 219 }
 220
 221 void
 222 ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable)
 223 {
 224         union ionic_dev_cmd cmd = {
 225                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 226                 .port_setattr.index = 0,
 227                 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
 228                 .port_setattr.an_enable = an_enable,
 229         };
 230
 231         ionic_dev_cmd_go(idev, &cmd);
 232 }
 233
 234 void
 235 ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type)
 236 {
 237         union ionic_dev_cmd cmd = {
 238                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 239                 .port_setattr.index = 0,
 240                 .port_setattr.attr = IONIC_PORT_ATTR_FEC,
 241                 .port_setattr.fec_type = fec_type,
 242         };
 243
 244         ionic_dev_cmd_go(idev, &cmd);
 245 }
 246
 247 void
 248 ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type)
 249 {
 250         union ionic_dev_cmd cmd = {
 251                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 252                 .port_setattr.index = 0,
 253                 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
 254                 .port_setattr.pause_type = pause_type,
 255         };
 256
 257         ionic_dev_cmd_go(idev, &cmd);
 258 }
 259
 260 void
 261 ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode)
 262 {
 263         union ionic_dev_cmd cmd = {
 264                 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
 265                 .port_setattr.index = 0,
 266                 .port_setattr.attr = IONIC_PORT_ATTR_LOOPBACK,
 267                 .port_setattr.loopback_mode = loopback_mode,
 268         };
 269
 270         ionic_dev_cmd_go(idev, &cmd);
 271 }
 272
 273 /* LIF commands */
 274
 275 void
 276 ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver)
 277 {
 278         union ionic_dev_cmd cmd = {
 279                 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY,
 280                 .lif_identify.type = type,
 281                 .lif_identify.ver = ver,
 282         };
 283
 284         ionic_dev_cmd_go(idev, &cmd);
 285 }
 286
 287 void
 288 ionic_dev_cmd_lif_init(struct ionic_dev *idev, uint16_t lif_index,
 289                        rte_iova_t info_pa)
 290 {
 291         union ionic_dev_cmd cmd = {
 292                 .lif_init.opcode = IONIC_CMD_LIF_INIT,
 293                 .lif_init.index = lif_index,
 294                 .lif_init.info_pa = info_pa,
 295         };
 296
 297         ionic_dev_cmd_go(idev, &cmd);
 298 }
 299
 300 void
 301 ionic_dev_cmd_lif_reset(struct ionic_dev *idev, uint16_t lif_index)
 302 {
 303         union ionic_dev_cmd cmd = {
 304                 .lif_init.opcode = IONIC_CMD_LIF_RESET,
 305                 .lif_init.index = lif_index,
 306         };
 307
 308         ionic_dev_cmd_go(idev, &cmd);
 309 }
 310
 311 struct ionic_doorbell *
 312 ionic_db_map(struct ionic_lif *lif, struct ionic_queue *q)
 313 {
 314         return lif->kern_dbpage + q->hw_type;
 315 }
 316
 317 int
 318 ionic_db_page_num(struct ionic_lif *lif, int pid)
 319 {
 320         return (lif->index * 0) + pid;
 321 }
 322
 323 void
 324 ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,
 325                 unsigned long index)
 326 {
 327         ionic_intr_clean(idev->intr_ctrl, index);
 328         intr->index = index;
 329 }
 330
 331 void
 332 ionic_dev_cmd_adminq_init(struct ionic_dev *idev,
 333                 struct ionic_qcq *qcq,
 334                 uint16_t lif_index, uint16_t intr_index)
 335 {
 336         struct ionic_queue *q = &qcq->q;
 337         struct ionic_cq *cq = &qcq->cq;
 338
 339         union ionic_dev_cmd cmd = {
 340                 .q_init.opcode = IONIC_CMD_Q_INIT,
 341                 .q_init.lif_index = lif_index,
 342                 .q_init.type = q->type,
 343                 .q_init.index = q->index,
 344                 .q_init.flags = IONIC_QINIT_F_ENA,
 345                 .q_init.intr_index = intr_index,
 346                 .q_init.ring_size = rte_log2_u32(q->num_descs),
 347                 .q_init.ring_base = q->base_pa,
 348                 .q_init.cq_ring_base = cq->base_pa,
 349         };
 350
 351         ionic_dev_cmd_go(idev, &cmd);
 352 }
 353
 354 int
 355 ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
 356                 struct ionic_intr_info *intr,
 357                 uint32_t num_descs, size_t desc_size)
 358 {
 359         if (desc_size == 0) {
 360                 IONIC_PRINT(ERR, "Descriptor size is %zu", desc_size);
 361                 return -EINVAL;
 362         }
 363
 364         if (!rte_is_power_of_2(num_descs) ||
 365             num_descs < IONIC_MIN_RING_DESC ||
 366             num_descs > IONIC_MAX_RING_DESC) {
 367                 IONIC_PRINT(ERR, "%u descriptors (min: %u max: %u)",
 368                         num_descs, IONIC_MIN_RING_DESC, IONIC_MAX_RING_DESC);
 369                 return -EINVAL;
 370         }
 371
 372         cq->lif = lif;
 373         cq->bound_intr = intr;
 374         cq->num_descs = num_descs;
 375         cq->desc_size = desc_size;
 376         cq->tail_idx = 0;
 377         cq->done_color = 1;
 378
 379         return 0;
 380 }
 381
 382 void
 383 ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa)
 384 {
 385         cq->base = base;
 386         cq->base_pa = base_pa;
 387 }
 388
 389 void
 390 ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q)
 391 {
 392         cq->bound_q = q;
 393         q->bound_cq = cq;
 394 }
 395
 396 uint32_t
 397 ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,
 398                  ionic_cq_cb cb, void *cb_arg)
 399 {
 400         uint32_t work_done = 0;
 401
 402         if (work_to_do == 0)
 403                 return 0;
 404
 405         while (cb(cq, cq->tail_idx, cb_arg)) {
 406                 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
 407                 if (cq->tail_idx == 0)
 408                         cq->done_color = !cq->done_color;
 409
 410                 if (++work_done == work_to_do)
 411                         break;
 412         }
 413
 414         return work_done;
 415 }
 416
 417 int
 418 ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
 419              struct ionic_queue *q, uint32_t index, uint32_t num_descs,
 420              size_t desc_size, size_t sg_desc_size)
 421 {
 422         uint32_t ring_size;
 423
 424         if (desc_size == 0 || !rte_is_power_of_2(num_descs))
 425                 return -EINVAL;
 426
 427         ring_size = rte_log2_u32(num_descs);
 428
 429         if (ring_size < 2 || ring_size > 16)
 430                 return -EINVAL;
 431
 432         q->lif = lif;
 433         q->idev = idev;
 434         q->index = index;
 435         q->num_descs = num_descs;
 436         q->desc_size = desc_size;
 437         q->sg_desc_size = sg_desc_size;
 438         q->head_idx = 0;
 439         q->tail_idx = 0;
 440
 441         return 0;
 442 }
 443
 444 void
 445 ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
 446 {
 447         q->base = base;
 448         q->base_pa = base_pa;
 449 }
 450
 451 void
 452 ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
 453 {
 454         q->sg_base = base;
 455         q->sg_base_pa = base_pa;
 456 }
 457
 458 void
 459 ionic_q_flush(struct ionic_queue *q)
 460 {
 461         writeq(IONIC_DBELL_QID(q->hw_index) | q->head_idx, q->db);
 462 }
 463
 464 void
 465 ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb,
 466              void *cb_arg)
 467 {
 468         struct ionic_desc_info *head = &q->info[q->head_idx];
 469
 470         head->cb = cb;
 471         head->cb_arg = cb_arg;
 472
 473         q->head_idx = (q->head_idx + 1) & (q->num_descs - 1);
 474
 475         if (ring_doorbell)
 476                 ionic_q_flush(q);
 477 }
 478
 479 uint32_t
 480 ionic_q_space_avail(struct ionic_queue *q)
 481 {
 482         uint32_t avail = q->tail_idx;
 483
 484         if (q->head_idx >= avail)
 485                 avail += q->num_descs - q->head_idx - 1;
 486         else
 487                 avail -= q->head_idx + 1;
 488
 489         return avail;
 490 }
 491
 492 bool
 493 ionic_q_has_space(struct ionic_queue *q, uint32_t want)
 494 {
 495         return ionic_q_space_avail(q) >= want;
 496 }
 497
 498 void
 499 ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index,
 500                 uint32_t stop_index, void *service_cb_arg)
 501 {
 502         struct ionic_desc_info *desc_info;
 503         uint32_t curr_q_tail_idx;
 504
 505         do {
 506                 desc_info = &q->info[q->tail_idx];
 507
 508                 if (desc_info->cb)
 509                         desc_info->cb(q, q->tail_idx, cq_desc_index,
 510                                 desc_info->cb_arg, service_cb_arg);
 511
 512                 desc_info->cb = NULL;
 513                 desc_info->cb_arg = NULL;
 514
 515                 curr_q_tail_idx = q->tail_idx;
 516                 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
 517
 518         } while (curr_q_tail_idx != stop_index);
 519 }
 520
 521 static void
 522 ionic_adminq_cb(struct ionic_queue *q,
 523                 uint32_t q_desc_index, uint32_t cq_desc_index,
 524                 void *cb_arg, void *service_cb_arg __rte_unused)
 525 {
 526         struct ionic_admin_ctx *ctx = cb_arg;
 527         struct ionic_admin_comp *cq_desc_base = q->bound_cq->base;
 528         struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
 529
 530         if (unlikely(cq_desc->comp_index != q_desc_index)) {
 531                 IONIC_WARN_ON(cq_desc->comp_index != q_desc_index);
 532                 return;
 533         }
 534
 535         memcpy(&ctx->comp, cq_desc, sizeof(*cq_desc));
 536
 537         ctx->pending_work = false; /* done */
 538 }
 539
 540 /** ionic_adminq_post - Post an admin command.
 541  * @lif:                Handle to lif.
 542  * @cmd_ctx:            Api admin command context.
 543  *
 544  * Post the command to an admin queue in the ethernet driver.  If this command
 545  * succeeds, then the command has been posted, but that does not indicate a
 546  * completion.  If this command returns success, then the completion callback
 547  * will eventually be called.
 548  *
 549  * Return: zero or negative error status.
 550  */
 551 int
 552 ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)
 553 {
 554         struct ionic_queue *adminq = &lif->adminqcq->q;
 555         struct ionic_admin_cmd *q_desc_base = adminq->base;
 556         struct ionic_admin_cmd *q_desc;
 557         int err = 0;
 558
 559         rte_spinlock_lock(&lif->adminq_lock);
 560
 561         if (!ionic_q_has_space(adminq, 1)) {
 562                 err = -ENOSPC;
 563                 goto err_out;
 564         }
 565
 566         q_desc = &q_desc_base[adminq->head_idx];
 567
 568         memcpy(q_desc, &ctx->cmd, sizeof(ctx->cmd));
 569
 570         ionic_q_post(adminq, true, ionic_adminq_cb, ctx);
 571
 572 err_out:
 573         rte_spinlock_unlock(&lif->adminq_lock);
 574
 575         return err;
 576 }