1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
5 #include <rte_malloc.h>
12 ionic_dev_setup(struct ionic_adapter *adapter)
14 struct ionic_dev_bar *bar = adapter->bars;
15 unsigned int num_bars = adapter->num_bars;
16 struct ionic_dev *idev = &adapter->idev;
21 /* BAR0: dev_cmd and interrupts */
23 IONIC_PRINT(ERR, "No bars found, aborting");
27 if (bar->len < IONIC_BAR0_SIZE) {
29 "Resource bar size %lu too small, aborting",
34 bar0_base = bar->vaddr;
35 idev->dev_info = (union ionic_dev_info_regs *)
36 &bar0_base[IONIC_BAR0_DEV_INFO_REGS_OFFSET];
37 idev->dev_cmd = (union ionic_dev_cmd_regs *)
38 &bar0_base[IONIC_BAR0_DEV_CMD_REGS_OFFSET];
39 idev->intr_status = (struct ionic_intr_status *)
40 &bar0_base[IONIC_BAR0_INTR_STATUS_OFFSET];
41 idev->intr_ctrl = (struct ionic_intr *)
42 &bar0_base[IONIC_BAR0_INTR_CTRL_OFFSET];
44 sig = ioread32(&idev->dev_info->signature);
45 if (sig != IONIC_DEV_INFO_SIGNATURE) {
46 IONIC_PRINT(ERR, "Incompatible firmware signature %" PRIx32 "",
51 for (i = 0; i < IONIC_DEVINFO_FWVERS_BUFLEN; i++)
52 adapter->fw_version[i] =
53 ioread8(&idev->dev_info->fw_version[i]);
54 adapter->fw_version[IONIC_DEVINFO_FWVERS_BUFLEN - 1] = '\0';
56 IONIC_PRINT(DEBUG, "Firmware version: %s", adapter->fw_version);
61 IONIC_PRINT(ERR, "Doorbell bar missing, aborting");
65 idev->db_pages = bar->vaddr;
66 idev->phy_db_pages = bar->bus_addr;
71 /* Devcmd Interface */
74 ionic_dev_cmd_status(struct ionic_dev *idev)
76 return ioread8(&idev->dev_cmd->comp.comp.status);
80 ionic_dev_cmd_done(struct ionic_dev *idev)
82 return ioread32(&idev->dev_cmd->done) & IONIC_DEV_CMD_DONE;
86 ionic_dev_cmd_comp(struct ionic_dev *idev, void *mem)
88 union ionic_dev_cmd_comp *comp = mem;
90 uint32_t comp_size = sizeof(comp->words) /
91 sizeof(comp->words[0]);
93 for (i = 0; i < comp_size; i++)
94 comp->words[i] = ioread32(&idev->dev_cmd->comp.words[i]);
98 ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
101 uint32_t cmd_size = sizeof(cmd->words) /
102 sizeof(cmd->words[0]);
104 for (i = 0; i < cmd_size; i++)
105 iowrite32(cmd->words[i], &idev->dev_cmd->cmd.words[i]);
107 iowrite32(0, &idev->dev_cmd->done);
108 iowrite32(1, &idev->dev_cmd->doorbell);
111 /* Device commands */
114 ionic_dev_cmd_identify(struct ionic_dev *idev, uint8_t ver)
116 union ionic_dev_cmd cmd = {
117 .identify.opcode = IONIC_CMD_IDENTIFY,
121 ionic_dev_cmd_go(idev, &cmd);
125 ionic_dev_cmd_init(struct ionic_dev *idev)
127 union ionic_dev_cmd cmd = {
128 .init.opcode = IONIC_CMD_INIT,
132 ionic_dev_cmd_go(idev, &cmd);
136 ionic_dev_cmd_reset(struct ionic_dev *idev)
138 union ionic_dev_cmd cmd = {
139 .reset.opcode = IONIC_CMD_RESET,
142 ionic_dev_cmd_go(idev, &cmd);
148 ionic_dev_cmd_port_identify(struct ionic_dev *idev)
150 union ionic_dev_cmd cmd = {
151 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY,
152 .port_init.index = 0,
155 ionic_dev_cmd_go(idev, &cmd);
159 ionic_dev_cmd_port_init(struct ionic_dev *idev)
161 union ionic_dev_cmd cmd = {
162 .port_init.opcode = IONIC_CMD_PORT_INIT,
163 .port_init.index = 0,
164 .port_init.info_pa = idev->port_info_pa,
167 ionic_dev_cmd_go(idev, &cmd);
171 ionic_dev_cmd_port_reset(struct ionic_dev *idev)
173 union ionic_dev_cmd cmd = {
174 .port_reset.opcode = IONIC_CMD_PORT_RESET,
175 .port_reset.index = 0,
178 ionic_dev_cmd_go(idev, &cmd);
182 ionic_dev_cmd_port_state(struct ionic_dev *idev, uint8_t state)
184 union ionic_dev_cmd cmd = {
185 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
186 .port_setattr.index = 0,
187 .port_setattr.attr = IONIC_PORT_ATTR_STATE,
188 .port_setattr.state = state,
191 ionic_dev_cmd_go(idev, &cmd);
195 ionic_dev_cmd_port_speed(struct ionic_dev *idev, uint32_t speed)
197 union ionic_dev_cmd cmd = {
198 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
199 .port_setattr.index = 0,
200 .port_setattr.attr = IONIC_PORT_ATTR_SPEED,
201 .port_setattr.speed = speed,
204 ionic_dev_cmd_go(idev, &cmd);
208 ionic_dev_cmd_port_mtu(struct ionic_dev *idev, uint32_t mtu)
210 union ionic_dev_cmd cmd = {
211 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
212 .port_setattr.index = 0,
213 .port_setattr.attr = IONIC_PORT_ATTR_MTU,
214 .port_setattr.mtu = mtu,
217 ionic_dev_cmd_go(idev, &cmd);
221 ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, uint8_t an_enable)
223 union ionic_dev_cmd cmd = {
224 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
225 .port_setattr.index = 0,
226 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
227 .port_setattr.an_enable = an_enable,
230 ionic_dev_cmd_go(idev, &cmd);
234 ionic_dev_cmd_port_fec(struct ionic_dev *idev, uint8_t fec_type)
236 union ionic_dev_cmd cmd = {
237 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
238 .port_setattr.index = 0,
239 .port_setattr.attr = IONIC_PORT_ATTR_FEC,
240 .port_setattr.fec_type = fec_type,
243 ionic_dev_cmd_go(idev, &cmd);
247 ionic_dev_cmd_port_pause(struct ionic_dev *idev, uint8_t pause_type)
249 union ionic_dev_cmd cmd = {
250 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
251 .port_setattr.index = 0,
252 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
253 .port_setattr.pause_type = pause_type,
256 ionic_dev_cmd_go(idev, &cmd);
260 ionic_dev_cmd_port_loopback(struct ionic_dev *idev, uint8_t loopback_mode)
262 union ionic_dev_cmd cmd = {
263 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
264 .port_setattr.index = 0,
265 .port_setattr.attr = IONIC_PORT_ATTR_LOOPBACK,
266 .port_setattr.loopback_mode = loopback_mode,
269 ionic_dev_cmd_go(idev, &cmd);
275 ionic_dev_cmd_lif_identify(struct ionic_dev *idev, uint8_t type, uint8_t ver)
277 union ionic_dev_cmd cmd = {
278 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY,
279 .lif_identify.type = type,
280 .lif_identify.ver = ver,
283 ionic_dev_cmd_go(idev, &cmd);
287 ionic_dev_cmd_lif_init(struct ionic_dev *idev, uint16_t lif_index,
290 union ionic_dev_cmd cmd = {
291 .lif_init.opcode = IONIC_CMD_LIF_INIT,
292 .lif_init.index = lif_index,
293 .lif_init.info_pa = info_pa,
296 ionic_dev_cmd_go(idev, &cmd);
300 ionic_dev_cmd_lif_reset(struct ionic_dev *idev, uint16_t lif_index)
302 union ionic_dev_cmd cmd = {
303 .lif_init.opcode = IONIC_CMD_LIF_RESET,
304 .lif_init.index = lif_index,
307 ionic_dev_cmd_go(idev, &cmd);
310 struct ionic_doorbell *
311 ionic_db_map(struct ionic_lif *lif, struct ionic_queue *q)
313 return lif->kern_dbpage + q->hw_type;
317 ionic_db_page_num(struct ionic_lif *lif, int pid)
319 return (lif->index * 0) + pid;
323 ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,
326 ionic_intr_clean(idev->intr_ctrl, index);
331 ionic_dev_cmd_adminq_init(struct ionic_dev *idev,
332 struct ionic_qcq *qcq,
333 uint16_t lif_index, uint16_t intr_index)
335 struct ionic_queue *q = &qcq->q;
336 struct ionic_cq *cq = &qcq->cq;
338 union ionic_dev_cmd cmd = {
339 .q_init.opcode = IONIC_CMD_Q_INIT,
340 .q_init.lif_index = lif_index,
341 .q_init.type = q->type,
342 .q_init.index = q->index,
343 .q_init.flags = IONIC_QINIT_F_ENA,
344 .q_init.pid = q->pid,
345 .q_init.intr_index = intr_index,
346 .q_init.ring_size = rte_log2_u32(q->num_descs),
347 .q_init.ring_base = q->base_pa,
348 .q_init.cq_ring_base = cq->base_pa,
351 ionic_dev_cmd_go(idev, &cmd);
355 ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
356 struct ionic_intr_info *intr,
357 uint32_t num_descs, size_t desc_size)
359 if (desc_size == 0) {
360 IONIC_PRINT(ERR, "Descriptor size is %zu", desc_size);
364 if (!rte_is_power_of_2(num_descs) ||
365 num_descs < IONIC_MIN_RING_DESC ||
366 num_descs > IONIC_MAX_RING_DESC) {
367 IONIC_PRINT(ERR, "%u descriptors (min: %u max: %u)",
368 num_descs, IONIC_MIN_RING_DESC, IONIC_MAX_RING_DESC);
373 cq->bound_intr = intr;
374 cq->num_descs = num_descs;
375 cq->desc_size = desc_size;
383 ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa)
386 cq->base_pa = base_pa;
390 ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q)
397 ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,
398 ionic_cq_cb cb, void *cb_arg)
400 uint32_t work_done = 0;
405 while (cb(cq, cq->tail_idx, cb_arg)) {
406 cq->tail_idx = (cq->tail_idx + 1) & (cq->num_descs - 1);
407 if (cq->tail_idx == 0)
408 cq->done_color = !cq->done_color;
410 if (++work_done == work_to_do)
418 ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
419 struct ionic_queue *q, uint32_t index, uint32_t num_descs,
420 size_t desc_size, size_t sg_desc_size, uint32_t pid)
424 if (desc_size == 0 || !rte_is_power_of_2(num_descs))
427 ring_size = rte_log2_u32(num_descs);
429 if (ring_size < 2 || ring_size > 16)
435 q->num_descs = num_descs;
436 q->desc_size = desc_size;
437 q->sg_desc_size = sg_desc_size;
446 ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
449 q->base_pa = base_pa;
453 ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)
456 q->sg_base_pa = base_pa;
460 ionic_q_flush(struct ionic_queue *q)
462 writeq(IONIC_DBELL_QID(q->hw_index) | q->head_idx, q->db);
466 ionic_q_post(struct ionic_queue *q, bool ring_doorbell, desc_cb cb,
469 struct ionic_desc_info *head = &q->info[q->head_idx];
472 head->cb_arg = cb_arg;
474 q->head_idx = (q->head_idx + 1) & (q->num_descs - 1);
481 ionic_q_space_avail(struct ionic_queue *q)
483 uint32_t avail = q->tail_idx;
485 if (q->head_idx >= avail)
486 avail += q->num_descs - q->head_idx - 1;
488 avail -= q->head_idx + 1;
494 ionic_q_has_space(struct ionic_queue *q, uint32_t want)
496 return ionic_q_space_avail(q) >= want;
500 ionic_q_service(struct ionic_queue *q, uint32_t cq_desc_index,
501 uint32_t stop_index, void *service_cb_arg)
503 struct ionic_desc_info *desc_info;
504 uint32_t curr_q_tail_idx;
507 desc_info = &q->info[q->tail_idx];
510 desc_info->cb(q, q->tail_idx, cq_desc_index,
511 desc_info->cb_arg, service_cb_arg);
513 desc_info->cb = NULL;
514 desc_info->cb_arg = NULL;
516 curr_q_tail_idx = q->tail_idx;
517 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1);
519 } while (curr_q_tail_idx != stop_index);
523 ionic_adminq_cb(struct ionic_queue *q,
524 uint32_t q_desc_index, uint32_t cq_desc_index,
525 void *cb_arg, void *service_cb_arg __rte_unused)
527 struct ionic_admin_ctx *ctx = cb_arg;
528 struct ionic_admin_comp *cq_desc_base = q->bound_cq->base;
529 struct ionic_admin_comp *cq_desc = &cq_desc_base[cq_desc_index];
531 if (unlikely(cq_desc->comp_index != q_desc_index)) {
532 IONIC_WARN_ON(cq_desc->comp_index != q_desc_index);
536 memcpy(&ctx->comp, cq_desc, sizeof(*cq_desc));
538 ctx->pending_work = false; /* done */
541 /** ionic_adminq_post - Post an admin command.
542 * @lif: Handle to lif.
543 * @cmd_ctx: Api admin command context.
545 * Post the command to an admin queue in the ethernet driver. If this command
546 * succeeds, then the command has been posted, but that does not indicate a
547 * completion. If this command returns success, then the completion callback
548 * will eventually be called.
550 * Return: zero or negative error status.
553 ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)
555 struct ionic_queue *adminq = &lif->adminqcq->q;
556 struct ionic_admin_cmd *q_desc_base = adminq->base;
557 struct ionic_admin_cmd *q_desc;
560 rte_spinlock_lock(&lif->adminq_lock);
562 if (!ionic_q_has_space(adminq, 1)) {
567 q_desc = &q_desc_base[adminq->head_idx];
569 memcpy(q_desc, &ctx->cmd, sizeof(ctx->cmd));
571 ionic_q_post(adminq, true, ionic_adminq_cb, ctx);
574 rte_spinlock_unlock(&lif->adminq_lock);