1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
2 * Copyright(c) 2018-2019 Pensando Systems, Inc. All rights reserved.
6 #include <rte_bus_pci.h>
7 #include <rte_ethdev.h>
8 #include <rte_ethdev_driver.h>
9 #include <rte_malloc.h>
10 #include <rte_ethdev_pci.h>
12 #include "ionic_logs.h"
14 #include "ionic_dev.h"
15 #include "ionic_mac_api.h"
16 #include "ionic_lif.h"
17 #include "ionic_ethdev.h"
18 #include "ionic_rxtx.h"
20 static int eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
21 static int eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev);
22 static int ionic_dev_info_get(struct rte_eth_dev *eth_dev,
23 struct rte_eth_dev_info *dev_info);
24 static int ionic_dev_configure(struct rte_eth_dev *dev);
25 static int ionic_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
26 static int ionic_dev_start(struct rte_eth_dev *dev);
27 static void ionic_dev_stop(struct rte_eth_dev *dev);
28 static void ionic_dev_close(struct rte_eth_dev *dev);
29 static int ionic_dev_set_link_up(struct rte_eth_dev *dev);
30 static int ionic_dev_set_link_down(struct rte_eth_dev *dev);
31 static int ionic_dev_link_update(struct rte_eth_dev *eth_dev,
32 int wait_to_complete);
33 static int ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev,
34 struct rte_eth_fc_conf *fc_conf);
35 static int ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev,
36 struct rte_eth_fc_conf *fc_conf);
37 static int ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask);
38 static int ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev,
39 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size);
40 static int ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev,
41 struct rte_eth_rss_reta_entry64 *reta_conf, uint16_t reta_size);
42 static int ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
43 struct rte_eth_rss_conf *rss_conf);
44 static int ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev,
45 struct rte_eth_rss_conf *rss_conf);
46 static int ionic_dev_stats_get(struct rte_eth_dev *eth_dev,
47 struct rte_eth_stats *stats);
48 static int ionic_dev_stats_reset(struct rte_eth_dev *eth_dev);
49 static int ionic_dev_xstats_get(struct rte_eth_dev *dev,
50 struct rte_eth_xstat *xstats, unsigned int n);
51 static int ionic_dev_xstats_get_by_id(struct rte_eth_dev *dev,
52 const uint64_t *ids, uint64_t *values, unsigned int n);
53 static int ionic_dev_xstats_reset(struct rte_eth_dev *dev);
54 static int ionic_dev_xstats_get_names(struct rte_eth_dev *dev,
55 struct rte_eth_xstat_name *xstats_names, unsigned int size);
56 static int ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
57 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
62 static const struct rte_pci_id pci_id_ionic_map[] = {
63 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_PF) },
64 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_VF) },
65 { RTE_PCI_DEVICE(IONIC_PENSANDO_VENDOR_ID, IONIC_DEV_ID_ETH_MGMT) },
66 { .vendor_id = 0, /* sentinel */ },
69 static const struct rte_eth_desc_lim rx_desc_lim = {
70 .nb_max = IONIC_MAX_RING_DESC,
71 .nb_min = IONIC_MIN_RING_DESC,
75 static const struct rte_eth_desc_lim tx_desc_lim = {
76 .nb_max = IONIC_MAX_RING_DESC,
77 .nb_min = IONIC_MIN_RING_DESC,
79 .nb_seg_max = IONIC_TX_MAX_SG_ELEMS,
80 .nb_mtu_seg_max = IONIC_TX_MAX_SG_ELEMS,
83 static const struct eth_dev_ops ionic_eth_dev_ops = {
84 .dev_infos_get = ionic_dev_info_get,
85 .dev_configure = ionic_dev_configure,
86 .mtu_set = ionic_dev_mtu_set,
87 .dev_start = ionic_dev_start,
88 .dev_stop = ionic_dev_stop,
89 .dev_close = ionic_dev_close,
90 .link_update = ionic_dev_link_update,
91 .dev_set_link_up = ionic_dev_set_link_up,
92 .dev_set_link_down = ionic_dev_set_link_down,
93 .mac_addr_add = ionic_dev_add_mac,
94 .mac_addr_remove = ionic_dev_remove_mac,
95 .mac_addr_set = ionic_dev_set_mac,
96 .vlan_filter_set = ionic_dev_vlan_filter_set,
97 .promiscuous_enable = ionic_dev_promiscuous_enable,
98 .promiscuous_disable = ionic_dev_promiscuous_disable,
99 .allmulticast_enable = ionic_dev_allmulticast_enable,
100 .allmulticast_disable = ionic_dev_allmulticast_disable,
101 .flow_ctrl_get = ionic_flow_ctrl_get,
102 .flow_ctrl_set = ionic_flow_ctrl_set,
103 .rxq_info_get = ionic_rxq_info_get,
104 .txq_info_get = ionic_txq_info_get,
105 .rx_queue_setup = ionic_dev_rx_queue_setup,
106 .rx_queue_release = ionic_dev_rx_queue_release,
107 .rx_queue_start = ionic_dev_rx_queue_start,
108 .rx_queue_stop = ionic_dev_rx_queue_stop,
109 .tx_queue_setup = ionic_dev_tx_queue_setup,
110 .tx_queue_release = ionic_dev_tx_queue_release,
111 .tx_queue_start = ionic_dev_tx_queue_start,
112 .tx_queue_stop = ionic_dev_tx_queue_stop,
113 .vlan_offload_set = ionic_vlan_offload_set,
114 .reta_update = ionic_dev_rss_reta_update,
115 .reta_query = ionic_dev_rss_reta_query,
116 .rss_hash_conf_get = ionic_dev_rss_hash_conf_get,
117 .rss_hash_update = ionic_dev_rss_hash_update,
118 .stats_get = ionic_dev_stats_get,
119 .stats_reset = ionic_dev_stats_reset,
120 .xstats_get = ionic_dev_xstats_get,
121 .xstats_get_by_id = ionic_dev_xstats_get_by_id,
122 .xstats_reset = ionic_dev_xstats_reset,
123 .xstats_get_names = ionic_dev_xstats_get_names,
124 .xstats_get_names_by_id = ionic_dev_xstats_get_names_by_id,
127 struct rte_ionic_xstats_name_off {
128 char name[RTE_ETH_XSTATS_NAME_SIZE];
132 static const struct rte_ionic_xstats_name_off rte_ionic_xstats_strings[] = {
134 {"rx_ucast_bytes", offsetof(struct ionic_lif_stats,
136 {"rx_ucast_packets", offsetof(struct ionic_lif_stats,
138 {"rx_mcast_bytes", offsetof(struct ionic_lif_stats,
140 {"rx_mcast_packets", offsetof(struct ionic_lif_stats,
142 {"rx_bcast_bytes", offsetof(struct ionic_lif_stats,
144 {"rx_bcast_packets", offsetof(struct ionic_lif_stats,
147 {"rx_ucast_drop_bytes", offsetof(struct ionic_lif_stats,
148 rx_ucast_drop_bytes)},
149 {"rx_ucast_drop_packets", offsetof(struct ionic_lif_stats,
150 rx_ucast_drop_packets)},
151 {"rx_mcast_drop_bytes", offsetof(struct ionic_lif_stats,
152 rx_mcast_drop_bytes)},
153 {"rx_mcast_drop_packets", offsetof(struct ionic_lif_stats,
154 rx_mcast_drop_packets)},
155 {"rx_bcast_drop_bytes", offsetof(struct ionic_lif_stats,
156 rx_bcast_drop_bytes)},
157 {"rx_bcast_drop_packets", offsetof(struct ionic_lif_stats,
158 rx_bcast_drop_packets)},
159 {"rx_dma_error", offsetof(struct ionic_lif_stats,
162 {"tx_ucast_bytes", offsetof(struct ionic_lif_stats,
164 {"tx_ucast_packets", offsetof(struct ionic_lif_stats,
166 {"tx_mcast_bytes", offsetof(struct ionic_lif_stats,
168 {"tx_mcast_packets", offsetof(struct ionic_lif_stats,
170 {"tx_bcast_bytes", offsetof(struct ionic_lif_stats,
172 {"tx_bcast_packets", offsetof(struct ionic_lif_stats,
175 {"tx_ucast_drop_bytes", offsetof(struct ionic_lif_stats,
176 tx_ucast_drop_bytes)},
177 {"tx_ucast_drop_packets", offsetof(struct ionic_lif_stats,
178 tx_ucast_drop_packets)},
179 {"tx_mcast_drop_bytes", offsetof(struct ionic_lif_stats,
180 tx_mcast_drop_bytes)},
181 {"tx_mcast_drop_packets", offsetof(struct ionic_lif_stats,
182 tx_mcast_drop_packets)},
183 {"tx_bcast_drop_bytes", offsetof(struct ionic_lif_stats,
184 tx_bcast_drop_bytes)},
185 {"tx_bcast_drop_packets", offsetof(struct ionic_lif_stats,
186 tx_bcast_drop_packets)},
187 {"tx_dma_error", offsetof(struct ionic_lif_stats,
189 /* Rx Queue/Ring drops */
190 {"rx_queue_disabled", offsetof(struct ionic_lif_stats,
192 {"rx_queue_empty", offsetof(struct ionic_lif_stats,
194 {"rx_queue_error", offsetof(struct ionic_lif_stats,
196 {"rx_desc_fetch_error", offsetof(struct ionic_lif_stats,
197 rx_desc_fetch_error)},
198 {"rx_desc_data_error", offsetof(struct ionic_lif_stats,
199 rx_desc_data_error)},
200 /* Tx Queue/Ring drops */
201 {"tx_queue_disabled", offsetof(struct ionic_lif_stats,
203 {"tx_queue_error", offsetof(struct ionic_lif_stats,
205 {"tx_desc_fetch_error", offsetof(struct ionic_lif_stats,
206 tx_desc_fetch_error)},
207 {"tx_desc_data_error", offsetof(struct ionic_lif_stats,
208 tx_desc_data_error)},
211 #define IONIC_NB_HW_STATS (sizeof(rte_ionic_xstats_strings) / \
212 sizeof(rte_ionic_xstats_strings[0]))
215 * Set device link up, enable tx.
218 ionic_dev_set_link_up(struct rte_eth_dev *eth_dev)
220 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
221 struct ionic_adapter *adapter = lif->adapter;
222 struct ionic_dev *idev = &adapter->idev;
227 ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_UP);
229 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
231 IONIC_PRINT(WARNING, "Failed to bring port UP");
239 * Set device link down, disable tx.
242 ionic_dev_set_link_down(struct rte_eth_dev *eth_dev)
244 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
245 struct ionic_adapter *adapter = lif->adapter;
246 struct ionic_dev *idev = &adapter->idev;
251 ionic_dev_cmd_port_state(idev, IONIC_PORT_ADMIN_STATE_DOWN);
253 err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
255 IONIC_PRINT(WARNING, "Failed to bring port DOWN");
263 ionic_dev_link_update(struct rte_eth_dev *eth_dev,
264 int wait_to_complete __rte_unused)
266 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
267 struct ionic_adapter *adapter = lif->adapter;
268 struct rte_eth_link link;
273 memset(&link, 0, sizeof(link));
274 link.link_autoneg = ETH_LINK_AUTONEG;
276 if (!adapter->link_up) {
277 /* Interface is down */
278 link.link_status = ETH_LINK_DOWN;
279 link.link_duplex = ETH_LINK_HALF_DUPLEX;
280 link.link_speed = ETH_SPEED_NUM_NONE;
282 /* Interface is up */
283 link.link_status = ETH_LINK_UP;
284 link.link_duplex = ETH_LINK_FULL_DUPLEX;
285 switch (adapter->link_speed) {
287 link.link_speed = ETH_SPEED_NUM_10G;
290 link.link_speed = ETH_SPEED_NUM_25G;
293 link.link_speed = ETH_SPEED_NUM_40G;
296 link.link_speed = ETH_SPEED_NUM_50G;
299 link.link_speed = ETH_SPEED_NUM_100G;
302 link.link_speed = ETH_SPEED_NUM_NONE;
307 return rte_eth_linkstatus_set(eth_dev, &link);
311 * Interrupt handler triggered by NIC for handling
312 * specific interrupt.
315 * The address of parameter registered before.
321 ionic_dev_interrupt_handler(void *param)
323 struct ionic_adapter *adapter = (struct ionic_adapter *)param;
326 IONIC_PRINT(DEBUG, "->");
328 for (i = 0; i < adapter->nlifs; i++) {
329 if (adapter->lifs[i])
330 ionic_notifyq_handler(adapter->lifs[i], -1);
335 ionic_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu)
337 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
338 uint32_t max_frame_size;
344 * Note: mtu check against IONIC_MIN_MTU, IONIC_MAX_MTU
345 * is done by the the API.
349 * Max frame size is MTU + Ethernet header + VLAN + QinQ
350 * (plus ETHER_CRC_LEN if the adapter is able to keep CRC)
352 max_frame_size = mtu + RTE_ETHER_HDR_LEN + 4 + 4;
354 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len < max_frame_size)
357 err = ionic_lif_change_mtu(lif, mtu);
365 ionic_dev_info_get(struct rte_eth_dev *eth_dev,
366 struct rte_eth_dev_info *dev_info)
368 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
369 struct ionic_adapter *adapter = lif->adapter;
370 struct ionic_identity *ident = &adapter->ident;
374 dev_info->max_rx_queues = (uint16_t)
375 ident->lif.eth.config.queue_count[IONIC_QTYPE_RXQ];
376 dev_info->max_tx_queues = (uint16_t)
377 ident->lif.eth.config.queue_count[IONIC_QTYPE_TXQ];
378 /* Also add ETHER_CRC_LEN if the adapter is able to keep CRC */
379 dev_info->min_rx_bufsize = IONIC_MIN_MTU + RTE_ETHER_HDR_LEN;
380 dev_info->max_rx_pktlen = IONIC_MAX_MTU + RTE_ETHER_HDR_LEN;
381 dev_info->max_mac_addrs = adapter->max_mac_addrs;
382 dev_info->min_mtu = IONIC_MIN_MTU;
383 dev_info->max_mtu = IONIC_MAX_MTU;
385 dev_info->hash_key_size = IONIC_RSS_HASH_KEY_SIZE;
386 dev_info->reta_size = ident->lif.eth.rss_ind_tbl_sz;
387 dev_info->flow_type_rss_offloads = IONIC_ETH_RSS_OFFLOAD_ALL;
389 dev_info->speed_capa =
397 * Per-queue capabilities. Actually most of the offloads are enabled
398 * by default on the port and can be used on selected queues (by adding
399 * packet flags at runtime when required)
402 dev_info->rx_queue_offload_capa =
403 DEV_RX_OFFLOAD_IPV4_CKSUM |
404 DEV_RX_OFFLOAD_UDP_CKSUM |
405 DEV_RX_OFFLOAD_TCP_CKSUM |
408 dev_info->tx_queue_offload_capa =
409 DEV_TX_OFFLOAD_VLAN_INSERT |
413 * Per-port capabilities
414 * See ionic_set_features to request and check supported features
417 dev_info->rx_offload_capa = dev_info->rx_queue_offload_capa |
418 DEV_RX_OFFLOAD_JUMBO_FRAME |
419 DEV_RX_OFFLOAD_VLAN_FILTER |
420 DEV_RX_OFFLOAD_VLAN_STRIP |
421 DEV_RX_OFFLOAD_SCATTER |
424 dev_info->tx_offload_capa = dev_info->tx_queue_offload_capa |
425 DEV_TX_OFFLOAD_MULTI_SEGS |
426 DEV_TX_OFFLOAD_TCP_TSO |
429 dev_info->rx_desc_lim = rx_desc_lim;
430 dev_info->tx_desc_lim = tx_desc_lim;
432 /* Driver-preferred Rx/Tx parameters */
433 dev_info->default_rxportconf.burst_size = 32;
434 dev_info->default_txportconf.burst_size = 32;
435 dev_info->default_rxportconf.nb_queues = 1;
436 dev_info->default_txportconf.nb_queues = 1;
437 dev_info->default_rxportconf.ring_size = IONIC_DEF_TXRX_DESC;
438 dev_info->default_txportconf.ring_size = IONIC_DEF_TXRX_DESC;
444 ionic_flow_ctrl_get(struct rte_eth_dev *eth_dev,
445 struct rte_eth_fc_conf *fc_conf)
447 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
448 struct ionic_adapter *adapter = lif->adapter;
449 struct ionic_dev *idev = &adapter->idev;
451 if (idev->port_info) {
452 fc_conf->autoneg = idev->port_info->config.an_enable;
454 if (idev->port_info->config.pause_type)
455 fc_conf->mode = RTE_FC_FULL;
457 fc_conf->mode = RTE_FC_NONE;
464 ionic_flow_ctrl_set(struct rte_eth_dev *eth_dev,
465 struct rte_eth_fc_conf *fc_conf)
467 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
468 struct ionic_adapter *adapter = lif->adapter;
469 struct ionic_dev *idev = &adapter->idev;
470 uint8_t pause_type = IONIC_PORT_PAUSE_TYPE_NONE;
473 switch (fc_conf->mode) {
475 pause_type = IONIC_PORT_PAUSE_TYPE_NONE;
478 pause_type = IONIC_PORT_PAUSE_TYPE_LINK;
480 case RTE_FC_RX_PAUSE:
481 case RTE_FC_TX_PAUSE:
485 an_enable = fc_conf->autoneg;
487 ionic_dev_cmd_port_pause(idev, pause_type);
488 ionic_dev_cmd_port_autoneg(idev, an_enable);
494 ionic_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
496 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
497 struct rte_eth_rxmode *rxmode;
498 rxmode = ð_dev->data->dev_conf.rxmode;
501 if (mask & ETH_VLAN_STRIP_MASK) {
502 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
503 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
504 struct ionic_qcq *rxq =
505 eth_dev->data->rx_queues[i];
506 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
508 lif->features |= IONIC_ETH_HW_VLAN_RX_STRIP;
510 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
511 struct ionic_qcq *rxq =
512 eth_dev->data->rx_queues[i];
513 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
515 lif->features &= ~IONIC_ETH_HW_VLAN_RX_STRIP;
519 if (mask & ETH_VLAN_FILTER_MASK) {
520 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
521 lif->features |= IONIC_ETH_HW_VLAN_RX_FILTER;
523 lif->features &= ~IONIC_ETH_HW_VLAN_RX_FILTER;
526 ionic_lif_set_features(lif);
532 ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev,
533 struct rte_eth_rss_reta_entry64 *reta_conf,
536 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
537 struct ionic_adapter *adapter = lif->adapter;
538 struct ionic_identity *ident = &adapter->ident;
539 uint32_t i, j, index, num;
543 if (!lif->rss_ind_tbl) {
544 IONIC_PRINT(ERR, "RSS RETA not initialized, "
545 "can't update the table");
549 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) {
550 IONIC_PRINT(ERR, "The size of hash lookup table configured "
551 "(%d) doesn't match the number hardware can supported "
553 reta_size, ident->lif.eth.rss_ind_tbl_sz);
557 num = lif->adapter->ident.lif.eth.rss_ind_tbl_sz / RTE_RETA_GROUP_SIZE;
559 for (i = 0; i < num; i++) {
560 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++) {
561 if (reta_conf[i].mask & ((uint64_t)1 << j)) {
562 index = (i * RTE_RETA_GROUP_SIZE) + j;
563 lif->rss_ind_tbl[index] = reta_conf[i].reta[j];
568 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
572 ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev,
573 struct rte_eth_rss_reta_entry64 *reta_conf,
576 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
577 struct ionic_adapter *adapter = lif->adapter;
578 struct ionic_identity *ident = &adapter->ident;
583 if (reta_size != ident->lif.eth.rss_ind_tbl_sz) {
584 IONIC_PRINT(ERR, "The size of hash lookup table configured "
585 "(%d) doesn't match the number hardware can supported "
587 reta_size, ident->lif.eth.rss_ind_tbl_sz);
591 if (!lif->rss_ind_tbl) {
592 IONIC_PRINT(ERR, "RSS RETA has not been built yet");
596 num = reta_size / RTE_RETA_GROUP_SIZE;
598 for (i = 0; i < num; i++) {
599 memcpy(reta_conf->reta,
600 &lif->rss_ind_tbl[i * RTE_RETA_GROUP_SIZE],
601 RTE_RETA_GROUP_SIZE);
609 ionic_dev_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
610 struct rte_eth_rss_conf *rss_conf)
612 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
617 if (!lif->rss_ind_tbl) {
618 IONIC_PRINT(NOTICE, "RSS not enabled");
622 /* Get key value (if not null, rss_key is 40-byte) */
623 if (rss_conf->rss_key != NULL &&
624 rss_conf->rss_key_len >= IONIC_RSS_HASH_KEY_SIZE)
625 memcpy(rss_conf->rss_key, lif->rss_hash_key,
626 IONIC_RSS_HASH_KEY_SIZE);
628 if (lif->rss_types & IONIC_RSS_TYPE_IPV4)
629 rss_hf |= ETH_RSS_IPV4;
630 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_TCP)
631 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
632 if (lif->rss_types & IONIC_RSS_TYPE_IPV4_UDP)
633 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
634 if (lif->rss_types & IONIC_RSS_TYPE_IPV6)
635 rss_hf |= ETH_RSS_IPV6;
636 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_TCP)
637 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
638 if (lif->rss_types & IONIC_RSS_TYPE_IPV6_UDP)
639 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
641 rss_conf->rss_hf = rss_hf;
647 ionic_dev_rss_hash_update(struct rte_eth_dev *eth_dev,
648 struct rte_eth_rss_conf *rss_conf)
650 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
651 uint32_t rss_types = 0;
656 if (rss_conf->rss_key)
657 key = rss_conf->rss_key;
659 if ((rss_conf->rss_hf & IONIC_ETH_RSS_OFFLOAD_ALL) == 0) {
661 * Can't disable rss through hash flags,
662 * if it is enabled by default during init
664 if (lif->rss_ind_tbl)
667 /* Can't enable rss if disabled by default during init */
668 if (!lif->rss_ind_tbl)
671 if (rss_conf->rss_hf & ETH_RSS_IPV4)
672 rss_types |= IONIC_RSS_TYPE_IPV4;
673 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP)
674 rss_types |= IONIC_RSS_TYPE_IPV4_TCP;
675 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP)
676 rss_types |= IONIC_RSS_TYPE_IPV4_UDP;
677 if (rss_conf->rss_hf & ETH_RSS_IPV6)
678 rss_types |= IONIC_RSS_TYPE_IPV6;
679 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP)
680 rss_types |= IONIC_RSS_TYPE_IPV6_TCP;
681 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP)
682 rss_types |= IONIC_RSS_TYPE_IPV6_UDP;
684 ionic_lif_rss_config(lif, rss_types, key, NULL);
691 ionic_dev_stats_get(struct rte_eth_dev *eth_dev,
692 struct rte_eth_stats *stats)
694 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
696 ionic_lif_get_stats(lif, stats);
702 ionic_dev_stats_reset(struct rte_eth_dev *eth_dev)
704 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
708 ionic_lif_reset_stats(lif);
714 ionic_dev_xstats_get_names(__rte_unused struct rte_eth_dev *eth_dev,
715 struct rte_eth_xstat_name *xstats_names,
716 __rte_unused unsigned int size)
720 if (xstats_names != NULL) {
721 for (i = 0; i < IONIC_NB_HW_STATS; i++) {
722 snprintf(xstats_names[i].name,
723 sizeof(xstats_names[i].name),
724 "%s", rte_ionic_xstats_strings[i].name);
728 return IONIC_NB_HW_STATS;
732 ionic_dev_xstats_get_names_by_id(struct rte_eth_dev *eth_dev,
733 struct rte_eth_xstat_name *xstats_names, const uint64_t *ids,
736 struct rte_eth_xstat_name xstats_names_copy[IONIC_NB_HW_STATS];
740 if (xstats_names != NULL) {
741 for (i = 0; i < IONIC_NB_HW_STATS; i++) {
742 snprintf(xstats_names[i].name,
743 sizeof(xstats_names[i].name),
744 "%s", rte_ionic_xstats_strings[i].name);
748 return IONIC_NB_HW_STATS;
751 ionic_dev_xstats_get_names_by_id(eth_dev, xstats_names_copy, NULL,
754 for (i = 0; i < limit; i++) {
755 if (ids[i] >= IONIC_NB_HW_STATS) {
756 IONIC_PRINT(ERR, "id value isn't valid");
760 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name);
767 ionic_dev_xstats_get(struct rte_eth_dev *eth_dev, struct rte_eth_xstat *xstats,
770 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
771 struct ionic_lif_stats hw_stats;
774 if (n < IONIC_NB_HW_STATS)
775 return IONIC_NB_HW_STATS;
777 ionic_lif_get_hw_stats(lif, &hw_stats);
779 for (i = 0; i < IONIC_NB_HW_STATS; i++) {
780 xstats[i].value = *(uint64_t *)(((char *)&hw_stats) +
781 rte_ionic_xstats_strings[i].offset);
785 return IONIC_NB_HW_STATS;
789 ionic_dev_xstats_get_by_id(struct rte_eth_dev *eth_dev, const uint64_t *ids,
790 uint64_t *values, unsigned int n)
792 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
793 struct ionic_lif_stats hw_stats;
794 uint64_t values_copy[IONIC_NB_HW_STATS];
798 if (!ids && n < IONIC_NB_HW_STATS)
799 return IONIC_NB_HW_STATS;
801 ionic_lif_get_hw_stats(lif, &hw_stats);
803 for (i = 0; i < IONIC_NB_HW_STATS; i++) {
804 values[i] = *(uint64_t *)(((char *)&hw_stats) +
805 rte_ionic_xstats_strings[i].offset);
808 return IONIC_NB_HW_STATS;
811 ionic_dev_xstats_get_by_id(eth_dev, NULL, values_copy,
814 for (i = 0; i < n; i++) {
815 if (ids[i] >= IONIC_NB_HW_STATS) {
816 IONIC_PRINT(ERR, "id value isn't valid");
820 values[i] = values_copy[ids[i]];
827 ionic_dev_xstats_reset(struct rte_eth_dev *eth_dev)
829 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
831 ionic_lif_reset_hw_stats(lif);
837 ionic_dev_configure(struct rte_eth_dev *eth_dev)
839 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
844 err = ionic_lif_configure(lif);
846 IONIC_PRINT(ERR, "Cannot configure LIF: %d", err);
853 static inline uint32_t
854 ionic_parse_link_speeds(uint16_t link_speeds)
856 if (link_speeds & ETH_LINK_SPEED_100G)
858 else if (link_speeds & ETH_LINK_SPEED_50G)
860 else if (link_speeds & ETH_LINK_SPEED_40G)
862 else if (link_speeds & ETH_LINK_SPEED_25G)
864 else if (link_speeds & ETH_LINK_SPEED_10G)
871 * Configure device link speed and setup link.
872 * It returns 0 on success.
875 ionic_dev_start(struct rte_eth_dev *eth_dev)
877 struct rte_eth_conf *dev_conf = ð_dev->data->dev_conf;
878 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
879 struct ionic_adapter *adapter = lif->adapter;
880 struct ionic_dev *idev = &adapter->idev;
881 uint32_t allowed_speeds;
887 ETH_LINK_SPEED_FIXED |
894 if (dev_conf->link_speeds & ~allowed_speeds) {
895 IONIC_PRINT(ERR, "Invalid link setting");
899 err = ionic_lif_start(lif);
901 IONIC_PRINT(ERR, "Cannot start LIF: %d", err);
905 if (eth_dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
906 uint32_t speed = ionic_parse_link_speeds(dev_conf->link_speeds);
909 ionic_dev_cmd_port_speed(idev, speed);
912 ionic_dev_link_update(eth_dev, 0);
918 * Stop device: disable rx and tx functions to allow for reconfiguring.
921 ionic_dev_stop(struct rte_eth_dev *eth_dev)
923 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
928 err = ionic_lif_stop(lif);
930 IONIC_PRINT(ERR, "Cannot stop LIF: %d", err);
934 * Reset and stop device.
937 ionic_dev_close(struct rte_eth_dev *eth_dev)
939 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
944 err = ionic_lif_stop(lif);
946 IONIC_PRINT(ERR, "Cannot stop LIF: %d", err);
950 err = eth_ionic_dev_uninit(eth_dev);
952 IONIC_PRINT(ERR, "Cannot destroy LIF: %d", err);
958 eth_ionic_dev_init(struct rte_eth_dev *eth_dev, void *init_params)
960 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
961 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
962 struct ionic_adapter *adapter = (struct ionic_adapter *)init_params;
967 eth_dev->dev_ops = &ionic_eth_dev_ops;
968 eth_dev->rx_pkt_burst = &ionic_recv_pkts;
969 eth_dev->tx_pkt_burst = &ionic_xmit_pkts;
970 eth_dev->tx_pkt_prepare = &ionic_prep_pkts;
972 /* Multi-process not supported, primary does initialization anyway */
973 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
976 rte_eth_copy_pci_info(eth_dev, pci_dev);
978 lif->index = adapter->nlifs;
979 lif->eth_dev = eth_dev;
980 lif->adapter = adapter;
981 adapter->lifs[adapter->nlifs] = lif;
983 IONIC_PRINT(DEBUG, "Up to %u MAC addresses supported",
984 adapter->max_mac_addrs);
986 /* Allocate memory for storing MAC addresses */
987 eth_dev->data->mac_addrs = rte_zmalloc("ionic",
988 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs, 0);
990 if (eth_dev->data->mac_addrs == NULL) {
991 IONIC_PRINT(ERR, "Failed to allocate %u bytes needed to "
992 "store MAC addresses",
993 RTE_ETHER_ADDR_LEN * adapter->max_mac_addrs);
998 err = ionic_lif_alloc(lif);
1000 IONIC_PRINT(ERR, "Cannot allocate LIFs: %d, aborting",
1005 err = ionic_lif_init(lif);
1007 IONIC_PRINT(ERR, "Cannot init LIFs: %d, aborting", err);
1011 /* Copy the MAC address */
1012 rte_ether_addr_copy((struct rte_ether_addr *)lif->mac_addr,
1013 ð_dev->data->mac_addrs[0]);
1015 IONIC_PRINT(DEBUG, "Port %u initialized", eth_dev->data->port_id);
1020 ionic_lif_free(lif);
1026 eth_ionic_dev_uninit(struct rte_eth_dev *eth_dev)
1028 struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
1029 struct ionic_adapter *adapter = lif->adapter;
1033 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1036 adapter->lifs[lif->index] = NULL;
1038 ionic_lif_deinit(lif);
1039 ionic_lif_free(lif);
1041 eth_dev->dev_ops = NULL;
1042 eth_dev->rx_pkt_burst = NULL;
1043 eth_dev->tx_pkt_burst = NULL;
1044 eth_dev->tx_pkt_prepare = NULL;
1050 ionic_configure_intr(struct ionic_adapter *adapter)
1052 struct rte_pci_device *pci_dev = adapter->pci_dev;
1053 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1056 IONIC_PRINT(DEBUG, "Configuring %u intrs", adapter->nintrs);
1058 if (rte_intr_efd_enable(intr_handle, adapter->nintrs)) {
1059 IONIC_PRINT(ERR, "Fail to create eventfd");
1063 if (rte_intr_dp_is_en(intr_handle))
1065 "Packet I/O interrupt on datapath is enabled");
1067 if (!intr_handle->intr_vec) {
1068 intr_handle->intr_vec = rte_zmalloc("intr_vec",
1069 adapter->nintrs * sizeof(int), 0);
1071 if (!intr_handle->intr_vec) {
1072 IONIC_PRINT(ERR, "Failed to allocate %u vectors",
1078 err = rte_intr_callback_register(intr_handle,
1079 ionic_dev_interrupt_handler,
1084 "Failure registering interrupts handler (%d)",
1089 /* enable intr mapping */
1090 err = rte_intr_enable(intr_handle);
1093 IONIC_PRINT(ERR, "Failure enabling interrupts (%d)", err);
1101 ionic_unconfigure_intr(struct ionic_adapter *adapter)
1103 struct rte_pci_device *pci_dev = adapter->pci_dev;
1104 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1106 rte_intr_disable(intr_handle);
1108 rte_intr_callback_unregister(intr_handle,
1109 ionic_dev_interrupt_handler,
1114 eth_ionic_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1115 struct rte_pci_device *pci_dev)
1117 char name[RTE_ETH_NAME_MAX_LEN];
1118 struct rte_mem_resource *resource;
1119 struct ionic_adapter *adapter;
1120 struct ionic_hw *hw;
1124 /* Check structs (trigger error at compilation time) */
1125 ionic_struct_size_checks();
1127 /* Multi-process not supported */
1128 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1133 IONIC_PRINT(DEBUG, "Initializing device %s",
1134 pci_dev->device.name);
1136 adapter = rte_zmalloc("ionic", sizeof(*adapter), 0);
1138 IONIC_PRINT(ERR, "OOM");
1143 adapter->pci_dev = pci_dev;
1146 hw->device_id = pci_dev->id.device_id;
1147 hw->vendor_id = pci_dev->id.vendor_id;
1149 err = ionic_init_mac(hw);
1151 IONIC_PRINT(ERR, "Mac init failed: %d", err);
1153 goto err_free_adapter;
1156 adapter->is_mgmt_nic = (pci_dev->id.device_id == IONIC_DEV_ID_ETH_MGMT);
1158 adapter->num_bars = 0;
1159 for (i = 0; i < PCI_MAX_RESOURCE && i < IONIC_BARS_MAX; i++) {
1160 resource = &pci_dev->mem_resource[i];
1161 if (resource->phys_addr == 0 || resource->len == 0)
1163 adapter->bars[adapter->num_bars].vaddr = resource->addr;
1164 adapter->bars[adapter->num_bars].bus_addr = resource->phys_addr;
1165 adapter->bars[adapter->num_bars].len = resource->len;
1166 adapter->num_bars++;
1169 /* Discover ionic dev resources */
1171 err = ionic_setup(adapter);
1173 IONIC_PRINT(ERR, "Cannot setup device: %d, aborting", err);
1174 goto err_free_adapter;
1177 err = ionic_identify(adapter);
1179 IONIC_PRINT(ERR, "Cannot identify device: %d, aborting",
1181 goto err_free_adapter;
1184 err = ionic_init(adapter);
1186 IONIC_PRINT(ERR, "Cannot init device: %d, aborting", err);
1187 goto err_free_adapter;
1190 /* Configure the ports */
1191 err = ionic_port_identify(adapter);
1193 IONIC_PRINT(ERR, "Cannot identify port: %d, aborting",
1195 goto err_free_adapter;
1198 err = ionic_port_init(adapter);
1200 IONIC_PRINT(ERR, "Cannot init port: %d, aborting", err);
1201 goto err_free_adapter;
1204 /* Configure LIFs */
1205 err = ionic_lif_identify(adapter);
1207 IONIC_PRINT(ERR, "Cannot identify lif: %d, aborting", err);
1208 goto err_free_adapter;
1211 /* Allocate and init LIFs */
1212 err = ionic_lifs_size(adapter);
1214 IONIC_PRINT(ERR, "Cannot size LIFs: %d, aborting", err);
1215 goto err_free_adapter;
1218 adapter->max_mac_addrs = adapter->ident.lif.eth.max_ucast_filters;
1221 for (i = 0; i < adapter->ident.dev.nlifs; i++) {
1222 snprintf(name, sizeof(name), "net_%s_lif_%lu",
1223 pci_dev->device.name, i);
1225 err = rte_eth_dev_create(&pci_dev->device, name,
1226 sizeof(struct ionic_lif),
1228 eth_ionic_dev_init, adapter);
1230 IONIC_PRINT(ERR, "Cannot create eth device for "
1231 "ionic lif %s", name);
1238 err = ionic_configure_intr(adapter);
1241 IONIC_PRINT(ERR, "Failed to configure interrupts");
1242 goto err_free_adapter;
1254 eth_ionic_pci_remove(struct rte_pci_device *pci_dev __rte_unused)
1256 char name[RTE_ETH_NAME_MAX_LEN];
1257 struct ionic_adapter *adapter = NULL;
1258 struct rte_eth_dev *eth_dev;
1259 struct ionic_lif *lif;
1262 /* Adapter lookup is using (the first) eth_dev name */
1263 snprintf(name, sizeof(name), "net_%s_lif_0",
1264 pci_dev->device.name);
1266 eth_dev = rte_eth_dev_allocated(name);
1268 lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
1269 adapter = lif->adapter;
1273 ionic_unconfigure_intr(adapter);
1275 for (i = 0; i < adapter->nlifs; i++) {
1276 lif = adapter->lifs[i];
1277 rte_eth_dev_destroy(lif->eth_dev, eth_ionic_dev_uninit);
1286 static struct rte_pci_driver rte_ionic_pmd = {
1287 .id_table = pci_id_ionic_map,
1288 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1289 .probe = eth_ionic_pci_probe,
1290 .remove = eth_ionic_pci_remove,
1293 RTE_PMD_REGISTER_PCI(net_ionic, rte_ionic_pmd);
1294 RTE_PMD_REGISTER_PCI_TABLE(net_ionic, pci_id_ionic_map);
1295 RTE_PMD_REGISTER_KMOD_DEP(net_ionic, "* igb_uio | uio_pci_generic | vfio-pci");
1297 RTE_INIT(ionic_init_log)
1299 ionic_logtype = rte_log_register("pmd.net.ionic");
1300 if (ionic_logtype >= 0)
1301 rte_log_set_level(ionic_logtype, RTE_LOG_NOTICE);